Product Folder Sample & Buy Support & Community Tools & Software Technical Documents TPS7B6925-Q1, TPS7B6933-Q1, TPS7B6950-Q1 SLVSCJ8B - NOVEMBER 2014 - REVISED JANUARY 2015 TPS7B69xx-Q1 High-Voltage Ultra-Low IQ Low-Dropout Regulator 1 Features 2 Applications * * * * * 1 * * * * * * * * Qualified for Automotive Applications AEC-Q100 Qualified With the Following Results: - Device Temperature Grade 1: -40C to 125C Ambient Operating Temperature Range - Device HBM ESD Classification Level 2 - Device CDM ESD Classification Level C4B 4 to 40-V Wide VI Input Voltage Range With up to 45-V Transient Maximum Output Current: 150 mA Low Quiescent Current (IQ): - 15 A Typical at Light Loads - 25 A Maximum Under Full Temperature 450-mV Typical Low Dropout Voltage at 100 mA Load Current Stable With Low ESR Ceramic Output Capacitor (2.2 to 100 F) Fixed 2.5-V, 3.3-V, and 5-V Output Voltage Options Integrated Fault Protection: - Thermal Shutdown - Short-Circuit Protection Packages: - 4-Pin SOT-223 Package - 5-Pin SOT-23 Package Automotive Infotainment Systems With Sleep Mode Always-On Battery Applications - Door Modules - Remote Keyless-Entry Systems - Immobilizers 3 Description The TPS7B69xx-Q1 device is a low-dropout linear regulator designed for up to 40-V VI operations. With only 15-A (typical) quiescent current at light load, the device is suitable for standby microcontrol-unit systems especially in automotive applications. The devices feature an integrated short-circuit and overcurrent protection. The TPS7B69xx-Q1 device operates over a -40C to 125C temperature range. Because of these features, the TPS7B6925-Q1, TPS7B6933-Q1, and TPS7B6950-Q1 devices are well suited in power supplies for various automotive applications. Device Information(1) PART NUMBER TPS7B6925-Q1 TPS7B6933-Q1 TPS7B6950-Q1 PACKAGE BODY SIZE (NOM) SOT-223 (4) 6.50 mm x 3.50 mm SOT-23 (5) 2.90 mm x 1.60 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. 4 Typical Application Schematic TPS7B69xx-Q1 IN Vbat OUT VI VO 10 F GND Vreg 4.7 F 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPS7B6925-Q1, TPS7B6933-Q1, TPS7B6950-Q1 SLVSCJ8B - NOVEMBER 2014 - REVISED JANUARY 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 Features .................................................................. Applications ........................................................... Description ............................................................. Typical Application Schematic............................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 1 2 3 4 7.1 7.2 7.3 7.4 7.5 7.6 4 4 4 4 5 6 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Typical Characteristics .............................................. Detailed Description ............................................ 10 8.1 Overview ................................................................. 10 8.2 Functional Block Diagram ....................................... 10 8.3 Feature Description................................................. 10 8.4 Device Functional Modes........................................ 11 9 Application and Implementation ........................ 12 9.1 Application Information............................................ 12 9.2 Typical Application .................................................. 12 10 Power Supply Recommendations ..................... 14 11 Layout................................................................... 14 11.1 Layout Guidelines ................................................. 14 11.2 Layout Example .................................................... 14 12 Device and Documentation Support ................. 15 12.1 12.2 12.3 12.4 12.5 Documentation Support ........................................ Related Links ........................................................ Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 15 15 15 15 15 13 Mechanical, Packaging, and Orderable Information ........................................................... 15 5 Revision History Changes from Revision A (December 2014) to Revision B Page * Changed the TPS7B6933-Q1 device status from Product Preview to Production Data ....................................................... 1 * Added the TPS7B6933-Q1 device test results to the Typical Characteristics section .......................................................... 6 Changes from Original (November 2014) to Revision A * 2 Page Changed the device status from Product Preview to Production Data ................................................................................. 1 Submit Documentation Feedback Copyright (c) 2014-2015, Texas Instruments Incorporated Product Folder Links: TPS7B6925-Q1 TPS7B6933-Q1 TPS7B6950-Q1 TPS7B6925-Q1, TPS7B6933-Q1, TPS7B6950-Q1 www.ti.com SLVSCJ8B - NOVEMBER 2014 - REVISED JANUARY 2015 6 Pin Configuration and Functions DCY Package 4-Pin SOT-223 Top View DBV Package 5-Pin SOT-23 Top View GND 4 1 2 3 IN GND OUT IN 1 NC 2 GND 3 5 OUT 4 GND NC - No internal connection Pin Functions PIN NAME NO. TYPE SOT-223 SOT-23 2 3 4 4 IN 1 NC OUT GND DESCRIPTION G Ground reference 1 P Input power-supply voltage -- 2 -- Not connected pin 3 5 P Output voltage Copyright (c) 2014-2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS7B6925-Q1 TPS7B6933-Q1 TPS7B6950-Q1 3 TPS7B6925-Q1, TPS7B6933-Q1, TPS7B6950-Q1 SLVSCJ8B - NOVEMBER 2014 - REVISED JANUARY 2015 www.ti.com 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) Unregulated input voltage Regulated output voltage MIN MAX UNIT IN (2) (3) (4) -0.3 45 V (2) (3) -0.3 7 V Operating junction temperature range, TJ -40 150 C Storage temperature, Tstg -65 150 C (1) (2) (3) (4) OUT Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to the GND terminal. Absolute negative voltage on these pins must not to go below -0.3 V. Absolute maximum voltage, withstands 45 V for 200 ms. 7.2 ESD Ratings VALUE Human body model (HBM), per AEC Q100-002 (1) Electrostatic discharge V(ESD) (1) Charged device model (CDM), per AEC Q100-011 UNIT 2000 Other pins 500 Corner pins (4 pin: 1, 3, and 4; 5 pin: 1, 3, 4, and 5) 750 V AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification. 7.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN MAX VI Unregulated input voltage 4 40 V VO Output voltage 0 5.5 V F (1) CO Output capacitor requirements ESRCO Output ESR requirements (2) TJ Operating junction temperature range (1) (2) UNIT 2.2 100 0.001 2 -40 150 C The output capacitance range specified in this table is the effective value. Relevant ESR value at = 10 kHz. 7.4 Thermal Information THERMAL METRIC (1) (2) DCY DBV 4 PINS 5 PINS RJA Junction-to-ambient thermal resistance 64.2 210.4 RJC(top) Junction-to-case (top) thermal resistance 46.8 126.1 RJB Junction-to-board thermal resistance 13.3 38.4 JT Junction-to-top characterization parameter 6.3 16 JB Junction-to-board characterization parameter 13.2 37.5 (1) (2) 4 UNIT C/W The thermal data is based on the JEDEC standard high-K profile, JESD 51-7, 2s2p four layer board with 2-oz copper. The copper pad is soldered to the thermal land pattern. Also correct attachment procedure must be incorporated. For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright (c) 2014-2015, Texas Instruments Incorporated Product Folder Links: TPS7B6925-Q1 TPS7B6933-Q1 TPS7B6950-Q1 TPS7B6925-Q1, TPS7B6933-Q1, TPS7B6950-Q1 www.ti.com SLVSCJ8B - NOVEMBER 2014 - REVISED JANUARY 2015 7.5 Electrical Characteristics VIN = 14 V, 1 m < ESR < 2 , TJ = -40C to 150 C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY VOLTAGE AND CURRENT (IN) VI Input voltage Fixed 2.5-V output, IO = 1 mA 4 40 Fixed 3.3-V output, IO = 1 mA 4 40 5.5 40 Fixed 5-V output, IO = 1 mA Fixed 2.5-V and 3.3-V version, VI = 4 to 40 V, Fixed 5-V version, VI = 5.5 to 40 V, IO = 0.2 mA IQ Quiescent current VIN(UVLO) IN undervoltage detection 15 Ramp VI up until the output turns on 25 3.65 Ramp VI down until the output turns OFF 3 V A V REGULATED OUTPUT (OUT) VO Regulated output Fixed 2.5-V version, VI = 4 to 40 V, IO = 1 to 150 mA -3% 3% Fixed 3.3-V version, VI = 5 to 40 V, IO = 1 to 150 mA -3% 3% Fixed 5-V version, VI = 6.5 to 40 V, IO = 1 to 150 mA -3% 3% VO(VI) Line regulation VI = 6 to 40 V, VO, IO = 10 mA VO(IL) Load regulation IO = 1 to 150 mA, VO VDROP mV 20 mV Fixed 2.5-V version, VI - VO, IO = 50 mA 1.575 Fixed 2.5-V version, VI - VO, IO = 100 mA 1.575 Fixed 3.3-V version, VI - VO, IO = 50 mA Dropout voltage 10 V 799 Fixed 3.3-V version, VI - VO, IO = 100 mA 800 Fixed 5-V version, VI - VO, IO = 50 mA 220 400 Fixed 5-V version, VI - VO, IO = 100 mA 450 800 IO Output current VO in regulation IOCL Output current-limit OUT short to ground PSRR Power supply ripple rejection (1) Vrip = 0.5 Vpp, Load = 10 mA, = 100 Hz, CO = 2.2 F mV 0 150 mA 150 500 mA 60 dB 175 C 25 C OPERATING TEMPERATURE RANGE Tsd Junction shutdown temperature Thys Hysteresis of thermal shutdown (1) Design Information--Not tested, ensured by characterization. Copyright (c) 2014-2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS7B6925-Q1 TPS7B6933-Q1 TPS7B6950-Q1 5 TPS7B6925-Q1, TPS7B6933-Q1, TPS7B6950-Q1 SLVSCJ8B - NOVEMBER 2014 - REVISED JANUARY 2015 www.ti.com 7.6 Typical Characteristics 6 3.8 IO = 1 mA IO = 80 mA 5.6 3.6 5.4 3.5 5.2 5 4.8 4.6 3.4 3.3 3.2 3.1 4.4 3 4.2 2.9 4 -55 -25 5 35 65 95 Junction Temperature (qC) IO = 1 mA IO = 80 mA 3.7 Output Voltage (V) Output Voltage (V) 5.8 2.8 -55 125 -25 5 35 65 95 Junction Temperature (qC) D001 125 D011 VI = 14 V Figure 1. 5-V Output Voltage vs Junction Temperature Figure 2. 3.3-V Output Voltage vs Junction Temperature 3 6 IO = 1 mA IO = 80 mA 2.9 5 2.7 Output Voltage (V) Output Voltage (V) 2.8 2.6 2.5 2.4 2.3 2.2 4 3 2 1 2.1 2 -55 0 -25 5 35 65 95 Junction Temperature (qC) 125 0 5 10 D008 VI = 14 V 15 20 25 Supply Voltage (V) 30 35 40 D002 IO = 0 mA Figure 3. 2.5-V Output Voltage vs Junction Temperature Figure 4. 5-V Output Voltage vs Supply Voltage 3 4 3.5 2.5 Output Voltage (V) Output Voltage (V) 3 2.5 2 1.5 2 1.5 1 1 0.5 0.5 0 0 0 5 10 15 20 25 Supply Voltage (V) 30 35 40 D012 IO = 0 mA Figure 5. 3.3-V Output Voltage vs Supply Voltage 6 Submit Documentation Feedback 0 5 10 15 20 25 Supply Voltage (V) 30 35 40 D009 IO = 0 mA Figure 6. 2.5-V Output Voltage vs Supply Voltage Copyright (c) 2014-2015, Texas Instruments Incorporated Product Folder Links: TPS7B6925-Q1 TPS7B6933-Q1 TPS7B6950-Q1 TPS7B6925-Q1, TPS7B6933-Q1, TPS7B6950-Q1 www.ti.com SLVSCJ8B - NOVEMBER 2014 - REVISED JANUARY 2015 Typical Characteristics (continued) 160 30 40qC 25qC 125qC 25 120 Qiescent Current (PA) Qiescent Current (PA) 140 100 80 60 40 40qC 25qC 125qC 20 20 15 10 5 0 0 0 30 60 90 Output Current (mA) 120 150 0 5 10 D003 15 20 25 Supply Voltage (V) 30 35 40 D010 IO = 0.2 mA Figure 7. Quiescent Current vs Output Current Figure 8. Quiescent Current vs Supply Voltage 1100 80 Power Supply Rejection Ratio (dB) 1000 Dropout Voltage (mV) 900 800 700 600 500 400 300 200 40qC 25qC 125qC 100 0 0 30 60 90 Output Current (mA) 120 70 60 50 40 30 20 10 0 1E+1 150 1E+2 D004 1E+3 1E+4 1E+5 Frequency (Hz) IO = 100 mA CO = 2.2 F Figure 9. Dropout Voltage vs Output Current VI = 14 V 1E+7 5E+7 D005 TA = 25C Figure 10. Power Supply Rejection Ratio 100 90 80 80 70 Load Capacitance (F) Power Supply Rejection Ratio (dB) 1E+6 60 50 40 30 20 60 Stable Region 40 20 10 0 1E+1 2.2 1E+2 IO = 10 mA CO = 2.2 F 1E+3 1E+4 1E+5 Frequency (Hz) 1E+6 VI = 14 V 1E+7 5E+7 D006 0.5 1 1.5 ESR of Output Capacitance () 2 D007 TA = 25C Figure 11. Power Supply Rejection Ratio Copyright (c) 2014-2015, Texas Instruments Incorporated 0.001 Figure 12. ESR Stability vs Output Capacitance Submit Documentation Feedback Product Folder Links: TPS7B6925-Q1 TPS7B6933-Q1 TPS7B6950-Q1 7 TPS7B6925-Q1, TPS7B6933-Q1, TPS7B6950-Q1 SLVSCJ8B - NOVEMBER 2014 - REVISED JANUARY 2015 www.ti.com Typical Characteristics (continued) VO (AC) 100 mV/div VO (AC) 100 mV/div IO (DC) 50 mA/div IO (DC) 50 mA/div VI = 14 V VO = 5 V CO = 2.2 F 1 ms/div VI = 14 V VO = 3.3 V Figure 13. Load Transient (1 to 100 mA, 5 V) VO (AC) 100 mV/div IO (DC) 50 mA/div IO (DC) 50 mA/div CO = 2.2 F VI = 14 V VO = 5 V 1 ms/div 1 ms/div VO (AC) 100 mV/div IO (DC) 50 mA/div IO (DC) 50 mA/div VI = 14 V VO = 3.3 V CO = 2.2 F 1 ms/div Figure 17. Load Transient (1 to 150 mA, 3.3 V) 8 CO = 2.2 F Figure 16. Load Transient (1 to 150 mA, 5 V) Figure 15. Load Transient (1 to 100 mA, 2.5 V) VO (AC) 100 mV/div 1 ms/div Figure 14. Load Transient (1 to 100 mA, 3.3 V) VO (AC) 100 mV/div VI = 14 V VO = 2.5 V CO = 2.2 F Submit Documentation Feedback VI = 14 V VO = 2.5 V CO = 2.2 F 1 ms/div Figure 18. Load Transient (1 to 150 mA, 2.5 V) Copyright (c) 2014-2015, Texas Instruments Incorporated Product Folder Links: TPS7B6925-Q1 TPS7B6933-Q1 TPS7B6950-Q1 TPS7B6925-Q1, TPS7B6933-Q1, TPS7B6950-Q1 www.ti.com SLVSCJ8B - NOVEMBER 2014 - REVISED JANUARY 2015 Typical Characteristics (continued) VO 20 mV/div VO 20 mV/div VI 5 V/div VI 5 V/div VI = 9 to 16 V IO = 10 mA CO = 2.2 F VI = 9 to 16 V IO = 10 mA 1 ms/div CO = 2.2 F 1 ms/div Figure 20. Line Transient (VO = 3.3 V) Figure 19. Line Transient (VO = 5 V) VO 20 mV/div VI 5 V/div VI 5 V/div VO 2 V/div VI = 9 to 16 V IO = 10 mA CO = 2.2 F 1 ms/div CO = 2.2 F, 400 s/div Figure 21. Line Transient (VO = 2.5 V) Figure 22. 5-V Power Up VI 5 V/div VI 5 V/div VO 1 V/div VO 1 V/div CO = 2.2 F, 400 s/div CO = 2.2 F, 400 s/div Figure 23. 3.3-V Power Up Figure 24. 2.5-V Power Up Copyright (c) 2014-2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS7B6925-Q1 TPS7B6933-Q1 TPS7B6950-Q1 9 TPS7B6925-Q1, TPS7B6933-Q1, TPS7B6950-Q1 SLVSCJ8B - NOVEMBER 2014 - REVISED JANUARY 2015 www.ti.com 8 Detailed Description 8.1 Overview The TPS7B69xx-Q1 high-voltage linear regulator operates over a 4-V to 40-V input voltage range. The device has an output current capability of 150 mA and offers fixed output voltages of 2.5 V (TPS7B6925-Q1), 3.3 V (TPS7B6933-Q1) or 5 V (TPS7B6950-Q1). The device features a thermal shutdown and short-circuit protection to prevent damage during over-temperature and overcurrent conditions. 8.2 Functional Block Diagram IN OUT Overcurrent detection UVLO Regulator control Band gap Thermal shutdown + Vref GND 8.3 Feature Description 8.3.1 Input (IN) The IN pin is a high-voltage-tolerant pin. A capacitor with a value higher than 0.1 F is recommended to be connected close to this pin to better the transient performance. 8.3.2 Output (OUT) The OUT pin is the regulated output based on the required voltage. The output has current limitation. During the initial power up, the regulator has a soft start incorporated to control the initial current through the pass element and the output capacitor. In the event that the regulator drops out of regulation, the output tracks the input minus a drop based on the load current. When the input voltage drops below the UVLO threshold, the regulator shuts down until the input voltage recovers above the minimum startup level. 8.3.3 Output Capacitor Selection For stable operation over the full temperature range and with load currents up to 150 mA, use a capacitor with an effective value between 2.2 F and 100 F and ESR smaller than 2 . To better the load transient performance, an output capacitor, such as a ceramic capacitor with low ESR, is recommended. 8.3.4 Low-Voltage Tracking At low input voltages, the regulator drops out of regulation and the output voltage tracks input minus a voltage based on the load current (IL) and switch resistor. This tracking allows for a smaller input capacitor and can possibly eliminate the need for a boost converter during cold-crank conditions. 10 Submit Documentation Feedback Copyright (c) 2014-2015, Texas Instruments Incorporated Product Folder Links: TPS7B6925-Q1 TPS7B6933-Q1 TPS7B6950-Q1 TPS7B6925-Q1, TPS7B6933-Q1, TPS7B6950-Q1 www.ti.com SLVSCJ8B - NOVEMBER 2014 - REVISED JANUARY 2015 Feature Description (continued) 8.3.5 Thermal Shutdown The TPS7B69xx-Q1 family of devices incorporates a thermal-shutdown (TSD) circuit as a protection from overheating. For continuous normal operation, the junction temperature should not exceed the TSD trip point. If the junction temperature exceeds the TSD trip point, the output turns off. When the junction temperature falls below the TSD trip point minus the hysteresis of TSD, the output turns on again. This cycling limits the dissipation of the regulator, protecting it from damage as a result of overheating. The purpose of the design of the internal protection circuitry of the TPS7B69xx-Q1 family of devices is for protection against overload conditions, not as a replacement for proper heat-sinking. Continuously running the TPS7B69xx-Q1 family of devices into thermal shutdown degrades device reliability. 8.4 Device Functional Modes 8.4.1 Operation With VI Less Than 4 V The TPS7B69xx-Q1 family of devices operates with input voltages above 4 V. The maximum UVLO voltage is 3 V and the device operates at an input voltage above 4 V. The device can also operate at lower input voltages; no minimum UVLO voltage is specified. At input voltages below the actual UVLO, the device shuts down. 8.4.2 Operation With VI Greater Than 4 V When VI is greater than 4 V, if the input voltage is higher than VO plus the dropout voltage, the output voltage is equal to the set value. Otherwise, the output voltage is equal to VI minus the dropout voltage. Copyright (c) 2014-2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS7B6925-Q1 TPS7B6933-Q1 TPS7B6950-Q1 11 TPS7B6925-Q1, TPS7B6933-Q1, TPS7B6950-Q1 SLVSCJ8B - NOVEMBER 2014 - REVISED JANUARY 2015 www.ti.com 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI's customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information The TPS7B69xx-Q1 family of devices is a 150-mA low-dropout linear regulator designed for up to 40-V VI operation with only 15-A quiescent current at light loads. Use the PSpice transient model to evaluate the base function of the device. To download the PSpice transient model, go to the device product folder on www.TI.com. In addition to this model, specific evaluation modules (EVM) are available for these devices. For the EVM and the EVM user guide, go to the device product folder. 9.2 Typical Application Figure 25 shows the typical application circuit for the TPS7B69xx-Q1 family of devices. Based on the endapplication, different values of external components can be used. An application can require a larger output capacitor during fast load steps to achieve better load transient response. TI recommends a low-ESR ceramic capacitor with a dielectric of type X5R or X7R for better load transient response. TPS7B69xx-Q1 IN OUT VI Vbat VO 10 F Vreg 4.7 F GND Figure 25. Typical Application Schematic for TPS7B69xx-Q1 9.2.1 Design Requirements For this design example, use the parameters listed in Table 1. Table 1. Design Parameters DESIGN PARAMETER EXAMPLE VALUES Input voltage range 4 to 40 V Output voltage 2.5 V, 3.3 V, 5 V Output current rating 150 mA Output capacitor range 2.2 to 100 F Output capacitor ESR range 1 m to 2 9.2.2 Detailed Design Procedure To * * * 12 begin the design process, determine the following: Input voltage range Output Voltage Output current rating Submit Documentation Feedback Copyright (c) 2014-2015, Texas Instruments Incorporated Product Folder Links: TPS7B6925-Q1 TPS7B6933-Q1 TPS7B6950-Q1 TPS7B6925-Q1, TPS7B6933-Q1, TPS7B6950-Q1 www.ti.com SLVSCJ8B - NOVEMBER 2014 - REVISED JANUARY 2015 9.2.2.1 Input Capacitor The device requires an input decoupling capacitor, the value of which depends on the application. The typical recommend value for the decoupling capacitor is higher than 0.1 F. The voltage rating must be greater than the maximum input voltage. 9.2.2.2 Output Capacitor The device requires an output capacitor to stabilize the output voltage. The output capacitor value should be between 2.2 F and 100 F. The ESR value range should be between 1 m and 2 . TI recommends a ceramic capacitor with low ESR to improve the load transient response. 9.2.2.3 Power Dissipation and Thermal Considerations Use Equation 1 to calculate the power dissipated in the device. PD = IO x (VI - VO) + IQ x VI where * * * * PD = continuous power dissipation IO = output current VI = input voltage VO = output voltage (1) Because IQ IO, the term IQ x VI in Equation 1 can be ignored. For a device under operation at a given ambient air temperature (TA), use Equation 2 to calculate the junction temperature (TJ). TJ = TA + (ZJA x PD) where * ZJA = junction-to-ambient air thermal impedance (2) Use Equation 3 to calculate the rise in junction temperature because of power dissipation. T = TJ - TA = (ZJA x PD) (3) For a given maximum junction temperature (TJmax), use Equation 4 to calculate the maximum ambient air temperature (TAmax) at which the device can operate. TAmax = TJmax - (ZJA x PD) (4) 9.2.3 Application Curve VI 5 V/div VO 2 V/div CO = 2.2 F, 400 s/div Figure 26. Power Up (5 V) Copyright (c) 2014-2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS7B6925-Q1 TPS7B6933-Q1 TPS7B6950-Q1 13 TPS7B6925-Q1, TPS7B6933-Q1, TPS7B6950-Q1 SLVSCJ8B - NOVEMBER 2014 - REVISED JANUARY 2015 www.ti.com 10 Power Supply Recommendations The device is designed to operate from an input-voltage supply range between 4 V and 40 V. This input supply must be well regulated. If the input supply is located more than a few inches from the TPS7B69xx-Q1 device, TI recommends adding an electrolytic capacitor with a value of 10 F and a ceramic bypass capacitor at the input. 11 Layout 11.1 Layout Guidelines For the layout of TPS7B69xx-Q1 family of devices, place the input and output capacitors close to the devices as shown in Figure 27 and Figure 28. To enhance the thermal performance, TI recommends surrounding the device with some vias. Minimize equivalent series inductance (ESL) and ESR to maximize performance and ensure stability. Place every capacitor as close as possible to the device and on the same side of the PCB as the regulator. Do not place any of the capacitors on the opposite side of the PCB from where the regulator is installed. TI strongly discourages the use of long traces because they can impact system performance negatively and even cause instability. If possible, and to ensure the maximum performance specified in this product data sheet, use the same layout pattern used for the TPS7B69xx-Q1 evaluation board. 11.2 Layout Example GND 4 1 2 3 IN GND OUT Figure 27. Layout Example for SOT-223 Package 14 Submit Documentation Feedback Copyright (c) 2014-2015, Texas Instruments Incorporated Product Folder Links: TPS7B6925-Q1 TPS7B6933-Q1 TPS7B6950-Q1 TPS7B6925-Q1, TPS7B6933-Q1, TPS7B6950-Q1 www.ti.com SLVSCJ8B - NOVEMBER 2014 - REVISED JANUARY 2015 Layout Example (continued) 1 IN 5 OUT 2 NC GND 3 4 GND Figure 28. Layout Example for SOT-23 Package 12 Device and Documentation Support 12.1 Documentation Support 12.1.1 Related Documentation For related documentation see the following: TPS7B6950EVM User's Guide, SLVUAC0. 12.2 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 2. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY TPS7B6925-Q1 Click here Click here Click here Click here Click here TPS7B6933-Q1 Click here Click here Click here Click here Click here TPS7B6950-Q1 Click here Click here Click here Click here Click here 12.3 Trademarks All trademarks are the property of their respective owners. 12.4 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 12.5 Glossary SLYZ022 -- TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Copyright (c) 2014-2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS7B6925-Q1 TPS7B6933-Q1 TPS7B6950-Q1 15 PACKAGE OPTION ADDENDUM www.ti.com 16-Jul-2015 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) TPS7B6925QDBVRQ1 ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR -40 to 125 ZBE2 TPS7B6925QDCYRQ1 ACTIVE SOT-223 DCY 4 2500 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 125 7B6925 TPS7B6933QDBVRQ1 ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR -40 to 125 ZBF2 TPS7B6933QDCYRQ1 ACTIVE SOT-223 DCY 4 2500 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 125 7B6933 TPS7B6950QDBVRQ1 ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR -40 to 125 ZAZ2 TPS7B6950QDCYRQ1 ACTIVE SOT-223 DCY 4 2500 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 125 7B6950 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 16-Jul-2015 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 16-Jul-2015 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) TPS7B6925QDBVRQ1 SOT-23 DBV 5 3000 178.0 9.0 TPS7B6925QDCYRQ1 SOT-223 DCY 4 2500 330.0 TPS7B6933QDBVRQ1 SOT-23 DBV 5 3000 178.0 TPS7B6933QDCYRQ1 SOT-223 DCY 4 2500 TPS7B6950QDBVRQ1 SOT-23 DBV 5 TPS7B6950QDCYRQ1 SOT-223 DCY 4 3.3 3.2 1.4 4.0 8.0 Q3 12.4 7.05 7.4 1.9 8.0 12.0 Q3 9.0 3.3 3.2 1.4 4.0 8.0 Q3 330.0 12.4 7.05 7.4 1.9 8.0 12.0 Q3 3000 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3 2500 330.0 12.4 7.05 7.4 1.9 8.0 12.0 Q3 Pack Materials-Page 1 W Pin1 (mm) Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 16-Jul-2015 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS7B6925QDBVRQ1 SOT-23 DBV 5 3000 190.0 190.0 30.0 TPS7B6925QDCYRQ1 SOT-223 DCY 4 2500 340.0 340.0 38.0 TPS7B6933QDBVRQ1 SOT-23 DBV 5 3000 190.0 190.0 30.0 TPS7B6933QDCYRQ1 SOT-223 DCY 4 2500 340.0 340.0 38.0 TPS7B6950QDBVRQ1 SOT-23 DBV 5 3000 180.0 180.0 18.0 TPS7B6950QDCYRQ1 SOT-223 DCY 4 2500 340.0 340.0 38.0 Pack Materials-Page 2 MECHANICAL DATA MPDS094A - APRIL 2001 - REVISED JUNE 2002 DCY (R-PDSO-G4) PLASTIC SMALL-OUTLINE 6,70 (0.264) 6,30 (0.248) 3,10 (0.122) 2,90 (0.114) 4 0,10 (0.004) M 3,70 (0.146) 3,30 (0.130) 7,30 (0.287) 6,70 (0.264) Gauge Plane 1 2 0,84 (0.033) 0,66 (0.026) 2,30 (0.091) 4,60 (0.181) 1,80 (0.071) MAX 3 0-10 0,10 (0.004) M 0,25 (0.010) 0,75 (0.030) MIN 1,70 (0.067) 1,50 (0.059) 0,35 (0.014) 0,23 (0.009) Seating Plane 0,08 (0.003) 0,10 (0.0040) 0,02 (0.0008) 4202506/B 06/2002 NOTES: A. B. C. D. All linear dimensions are in millimeters (inches). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion. Falls within JEDEC TO-261 Variation AA. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as "components") are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. 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