SCHS228B - SEPTEMBER 1998 - REVISED MARCH 2004 D AC Types Feature 1.5-V to 5.5-V Operation D D D D D D D E OR M PACKAGE (TOP VIEW) and Balanced Noise Immunity at 30% of the Supply Voltage Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption Greater Noise Immunity Than Standard Inverters Operates With Much Slower Than Standard Input Rise and Fall Slew Rates Balanced Propagation Delays 24-mA Output Drive Current - Fanout to 15 F Devices SCR Latchup-Resistant CMOS Process and Circuit Design Exceeds 2-kV ESD Protection Per MIL-STD-883, Method 3015 1A 1Y 2A 2Y 3A 3Y GND 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 6A 6Y 5A 5Y 4A 4Y description/ordering information The CD74AC14 contains six independent inverters. This device performs the Boolean function Y = A. Each circuit functions as an independent inverter, but because of the Schmitt action, the inverters have different input threshold levels for positive-going (VT+) and negative-going (VT-) signals. ORDERING INFORMATION PDIP - E -55C 125C -55 C to 125 C ORDERABLE PART NUMBER PACKAGE TA SOIC - M Tube CD74AC14E Tube CD74AC14M Tape and reel CD74AC14M96 TOP-SIDE MARKING CD74AC14E AC14M Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE (each inverter) INPUT A OUTPUT Y H L L H logic diagram, each inverter (positive logic) A Y Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2004, Texas Instruments Incorporated !" #!$% &"' &! #" #" (" " ") !" && *+' &! #", &" ""%+ %!&" ", %% #""' POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 SCHS228B - SEPTEMBER 1998 - REVISED MARCH 2004 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 6 V Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA Package thermal impedance, JA (see Note 2): E package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80C/W M package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 3) TA = 25C MIN -55C to 125C MAX MIN -40C to 85C MAX MIN UNIT MAX VCC VI Supply voltage 1.5 5.5 1.5 5.5 1.5 5.5 V Input voltage 0 0 0 VCC VCC V Output voltage VCC VCC 0 VO IOH VCC VCC 0 0 V High-level output current VCC = 4.5 V to 5.5 V -24 -24 -24 mA IOL Low-level output current VCC = 4.5 V to 5.5 V 24 24 24 mA NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 2 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SCHS228B - SEPTEMBER 1998 - REVISED MARCH 2004 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS -55C to 125C TA = 25C VCC -40C to 85C UNIT MIN MAX MIN MAX MIN MAX VT+ Positive-going threshold 5V 2.6 3.4 2.6 3.4 2.6 3.4 V VT- Negative-going threshold 5V 1.6 2.4 1.6 2.4 1.6 2.4 V VT Hysteresis (VT+ - VT-) 5V 0.5 0.5 0.5 1.5 V 1.4 1.4 1.4 3V 2.9 2.9 2.9 4.5 V 4.4 4.4 4.4 IOH = -50 A VOH VI = VT+ IOH = -4 mA IOH = -24 mA IOH = -50 mA 3V 2.58 2.4 2.48 4.5 V 3.94 3.7 3.8 IOH = -75 mA 5.5 V IOL = 50 A VOL II ICC VI = VT- VI = VCC or GND VI = VCC or GND, 5.5 V V V 3.85 3.85 1.5 V 0.1 0.1 0.1 3V 0.1 0.1 0.1 4.5 V 0.1 0.1 0.1 IOL = 12 mA IOL = 24 mA IOL = 50 mA 3V 0.36 0.5 0.44 4.5 V 0.36 0.5 0.44 IOL = 75 mA 5.5 V IO = 0 5.5 V V 1.65 1.65 5.5 V 0.1 1 1 A 5.5 V 4 80 40 A 10 10 10 Ci pF Test one output at a time, not exceeding 1-second duration. Measurement is made by forcing indicated current and measuring voltage to minimize power dissipation. Test verifies a minimum 50- transmission-line drive capability at 85C and 75- transmission-line drive capability at 125C. switching characteristics over recommended operating free-air temperature range, VCC = 5 V 0.5 V, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER tPLH tPHL FROM (INPUT) TO (OUTPUT) A Y -55C TO 125C -40C TO 85C MIN MAX MIN MAX 2.6 10.5 2.7 9.5 2.6 10.5 2.7 9.5 UNIT ns operating characteristics, VCC = 5 V, TA = 25C PARAMETER Cpd TYP Power dissipation capacitance 45 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 UNIT pF 3 SCHS228B - SEPTEMBER 1998 - REVISED MARCH 2004 PARAMETER MEASUREMENT INFORMATION S1 R1 = 500 From Output Under Test 2 x VCC Open GND CL = 50 pF (see Note A) R2 = 500 TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 2 x VCC GND tw VCC When VCC = 1.5 V, R1 = R2 = 1 k Input 50% VCC 50% VCC 0V LOAD CIRCUIT VOLTAGE WAVEFORMS PULSE DURATION CLR Input VCC Reference Input VCC 50% VCC 50% VCC 0V 0V tsu trec Data 50% Input 10% VCC 50% VCC CLK 90% VOLTAGE WAVEFORMS RECOVERY TIME tf VCC 50% VCC 50% VCC tPLH tPHL 50% 10% 90% 90% tr tPHL Out-of-Phase Output VCC 50% VCC 10% 0 V VOLTAGE WAVEFORMS SETUP AND HOLD AND INPUT RISE AND FALL TIMES 0V In-Phase Output 90% tr 0V Input th 90% VOH 50% VCC 10% VOL tf Output Waveform 1 S1 at 2 x VCC (see Note B) tPLH 50% VCC 10% tf 50% 10% 90% tr VOH VOL VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES VCC Output Control 50% VCC 50% VCC 0V tPLZ tPZL 50% VCC tPHZ tPZH Output Waveform 2 S1 at GND (see Note B) VCC 20% VCC VOL 50% VCC VOH 80% VCC 0 V VOLTAGE WAVEFORMS OUTPUT ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and test-fixture capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO = 50 , tr = 3 ns, tf = 3 ns. Phase relationships between waveforms are arbitrary. D. For clock inputs, fmax is measured with the input duty cycle at 50%. E. The outputs are measured one at a time, with one input transition per measurement. F. tPLH and tPHL are the same as tpd. G. tPZL and tPZH are the same as ten. H. tPLZ and tPHZ are the same as tdis. Figure 1. Load Circuit and Voltage Waveforms 4 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 23-Apr-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty CD74AC14E ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type CD74AC14EE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type CD74AC14M ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74AC14M96 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74AC14M96E4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74AC14M96G4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74AC14ME4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74AC14MG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device CD74AC14M96 Package Package Pins Type Drawing SOIC D 14 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 16.4 Pack Materials-Page 1 6.5 B0 (mm) K0 (mm) P1 (mm) 9.0 2.1 8.0 W Pin1 (mm) Quadrant 16.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CD74AC14M96 SOIC D 14 2500 367.0 367.0 38.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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