DALLAS SEMICONDUCTOR CORP DALLAS SEMICONDUCTOR Bes | eee one at Sere ed 39E D MM 2614150 0003405 & MMDAL 0S1230Y/AB Pdh-23-39 DS1230Y/AB 256K Nonvolatile SRAM FEATURES e Data retention in the absence of V,, e Data Is automatically protected during the de crease In V,, at power loss Directly replaces 32K x 8 volatile static RAM or EEPROM e Unlimited write cycles e Low-power CMOS Over 10 years of data retention Standard 28-pin JEDEC pinout e Avaliable In 70ns, 100ns, 120ns, 150ns, or 200ns read access times Read cycle time equals write cycle time @ Lithlum energy source Is electrically discon- nected to retain freshness until power Is ap- plled for the first time @ Optional +5% and 410% operating range DESCRIPTION The DS1230AB and DS1230Y 256K Non- volatile SRAMs are 262,144-bit, fully static, nonvolatile RAMs organized as 32,768 words by 8 bits. Each NV SRAM has a self- contained lithlum energy source and control clrcultry that constantly monitors Veo for an out-of-tolerance condition. When such a condition occurs, the lithium energy source Is automatically switched on and write protec- Vv WE\ Ai3 Aa AQ 23 B Ai OE\ Ai0 CE\ par DQ6 pas 16 J) pa is Zioas fr 8 8 [SSSI | & 8 SS ES AY 2B Ba P A SS BS _ m2 SY PIN NAMES (\ Denotes Condition Low) AQ -A14 - Address Inputs CE\ - Chip Enable GND - Ground DQ0-DQ7 - Data In/Data Out Voc - Power (+5V) WE\ - Write Enable OEF\ - Output Enable tion is unconditionally enabled to prevent garbled data. The NV SRAM can be used In - place of existing 32K x 8 static RAMs directly conforming to the popular bytewide 28-pin DIP Standard. The DS1230AB also matches the pinout of the 28256 EEPROM, allowing direct substitution while enhancing performance. There Is no filmit on the number of write cycles that can be executed and no additional support circuitry Is required for microprocessor Inter- face, 070390 1/7 285READ MODE The DS1230AB and DS1230Y execute a read cycle whenever WE\ (Write Enable) Is inactive (high) and CE\ (Chip Enable) Is active (low). The unique address specifled by the 15 address inputs (A,-A,,) defines which of the 32,768 bytes of data Is to be accessed. Valid data will be avallable to the elght data output drivers. within taco (Access Time) after the last address Input signal is stable, providing that CE\ and OE\ (Output Enable) access times are also satisfled. If OE\ and CE\ access times are not satisfled, then data access must be measured from the later occurring signal (CE\ or OE\) and the limit- ing parameter Is either t,, for CE\ or t,, for OE\ rather than address access. WRITE MODE The DS1230AB and DS1230Y are in the write mode whenever the WE\ and CE\ signals are In the active (low) state after address Inputs are stable. The latter occurring falling edge of CE\or WE\ will determine the start of the write cycle. The write cycle Is terminated by the earller rising edge of CE\ or WE\. All address Inputs must be kept valid throughout the write cycle, WE\ must return to the high state for a minimum recovery time (t,,,) before another cycle can be Initiated. The OE\ control signal should be kept Inactive (high) during write cycles to avold bus conten- tlon. However, If the output bus has been enabled (CE\ and OE\ active) then WE\ will disable the outputs In topy from its falling edge. DATA RETENTION MODE The DS1230AB provides full functional capabll- ity for V,, greater than 4.75 volts and write protects at 4.5 volts. The DS1230Y provides full functional capability for V,, greater than 4.5 volts and write protects by 4.25 volts. Data is DALLAS SEMICONDUCTOR CORP 395E D MM 2614130 OO0340b T MEDAL DS12307/AB T- 46-23-37 maintained in the absence of V,,, without any additional support circuitry. The nonvolatile static RAM constantly monitors V,,. Should the supply voltage decay, the RAM automatically write protects Itself. All Inputs to the RAM become don't care and all outputs are high Impedance. As V,, falls below approximately 3.0 volts, the power switching circuit connects the lithium energy source to RAM to retain data. During power-up, when V,, rises above approxi- mately 3.0 volts, the power switching circuit connects external V,,. to the RAM and discon- nects the lithium energy source, Normal RAM operation can resume after V,, exceeds 4.5 volts for DS1230Y and 4.75 volts for the DS1230AB. FRESHNESS SEAL AND BATTERY REDUNDANCY The DS1230Y and DS1230AB are shipped from Dallas Semiconductor with the lithium energy source disconnected, guaranteeing full energy capacity. When V,, Is first applied at a level of greater than 4.25 volts, the lithlum energy source Is enabled for battery back-up operation. Battery redundancy Is also provided to ensure rellability. The DS1230Y and DS1230AB contain two lithium energy calls separated by an intemal isolation switch. During battery backup time the cell with the highest voltage is selected for use. If one battery fails, the other battery automati- cally takes over. The switch between batteries is transparent to the user, 070390 2/7 286DALLAS SEMICONDUCTOR CORP 396 D MM 2614130 0003407 1 MMDAL OS1230Y/AB PIO 23-39 ABSOLUTE MAXIMUM RATINGS* Voltage on any Pin Relative to Ground -0.3V to +7.0V Operating Temperature 0C to 70C Storage Temperature -40C to +70C Soldering Temperature 260C for 10 sec. * This Is a stress rating only and functional operation of the device at these or any other conditions above those Indicated in the operation sections of this specification !s not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect rellability. RECOMMENDED DC OPERATING CONDITIONS (0C to 70C) PARAMETER SYMBOL MIN TYP MAX} UNITS NOTES DS1230AB Power Supply Voltage Voc 4.75 5.0 5.25| V DS1230Y Power | ) Supply Voltage Voc 4.5 5.0 5.5 V Input Logic 7 Vin 2.2 Voo | V input Logic 0 Vii 0.0 08] V _ (0%C to 70C; V,, = BV a 10% for DS1230Y) DC ELECTRICAL CHARACTERISTICS (0C to 70C; V., = 5V +5%forDS1230AB) PARAMETER SYMBOL |. MIN TYP | MAX UNITS | NOTES] Input Leakage Cutrent A -1.0 +1.0 | UA VO Leakage Current CE\ > Vis $ Voc lo 1.0 +10 | uA Output Current @24V | 1, | -1.0 mA Output Current @04V- | 1, 2.0 mA Standby Current CEISZ2V) Toc, 5.0 | 10 mA Standby Current , CE\=Vo, + 0.5V loose 3.0 | 5.0 | mA Operating Current toyo = 200ns lecor 85 mA Write Protection a Voltage (DS1230AB) Vie 45 | 4.62] 475] Vv Write Protection Voltage (DS1230Y) Vip 4.25 | 4.37] 4.5 V DC Test Conditions: Outputs open; all voltages are referenced to ground. CAPACITANCE (t,=25C) PARAMETER SYMBOL TYP | MAX] UNITS NOTES Input Capacitance Cn 5 10 pF Input/Output Capacitance Cro | 5 | 10 pF 070390 4/7 287DALLAS SEMICONDUCTOR CORP 34E D WM 26134230 0003408 3 MMDAL T- Ly) b . 2 3 -3 DS1230Y/AB AC ELECTRICAL CHARACTERISTICS (0C to 70C; V,.=5.0V + 10% for DS1230Y) (0C to 70C; V_,=5.0V + 5% for DS1230AB) DSt230y-70 BS12a0y-100 DSi2d07-120 | DStesov-160 | DS1ad0V-200 1280AB-70 1230A8-100 1230AB-120 1230AB-150 0S1230A8-200 PARAMETER SYM| MIN|MAX{ MIN | MAX] MIN. | MAX | MIN | MAX MIN | MAX [U [N Read Cycle . Time tao | 70 100 120 150 200 ns Accass Time theo 70 ~ | 100 120 150 200 [ns OE\ to Output Valid tor 35 50 60 70 100 [ns CE\ to Output Valid too 70]. .. | 100 120 150 200 jns OE\ or CE\ to Output Active toon | 5 5 5 5 5 ns] 5 Output High Z from . Deselection top 25 35 40 70 100 jns| 5 Output Hold from Address Change tor | 5 5 5 5 5 ns Write Cycle Time two | 70 100 120 150ng 200 ns Write Pulse / Width twe | 55 75 90 100 100 ns} 3 Address Setup Time ty | o 0 0 o | 0 ns Write Recovery Time twa 20 20 20 20 20 ns Output _ High Z from WE\ toow 25 35 _ 40 70 80 Ins} 5 Output , Active from WE\ tow | 5 5 5 5 5 ns] 5 Data Setup Time tog | 30 40 50 60 80 nsj 4 Data Hold ~{ me from WE\ toy | 20 20 20 20 20 ns} 4 AC Test Conditions Output Load: 100 pF + 1TTL Gate Input Pulse Levels; 0-3.0V Timing Measurement Reference Levels input: 1.5V Output: 1.5V Input Pulse Rise and Fail Times: 5ns "970390 47 288DALLAS SEMICONDUCTOR CORP 35E D MM 2614130 0003409 5 MHDAL DS1230Y/AB READ CYCLE (1) i~ 76-23-39 Addresses cn O8\ Dour OUTPUT Vo. DATA VALID Vo. WRITE CYCLE 1 (2), (6), (7) Addresses MH Dw DATA IN STABLE WRITE CYCLE 2 (2), (8) Mi two Addresses ; ; XL / yi pL oR we jah cay MH vw MLA MH Mu Mn we NNNNSNYS So WLIO coe } ro toow Pour NZSCAY i. os fon : fn MH IH Bn DATA IN STABLE Ve A 070390 /7DALLAS SEMICONDUCTOR CORP 35E D POWER-DOWN/POWER-UP CONDITION Yoo stay 4g9y we NE ee ee - Y___ - DS1230AB 4.75V / | EM 2634130 OO03410 1 BMDAL DS1230V/AB LEAKAGE CURRENT A IL SUPPLIES ron Uf / UTHIUM CELL | DATA RETENTION TIME tm / / / f tor POWER-DOWN/POWER-UP TIMING SYM | PARAMETER ; MIN {| MAX | UNITS | NOTES ten CE\ at V,,, before Power-Down 0 us te Veg Slew trom 4.75V to OV . (CE\ at V,.) 300 us DS1230AB t Veo Stew from 4.5V to OV (CE\ at V,.,) 300 us DS1230Y ta Voc Slew from OV to 4,75V (CE\ at Vi) 0 us | DS1230AB ta Veg Slew from OV to 4.5V (CE\ at V,,) 0 us DS1230Y taco | CE\at V,, after Power-Up 2 125 | ms (t,=25C) SYM | PARAMETER MIN | MAX | UNITS | NOTES toa Expected Data Retention Time 10 years .|9 WARNING: . Under no clrcunstance are negative undershoots, of any amplitude, allowed when device ls In battery backup mode, 070380 6/7DALLAS SEMICONDUCTOR CORP 395E D 2644430 0003411 3 MDAL DS1230Y/AB NOTES T= 46 -23-39 1. WEV\Is high for a read cyclo. 2. OE\=V,,orV,,. IfOE\= V,, during write cycle, the output buffers remain in a high Impedance state. 3. twp Is specified as the logical AND of CE\ and WE\, twp Is measured from the latter of CE\ or WE\ going low to the earlier of CE\ or WE\ going high. 4. to. tpg are measured from the earlier of CE\ or WE\ going high. 5, These parameters are sampled with a 5 pF load and are not 100% tested. 6. If the CE\ low transition occurs simultaneously with or later than the WE\ low transition In Write Cycle 1, the output buffers remain in a high impedance state during this period. 7. lfthe CE\ high transition occurs prior to or simultaneously with the WE\ high transition, the output buffers remain In a high Impedance state during this period. 8. If WE\is low or the WE\ low transition occurs prior to or simultaneously with the CE\ low trans!- tion, the output buffers remaln in a high Impedance state during this period, 9, Each DS1230 has a bullt-in switch that disconnects the lithium source until V,, Is first applied by the user. The expected tp, Is defined as accumulative time In the absence of V., stating from the time power Is first applied by the user. 070390 7/7 291