A4407KLPTR-T - Allegro MicroSystems Europe Ltd.

Description

The A4407 is an automotive power management IC that uses a

2.2 MHz constant on-time (COT) buck pre-regulator to supply

a 5 V linear regulator, a 5 V tracking/protected linear regulator,

a 3.3 V linear FET controller/driver, and a 1.2 V/1.5 V/1.8 V

linear FET controller/driver. The A4407 provides a pin to set

the master reference for the 5 V tracking regulator to either the

3.3 V or the 5 V output. The on-time of the buck is internally

adjusted as a function of VIN to maintain the 2.2 MHz switching

frequency. Efficient operation is achieved by using the buck

pre-regulator to drop the input voltage before supplying the

linear regulators. Designed to supply CAN and microprocessor

power supplies in high temperature environments, the A4407

is ideal for under hood applications.

The switching regulator is designed to operate at a nominal

switching frequency of 2.2 MHz. The high switching frequency

enables the customer to select low value inductors and ceramic

capacitors while avoiding EMI in the AM frequency band.

Protection features include: undervoltage lockout, pulse-by-

pulse current limit, LX short circuit protection, and thermal

shutdown. In case of a shorted load all linear regulators feature

foldback overcurrent protection. In addition, the V5P output is

protected from a short-to-battery event. The A4407 features both

a logic level and a high-voltage (current and voltage limited)

enable input. The A4407 also features a power-on-reset (NPOR)

output with adjustable delay for microprocessor control.

The A4407 is supplied in a low profile (1.1 mm) 24-lead TSSOP

package with exposed pad for enhanced thermal dissipation

(suffix LP). The package is lead (Pb) free with 100% matte-tin

leadframe plating.

A4407-DS, Rev. 3

Features and Benefits

• AEC Q100 Grade 0 qualified

• Internal buck pre-regulator followed by LDO outputs

• 5.5 to 36 V VIN operating range (50 V maximum);

for start/stop, cold crank, and load dump requirements

• Constant on-time (COT) buck pre-regulator

• Valley current sensing achieves shortest buck on-times

• 2.2 MHz (VIN

- adjusted) switching frequency

• 5 V internal low-dropout tracking linear regulator with

foldback short circuit and short-to-battery protections

• 5 V internal low-dropout linear regulator with foldback

short circuit protection

• 3.3 V external FET controller/driver with programmable

current limit and foldback short circuit protection

• 1.2 V/1.5 V/1.8 V external FET controller/driver with

programmable current limit and foldback protection

• Power-on reset (NPOR) with adjustable rising delay

• Logic enable input (ENB) for microprocessor control

• Ignition enable input (ENBAT) for remote startup

• Ignition status indicator (ENBATS) output

• Buck pulse-by-pulse overcurrent protection

• Buck LX short circuit protection (latched)

• Missing asynchronous diode protection (latched)

• UVLO for VIN, charge pump, and the internal rail

• Thermal shutdown protection

• −40ºC to 150ºC junction temperature range

2.2 MHz Constant On-T ime Buck Regulator

W ith Two External and T wo Internal Linear Regulators

Package: 24-pin TSSOP with exposed

thermal pad (suffix LP)

Simplified Functional Block Diagram

Not to scale

A4407

Applications:

Automotive Control Modules, such as:

• Electronic power steering (EPS)

• Transmission control (TCU)

• Antilock braking (ABS)

• Emissions control

External

Controller

with Foldback

(1V 2)

Charge

Pump

A4407

5. 45 V

(VREG)

PWM

Control

(V5)

5 V LDO

with Foldback

Thermal

Shutdown

(TSD)

Soft Start

5 V LDO

(V5P)

with Tracking,

Foldback, and

Short to V

BAT

Protection

NPOR

Output

Tracking

Control

2:1 M UX

3V3

(3V3)

External

Controller

with Foldback

2.2 MHz Constant On-T ime Buck Regulator

W ith Two External and T wo Internal Linear Regulators

A4407

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Absolute Maximum Ratings*

Characteristic Symbol Notes Rating Unit

VIN Pin 0.3 to 50 V

LX Pin VLX

–0.3 to 50 V

t < 250 ns –1.5 V

VCP, CP1, CP2 Pins 0.3 to 60 V

ISEN– Pin 0.5 to 1 V

ISEN+ Pin 0.5 to 0.5 V

ENBAT Pin

The ENBAT pin is internally clamped to approximately 8.5 V

due to an ESD protection device. 0.3 V

50 to 50 mA

VREG Pin 0.3 to 8 V

G1V2 and G3V3 Pins These pins are internally clamped by an ESD protection

device. Clamp voltages range from 10 V (min) to 15 V (max). 0.3 V

CL1V2 and CL3V3 Pins 0.3 to 10 V

V5P Pin –0.3 to VIN+0.5 V

V5 Pin 0.3 to 7 V

TON Pin 0.3 to 50 V

NPOR, CPOR, ENB, ENBATS,

TRACK, 1V2, and 3V3 Pins 0.3 to 7 V

Operating Ambient Temperature TARange K 40 to 135 ºC

Junction Temperature TJ40 to 150 ºC

Storage Temperature Range Tstg 40 to 150 ºC

*Absolute Maximum Ratings are limiting values that should not be exceeded under worst case operating conditions or damage may occur. Stresses

beyond those listed in this table may cause permanent damage to the device. The Absolute Maximum ratings are stress ratings only, and functional

operation of the device at these or any other conditions beyond those indicated in the Electrical Characteristics table is not implied. Exposure to

Absolute-Maximum–rated conditions for extended periods may affect device reliability.

Selection Guide

Part Number Operating Ambient

Temperature Range

TA, (°C) Package Packing* Leadframe

Plating

A4407KLPTR-T –40 to 135 24-pin TSSOP with

exposed thermal pad

4000 pieces per

13-in. reel 100% matte tin

*Contact Allegro™ for additional packing options.

Thermal Characteristics may require derating at maximum conditions, see application information

Characteristic Symbol Test Conditions* Value Unit

Package Thermal Resistance RθJA On 4-layer PCB based on JEDEC standard 28 ºC/W

*Additional thermal information available on the Allegro™ website.

2.2 MHz Constant On-T ime Buck Regulator

W ith Two External and T wo Internal Linear Regulators

A4407

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Functional Block Diagram

VIN

TON

CP2

CP1

VCP

F0.1 FF

CIN1 CIN2

F

FF

ISENSE

F

k

k8.5 V

Microcontroller

5 V Protected

Enable

k

RTON

H

(Max)

F

COUT1

Soft

Start

Power

Control

Foldback

External

Controller

with

Foldback

External

Controller

with

Foldback

Fault Logic

and

Timing

Tracking

COUT2

RSENSE

DBUCK

DIN

F

FFF

VOUT3V3

Q3V3

Q1V2

COUTV5

COUTV5P

COUT3V3

COUT1V2

VOUT1V2

FF

k

Microcontroller

Reset

VOUTV5

VOUTV5P

VIGN

B240A

VIN(Pin2)

B240A

ProtecƟon diodes D1 and D2 are required when the V5P pin is driving a wiring harness (or excessively long

PCB trace) where parasiƟc inductance will cause the voltage at the V5P to momentarily transiƟon above

VIN or below ground during a fault condiƟon.

2.2 MHz Constant On-T ime Buck Regulator

W ith Two External and T wo Internal Linear Regulators

A4407

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Pin-out Diagram

CP2

CP1

ISEN+

ISEN–

VREG

CL3V3

G3V3

3V3

CL1V2

G1V2

1V2

VCP

VIN

GND

TON

ENBAT

ENB

ENBATS

NPOR

CPOR

TRACK

V5P

PAD

Terminal List Table

Number Name Function

1 VCP Charge pump reservoir capacitor

2 VIN Input voltage

3 GND Ground

4 TON Buck regulator on-time programming pin

5 ENBAT Ignition enable input from the key/switch via a 1 k resistor

6 ENB Logic enable input from the microcontroller

7 ENBATS Open drain ignition status output

8 NPOR Open-drain fault indication output; active low

9 CPOR NPOR delay programming pin

10 TRACK Sets the V5P tracking to either the 3V3 or V5 linear regulator

11 V5 5 V regulator output

12 V5P 5 V tracking/protected regulator output

13 1V2 1.2 V/1.5 V/1.8 V regulator output

14 G1V2 Gate driver to the external MOSFET for 1.2 V/1.5 V/1.8 V regulation

15 CL1V2 1.2 V/1.5 V/1.8 V current sense/limit input

16 3V3 3.3 V regulator output

17 G3V3 Gate driver to the external MOSFET for 3.3 V regulation

18 CL3V3 3.3 V current sense/limit input

19 VREG Buck regulator DC output and input to the 3.3 V external regulator

20 ISEN–Buck negative current sense pin, sense resistor and diode node

21 ISEN+Buck positive current sense pin, sense resistor/ground node

22 LX Buck regulator switching node

23 CP1 Charge pump capacitor connection

24 CP2 Charge pump capacitor connection

– PAD Exposed thermal pad for enhanced heat dissipation

2.2 MHz Constant On-T ime Buck Regulator

W ith Two External and T wo Internal Linear Regulators

A4407

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

General Specifications

Functional Input Voltage VIN(FUNC) A4407 functional, parameters not guaranteed 5.5 46 V

Operating Input Voltage VIN(OP) 5.5 13.5 36 V

Supply Quiescent Current1

VIN = 13.5 V, VIGN > VIGN(H) or VENB > VENB(H)

no load on VREG –10–mA

IQ(SLEEP)

VIN = 13.5 V, VIGN < VIGN(L) and VENB < VENB(L) ,

no load on VREG ––10A

Buck Switching Regulator (VREG)

Switcher Output – Regulating VREG(PWM)

VIN(SWNOM) < VIN < 27 V, VENB = high,

100 mA < IVREG < 1100 mA 5.30 5.45 5.60 V

Switcher Output – Dropout VREG(100%)

VIN = 5.5 V, LX at 100% duty cycle,

IVREG = 1100 mA 5.03 – – V

VIN = 6.4 V and LX at 100% duty cycle,

IVREG = 200 mA – – 6.38 V

Switcher Period2

TSW(L) VIN(SWL) < VIN < VIN(SWNOM) , RTON = 412 k– 1.6 – s

TSW(NOM) VIN(SWNOM) < VIN < VIN(SWH) , RTON = 412 k– 450 – ns

TSW(H) VIN(SWH) < VIN < 36 V, RTON = 412 k– 1.6 – s

Switcher On-Time tON

VIN = 7.5 V, RTON = 412 k1030 1290 1550 ns

VIN = 13.5 V, RTON = 412 k160 200 240 ns

VIN = 27 V, RTON = 412 k80 118 135 ns

VIN = 35 V, RTON = 412 k225 280 335 ns

Switcher Period Threshold

VIN(SWL)

VIN falling, TSW changes from

TSW(L) to 100% duty cycle 6.2 6.5 6.8 V

VIN(SWNOM)

VIN falling, TSW changes from

TSW(NOM) to TSW(L)

8.0 8.6 9.2 V

VIN(SWH)

VIN rising, TSW changes from

TSW(NOM) to TSW(H)

28 31 34 V

Switcher Period Hysteresis

VIN(SWL)hys

Relative to the VIN voltage that initially caused

the switcher period to change – 250 – mV

VIN(SWNOM)

hys

Relative to the VIN voltage that initially caused

the switcher period to change – 250 – mV

VIN(SWH)hys

Relative to the VIN voltage that initially caused

the switcher period to change – 700 – mV

Switch On-Resistance RDS(on)

TJ = 25°C, IDS = 0.1 A – 135 180 m

TJ = 150°C, IDS = 0.1 A – 270 360 m

Minimum On-Time tON(min) VIN = 13.5 V, RTON = 49.9 k–6590ns

Minimum Off-Time tOFF(min) VIN = 13.5 V 85 110 140 ns

ELECTRICAL CHARACTERISTICS Valid at 5.5 V < VIN < 36 V, 40ºC < TJ < 150ºC; unless otherwise specified

Characteristic Symbol Test Conditions Min. Typ. Max. Unit

Continued on the next page…

2.2 MHz Constant On-T ime Buck Regulator

W ith Two External and T wo Internal Linear Regulators

A4407

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

ELECTRICAL CHARACTERISTICS (continued) Valid at 5.5 V < VIN < 36 V, 40ºC < TJ < 150ºC; unless otherwise specified

Characteristic Symbol Test Conditions Min. Typ. Max. Unit

Buck Switching Regulator (VREG) (continued)

Current Feedback Gain2GISEN – 4.0 – V/V

Error Amplifier Transconductance2gm– 7.5 – A/V

Error Amplifier Open Loop Gain2AVOL –57–dB

0 dB Crossover Frequency2fC

VIN = 13.5 V, RSENSE = 300 m, CO = 10 F,

RL = 5.5 – 65 – kHz

Soft Start Ramp Time tSS –10–ms

5 V and 5VP Linear Regulators

V5 Accuracy and Load Regulation errV5 10 mA < IV5 < 215 mA, VREG  5.25 V 4.9 5.0 5.1 V

V5P Accuracy and Load Regulation errV5P 10 mA < IV5P < 280 mA, VREG  5.25 V 4.9 5.0 5.1 V

V5P/3V3 Tracking Ratio VV5P / V3V3 1.507 1.515 1.523 –

V5P/3V3 Tracking Accuracy errTrack3V3

2.69 V < V3V3 < 3.37 V, IV5P = 75 mA,

5.5 V < VIN < 27 V 0.5 – +0.5 %

V5P/V5 Tracking Accuracy3errTrackV5

IV5P = IV5 = 75 mA, 5.5 V < VIN < 27 V,

–20°C < TJ < 150°C 25 – +25 mV

IV5P = IV5 = 75 mA, 5.5 V < VIN < 27 V,

TJ = –40°C 32 – +32 mV

3.3 V Linear Regulator and FET Driver

3V3 Accuracy err3V3 10 mA < I3V3 < 700 mA 3.23 3.30 3.37 V

3V3 Input Resistance RIN3V3 – 300 – k

G3V3 Source Current1IG3V3(SRC) V3V3 = 3.0 V, VG3V3 = VG3V3(MAX) – 1 V 160 320 –480 A

G3V3 Sink Current1IG3V3(SINK) V3V3 = 3.6 V, VG3V3 = 6 V 0.5 4 – mA

G3V3 Maximum Voltage VG3V3(MAX) V3V3 = 3.0 V 9 – 15 V

G3V3 Minimum Voltage VG3V3(MIN) V3V3 = 3.6 V – 0.7 1.0 V

G3V3 Output Impedance2ROUT(G3V3) – 175 – 

3V3 External FET Gate Capacitance2CISS3V3 250 – 5200 pF

1.2 V/1.5 V/1.8 V Linear Regulator and FET Driver

1V2 Accuracy err1V2 10 mA < I1V2 < 500 mA 1.174 1.205 1.236 V

1V2 Bias Current1I1V2 –100 – nA

G1V2 Source Current1IG1V2(SRC) V1V2 = 0.9 V, VG1V2 = VG1V2(MAX) – 1V 120 240 –360 A

G1V2 Sink Current1IG1V2(SINK) V1V2 = 1.5 V, VG1V2 = 6 V 0.5 3 – mA

G1V2 Maximum Voltage VG1V2(MAX) V1V2 = 0.9 V 9 – 15 V

G1V2 Minimum Voltage VG1V2(MIN) V1V2 = 1.5 V – 0.7 1.0 V

G1V2 Output Impedance2ROUT(G1V2) – 175 – 

1V2 External FET Gate Capacitance2CISS1V2 250 – 3900 pF

Charge Pump (VCP)

VCP Output Voltage VCP VCP  VIN 4.1 6.6 – V

VCP Switching Frequency fSW(CP) – 100 – kHz

Continued on the next page…

2.2 MHz Constant On-T ime Buck Regulator

W ith Two External and T wo Internal Linear Regulators

A4407

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

ELECTRICAL CHARACTERISTICS (continued) Valid at 5.5 V < VIN < 36 V, 40ºC < TJ < 150ºC; unless otherwise specified

Characteristic Symbol Test Conditions Min. Typ. Max. Unit

Continued on the next page…

Logic Enable Input (ENB)

ENB Logic Input Threshold VENB(H) VENB rising – – 2.0 V

VENB(L) VENB falling 0.8 – – V

ENB Logic Input Current1IENB(IN) VENB = 3.3 V – – 100 A

ENB Pulldown Resistance RENB –60–k

Ignition Enable Input (ENBAT) and Ignition Status Output (ENBATS)

ENBAT and ENBATS Thresholds

VIGN(H)

VIGN rising via a 1 k series resistance,

measure VIGN when IQ occurs – 3.3 4.0 V

VIGN(L)

VIGN falling via a 1 k series resistance,

measure VIGN when IQ(SLEEP) occurs 2.2 2.7 – V

ENBAT Input Current1IENBAT(IN)

VIGN = 5.5 V via a 1 k series resistance – 50 100 A

VIGN = 0.8 V via a 1 k series resistance 0.5 – 5 A

ENBAT Input Resistance RENBAT – 650 – k

ENBATS Output Voltage VENBATS(L) IENBATS = 4 mA – – 400 mV

ENBATS Leakage Current1IENBATS(LKG) VENBATS = 3.3 V – – 1 A

ENBATS Turn-On Delay tENBATS Sleep mode to VENBATS = 3.3 V – 11 – ms

TRACK Input

TRACK Voltage Threshold VTRACK(H) VTRACK rising – – 2.0 V

VTRACK(L) VTRACK falling 0.8 – – V

TRACK Bias Current1ITRACK(BIAS) –100 – A

NPOR Output

NPOR Power-Up Delay tNPOR CPOR = 0.22 F – 20 – ms

NPOR Output Voltage VNPOR(L)

VENB = high or VENBAT = high,

VREG < VREGUV(L) or V3V3 < V3V3UV(L)

INPOR  4mA

– – 400 mV

VENBAT = low, VENB transitioning low,

VREG = 5.45 V, INPOR  0.3 mA,

0.8 V < V3V3 < err3V3

, 0°C  TJ  150°C

– 350 800 mV

VENBAT = low, VENB transitioning low,

VREG = 5.45 V, INPOR  0.3 mA,

1.0 V < V3V3 < err3V3

, 40°C  TJ  150°C

– – 800 mV

NPOR Leakage Current1INPOR(LEAK) VNPOR = 3.3 V – – 1 A

CPOR Characteristics

CPOR Charge Current1ICPOR(SRC) –13 – A

CPOR Voltage Threshold VCPOR(H) VCPOR rising 1.0 1.2 1.4 V

2.2 MHz Constant On-T ime Buck Regulator

W ith Two External and T wo Internal Linear Regulators

A4407

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

ELECTRICAL CHARACTERISTICS (continued) Valid at 5.5 V < VIN < 36 V, 40ºC < TJ < 150ºC; unless otherwise specified

Characteristic Symbol Test Conditions Min. Typ. Max. Unit

NPOR Thresholds

VREG UVLO Thresholds VREGUV(H) VREG rising, NPOR transitions high 4.80 5.00 5.20 V

VREGUV(L) VREG falling, NPOR transitions low 4.75 4.94 5.14 V

VREG UVLO Hysteresis VREGUVHYS –60–mV

3V3 UVLO Thresholds V3V3UV(H) V3V3 rising, NPOR transitions high 2.80 2.95 3.10 V

V3V3UV(L) V3V3 falling, NPOR transitions low – 2.83 – V

3V3 UVLO Hysteresis V3V3UVHYS – 125 – mV

1V2 UVLO Thresholds

V1V2UV(H)

Measured as percentage of err1V2 ;

V1V2 rising, NPOR transitions high 85 89 93 %

V1V2UV(L)

Measured as percentage of err1V2 ;

V1V2 falling, NPOR transitions low –84–%

1V2 UVLO Hysteresis V1V2UVHYS –5–%

Buck (VREG) Current Protection

VREG ISEN Voltage Threshold VISEN(th) VISEN+ – VISEN– 265 350 435 mV

VREG Valley Current Limit ILIM(VALLEY) RSENSE = 300 m, VIN > VINSW(L) 883 1167 1450 mA

VREG Peak Current Limit ILIM(PEAK) 3.0 5.5 – A

3.3 V Overcurrent Protection

3V3 Overcurrent Threshold VCL3V3 VREG – VCL3V3 210 235 280 mV

3V3 Current Limit I3V3LIM RCL3V3 = 300 m700 783 – mA

3V3 Foldback Threshold I3V3FB V3V3 = 0 V, VREG – VCL3V3 48 65 90 mV

1.2 V/1.5 V/1.8 V Overcurrent Protection

1V2 Overcurrent Threshold VCL1V2 V1V2 = 1.2 V, V3V3 – VCL1V2 179 218 245 mV

1V2 Current Limit I1V2LIM RCL1V2 = 390 m459 559 – mA

1V2 Foldback Threshold I1V2FB V1V2 = 0 V, V3V3 – VCL1V2 45 60 84 mV

5VP Overcurrent Protection

V5P Current Limit1IV5PLIM VV5P = 5 V 280 415 – mA

V5P Foldback Current1IV5PFB VV5P = 0 V 70 110 150 mA

5V Overcurrent Protection

V5 Current Limit1IV5LIM VV5 = 5 V 215 310 – mA

V5 Foldback Current1IV5FB VV5 = 0 V 74 92 135 mA

Thermal Protection

Thermal Shutdown Threshold TJTSD TJ rising 155 170 – ºC

Thermal Shutdown Hysteresis TJTSDHYS –20–ºC

1For input and output current specifications, negative current is defined as coming out of the node or pin (sourcing), positive current is defined as

going into the node or pin (sinking).

2Ensured by design and characterization, not production tested.

3–20°C ensured by design and characterization, not production tested.

2.2 MHz Constant On-T ime Buck Regulator

W ith Two External and T wo Internal Linear Regulators

A4407

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Characteristic Performance

VREG Output versus Temperature TON versus Temperature

V5 Output versus Temperature V5P Output versus Temperature

3V3 Output versus Temperature 1V2 Output versus Temperature

5.40

5.41

5.42

5.43

5.44

5.45

5.46

5.47

5.48

5.49

5.50

-40 -20 0 20 40 60 80 100 120 140

VREG Output Voltage (V)

Temperature

(°C)

100

200

300

400

500

600

700

800

900

1,000

1,100

1,200

1,300

1,400

-40 -20 0 20 40 60 80 100 120 140

TON Pulse Width (ns)

Temperature

(°C)

7.5

13.5

4.95

4.96

4.97

4.98

4.99

5.00

5.01

5.02

5.03

5.04

5.05

-40 -20 0 20 40 60 80 100 120 140

V5 Output Voltage (V)

Temperature

(°C)

4.95

4.96

4.97

4.98

4.99

5.00

5.01

5.02

5.03

5.04

5.05

-40 -20 0 20 40 60 80 100 120 140

V5P Output Voltage (V)

Temperature

(°C)

3.27

3.28

3.29

3.30

3.31

3.32

3.33

-40 -20 0 20 40 60 80 100 120 140

3V3 Output Voltage (V)

Temperature

(°C)

1.190

1.195

1.200

1.205

1.210

1.215

1.220

-40 -20 0 20 40 60 80 100 120 140

1V2 Output Voltage (V)

Temperature

(°C)

(V)

2.2 MHz Constant On-T ime Buck Regulator

W ith Two External and T wo Internal Linear Regulators

A4407

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

ENBAT Start / Stop Thresholds versus Tempera ture ENABLE Start / Stop Thresholds versus Temperature

CPOR Charging Current versus Temperature ENBATS (Low) Voltage versus Temperature

VREG Valley Current Limit versus Temperature 1V2 and 3V3 Overcurrent Threshold versus Temperature

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

3.8

4.0

-40 -20 0 20 40 60 80 100 120 140

ENBAT Threshold (V)

Temperature (°C)

START

STOP

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

-40-20 0 20406080100120140

ENABLE Threshold (V)

Temperature (°C)

START

STOP

-40 -20 0 20 40 60 80 100 120 140

CPOR Charging Current (uA)

Temperature (°C)

100

150

200

250

300

350

400

-40 -20 0 20 40 60 80 100 120 140

NPOR Voltage at 4 mA (mV)

Temperature (°C)

250

275

300

325

350

375

400

425

450

-40 -20 0 20 40 60 80 100 120 140

VREG Valley Current Limit (mV)

Temperature (°C)

180

190

200

210

220

230

240

250

260

270

-40 -20 0 20 40 60 80 100 120 140

Overcurrent Threshold (mV)

Temperature (°C)

1V2

3V3

2.2 MHz Constant On-T ime Buck Regulator

W ith Two External and T wo Internal Linear Regulators

A4407

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Functional Description

Overview

The A4407 contains a constant on-time (COT), buck switch-

ing pre-regulator with valley sensing current mode control, two

integrated 5 V linear regulators, and two N-channel FET drivers:

one for a 1.2 V, 1.5 V, or 1.8 V linear regulator, and the other for

a 3.3 V linear regulator. The COT converter maintains a constant

output frequency because the on-time is inversely proportional

to the supply voltage. As the input voltage decreases, the on-time

is increased, which maintains a relatively constant period and

frequency. Valley mode current control allows the converter to

achieve very short on-times because current is measured during

the off-time, so there is no requirement for blanking.

With very low input voltages, the buck switch transitions to a

100% duty cycle. This turns the buck switch on 100% of the time

(no switching), and allows the regulator to operate in dropout

mode.

The device is enabled via the logic level input (ENB) or the high

voltage ignition input (ENBAT). When the device is enabled,

the converter starts up under the control of a 10 ms internal soft

start ramp. The two enable inputs are logically ORed together, so

either of the inputs can be used to enable the device. Both inputs

must be low to disable the device.

Under light load conditions, the switch enters pulse-skipping

mode to ensure regulation is maintained. In order to accept a

wide input voltage range, the switcher period is extended when

either the minimum on- or off-time is reached, or when the input

supply is at either end of its range.

The A4407 features overcurrent protection on all regulators

including the VREG pre-regulator. The buck switch current

limit is determined by the selection of the sense resistor between

the ISENx pins. Output current from the internal 5 V and 5 V

protected linear regulators is also monitored, and if shorted the

outputs would fold back. The external FET drivers have current

limit sensing that can be used with a sense resistor to trigger

fold back protection.

Buck Dropout Mode

The topology of a COT timer is ideal for systems that have high

input voltages. Because current is measured during the off-time,

very short on-times can be achieved. With low input voltages,

the switcher must maintain very short off-times. To prevent

the switcher from reaching its minimum off-time, the switcher

is designed to enter a 100% duty cycle mode. This causes the

switcher to stop acting as a buck switch. The voltage at the

VREG pin then becomes simply the supply voltage minus the

drop across the buck switch and inductor. In this mode, maximum

available current may be lower, depending on ambient tempera-

ture and supply voltage while in dropout mode.

Soft Start

An internal ramp generator and counter allow the output voltages

to ramp up. This limits the maximum demand on the external

power supply by controlling the inrush current required to charge

the external capacitor and any DC load at startup. Internally,

the ramp is set to 10 ms typical. The following conditions are

required to trigger a soft start:

• ENBAT or ENB transition high, and

• There is no thermal shutdown (TSD = 0), and

• 3V3 voltage is below its undervoltage lockout (UV)

threshold, and

• 1V2 voltage is below its UV threshold, and

• VREG voltage is below its UV threshold

Buck Pulse Width (TON)

A resistor from the TON input to VIN sets the on-time of the

converter for a given input voltage. When the supply voltage

is between 8.6 and 31 V, the switcher period remains constant,

based on the selected value of RTON

. At voltages lower than

6.5 V, the switch is in dropout mode (100% duty cycle). Within

reasonable input voltage ranges, the period of the converter is

held constant. This results in a constant operating frequency

across the input supply range. More information on how to

choose RTON can be found in the Application Information section.

The formula to calculate the on-time resistor value is:

ton = ( RTON / VIN

) × 6.36 × 10–12 + 5 × 10–9 (ns) (1)

Buck Current Sense (ISEN+, ISEN–)

The sense inputs are used to sense the current in the buck regula-

tor free-wheeling diode during the off-time. The value of the

2.2 MHz Constant On-T ime Buck Regulator

W ith Two External and T wo Internal Linear Regulators

A4407

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

sense resistor, RSENSE , between the ISENx pins, can be calcu-

lated from:

RSENSE = VISEN / ILIM(VALLEY) (2)

where VISEN is documented in the Electrical Characteristics table,

350 mV typical, and ILIM(VALLEY) is the lowest current measured

during the off-time.

It is recommended that the current sense resistor be sized so that,

at peak output current, the voltage at the ISEN– pin does not

exceed –0.75 V during PWM operation (that is, a transient condi-

tion). Because the diode current is measured when the inductor

current is at the valley, the average output current is greater than

the ILIM(VALLEY) value. The value for ILIM(VALLEY) should be:

LIM(VALLEY) = IOUT(avg) – 0.5 × IRIPPLE + K (3)

where IOUT(avg) is the average of all the regulator outputs cur-

rents, IRIPPLE is the inductor ripple current, and K is a design

margin allowing for component tolerances.

The peak current in the switch is simply:

IPEAK = ILIM(VALLEY) + IRIPPLE (4)

Information on how to calculate the ripple current is included in

the Application Information section.

Buck Overcurrent Protection

The converter utilizes pulse-by-pulse valley current limiting,

which is activated when the current through the sense resis-

tor (that is, the buck output current) is high enough to create

–350 mV at the ISEN– pin. During an overload condition, the

switch is turned on for a period determined by the constant

on-time circuitry. The switch off-time is extended until the cur-

rent decays to the current limit value set by the selection of the

sense resistor, at which point the switch is allowed to turn-on

again. Because no slope compensation is required in this control

scheme, the current limit is maintained at a reasonably constant

level across the input voltage range.

Figure 1 illustrates how the current is limited during an overload

condition. The current decay (period with switch off) is propor-

tional to the output voltage. As the overload is increased, the out-

put voltage tends to decrease and the switching period increases.

LX Short Circuit Protection

If the LX node is shorted to ground, there would be a relatively

high peak current in the buck MOSFET within a very short time.

The A4407 protects itself by detecting the unusually high current,

turning off the buck MOSFET, and latching itself off. To avoid

false tripping, the current required to activate the peak current

protection, ILIM(PEAK) , 5.5 A typical, is set well above the normal

range of currents. After peak current limiting is activated, the

A4407 will be latched off until either: VIN is cycled below its

UVLO threshold, or the A4407 is disabled (both ENBAT and

ENB must be brought low) and re-enabled. NPOR is not directly

activated (pulled low) by the peak current protection circuitry.

However, NPOR will be in the correct state depending on the

VREG, 3V3, and 1V2 outputs.

Time

Current Limit level

Inductor CurrentInductor Current

Constant On-Time

Constant Period

Extended Period

Maximum load

Overload

Time

Constant On-Time

Figure 1. Buck current limiting during overload conditions: (upper) with

inductor current operating at maximum load, and (lower) inductor current

operating in a “soft” overload.

2.2 MHz Constant On-T ime Buck Regulator

W ith Two External and T wo Internal Linear Regulators

A4407

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Missing Asynchronous Diode Protection

In most high voltage asynchronous buck regulators, if the asyn-

chronous diode is missing or damaged the LX pin will transition

to a very high negative voltage when the upper MOSFET turns

off, resulting in damage to the regulator. The A4407 includes pro-

tection circuitry to detect when the asynchronous diode is missing

or damaged. If the LX pin becomes more negative than 1.6 V at

25°C for more than 157 ns, the A4407 will latch itself in the off

state to prevent damage. After a missing diode fault occurs, the

latch must be reset by either cycling VIN or ENBAT or ENB. See

figure 2 for the missing diode voltage threshold and time filtering

versus temperature.

Thermal Shutdown

If the A4407 junction temperature becomes too high, a thermal

shutdown circuit would disable the VREG output, thus protect-

ing the A4407 from damage. When a thermal shutdown occurs,

the buck regulator stops switching and the VREG voltage decays.

When VREG crosses UVLO threshold for it, the NPOR signal is

pulled low. Thermal shutdown is not a latched condition, so when

the junction temperature cools to an acceptable level, the A4407

automatically restarts.

Power On Reset (NPOR)

The NPOR output is an open drain pin that can be used to signal

a reset event to a DSP or microcontroller. The NPOR block

actively monitors ENBAT, ENB, 3V3, 1V2, VCP, and VREG.

During power-up, NPOR is held low for a programmable amount

of time ( tNPOR

) after VREG, 3V3, and 1V2 all transition above

the upper UVLO threshold for each. The rising edge delay allows

time for the regulators to be within specification when the DSP or

microcontroller begins processing. The amount of the rising edge

delay is determined by the value of the external capacitor from

the CPOR pin to ground. The rising delay can be calculated from

the following equation:

tNPOR = 92.3 × 103 × CPOR (seconds) (5)

Any of the following conditions forces NPOR to transition low

immediately (within a few microseconds):

• 3V3 voltage falls below its UVLO threshold, or

• 1V2 voltage falls below its UVLO threshold, or

• VREG voltage falls below its UVLO threshold, or

• ENBAT and ENB are both low, or

• Charge pump voltage, VCP

, is too low, or

• Internal IC power rail voltage, VRAIL , is too low

When a thermal shutdown (TSD) occurs: PWM switching termi-

nates; VREG, or 3V3, or 1V2 decay below the UVLO threshold

for it; and NPOR transitions low. Thus, a TSD event indirectly

causes NPOR to transition low.

When the A4407 is disabled (ENB and ENBAT are both low or

VIN is removed) the NPOR output is held low until the voltage

from the 3.3V regulator (3V3) falls below 1.0 V (see figure 3).

This assumes maximum initial current (4 mA) in the NPOR open

drain DMOS. The NPOR voltages would be somewhat lower for

lower values of INPOR

Figure 3. NPOR and 3V3 shutdown characteristics

Figure 2. Missing diode protection versus device junction temperature

ENB, ENBAT

V3V3

INPOR

VNPOR

3.3 V

 1.0 V

 0.3 mA

800 mV

 4mA

350 mV TYP

400 mV

120

130

140

150

160

170

180

190

200

210

1.10

1.20

1.30

1.40

1.50

1.60

1.70

1.80

1.90

2.00

-50 -25 0 25 50 75 100 125 150

Time Filtering (ns)

NegaƟve Voltage Threshold (V)

JuncƟon Temperature (°C)

Voltage Threshold

Time Filtering

2.2 MHz Constant On-T ime Buck Regulator

W ith Two External and T wo Internal Linear Regulators

A4407

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

5 V Regulator (V5)

The 5V linear regulator is provided to supply local circuitry. This

regulator can deliver 310 mA typical, 215 mA minimum. When

a direct short is applied to this regulator, the output current folds

back to 0 V at approximately 92 mA typical (figure 4).

5 V Protected Tracking Regulator (V5P)

The 5VP linear tracking regulator is provided to supply remote

circuitry such as off-board sensors. The output is monitored and

in case of a short to battery condition the output is disabled and

protected until the short is removed. The regulator can deliver

415 mA typical, 280 mA minimum. When a direct short is

applied to this regulator, the output the current folds back to 0 V

at approximately 110 mA typical (figure 5).

The V5P regulator is designed to track the either the 3V3 output

or the V5 output. The V5P master reference is set by the status of

the TRACK pin. The V5P regulator will track the 3.3V output to

within ±0.5% and the V5 output to within ±25 mV under normal

steady state operating conditions. If the master reference (either

3V3 or V5) is decreasing, the V5P regulator will accurately

track the master reference down to the point at which the master

reference crosses its undervoltage threshold (either V3V3UV(L) or

V1V2UV(L) in the Electrical Characteristic tables).

50 100 150 200 250 300 350 500450400

Output Voltage (V)

Output Current (mA)

Typical

Minimum

Figure 5. Fold back current limiting of the 5VP regulator

Figure 4. Fold back current limiting of the 5 V regulator

50 75 100 125 150 175 200 225 250 275 300 325 350 375 400

Output Voltage (V)

Output Current (mA)

Typical

Minimum

2.2 MHz Constant On-T ime Buck Regulator

W ith Two External and T wo Internal Linear Regulators

A4407

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Figures 6 and 7 show the A4407 operation when the V5P pin is

shorted to ground and VIN (battery). In both cases, the V5P output

is disabled and/or disconnected while the other outputs (VREG,

V5, V33, and 1V5) remain active.

Tracking Control

The TRACK input sets the master reference for the V5P track-

ing regulator. TRACK is meant to be either connected to ground

or left unconnected by the PCB routing. When TRACK is left

unconnected, it is pulled high by an internal current source and

V5P tracks the 3V3 regulator. When TRACK is connected to

ground, then V5P tracks the V5 regulator.

3V3 Linear Regulator (3V3)

A 3.3 V linear regulator can be implemented using an external

MOSFET. In the event the 3.3 V regulator output is shorted to

ground, the A4407 protects the external MOSFET by folding

back when the programmed current limit, I3V3LIM

, is exceeded.

The current limit is determined by the voltage developed across

the external sense resistor, RCL1

, shown in the Functional Block

diagram. The 3.3 V regulator current limit can be calculated using

the following formula:

I3V3LIM =VCL3V3 / RCL1 (6)

where VCL3V3 is documented in the Electrical Characteristics

table, 235 mV typical. Usually, RCL1 has a fairly low value so it

will not dissipate significant power (1/4 W should be adequate)

but the tolerance should be 1% or less. When I3V3LIM is exceeded,

the maximum load current through the external MOSFET is

folded back to 27% typical of I3V3LIM as shown in figure 8.

3.5

3.0

2.5

2.0

1.5

1.0

50 10 20 30 40 50 60 12090 100 1108070

Output Voltage (V)

Percentage of Normal Current Seng (%)

Typical

Minimum

Maximum

Figure 8. Fold back current limiting of the 3V3 regulator

Figure 6. V5P shorted to ground in 5 s (DV5P is populated); shows VREG

(ch1, 2 V/div.), V3V3 (ch2, 1 V/div.), VV5 (ch3, 2 V/div.), V1V5 (ch4, 1 V/div.),

VV5P (ch5, 2 V/div.), t = 10 s/div.

VREG

V3V3

VV5

V1V5

VV5P

Figure 7. V5P is shorted to a 25 V battery; shows VVREG (ch1, 2 V/div.),

V3V3 (ch2, 2 V/div.), VIN pin (ch3, 5 V/div.), VV5P (ch4, 5 V /div.),

t = 10 s/div.

V3V3

VREG

VV5P

5 V

25 V

30 V

VIN pin

Ringing due to parasitics from a long wire

V5P is clamped to a safe level above VIN

by D2 (see application schematic)

All

2.2 MHz Constant On-T ime Buck Regulator

W ith Two External and T wo Internal Linear Regulators

A4407

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

1.2 V/1.5 V/1.8 V Linear Regulator (1V2)

A 1.2 V, 1.5 V, or 1.8 V linear regulator can be implemented using

an external MOSFET. In the event this regulator output is shorted

to ground, the A4407 protects the external MOSFET by folding

back when the programmed current limit, I1V2LIM

, is exceeded.

The current limit is determined by the voltage developed across

the external sense resistor, RCL2 , shown in the Functional Block

diagram. The 1.2 V/1.5 V/1.8 V regulator current limit can be

calculated using the following formula:

I1V2LIM = VCL1V2 / RCL2 (7)

where VCL1V2 is documented in the Electrical Characteristic

table, 218 mV typical. Usually RCL2 has a fairly low value so it

will not dissipate significant power (1/4W should be adequate) but

the tolerance should be 1% or less. When I1V2LIM is exceeded, the

maximum load current through the external MOSFET is folded

back to 27% typical of I1V2LIM , as shown in figure 9.

This regulator is designed to provide 1.2 V, but by using an exter-

nal resistive divider between VOUT1V2 and the 1V2 pin, other

voltages can be achieved, such as1.5 V or 1.8 V.

Charge Pump

The charge pump is used to generate a supply above VIN . A

0.22 μF monolithic ceramic capacitor should be connected

between VCP and VIN to act as a reservoir to run the internal

DMOS and the external MOSFETs. The VCP voltage is internally

monitored to ensure that the switching regulator would be dis-

abled in the case of a fault condition. A 0.22 μF ceramic mono-

lithic capacitor should be connected between CP1 and CP2.

ENBAT

ENBAT is a level-triggered enable input, used to enable the

device based on a high voltage ignition or battery switch (via a

1 kΩ resistor). The ENBAT comparator thresholds are VIGN(L) =

2.2 V minimum and VIGN(H) = 4.0 V maximum. ENBAT is used

only as a momentary switch to enable, or wake up, the A4407.

The ENB and ENBAT signals are logically ORed together inter-

nally, so individually either can wake up the A4407, that is, only

one of these two inputs must be pulled high in order to enable the

A4407. However, when ENBAT is removed, ENB must be high

to keep the A4407 enabled. If there is no need for the ignition

switch, ENBAT can be pulled low, making ENB a single reset

control. Power-up and power-down scenarios using these inputs

are shown in figures 10 and 11.

When an external resistor and capacitor are used to form a

low-pass filter to the ENBAT pin, then a 100 Ω resistor must be

used to prevent the external capacitor from discharging into and

damaging the ENBAT pin. See the Functional Block diagram for

connection of these three components.

ENBATS

When a logic high is sensed on the ENBAT input, the ENBATS

open drain output goes high, signaling to the user that the ignition

input is high. When a logic low is sensed on the ENBAT input,

then ENBATS transitions low. The ENBATS input logic levels

are identical to the ENBAT input logic levels.

ENB

This pin can be used as an enable input from either a DSP or a

microcontroller. This input has an internal pull down resistor so it

can be left unconnected if not needed.

Figure 9. Fold back current limiting of the 1V2 regulator

1.4

1.2

1.0

0.8

0.6

0.4

0.2

50 10 20 30 40 50 60 12090 100 1108070

Output Voltage (V)

Percentage of Normal Current Seng (%)

Typical

Minimum

Maximum

2.2 MHz Constant On-T ime Buck Regulator

W ith Two External and T wo Internal Linear Regulators

A4407

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Figure 10. Typical power-up and power-down by ENBAT and ENB with VIN = 13.5 V; ENBATS is assumed to be connected to 3V3 via a pull up resistor

VIN

NPOR

CPOR

ENBATS

ENBAT

ENB

V5P

3V3

Internal

RAIL

or VCP

VREG

=4.0V

=2.2V

10 ms

20 ms

1. 2 V

13.5 V

=5.00V

=2.95V

Clamped at 8.5 V via 1 k

=4.94V

=2.83V

=2V

=0.8V

Internal

UVLO

1.0 V

0.8 V

MAX

Internal

UVLO

1V2

=1.07V

=1.01 V

VREG > 5.00V and

3V3 > 2.95V and

1V2 > 1.07V

ENB < 0.8V or

VREG < 4.94V or

3V3 < 2.83V or

1V2 < 1.01V or

VCP low or

INT. VRAIL low

NPOR is open-drain, pulled up to 3V3

Decay rates of VREG, V5, V5P,

3V3, and 1V2 depend on output

capacitances and loading

ENBATS is open-drain, pulled up to 3V3

V5, V5P, 3V3, 1V2 ramp

at approximately the

same rate as VREG

2.2 MHz Constant On-T ime Buck Regulator

W ith Two External and T wo Internal Linear Regulators

A4407

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

VIN

NPOR

CPOR

ENBATS

ENBAT

ENB

V5P

3V3

Internal

RAIL

or VCP

VREG 10 ms

20 ms

1. 2 V

13.5 V

=5.00V

=2.95V

=4.94V

=2.83 V

6.5 V

Internal

UVLO

5.2 V 5.5 V 4.9 V

ENBAT

= 0V

ENBATS is not connected

100 % Duty

Cycle

Internal regulators

collapse

0.8 V

MAX

1.0 V

Internal

UVLO

1V2 V

=1.07V V

=1.01 V

ENB

 2V prior to

ramping up

VREG > 5.00V and

3V3 > 2.95V and

1V2 > 1.07V

ENB < 0.8V or

VREG < 4.94V or

3V3 < 2.83V or

1V2 < 1.01V or

VCP low or

VRAIL low

V5P tracks 3V3 until

3V3UV(L)

or V

< 5.5 V

V5, V5P, 3V3, 1V2 ramp at

approximately the same

rate as VREG

NPOR is open-drain, pulled up to 3V3

Decay rates of VREG, V5, V5P,

3V3, and 1V2 depend on output

capacitances and loading

Figure 11. Typical power up and power down via VIN with ENB always logic high; ENBAT and ENBATS are not used

2.2 MHz Constant On-T ime Buck Regulator

W ith Two External and T wo Internal Linear Regulators

A4407

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Component Selection

Buck On-Time and Switching Frequency

In order for the switcher to maintain regulation, the energy that is

transferred to the inductor during the on-time must be transferred

to the capacitor during the off-time. Because of this relationship,

the load current and IR drops, as well as the input and output

voltages, affect the on-time of the converter. The equation that

governs switcher on-time is:

tON VIN + Vf – (RDS(on) × Ipeak)

TSW [VREG + (RL × Ipeak) +Vf + (RSENSE × Ip

(8)

The effects of the voltage drop on the inductor and trace resis-

tance affect the switching frequency. However, the frequency

variation due to these factors is small, and is covered in the varia-

tion of the switcher period, which is ±25% of the target. Remov-

ing these current dependant terms simplifies the equation:

= ×

tON VIN + Vf – (RDS(on) × Ipeak)fSW

VREG + Vf + (RSENSE × Ipeak)1

(9)

Be sure to use worst-case sense voltage and forward voltage

of the diode including any effects due to temperature. For the

example provided, assume a 1 A converter with a supply voltage

of 13.5 V. The output voltage is 5.45 V, Vf is 0.45 V, RSENSE ×

Ipeak is 0.34 V, RDS(on) × Ipeak is 0.15 V, and the target frequency

is 2.2 MHz. Applying equation 9, we can solve for tON:

tON 13.5 (V) + 0.45 (V) – 0.15 (V)

205 ns

2.2 (MHz)

5.45 (V) + 0.45 (V) + 0.34 (V) 1

The formulas above describe how tON changes based on input and

load conditions. Because load changes are minimal and the out-

put voltage is fixed, the only factor that affects the on-time is the

input voltage. The converter is able to maintain a constant period

over a varying supply voltage because the on-time changes based

on the input voltage. The current into the TON pin is derived

from a resistor tied to VIN, which sets the on-time proportional to

the supply voltage. Selecting the resistor value based on the tON

calculated above is done using the following formula:

RTON

VIN × (tON – 5 (ns)

)

6.36 × 10–12

(10)

When the resistor is selected and a suitable tON is found, tON must

be demonstrated that it does not, under worst-case conditions,

exceed the minimum on-time or minimum off-time of the con-

verter. The minimum on-time occurs at maximum input voltage

and minimum load. The maximum off-time occurs at minimum

supply voltage and maximum load. For supply voltages above

6.5 V but below 8.6 V, refer to the section entitled Low Voltage

Operation.

Low Voltage Operation

The converter can run at very low input voltages; for example,

with a 5.25 V output, the minimum input supply can be as low

as 5.5 V. When operating at high frequencies, the on-time of the

converter must be very short because the available period is short.

At high input voltages the converter should not violate the mini-

mum on-time, tON(min)

, and at low input voltages the converter

should not violate the minimum off-time, tOFF(min)

. Rather than

limit the supply voltage range, the converter solves this problem

by automatically increasing the period. With the period extended,

the converter does not violate the minimum on-time or off-time

specifications. If the input voltage is between 8.6 and 31 V, the

converter will maintain a constant period. When calculating worst

case on- and off-times, make sure to use the highest switching

frequency if the supply voltage is in that range.

When operating at voltages below 8.6 V, additional care must

be taken when selecting the inductor and diode. At low voltages

the maximum current may be limited, due to the IR drops in the

current path. When selecting external components for low voltage

operation, the IR drops must be considered when determining

on-time, so the complete formula (equation 8) should be used to

make sure the converter does not violate the timing specification.

Inductor Selection

Choosing the proper inductor is critical to the correct operation of

the switcher. The converter is capable of running at frequencies

above 2 MHz, making it possible to use small inductor values and

reducing cost and board area.

The inductor value determines the ripple current. It is important

to size the inductor so that under worst-case conditions the over-

current threshold equals the average current minus half the ripple

current plus reasonable margin. When the ripple current is too

large, the converter reaches current limit. Typically, peak-to-peak

ripple current should be limited to 20% to 25% of the maximum

average load current.

Application Information

2.2 MHz Constant On-T ime Buck Regulator

W ith Two External and T wo Internal Linear Regulators

A4407

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Worst-case ripple current occurs at maximum supply voltage.

After calculating the duty cycle for this condition, the ripple cur-

rent can be calculated:

DVIN(max) + Vf – (RDS(on) × Ipeak)

VREG + Vf + (RSENSE × Ipeak)

(11)

Using the duty cycle, the inductor value can be calculated using

the formula below:

= × ×

Iripple

VIN –fSW (min)

VREG 1

(12)

Where Iripple is 25% of the maximum load current, and fSW(min)

is the minimum switching frequency, nominal frequency minus

25%. Continuing the example used above (using equation 9), a

1 A converter with a supply voltage of 13.5 V is the design objec-

tive. Assume the supply voltage can vary by ±10%, the output

voltage is 5.45 V, Vf is 0.5 V, VSENSE is 0.20, and the target fre-

quency is 2.2 MHz. Using equation 11, the duty cycle is calcu-

lated to be 36.45%. Assume the worst-case frequency is 2.2 MHz

minus 20%, or 1.76 MHz. Using these numbers in equation 12

shows that the minimum inductance for this converter is 9.6 μH.

Output Capacitor

The buck converter is designed to operate with a low-ESR

ceramic output capacitor. When choosing a ceramic capacitor,

make sure the rated voltage is at least 3 times the maximum

output voltage of the converter. This is because the capacitance of

a ceramic decreases the closer it is operated to its rated voltage. It

is recommended that the output be decoupled with a 10 μF, 16 V,

X7R ceramic capacitor. Larger capacitance may be required on

the outputs if load surges dramatically influence the output volt-

age.

Output voltage ripple is determined by the output capacitance;

and the effects of ESR and ESL can be ignored, assuming recom-

mended layout techniques are followed. The output voltage ripple

is approximated by:

Vripple = Iripple / (8 × fsw × COUT) (13)

Input Capacitor

The value of the input capacitance affects the amount of cur-

rent ripple on the input. This current ripple is usually the source

of supply-side EMI. The amount of interference depends on the

impedance from the input capacitor and the bulk capacitance

located on the supply bus. In addition to the two 4.7 μF capaci-

tors, placing a small 0.1 μF ceramic capacitor very close to the

input supply pin helps reduce EMI effects. The small capacitor

helps reduce the very high frequency transient currents on the

supply line.

Non-Synchronous Diode

The non-synchronous diode (DBUCK in the Functional Block dia-

gram) conducts the current during the off-time. A Schottky diode

is required to minimize the forward drop and switching losses. In

order to size the diode correctly, it is necessary to find the aver-

age diode conduction current using the following formula:

ID(avg) = I load × (1 – D(min

)) (14)

where D(min) is the minimum duty cycle, defined as:

D(min

) = (VREG + Vf ) / (VIN + Vf ) (15)

where VIN is the maximum input voltage and Vf is the maximum

forward voltage of the diode.

The average power dissipation in the diode is:

PDBUCK(avg) = IBUCK(avg) × D(min

) × Vf (16)

The power dissipation in the sense resistor must also be consid-

ered using I2R and the minimum duty cycle.

External MOSFET Selections

To choose an external MOSFET for the 3.3 V or for the

1.2 V/1.5 V/1.8 V linear regulator, consider: the maximum drain-

to-source voltage, VDS

, the maximum continuous drain current,

ID , the threshold voltage, VGSTH

, the on-resistance (RDS(on)(FET)),

and the thermal resistance (RJC(FET)).

2.2 MHz Constant On-T ime Buck Regulator

W ith Two External and T wo Internal Linear Regulators

A4407

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

The buck switcher pre-regulates the voltage to the external

MOSFET, so even under worst-case conditions, it does not have

to support more than 7 V from drain to source. Also, the external

LDOs usually deliver 500 mA to 1 A. Numerous MOSFETs are

available, with VDS ratings of at least 20 V, that can support much

more than 1A. These two goals should not be difficult to achieve.

The A4407 gate drive circuitry is guaranteed to pull the G3V3

and G1V2 voltage down to 1 V, maximum. Therefore, Allegro

recommends using external MOSFETs with a VGS threshold

higher than 1 V. Do not use a MOSFET that will conduct signifi-

cant current when VGS is at 1 V and the system is at the highest

expected ambient temperature.

One of the more critical specifications is the MOSFET on-

resistance, RDS(on)(FET). If the on-resistance were too high, then

the external regulator would not be able to maintain its output at

the maximum load current. Calculate the typical RDS(on)(FET) (at

25°C) using the following formula:

<–

RDS(on)(FET)25C RDROP1

0.6 × I3V3LIM

1.56 (V)

(17)

where I3V3LIM is the maximum current from the 3.3 V regula-

tor and RDROP1 is the value of the resistor connected from the

CL3V3 pin to the drain of the MOSFET. The multiplier of 0.6

in the equation allows a 66% increase in RDS(on)(FET) when the

MOSFET is very hot.

The necessity and value of RDROP1 is closely related to the

thermal resistance of the MOSFET, RJC(FET) . For a medium size

MOSFET (like a SOT-223) including RDROP1 in the PCB layout

is highly recommended. For a large size MOSFET with a very

low thermal resistance (like a D2PAK) RDROP1 is probably not

necessary.

The thermal resistance of a MOSFET is a function of die size,

package size, and cost. So choosing RDROP1 and RJC(FET)

together should result in optimal performance, minimal compo-

nent sizes, and lowest system cost. Determining the value and

power dissipated by the series dropping resistor and MOSFET

thermal resistance are addressed in detail in the next section.

3.3V Regulator External Resistors (RCL1, RDROP1)

In the Functional Block diagram, there are two resistors, RCL1

and RDROP1 from the output of the buck regulator to the drain

of the 3.3 V external MOSFET. RCL1 must always be pres-

ent because it sets the 3.3 V regulator current limit threshold.

However, RDROP1 , if used, prevents the external MOSFET from

dissipating too much power during certain conditions. In particu-

lar, when the battery voltage is extremely low (VBAT ≤ 6.5 V) and

the buck regulator transitions to dropout mode (100% duty cycle)

then VREG is approximately 1 V higher than normal. In this situ-

ation, without RDROP1

, the MOSFET could dissipate too much

power.

The value of RDROP1 depends on the maximum PCB temperature,

the maximum current load on the 3.3 V regulator, the maximum

allowable junction temperature of the MOSFET, and the thermal

resistance of the MOSFET. The 3.3 V regulator must conduct its

own load current (250 mA in the Functional Block diagram) plus

the load planned for the 1.2 V/1.5 V/1.8 V regulator (450 mA to

525 mA in the Functional Block diagram).

As the thermal resistance of the MOSFET decreases, the required

value of RDROP1 also decreases. If the MOSFET is relatively

large and has a very low thermal resistance then RDROP1 is not

required (0 Ω).

2.2 MHz Constant On-T ime Buck Regulator

W ith Two External and T wo Internal Linear Regulators

A4407

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Figure 12 shows recommended values of RDROP1 versus the

MOSFET thermal resistance at various 3.3 V regulator maxi-

mum current settings, I3V3LIM . This graph assumes: steady-state

operation (that is, for t >> 50 ms), a PCB temperature of 135°C, a

maximum MOSFET junction temperature of 175°C, a duty cycle

for tON of 100% , a VBAT of 6.69 V, and an output of 3.23 V from

the 3.3 V linear regulator. This graph takes into account the volt-

age drop across the 3.3 V current limit resistor, RCL1.

After a value for RDROP1 is determined, the designer should

calculate its maximum power dissipation (I2 × R) and select

an appropriate component, allowing adequate design margin.

Assuming the RDROP1 value was chosen from figure 12, then

figure 13 shows the power dissipated by RDROP1 versus the

MOSFET thermal resistance at various 3.3 V regulator current

settings.

The exact value of RDROP1 is not critical, so a component with

1% or 5% tolerance could be used.

1.2 V/1.5 V/1.8 V Regulator External Resistors

(RCL2, RDROP2)

In the Functional Block diagram, there are two resistors, RCL2

and RDROP2 from the output of the 3.3 V regulator to the drain

of the 1.2 V/1.5 V/1.8 V external MOSFET. RCL2 must always

be present because it sets the 1.2 V/1.5 V/1.8 V regulator current

limit threshold. However, RDROP2

, if used, prevents the external

MOSFET from dissipating too much power.

The value of RDROP2 depends on the maximum PCB temperature,

the maximum current load on the 1.2 V/1.5 V/1.8 V regulator

(I1V2LIM), the maximum allowable junction temperature of the

MOSFET, and the thermal resistance of the MOSFET.

As the thermal resistance of the MOSFET decreases, the required

value of RDROP2 also decreases. If the MOSFET is relatively

large and has a very low thermal resistance, then RDROP2 is not

required (0 Ω).

Figure 12. RDROP1 value versus 3.3 V MOSFET thermal resistance

at various 3.3 V regulator maximum current settings

Figure 13. RDROP1 power dissipation versus 3.3 V MOSFET thermal

resistance at various 3.3 V regulator maximum current settings

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

15 20 25 30 35 40 45 806560 70 755550

PD(RDROP2) (W)

MOSFET Thermal Resistance (°C/W)

635 mA

710 mA

785 mA

850 mA

935 mA

3.0

2.8

2.5

2.3

2.0

1.8

1.5

1.3

1.0

0.8

0.5

0.3

15 20 25 30 35 40 45 806560 70 755550

DROP1

(Ω)

MOSFET Thermal Resistance (°C/W)

635 mA

710 mA

785 mA

850 mA

935 mA

2.2 MHz Constant On-T ime Buck Regulator

W ith Two External and T wo Internal Linear Regulators

A4407

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Figure 14 shows recommended values of RDROP2 versus

MOSFET thermal resistance at various 1.5 V regulator maximum

current settings, I1V2LIM . This graph assumes a PCB temperature

of 135°C, a maximum MOSFET junction temperature of 175°C,

and 3.37 V from the upstream (3.3 V) linear regulator. This graph

takes into account the voltage drop across the 1.5 V current limit

resistor, RCL2

After a value of RDROP2 is determined the designer should calcu-

late its maximum power dissipation (I2 × R) and select an appro-

priate component, allowing adequate design margin. Assuming

the RDROP2 value was chosen from figure 14, then figure 15

shows the power dissipated by RDROP2 versus the MOSFET ther-

mal resistance at various 1.5 V regulator current settings.

The exact value of RDROP2 is not critical, so a component with

1% or 5% tolerance could be used.

2.0

1.8

1.5

1.3

1.0

0.8

0.5

0.3

30 35 40 45 80 85 90 95 1006560 70 755550

DROP2

(Ω)

MOSFET Thermal Resistance (°C/W)

675 mA

600 mA

525 mA

450 mA

375 mA

0.7

0.6

0.5

0.4

0.3

0.2

0.1

D(RDROP2)

(W)

MOSFET Thermal Resistance (°C/W)

30 35 40 45 80 85 90 95 1006560 70 755550

675 mA

600 mA

525 mA

450 mA

375 mA

Figure 14. RDROP2 value versus 1.5 V MOSFET thermal resistance

at various 1.5 V regulator maximum current settings

Figure 15. RDROP2 power dissipation versus 1.5 V MOSFET thermal

resistance at various 1.5 V regulator maximum current settings

2.2 MHz Constant On-T ime Buck Regulator

W ith Two External and T wo Internal Linear Regulators

A4407

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

PCB Component Placement and Routing

The board layout has a large impact on the performance of the

device. It is important to isolate high current ground returns to

minimize ground bounce that could produce reference errors in

the device. The method used to isolate power ground from noise

sensitive circuitry is to use a star ground. This approach makes

sure that the high current components such as the input capacitor,

output capacitor, and diode have very low impedance paths to

each other. Figure 16 illustrates the technique.

The ground traces for each of the components should be very

close to each other and should be connected to each other on the

same surface as the components. Internal ground planes should

not be used for the star ground connection, because vias add

impedance to the current path.

In order to further reduce noise effects on the PCB, noise sensi-

tive traces should not be connected to internal ground planes.

The feedback network from the switcher output should have an

independent ground trace that goes directly to the exposed pad

underneath the device. The exposed pad should be connected to

internal ground planes and to any exposed copper used for heat

dissipation. If the grounds from the device are also connected

directly to the exposed pad, the ground reference from the feed-

back network will be less susceptible to noise injection or ground

bounce.

To reduce radiated emissions from the high frequency switching

nodes, it is important to have an internal ground plane directly

under the LX node. That ground plane should not be broken

directly under the node, because the lowest impedance path back

to the star ground is directly under the signal trace. If another

trace does break the return path, the energy would have to find

another path, which would be through radiated emissions.

The peak-to-peak amplitude of the buck current sense signal

will typically be only tens of millivolts. The current sense pins,

ISEN+ and ISEN–, and internal differential amplifier comprise a

differential signal receiver, and balanced pair of traces should be

routed from the pins of the buck current sense resistor, RSENSE ,

as shown in figure 17 (upper panel). The ISEN+ pin and the sense

resistor ground should not be separated by simply using local via

connections to the ground plane (figure 17 lower panel). Incorrect

routing of the ISEN+ pin would likely add an offset error to the

buck current sense signal.

Star Ground

A4407

DBUCK Current path

(off-cycle)

Current path (on-cycle)

RSENSE

VIN

CIN

RLOAD

COUT1

Figure 16. Illustration of star ground connection

Figure 17. Comparison of routing paths for the traces between the

A4407 ISEN+ and ISEN– traces and the sense resistor, RSENSE

ISEN–

ISEN+

A4407

Differential

Amplifier DBUCK

(Asynchronous)

RSENSE

–

ISEN–

ISEN+

Ground plane

A4407

Differential

Amplifier DBUCK

(Asynchronous)

RSENSE

–

Correct routing of ISEN+ and ISEN– traces

(direct on same plane)

Incorrect routing of ISEN+ and ISEN– traces

(using vias to a ground plane)

2.2 MHz Constant On-T ime Buck Regulator

W ith Two External and T wo Internal Linear Regulators

A4407

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Application Circuit Performance

Application schematic is shown in Functional Block diagram.

egu

At ILOAD = 215 mA and 1.1 A

0.10 0.20 0.30 0.40 0.50 0.60 0.70 0.80 0.90 1.00 1.10

Eﬃciency (%)

Output Current, I

OUT

(A)

-0.50

-0.45

-0.40

-0.35

-0.30

-0.25

-0.20

-0.15

-0.10

-0.05

0.00

0.10 0.20 0.30 0.40 0.50 0.60 0.70 0.80 0.90 1.00 1.10

Drop (%)

Output Current, I

OUT

(A)

-0.8

-0.7

-0.6

-0.5

-0.4

-0.3

-0.2

-0.1

0.000 0.100 0.200 0.300 0.400 0.500

VOUT Percentage

Drop (%)

Output Current, I

OUT

(A)

egu

(VREG)

Effi

ency

Buck Regulator (VREG) Load Regulation Linear Regulator Load Regulation

= 8 V

= 12 V

= 16 V

= 8 V

= 16 V

V5P

3V3

1V5

Frequency (kHz)

Phase (°)

Gain (dB)

103

10010110–1

-12

-24

-36

-48

-60

200

160

120

-40

-80

-120

-160

-200

Gain 215 mA

Gain 1.1 A

Gain Margin 15 dB

Phase 215 mA

Phase Margin 215 mA (46°)

Phase Margin 1.1 A (51°)

Phase 1.1 A

Gain 0 dB ( 65 kHz)

Bill of Materials for Critical Components

This design is capable of full load, 135°C ambient, and 5.5 VBAT indefinitely with an adequate thermal solution

Component Description Package Manufacturer Part Number

Q3V3 MOSFET, 40 V, 90 A, 4.3 m, TJ 175°C DPAK Infineon IPD90N04S3-04

Q1V5 MOSFET, 30 V, 30 A, 13.5 , TJ 175°C DPAK Infineon IPD135N03LG

RSENSE

, RCL1 Resistor, 0.300 , 1/4 W, 1% 1206

RCL2 Resistor, 0.390 , 1/4 W, 1% 1206

RDROP1 Resistor, 2.2  total, 2 W total, 5% Multiple SMT components may be used in parallel or series

RDROP2 Resistor, 1.5 , 1 W, 5% 2512 Vishay/Dale CRCW25121R50JNEG

CIN1

, CIN2 Capacitor, Ceramic, 4.7 F, 50 V, 10%, X7R 1210 Murata GCM32ER71H475KA55L

OUT1 Capacitor, Ceramic, 10 F, 16 V, 10%, X7R 1206 Kemet C1206C106K4RACTU

OUT2 Capacitor, Ceramic, 0.47 F, 16 V, 10%, X7R 0603

COUT3V3, COUT1V5, COUTV5, COUTV5P Capacitor, Ceramic, 2.2 F, 16 V, 10%, X7R 1206 Murata GRM31MR71C225KA35L

DBUCK , DIN Diode, Schottky, 2 A, 40 V SMA Diodes, Inc. B240A-13-F

L1 Inductor, 10 H, 64 m, 2.39 Asat

, 165°C 7.6 x 7.6 mm Cooper/Bussman DRA73-100-R

2.2 MHz Constant On-T ime Buck Regulator

W ith Two External and T wo Internal Linear Regulators

A4407

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Startup at VBAT = 13.5 V; shows VREG (ch1, 2 V/div.), V3V3 (ch2, 2 V/div.),

V1V5 (ch3, 1 V/div.), NPOR (ch4, 2 V /div.), t = 5 ms/div.

V3V3

V1V5

NPOR

VREG

PWM at VBAT = 12 V with a 25 mA load; shows VREG (ch1, 5 V/div.),

VLX (ch2, 5 V/div.), IL (ch3, 100 mA/div.), t = 2 s/div.

VREG

VLX

PWM at VBAT = 12 V with a 1.0 A load; shows VREG (ch1, 5 V/div.),

VLX (ch2, 5 V/div.), IL (ch3, 100 mA/div.), t = 200 ns/div.

VREG

VLX

Startup at VBAT = 13.5 V; shows VREG (ch1, 2 V/div.), VV5 (ch2, 2 V/div.),

VV5P (ch3, 2 V/div.), NPOR (ch4, 2 V /div.), t = 5 ms/div.

VV5

VV5P

NPOR

VREG

Startup at VBAT = 6.5 V; shows VREG (ch1, 2 V/div.), VV5 (ch2, 2 V/div.),

VV5P (ch3, 2 V/div.), NPOR (ch4, 2 V /div.), t = 5 ms/div.

VV5

VV5P

NPOR

VREG

Startup at VBAT = 6.5 V; shows VREG (ch1, 2 V/div.), V3V3 (ch2, 2 V/div.),

V1V5 (ch3, 1 V/div.), NPOR (ch4, 2 V /div.), t = 5 ms/div.

V3V3

V1V5

NPOR

VREG

2.2 MHz Constant On-T ime Buck Regulator

W ith Two External and T wo Internal Linear Regulators

A4407

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

V3.3V

I3.3V

V3.3V transient response, 125 to 250 mA; shows V3.3V (ch1, 50 mV/div.),

I3.3V (ch2, 100 mA/div.), t = 50 s/div.

V1.5V transient response, 225 to 450 mA; shows V1.5V (ch1, 50 mV/div.),

I1.5V (ch2, 200 mA/div.), t = 50 s/div.

V1.5V

I1.5V

VV5

IV5

VV5 transient response, 100 to 200 mA; shows VV5 (ch1, 50 mV/div.),

IV5 (ch2, 100 mA/div.), t = 50 s/div.

VREG

VREG short circuit operation at VIN = 12 V; shows VREG (ch1, 2 V/div.),

IL (ch2, 500 mA/div.), t = 5 s/div.

VV5P transient response, 125 to 250 mA; shows VV5P (ch1, 50 mV/div.),

IV5P (ch2, 100 mA/div.), t = 50 s/div.

VV5P

IV5P

VREG normal (left) and overload (right) operation at VIN = 12 V; shows

VREG (ch1, 2 V/div.), IL (ch2, 250 mA/div.)

VREG

Normal operation

(before overcurrent event)

Overloaded operation

(during overcurrent condition)

2.2 MHz Constant On-T ime Buck Regulator

W ith Two External and T wo Internal Linear Regulators

A4407

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Package LP, 24-Pin TSSOP

with Exposed Thermal Pad

1.20 MAX

0.15

0.00

0.30

0.19

0.20

0.09

8º

0º

0.60 ±0.15

1.00 REF

SEATING

PLANE

C0.10

24X

0.65 BSC

0.25 BSC

7.80±0.10

4.40±0.10 6.40±0.20

GAUGE PLANE

SEATING PLANE

ATerminal #1 mark area

For Reference Only; not for tooling use (reference MO-153 ADT)

Dimensions in millimeters

Dimensions exclusive of mold flash, gate burrs, and dambar protrusions

Exact case and lead configuration at supplier discretion within limits shown

Exposed thermal pad (bottom surface)

4.32 NOM

3 NOM

0.65

6.103.00

4.32

1.65

0.45

Reference land pattern layout (reference IPC7351

TSOP65P640X120-25M); all pads a minimum of 0.20 mm from all

adjacent pads; adjust as necessary to meet application process

requirements and PCB layout tolerances; when mounting on a multilayer

PCB, thermal vias at the exposed thermal pad land can improve thermal

dissipation (reference EIA/JEDEC Standard JESD51-5)

PCB Layout Reference View

2.2 MHz Constant On-T ime Buck Regulator

W ith Two External and T wo Internal Linear Regulators

A4407

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Allegro MicroSystems, LLC reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to

permit improvements in the per for mance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that

the information being relied upon is current.

Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the

failure of that life support device or system, or to affect the safety or effectiveness of that device or system.

The in for ma tion in clud ed herein is believed to be ac cu rate and reliable. How ev er, Allegro MicroSystems, LLC assumes no re spon si bil i ty for its use;

nor for any in fringe ment of patents or other rights of third parties which may result from its use.

For the latest version of this document, visit our website:

www.allegromicro.com

Revision History

Revision Revision Date Description of Revision

Rev. 3 February 11, 2013 Update asynchronous diode description