R1LP0408CSP-7LC#B0 - Renesas Electronics

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April 1st, 2010

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Rev.2.00, May.26.2004, page 1 of 12

R1LP0408C-C Series

4M SRAM (512-kword × 8-bit)

REJ03C0077-0200Z

Rev. 2.00

May.26.2004

Description

The R1LP0408C-C is a 4-Mbit static RAM organized 512-kword × 8-bit. R1LP0408C-C Series has

realized higher density, higher performance and low power consumption by employing CMOS process

technology (6-transistor memory cell). The R1LP0408C-C Series offers low power standby power

dissipation; therefore, it is suitable for battery backup systems. It has packaged in 32-pin SOP, 32-pin

TSOP II.

Features

• Single 5 V supply: 5 V ± 10%

• Access time: 55/70 ns (max)

• Power dissipation:

 Active: 10 mW/MHz (typ)

 Standby: 4 µW (typ)

• Completely static memory.

 No clock or timing strobe required

• Equal access and cycle times

• Common data input and output.

 Three state output

• Directly TTL compatible.

 All inputs and outputs

• Battery backup operation.

• Operating temperature: −20 to +70°C

R1LP0408C-C Series

Rev.2.00, May.26.2004, page 2 of 12

Ordering Information

Type No. Access time Package

R1LP0408CSP-5SC 55 ns 525-mil 32-pin plastic SOP (32P2M-A)

R1LP0408CSP-7LC 70 ns

R1LP0408CSB-5SC 55 ns 400-mil 32-pin plastic TSOP II (32P3Y-H)

R1LP0408CSB-7LC 70 ns

R1LP0408CSC-5SC 55 ns 400-mil 32-pin plastic TSOP II reverse (32P3Y-J)

R1LP0408CSC-7LC 70 ns

R1LP0408C-C Series

Rev.2.00, May.26.2004, page 3 of 12

Pin Arrangement

A18

A16

A14

A12

I/O0

I/O1

I/O2

A15

A17

WE#

A13

A11

OE#

A10

CS#

I/O7

I/O6

I/O5

I/O4

I/O3

(Top view)

32-pin SOP

32-pin TSOP

A18

A16

A14

A12

I/O0

I/O1

I/O2

A15

A17

WE#

A13

A11

OE#

A10

CS#

I/O7

I/O6

I/O5

I/O4

I/O3

(Top view)

32-pin TSOP (reverse)

Pin Description

Pin name Function

A0 to A18 Address input

I/O0 to I/O7 Data input/output

CS# (CS) Chip select

OE# (OE) Output enable

WE# (WE) Write enable

VCC Power supply

VSS Ground

R1LP0408C-C Series

Rev.2.00, May.26.2004, page 4 of 12

Block Diagram

•

I/O0

I/O7

CS#

WE#

OE#

A3 A2A1A0 A6A5

Row

Decoder

Memory Matrix

2,048 2,048

Column I/O

Column Decoder

Input

Data

Control

Timing Pulse Generator

Read/Write Control

A4 A7

A11

A15

A18

A10

A13

A17

A16

A14

A12

LSB

MSB

LSB

MSB

R1LP0408C-C Series

Rev.2.00, May.26.2004, page 5 of 12

Operation Table

WE# CS# OE# Mode VCC current I/O0 to I/O7 Ref. cycle

× H × Not selected ISB, ISB1 High-Z 

H L H Output disable ICC High-Z 

H L L Read ICC Dout Read cycle

L L H Write ICC Din Write cycle (1)

L L L Write ICC Din Write cycle (2)

Note: H: VIH, L: VIL, ×: VIH or VIL

Absolute Maximum Ratings

Parameter Symbol Value Unit

Power supply voltage relative to VSS V

CC −0.5 to +7.0 V

Terminal voltage on any pin relative to VSS V

T −0.5*1 to VCC + 0.3*2 V

Power dissipation PT 0.7 W

Operating temperature Topr −20 to +70 °C

Storage temperature range Tstg −65 to +150 °C

Storage temperature range under bias Tbias −20 to +85 °C

Notes: 1. VT min: −3.0 V for pulse half-width ≤ 30 ns.

2. Maximum voltage is +7.0 V.

DC Operating Conditions

(Ta = −20 to +70°C)

Parameter Symbol Min Typ Max Unit

Supply voltage VCC 4.5 5.0 5.5 V

SS 0 0 0 V

Input high voltage VIH 2.2  V

CC + 0.3 V

Input low voltage VIL −0.3*1  0.8 V

Note: 1. VIL min: −3.0 V for pulse half-width ≤ 30 ns.

R1LP0408C-C Series

Rev.2.00, May.26.2004, page 6 of 12

DC Characteristics

Parameter Symbol Min Typ Max Unit Test conditions

Input leakage current |ILI|   1 µA Vin = VSS to VCC

Output leakage current |ILO|   1 µA CS# = VIH or OE# = VIH or

WE# = VIL or VI/O = VSS to VCC

Operating current ICC  1.5*1 3 mA CS# = VIL,

Others = VIH/ VIL, II/O = 0 mA

Average operating current ICC1  8*1 25 mA Min. cycle, duty = 100%,

CS# = VIL, Others = VIH/VIL

II/O = 0 mA

CC2  2*1 5 mA Cycle time = 1 µs,

duty = 100%,

II/O = 0 mA, CS# ≤ 0.2 V,

VIH ≥ VCC − 0.2 V, VIL ≤ 0.2 V

Standby current ISB  0.1*1 0.5 mA CS# = VIH

to +70°C ISB1   8 µA Vin ≥ 0 V, CS# ≥ VCC − 0.2 V

to +40°C ISB1  1.0*2 3 µA

−5SC

to +25°C ISB1  0.8*1 3 µA

to +70°C ISB1   16 µA

to +40°C ISB1  1.0*2 10 µA

Standby current

−7LC

to +25°C ISB1  0.8*1 10 µA

Output low voltage VOL   0.4 V IOL = 2.1 mA

Output high voltage VOH 2.4   V IOH = −1.0 mA

OH2 2.6   V IOH = −0.1 mA

Notes: 1. Typical values are at VCC = 5.0 V, Ta = +25°C and specified loading, and not guaranteed.

2. Typical values are at VCC = 5.0 V, Ta = +40°C and specified loading, and not guaranteed.

Capacitance

(Ta = +25°C, f = 1.0 MHz)

Parameter Symbol Min Typ Max Unit Test conditions Note

Input capacitance Cin   8 pF Vin = 0 V 1

Input/output capacitance CI/O   10 pF VI/O = 0 V 1

Note: 1. This parameter is sampled and not 100% tested.

R1LP0408C-C Series

Rev.2.00, May.26.2004, page 7 of 12

AC Characteristics

(Ta = −20 to +70°C, VCC = 5 V ± 10%, unless otherwise noted.)

Test Conditions

• Input pulse levels: VIL = 0.4 V, VIH = 2.4 V

• Input rise and fall time: 5 ns

• Input and output timing reference levels: 1.5 V

• Output load: 1 TTL Gate + CL (50 pF) (R1LP0408C-5SC)

1 TTL Gate + CL (100 pF) (R1LP0408C-7LC)

(Including scope and jig)

Read Cycle

R1LP0408C-C

-5SC -7LC

Parameter Symbol Min Max Min Max Unit Notes

Read cycle time tRC 55  70  ns

Address access time tAA  55  70 ns

Chip select access time tCO  55  70 ns

Output enable to output valid tOE  25  35 ns

Chip select to output in low-Z tLZ 10  10  ns 2

Output enable to output in low-Z tOLZ 5  5  ns 2

Chip deselect to output in high-Z tHZ 0 20 0 25 ns 1, 2

Output disable to output in high-Z tOHZ 0 20 0 25 ns 1, 2

Output hold from address change tOH 10  10  ns

R1LP0408C-C Series

Rev.2.00, May.26.2004, page 8 of 12

Write Cycle

R1LP0408C-C

-5SC -7LC

Parameter Symbol Min Max Min Max Unit Notes

Write cycle time tWC 55  70  ns

Chip selection to end of write tCW 50  60  ns 4

Address setup time tAS 0  0  ns 5

Address valid to end of write tAW 50  60  ns

Write pulse width tWP 40  50  ns 3, 12

Write recovery time tWR 0  0  ns 6

Write to output in high-Z tWHZ 0 20 0 25 ns 1, 2, 7

Data to write time overlap tDW 25  30  ns

Data hold from write time tDH 0  0  ns

Output active from end of write tOW 5  5  ns 2

Output disable to output in high-Z tOHZ 0 20 0 25 ns 1, 2, 7

Notes: 1. tHZ, tOHZ and tWHZ are defined as the time at which the outputs achieve the open circuit conditions

and are not referred to output voltage levels.

2. This parameter is sampled and not 100% tested.

3. A write occurs during the overlap (tWP) of a low CS# and a low WE#. A write begins at the later

transition of CS# going low or WE# going low. A write ends at the earlier transition of CS# going

high or WE# going high. tWP is measured from the beginning of write to the end of write.

4. tCW is measured from CS# going low to the end of write.

5. tAS is measured from the address valid to the beginning of write.

6. tWR is measured from the earlier of WE# or CS# going high to the end of write cycle.

7. During this period, I/O pins are in the output state so that the input signals of the opposite phase

to the outputs must not be applied.

8. If the CS# low transition occurs simultaneously with the WE# low transition or after the WE#

transition, the output remain in a high impedance state.

9. Dout is the same phase of the write data of this write cycle.

10. Dout is the read data of next address.

11. If CS# is low during this period, I/O pins are in the output state. Therefore, the input signals of

the opposite phase to the outputs must not be applied to them.

12. In the write cycle with OE# low fixed, tWP must satisfy the following equation to avoid a problem of

data bus contention. tWP ≥ tDW min + tWHZ max

R1LP0408C-C Series

Rev.2.00, May.26.2004, page 9 of 12

Timing Waveform

Read Timing Waveform (WE# = VIH)

OLZ

OHZ

Valid data

Valid address

High impedance

Address

CS#

OE#

Dout

R1LP0408C-C Series

Rev.2.00, May.26.2004, page 10 of 12

Write Timing Waveform (1) (OE# Clock)

OHZ

Address

OE#

CS#

WE#

Dout

Din Valid data

Valid address

High impedance

R1LP0408C-C Series

Rev.2.00, May.26.2004, page 11 of 12

Write Timing Waveform (2) (OE# Low Fixed)

Address

CS#

WE#

Dout

Din

WHZ

*11

*9 *10

Valid data

Valid address

High impedance

R1LP0408C-C Series

Rev.2.00, May.26.2004, page 12 of 12

Low VCC Data Retention Characteristics

(Ta = −20 to +70°C)

Parameter Symbol Min Typ Max Unit Test conditions*3

VCC for data retention VDR 2   V CS# ≥ VCC − 0.2 V, Vin ≥ 0 V

to +70°C ICCDR   8 µA VCC = 3.0 V, Vin ≥ 0 V

to +40°C ICCDR  1.0*23 µA CS# ≥ VCC − 0.2 V

−5SC

to +25°C ICCDR  0.8*13 µA

to +70°C ICCDR   16 µA

to +40°C ICCDR  1.0*210 µA

Data

retention

current

−7LC

to +25°C ICCDR  0.8*110 µA

Chip deselect to data retention time tCDR 0   ns See retention waveform

Operation recovery time tR t

RC*4  ns

Notes: 1. Typical values are at VCC = 3.0 V, Ta = +25°C and specified loading, and not guaranteed.

2. Typical values are at VCC = 3.0 V, Ta = +40°C and specified loading, and not guaranteed.

3. CS# controls address buffer, WE # buffer, OE# buffer, and Din buffer. In data retention mode,

Vin levels (address, WE#, OE#, I/O) can be in the high impedance state.

4. tRC = read cycle time.

Low VCC Data Retention Timing Waveform (CS# Controlled)

4.5 V

2.2 V

0 V

CS#

CDR

CS# ≥ V

– 0.2 V

Data retention mode

Revision History R1LP0408C-C Series Data Sheet

Contents of Modification Rev. Date

Page Description

1.00 Aug.01.2003  Initial issue

2.00 May.26.2004 6

DC characteristics

−5SC and −7LC items’ description are divided.

Low VCC Data Retention Characteristics

−5SC and −7LC items’ description are divided.

Low VCC Data Retention Timing Waveform

2.4 V to 2.2 V

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