OPA2141
OPA141
OPA4141
200nV/div
Time(1s/div)
Competitor’sDevice
OPAx141
V = 18V
SUPPLY ±
OPA141
OPA2141
OPA4141
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SBOS510B –MARCH 2010–REVISED MAY 2010
Single-Supply, 10MHz, Rail-to-Rail Output,
Low-Noise, JFET Amplifier
Check for Samples: OPA141,OPA2141,OPA4141
1FEATURES DESCRIPTION
2• Low Supply Current: 2.3mA max The OPA141, OPA2141, and OPA4141 amplifier
family is a series of low-power JFET input amplifiers
• Low Offset Drift: 10mV/°C max that feature good drift and low input bias current. The
• Low Input Bias Current: 20pA max rail-to-rail output swing and input range that includes
• Very Low 1/f Noise: 250nVPP V– allow designers to take advantage of the
• Low Noise: 6.5nV/√Hz low-noise characteristics of JFET amplifiers while
also interfacing to modern, single-supply, precision
• Wide Bandwidth: 10MHz analog-to-digital converters (ADCs) and
• Slew Rate: 20V/msdigital-to-analog converters (DACs).
• Input Voltage Range Includes V– The OPA141 achieves 10MHz unity-gain bandwidth
• Rail-to-Rail Output and 20V/ms slew rate while consuming only 1.8mA
• Single-Supply Operation: 4.5V to 36V (typ) of quiescent current. It runs on a single 4.5 to
36V supply or dual ±2.25V to ±18V supplies.
• Dual-Supply Operation: ±2.25V to ±18V All versions are fully specified from –40°C to +125°C
• No Phase Reversal for use in the most challenging environments. The
• MSOP-8, TSSOP Packages OPA141 (single) and OPA2141 (dual) versions are
available in both MSOP-8 and SO-8 packages; the
APPLICATIONS OPA4141 (quad) is available in the SO-14 and
• Battery-Powered Instruments TSSOP-14 packages.
• Industrial Controls RELATED PRODUCTS
• Medical Instrumentation FEATURES PRODUCT
• Photodiode Amplifiers Precision, Low-Power, 10MHz FET
• Active Filters OPA140(1)
Input Industrial Op Amp
• Data Acquisition Systems 2.2nV/√Hz, Low-Power, 36V
• Portable Audio Operational Amplifier in SOT-23 OPA209(1)
Package
• Automatic Test Systems Low-Noise, High-Precision, OPA827
JFET-Input Operational Amplifier
0.1Hz to 10Hz NOISE Low-Noise, Low IQPrecision OPA376
Operational Amplifier
High-Speed, FET-Input Operational OPA132
Amplifier
1. Preview product; estimated availability in Q3
2010.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2010, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
OPA141
OPA2141
OPA4141
SBOS510B –MARCH 2010–REVISED MAY 2010
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ABSOLUTE MAXIMUM RATINGS(1)
Over operating free-air temperature range (unless otherwise noted). VALUE UNIT
Supply Voltage ±20 V
Voltage(2) (V–) –0.5 to (V+) +0.5 V
Signal Input
Terminals Current(2) ±10 mA
Output Short-Circuit(3) Continuous
Operating Temperature, TA–55 to +150 °C
Storage Temperature, TA–65 to +150 °C
Junction Temperature, TJ+150 °C
Human Body Model (HBM) 2000 V
ESD Ratings Charged Device Model (CDM) 500 V
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not supported.
(2) Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5V beyond the supply rails should
be current limited to 10 mA or less.
(3) Short-circuit to VS/2 (ground in symmetrical dual-supply setups), one amplifier per package.
PACKAGE INFORMATION(1)
PRODUCT PACKAGE-LEAD PACKAGE DESIGNATOR PACKAGE MARKING
SO-8 D O141A
OPA141 MSOP-8 DGK 141
SO-8 D O2141A
OPA2141 MSOP-8 DGK 2141
TSSOP-14 PW O4141A
OPA4141 SO-14 D O4141AG4
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the
device product folder at www.ti.com.
2Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): OPA141 OPA2141 OPA4141
OPA141
OPA2141
OPA4141
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SBOS510B –MARCH 2010–REVISED MAY 2010
THERMAL INFORMATION OPA141, OPA141,
OPA2141 OPA2141
THERMAL METRIC UNITS
D (SO) DGK (MSOP)(1)
8 8
qJA Junction-to-ambient thermal resistance(2) 160 180
qJC(top) Junction-to-case(top) thermal resistance(3) 75 55
qJB Junction-to-board thermal resistance(4) 60 130 °C/W
yJT Junction-to-top characterization parameter(5) 9 n/a
yJB Junction-to-board characterization parameter(6) 50 120
qJC(bottom) Junction-to-case(bottom) thermal resistance(7) n/a n/a
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific
JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, yJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining qJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, yJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining qJA , using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
THERMAL INFORMATION OPA4141 OPA4141
THERMAL METRIC D (SO) PW (TSSOP)(1) UNITS
14 14
qJA Junction-to-ambient thermal resistance(2) 97 135
qJC(top) Junction-to-case(top) thermal resistance(3) 56 45
qJB Junction-to-board thermal resistance(4) 53 66 °C/W
yJT Junction-to-top characterization parameter(5) 19 n/a
yJB Junction-to-board characterization parameter(6) 46 60
qJC(bottom) Junction-to-case(bottom) thermal resistance(7) n/a n/a
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific
JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, yJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining qJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, yJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining qJA , using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Copyright © 2010, Texas Instruments Incorporated 3
Product Folder Link(s): OPA141 OPA2141 OPA4141
OPA141
OPA2141
OPA4141
SBOS510B –MARCH 2010–REVISED MAY 2010
www.ti.com
ELECTRICAL CHARACTERISTICS: VS= +4.5V to +36V; ±2.25V to ±18V
Boldface limits apply over the specified temperature range, TA= –40°C to +125°C.
At TA= +25°C, RL= 2kΩconnected to midsupply, VCM = VOUT = midsupply, unless otherwise noted.
OPA141, OPA2141, OPA4141
PARAMETER CONDITIONS MIN TYP MAX UNIT
OFFSET VOLTAGE
Offset Voltage, RTI VOS VS= ±18V ±1 ±3.5 mV
Over Temperature VS= ±18V ±4.3 mV
Drift dVOS/dT VS= ±18V ±2 ±10 mV/°C
vs Power Supply PSRR VS= ±2.25V to ±18V ±0.14 ±2 mV/V
xxxOver Temperature VS= ±2.25V to ±18V ±4 mV/V
INPUT BIAS CURRENT
Input Bias Current IB±2 ±20 pA
Over Temperature ±5 nA
Input Offset Current IOS ±2 ±20 pA
Over Temperature ±1 nA
NOISE
Input Voltage Noise
f = 0.1Hz to 10Hz 250 nVPP
f = 0.1Hz to 10Hz 42 nVRMS
Input Voltage Noise Density en
f = 10Hz 12 nV/√Hz
f = 100Hz 6.5 nV/√Hz
f = 1kHz 6.5 nV/√Hz
Input Current Noise Density in
f = 1kHz 0.8 fA/√Hz
INPUT VOLTAGE RANGE
Common-Mode Voltage Range VCM (V–) –0.1 (V+)–3.5 V
VS= ±18V, VCM = (V–) –0.1V
Common-Mode Rejection Ratio CMRR 120 126 dB
to (V+) – 3.5V
VS= ±18V, VCM = (V–) –0.1V
Over Temperature 120 dB
to (V+) – 3.5V
INPUT IMPEDANCE
Differential 1013 || 8 Ω|| pF
Common-Mode VCM = (V–) –0.1V to (V+) –3.5V 1013 || 6 Ω|| pF
OPEN-LOOP GAIN
Open-Loop Voltage Gain AOL VO= (V–)+0.35V to (V+)–0.35V, RL= 2kΩ114 126 dB
Over Temperature VO= (V–)+0.35V to (V+)–0.35V, RL= 2kΩ108 dB
FREQUENCY RESPONSE
Gain Bandwidth Product BW 10 MHz
Slew Rate 20 V/ms
Settling Time, 12-bit (0.024) 880 ns
THD+N 1kHz, G = 1, VO= 3.5VRMS 0.00005 %
Overload Recovery Time 600 ns
4Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): OPA141 OPA2141 OPA4141
OPA141
OPA2141
OPA4141
www.ti.com
SBOS510B –MARCH 2010–REVISED MAY 2010
ELECTRICAL CHARACTERISTICS: VS= +4.5V to +36V; ±2.25V to ±18V (continued)
Boldface limits apply over the specified temperature range, TA= –40°C to +125°C.
At TA= +25°C, RL= 2kΩconnected to midsupply, VCM = VOUT = midsupply, unless otherwise noted.
OPA141, OPA2141, OPA4141
PARAMETER CONDITIONS MIN TYP MAX UNIT
OUTPUT
Voltage Output VORL= 10kΩ(V–)+0.2 (V+)–0.2 V
RL= 2kΩ(V–)+0.35 (V+)–0.35 V
Short-Circuit Current ISC Source +36 mA
Sink –30 mA
Capacitive Load Drive CLOAD See Figure 19 and Figure 20
Open-Loop Output Impedance ROf = 1MHz, IO= 0 (See Figure 18) 10 Ω
POWER SUPPLY
Specified Voltage Range VS±2.25 ±18 V
Quiescent Current IQIO= 0mA 1.8 2.3 mA
(per amplifier)
Over Temperature 3.1 mA
CHANNEL SEPARATION
Channel Separation At dc 0.02 mV/V
At 100kHz 10 mV/V
TEMPERATURE RANGE
Specified Range –40 +125 °C
Operating Range –55 +150 °C
Copyright © 2010, Texas Instruments Incorporated 5
Product Folder Link(s): OPA141 OPA2141 OPA4141
1
2
3
4
8
7
6
5
NC(1)
V+
Out
NC(1)
NC(1)
-In
+In
V-
(1)NCdenotesnointernalconnection.
OutA
-InA
+InA
V+
+InB
-InB
OutB
1
2
3
4
5
6
7
14
13
12
11
10
9
8
DA
B C
OutD
-InD
+InD
V-
+InC
-InC
OutC
1
2
3
4
8
7
6
5
V+
OutB
-InB
+InB
OUTA
-InA
+InA
V-
A
B
IN-
Pre-OutputDriver OUT
IN+
V+
V-
OPA141
OPA2141
OPA4141
SBOS510B –MARCH 2010–REVISED MAY 2010
www.ti.com
PIN ASSIGNMENTS
OPA141 OPA4141
SO-8, MSOP-8 SO-14, TSSOP-14
(TOP VIEW) (TOP VIEW)
OPA2141
SO-8, MSOP-8
(TOP VIEW)
SIMPLIFIED BLOCK DIAGRAM
Figure 1.
6Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): OPA141 OPA2141 OPA4141
OPA141
OPA2141
OPA4141
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SBOS510B –MARCH 2010–REVISED MAY 2010
TYPICAL CHARACTERISTICS SUMMARY
TABLE OF GRAPHS
Table 1. Characteristic Performance Measurements
DESCRIPTION FIGURE
Offset Voltage Production Distribution Figure 2
Offset Voltage Drift Distribution Figure 3
Offset Voltage vs Common-Mode Voltage (Max Supply) Figure 4
IBand IOS vs Common-Mode Voltage Figure 5
Output Voltage Swing vs Output Current Figure 6
CMRR and PSRR vs Frequency (RTI) Figure 7
Common-Mode Rejection Ratio vs Temperature Figure 8
0.1Hz to 10Hz Noise Figure 9
Input Voltage Noise Density vs Frequency Figure 10
THD+N Ratio vs Frequency (80kHz AP Bandwidth) Figure 11
THD+N Ratio vs Output Amplitude Figure 12
Quiescent Current vs Temperature Figure 13
Quiescent Current vs Supply Voltage Figure 14
Gain and Phase vs Frequency Figure 15
Closed-Loop Gain vs Frequency Figure 16
Open-Loop Gain vs Temperature Figure 17
Open-Loop Output Impedance vs Frequency Figure 18
Small-Signal Overshoot vs Capacitive Load (G = +1) Figure 19
Small-Signal Overshoot vs Capacitive Load (G = –1) Figure 20
No Phase Reversal Figure 21
Positive Overload Recovery Figure 22
Negative Overload Recovery Figure 23
Small-Signal Step Response (G = +1) Figure 24
Small-Signal Step Response (G = –1) Figure 25
Large-Signal Step Response (G = +1) Figure 26
Large-Signal Step Response (G = –1) Figure 27
Short-Circuit Current vs Temperature Figure 28
Maximum Output Voltage vs Frequency Figure 29
Channel Separation vs Frequency Figure 30
Copyright © 2010, Texas Instruments Incorporated 7
Product Folder Link(s): OPA141 OPA2141 OPA4141
Population
0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
3.0
3.3
3.6
3.9
4.2
4.5
4.8
5.1
5.4
5.7
6.0
OffsetVoltageDrift( V/ C)m°
-3300
-3000
-2700
-2400
-2100
-1800
-1500
-1200
-900
-600
-300
0
300
600
900
1200
1500
1800
2100
2400
2700
3000
3300
OffsetVoltage( V)m
Population
-18 -12 -6 0 6 12
V (V)
CM
3500
2500
1500
500
500
1500
2500
3500
-
-
-
-
0
V ( V)m
OS
10TypicalUnitsShown
18
OutputVoltage(V)
0 10 20 30 40 50
OutputCurrent(mA)
+85 C°
+25 C°
-40 C°
18.0
17.5
17.0
16.5
16.0
-16.0
16.5
17.0
17.5
18.0
-
-
-
-
+125 C°
160
140
120
100
80
60
40
20
0
Common-ModeRejectionRatio(dB)
Power-SupplyRejectionRatio(dB)
1 10 100 1k 10k 100k 1M 10M 100M
Frequency(Hz)
CMRR
+PSRR
-PSRR
OPA141
OPA2141
OPA4141
SBOS510B –MARCH 2010–REVISED MAY 2010
www.ti.com
TYPICAL CHARACTERISTICS
At TA= +25°C, VS= ±18V, RL= 2kΩconnected to midsupply, VCM = VOUT = midsupply, unless otherwise noted.
OFFSET VOLTAGE PRODUCTION DISTRIBUTION OFFSET VOLTAGE DRIFT DISTRIBUTION
Figure 2. Figure 3.
OFFSET VOLTAGE vs COMMON-MODE VOLTAGE IBAND IOS vs COMMON-MODE VOLTAGE
Figure 4. Figure 5.
OUTPUT VOLTAGE SWING vs OUTPUT CURRENT
(MAX SUPPLY) CMRR AND PSRR vs FREQUENCY (Referred to Input)
Figure 6. Figure 7.
8Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): OPA141 OPA2141 OPA4141
100nV/div
Time(1s/div)
0.12
0.10
0.08
0.06
0.04
0.02
0
CMRR( V/V)m
-50 -25
-75 0 25 50 75 100 125 150
Temperature( C)
°
0.001
0.0001
0.00001
-100
-
-
120
140
TotalHarmonicDistortion+Noise(%)
TotalHarmonicDistortion+Noise(dB)
10 100 1k 10k 20k
Frequency(Hz)
G=+1
R =2k
LW
G= -1
R =2k
LW
V =3V
BW=80kHz
OUT RMS
VoltageNoiseDensity(nV/ )ÖHz
0.1
Frequency(Hz)
100k101 100 1k 10k
100
10
1
0.01
0.001
0.0001
0.00001
TotalHarmonicDistortion+Noise(%)
TotalHarmonicDistortion+Noise(dB)
0.1 1 10 20
OutputAmplitude(V )
RMS
-
-
-
80
100
120
140-
BW=80kHz
1kHzSignal
G= 1,-R =2k
R =2k
L
L
W
WG=+1,
2.5
2.0
1.5
1.0
0.5
0
I (mA)
Q
-50 -25
-75 0 25 50 75 100 125 150
Temperature( C)
°
OPA141
OPA2141
OPA4141
www.ti.com
SBOS510B –MARCH 2010–REVISED MAY 2010
TYPICAL CHARACTERISTICS (continued)
At TA= +25°C, VS= ±18V, RL= 2kΩconnected to midsupply, VCM = VOUT = midsupply, unless otherwise noted.
COMMON-MODE REJECTION RATIO vs TEMPERATURE 0.1Hz to 10Hz NOISE
Figure 8. Figure 9.
INPUT VOLTAGE NOISE DENSITY vs FREQUENCY THD+N RATIO vs FREQUENCY
Figure 10. Figure 11.
THD+N RATIO vs OUTPUT AMPLITUDE QUIESCENT CURRENT vs TEMPERATURE
Figure 12. Figure 13.
Copyright © 2010, Texas Instruments Incorporated 9
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140
120
100
80
60
40
20
0
20-
180
135
90
45
0
Gain(dB)
Phase(degrees)
10 100 1k 10k 100k 1M 10M 100M
Frequency(Hz)
Phase
Gain
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0
I (mA)
Q
048 12 16 20 24 28 32 36
SupplyVoltage(V)
SpecifiedSupply-VoltageRange
30
20
10
0
10
20
-
-
Gain(dB)
100k 1M 10M 100M
Frequency(Hz)
G=+10
G=+1
G= 1-
-50 -25
-75 0 25 50 75 100 125 150
Temperature( C)
°
0
0.2
0.4
0.6
0.8
1.0
-
-
-
-
-
-
-
1.2
1.4
A ( V/V)m
OL
2k LoadW
10k LoadW
Z ( )W
O
10
Frequency(Hz)
100M
100 1k 10k 100k 10M1M
1k
100
10
1
40
35
30
25
20
15
10
5
0
Overshoot(%)
0 100 200 300 400 500 600 700 800 900 1000
CapacitiveLoad(pF)
R =0W
OUT
R =24W
OUT
+15V
-15V
ROUT
CL
OPA141
RL
G=+1
R =51W
OUT
OPA141
OPA2141
OPA4141
SBOS510B –MARCH 2010–REVISED MAY 2010
www.ti.com
TYPICAL CHARACTERISTICS (continued)
At TA= +25°C, VS= ±18V, RL= 2kΩconnected to midsupply, VCM = VOUT = midsupply, unless otherwise noted.
QUIESCENT CURRENT vs SUPPLY VOLTAGE GAIN AND PHASE vs FREQUENCY
Figure 14. Figure 15.
CLOSED-LOOP GAIN vs FREQUENCY OPEN-LOOP GAIN vs TEMPERATURE
Figure 16. Figure 17.
SMALL-SIGNAL OVERSHOOT
OPEN-LOOP OUTPUT IMPEDANCE vs FREQUENCY vs CAPACITIVE LOAD (100mV Output Step)
Figure 18. Figure 19.
10 Copyright © 2010, Texas Instruments Incorporated
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Output
Output
Time(0.4 s/div)m
5V/div
+18V
-18V
37VPP
SineWave
( 18.5V)±
OPA141
45
40
35
30
25
20
15
10
5
0
Overshoot(%)
0 100 200 300 400 500 600 700 800 900 1000
CapacitiveLoad(pF)
R =0W
OUT
R =24W
OUT
R =51W
OUT
OPA141
R =
I2kW
ROUT
CL
RF=2kW
+15V
-15V
G= 1-
Time(0.4 s/div)m
2kW
20kW
VIN
VOUT
OPA141
5V/div
VIN
VOUT
G=+10
Time(0.4 s/div)m
2kW
20kW
VIN
VOUT
OPA141
5V/div
VIN
VOUT G= 10-
Time(100ns/div)
20mV/div
C =100pF
L
+15V
-15V
R 2kW
F=R 2kW
I=
CL
OPA141
G= 1-
20mV/div
Time(100ns/div)
C =100pF
L
+15V
-15V CL
RL
OPA141
G=+1
OPA141
OPA2141
OPA4141
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SBOS510B –MARCH 2010–REVISED MAY 2010
TYPICAL CHARACTERISTICS (continued)
At TA= +25°C, VS= ±18V, RL= 2kΩconnected to midsupply, VCM = VOUT = midsupply, unless otherwise noted.
SMALL-SIGNAL OVERSHOOT
vs CAPACITIVE LOAD (100mV Output Step) NO PHASE REVERSAL
Figure 20. Figure 21.
POSITIVE OVERLOAD RECOVERY NEGATIVE OVERLOAD RECOVERY
Figure 22. Figure 23.
SMALL-SIGNAL STEP RESPONSE SMALL-SIGNAL STEP RESPONSE
(100mV) (100mV)
Figure 24. Figure 25.
Copyright © 2010, Texas Instruments Incorporated 11
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2V/div
Time(400ns/div)
G=+1
C =100pF
L
2V/div
Time(400ns/div)
G= 1
C =100pF
-
L
35
30
25
20
15
10
5
0
OutputVoltage(V )
PP
10k 100k 1M 10M
Frequency(Hz)
V = 2.25V
S±
V = 5V
S±
V = 15V
S±
Maximumoutput
voltagerange
withoutslew-rate
induceddistortion
-
-
-
-
-
-
-
80
90
100
110
120
130
140
ChannelSeparation(dB)
10
Frequency(Hz)
100k
100 1k 10k
V = 15V
S
V =3V
OUT RMS
G=+1
±
R =2kW
L
R =600W
L
L
R =5kW
OPA141
OPA2141
OPA4141
SBOS510B –MARCH 2010–REVISED MAY 2010
www.ti.com
TYPICAL CHARACTERISTICS (continued)
At TA= +25°C, VS= ±18V, RL= 2kΩconnected to midsupply, VCM = VOUT = midsupply, unless otherwise noted.
LARGE-SIGNAL STEP RESPONSE LARGE-SIGNAL STEP RESPONSE
Figure 26. Figure 27.
SHORT-CIRCUIT CURRENT vs TEMPERATURE MAXIMUM OUTPUT VOLTAGE vs FREQUENCY
Figure 28. Figure 29.
CHANNEL SEPARATION vs FREQUENCY
Figure 30.
12 Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): OPA141 OPA2141 OPA4141
100k 1M
SourceResistance,R (W)
S
100 1k 10k
10k
1k
100
10
1
VotlageNoiseSpectralDensity,EO
RS
EO
E =e
O n n S S
+(i R ) +4kTR
2 2 2
ResistorNoise
OPA211
OPA141
OPA141
OPA2141
OPA4141
www.ti.com
SBOS510B –MARCH 2010–REVISED MAY 2010
APPLICATION INFORMATION
with total circuit noise calculated. The op amp itself
The OPA141, OPA2141, and OPA4141 are unity-gain contributes both a voltage noise component and a
stable, operational amplifiers with very low noise, current noise component. The voltage noise is
input bias current, and input offset voltage. commonly modeled as a time-varying component of
Applications with noisy or high-impedance power the offset voltage. The current noise is modeled as
supplies require decoupling capacitors placed close the time-varying component of the input bias current
to the device pins. In most cases, 0.1mF capacitors and reacts with the source resistance to create a
are adequate. Figure 1 shows a simplified schematic voltage component of noise. Therefore, the lowest
of the OPA141. noise op amp for a given application depends on the
source impedance. For low source impedance,
OPERATING VOLTAGE current noise is negligible, and voltage noise
generally dominates. The OPA141, OPA2141, and
The OPA141, OPA2141, and OPA4141 series of op OPA4141 family has both low voltage noise and
amps can be used with single or dual supplies from extremely low current noise because of the FET input
an operating range of VS= +4.5V (±2.25V) and up to of the op amp. As a result, the current noise
VS= +36V (±18V). These devices do not require contribution of the OPAx141 series is negligible for
symmetrical supplies; they only require a minimum any practical source impedance, which makes it the
supply voltage of +4.5V (±2.25V). For VSless than better choice for applications with high source
±3.5V, the common-mode input range does not impedance.
include midsupply. Supply voltages higher than +40V
can permanently damage the device; see the The equation in Figure 31 shows the calculation of
Absolute Maximum Ratings table. Key parameters the total circuit noise, with these parameters:
are specified over the operating temperature range, • en= voltage noise
TA= –40°C to +125°C. Key parameters that vary over • In= current noise
the supply voltage or temperature range are shown in
the Typical Characteristics section of this data sheet. • RS= source impedance
• k = Boltzmann's constant = 1.38 × 10–23 J/K
CAPACITIVE LOAD AND STABILITY • T = temperature in degrees Kelvin (K)
The dynamic characteristics of the OPAx141 have For more details on calculating noise, see the section
been optimized for commonly encountered gains, on Basic Noise Calculations.
loads, and operating conditions. The combination of
low closed-loop gain and high capacitive loads
decreases the phase margin of the amplifier and can
lead to gain peaking or oscillations. As a result,
heavier capacitive loads must be isolated from the
output. The simplest way to achieve this isolation is to
add a small resistor (ROUT equal to 50Ω, for example)
in series with the output.
Figure 19 and Figure 20 illustrate graphs of
Small-Signal Overshoot vs Capacitive Load for
several values of ROUT. Also, refer to Applications
Bulletin AB-028 (literature number SBOA015,
available for download from the TI web site) for
details of analysis techniques and application circuits.
NOISE PERFORMANCE
Figure 31. Noise Performance of the OPA141 and
Figure 31 shows the total circuit noise for varying OPA211 in Unity-Gain Buffer Configuration
source impedances with the operational amplifier in a
unity-gain configuration (with no feedback resistor
network and therefore no additional noise
contributions). The OPA141 and OPA211 are shown
Copyright © 2010, Texas Instruments Incorporated 13
Product Folder Link(s): OPA141 OPA2141 OPA4141
R1
R2
EO
R1
R2
EO
RS
VS
RS
VS
A)NoiseinNoninvertingGainConfiguration
B)NoiseinInvertingGainConfiguration
Noiseattheoutput:
Wheree =
S4kTRS
4kTR1
4kTR2
=thermalnoiseofRS
=thermalnoiseofR1
=thermalnoiseofR2
e =
1
e =
2
Noiseattheoutput:
E =
O
21+ R2
R +R
1 S
R2
R +R
1 S
2 22
Wheree =
S4kTRS
4kTR1
4kTR2
=thermalnoiseofRS
=thermalnoiseofR1
=thermalnoiseofR2
e =
1
e =
2
R2
R +R
1 S
2
1+ R2
R1
1+ R2
R1
2
R2
R1
2
e +e +
1 2
2 2
E =
O
2e +
n
2es
2
e +e +
1 2
2 2 es
2
e +
n
2
OPA141
OPA2141
OPA4141
SBOS510B –MARCH 2010–REVISED MAY 2010
www.ti.com
BASIC NOISE CALCULATIONS Figure 32 illustrates both noninverting (A) and
inverting (B) op amp circuit configurations with gain.
Low-noise circuit design requires careful analysis of In circuit configurations with gain, the feedback
all noise sources. External noise sources can network resistors also contribute noise. In general,
dominate in many cases; consider the effect of the current noise of the op amp reacts with the
source resistance on overall op amp noise feedback resistors to create additional noise
performance. Total noise of the circuit is the components. However, the extremely low current
root-sum-square combination of all noise noise of the OPAx141 means that its current noise
components. contribution can be neglected.
The resistive portion of the source impedance The feedback resistor values can generally be
produces thermal noise proportional to the square chosen to make these noise sources negligible. Note
root of the resistance. This function is plotted in that low impedance feedback resistors load the
Figure 31. The source impedance is usually fixed; output of the amplifier. The equations for total noise
consequently, select the op amp and the feedback are shown for both configurations.
resistors to minimize the respective contributions to
the total noise. space
For the OPAx141 series of operational amplifiers at 1kHz, en= 6.5nV/√Hz.
Figure 32. Noise Calculation in Gain Configurations
14 Copyright © 2010, Texas Instruments Incorporated
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OPA2141
OPA4141
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SBOS510B –MARCH 2010–REVISED MAY 2010
PHASE-REVERSAL PROTECTION Although the output current is limited by internal
protection circuitry, accidental shorting of one or more
The OPA141, OPA2141, and OPA4141 family has output channels of a device can result in excessive
internal phase-reversal protection. Many FET- and heating. For instance, when an output is shorted to
bipolar-input op amps exhibit a phase reversal when mid-supply, the typical short-circuit current of 36mA
the input is driven beyond its linear common-mode leads to an internal power dissipation of over 600mW
range. This condition is most often encountered in at a supply of ±18V.
noninverting circuits when the input is driven beyond
the specified common-mode voltage range, causing In the case of a dual OPA2141 in an MSOP-8
the output to reverse into the opposite rail. The input package (thermal resistance qJA = 180°C/W), such
circuitry of the OPA141, OPA2141, and OPA4141 power dissipation would lead the die temperature to
prevents phase reversal with excessive be 220°C above ambient temperature, when both
common-mode voltage; instead, the output limits into channels are shorted. This temperature increase
the appropriate rail (see Figure 21). significantly decreases the operating life of the
device.
OUTPUT CURRENT LIMIT In order to prevent excessive heating, the OPAx141
series has an internal thermal shutdown circuit, which
The output current of the OPAx141 series is limited shuts down the device if the die temperature exceeds
by internal circuitry to +36mA/–30mA approximately +180°C. Once this thermal shutdown
(sourcing/sinking), to protect the device if the output circuit activates, a built-in hysteresis of 15°C ensures
is accidentally shorted. This short-circuit current that the die temperature must drop to approximately
depends on temperature, as shown in Figure 28.+165°C before the device switches on again.
POWER DISSIPATION AND THERMAL Additional consideration should be given to the
PROTECTION combination of maximum operating voltage,
maximum operating temperature, load, and package
The OPAx141 series of op amps are capable of type. Figure 33 and Figure 34 show several practical
driving 2kΩloads with power-supply voltages of up to considerations when evaluating the OPA2141 (dual
±18V over the specified temperature range. In a version) and the OPA4141 (quad version).
single-supply configuration, where the load is
connected to the negative supply voltage, the As an example, the OPA4141 has a maximum total
minimum load resistance is 2.8kΩat a supply voltage quiescent current of 12.4mA (3.1mA/channel) over
of +36V. For lower supply voltages (either temperature. The TSSOP-14 package has a typical
single-supply or symmetrical supplies), a lower load thermal resistance of 135°C/W. This parameter
resistance may be used, as long as the output current means that because the junction temperature should
does not exceed 13mA; otherwise, the device not exceed 150°C in order to ensure reliable
short-circuit current protection circuit may activate. operation, either the supply voltage must be reduced,
or the ambient temperature should remain low
Internal power dissipation increases when operating enough so that the junction temperature does not
at high supply voltages. Copper leadframe exceed 150°C. This condition is illustrated in
construction used in the OPA141, OPA2141, and Figure 33 for various package types. Moreover,
OPA4141 series devices improves heat dissipation resistive loading of the output causes additional
compared to conventional materials. Printed circuit power dissipation and thus self-heating, which also
board (PCB) layout can also help reduce a possible must be considered when establishing the maximum
increase in junction temperature. Wide copper traces supply voltage or operating temperature. To this end,
help dissipate the heat by acting as an additional Figure 34 shows the maximum supply voltage versus
heatsink. Temperature rise can be further minimized temperature for a worst-case dc load resistance of
by soldering the devices directly to the PCB rather 2kΩ.
than using a socket.
Copyright © 2010, Texas Instruments Incorporated 15
Product Folder Link(s): OPA141 OPA2141 OPA4141
OPA141
OPA2141
OPA4141
SBOS510B –MARCH 2010–REVISED MAY 2010
www.ti.com
functions have electrical stress limits determined by
the voltage breakdown characteristics of the
particular semiconductor fabrication process and
specific circuits connected to the pin. Additionally,
internal electrostatic discharge (ESD) protection is
built into these circuits to protect them from
accidental ESD events both before and during
product assembly.
It is helpful to have a good understanding of this
basic ESD circuitry and its relevance to an electrical
overstress event. See Figure 35 for an illustration of
the ESD circuits contained in the OPAx141 series
(indicated by the dashed line area). The ESD
protection circuitry involves several current-steering
diodes connected from the input and output pins and
routed back to the internal power-supply lines, where
they meet at an absorption device internal to the
operational amplifier. This protection circuitry is
Figure 33. Maximum Supply Voltage vs intended to remain inactive during normal circuit
Temperature (OPA2141 and OPA4141), Quiescent operation.
Condition An ESD event produces a short duration,
high-voltage pulse that is transformed into a short
duration, high-current pulse as it discharges through
a semiconductor device. The ESD protection circuits
are designed to provide a current path around the
operational amplifier core to prevent it from being
damaged. The energy absorbed by the protection
circuitry is then dissipated as heat.
When an ESD voltage develops across two or more
of the amplifier device pins, current flows through one
or more of the steering diodes. Depending on the
path that the current takes, the absorption device
may activate. The absorption device has a trigger, or
threshold voltage, that is above the normal operating
voltage of the OPAx141 but below the device
breakdown voltage level. Once this threshold is
exceeded, the absorption device quickly activates
and clamps the voltage across the supply rails to a
safe level.
Figure 34. Maximum Supply Voltage vs When the operational amplifier connects into a circuit
Temperature (OPA2141 and OPA4141), Maximum such as the one Figure 35 shows, the ESD protection
DC Load components are intended to remain inactive and not
become involved in the application circuit operation.
However, circumstances may arise where an applied
ELECTRICAL OVERSTRESS voltage exceeds the operating voltage range of a
Designers often ask questions about the capability of given pin. Should this condition occur, there is a risk
an operational amplifier to withstand electrical that some of the internal ESD protection circuits may
overstress. These questions tend to focus on the be biased on, and conduct current. Any such current
device inputs, but may involve the supply voltage pins flow occurs through steering diode paths and rarely
or even the output pin. Each of these different pin involves the absorption device.
16 Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): OPA141 OPA2141 OPA4141
RF
OpAmp
Core
RI
RL
V(1)
IN
ID
-In
Out
+In
ESDCurrent-
SteeringDiodes
Edge-TriggeredESD
AbsorptionCircuit
+VS
+V
-V
-VS
OPA141
RS
(3)
TVS(2)
TVS(2)
OPA141
OPA2141
OPA4141
www.ti.com
SBOS510B –MARCH 2010–REVISED MAY 2010
Figure 35 depicts a specific example where the input Again, it depends on the supply characteristic while at
voltage, VIN, exceeds the positive supply voltage 0V, or at a level below the input signal amplitude. If
(+VS) by 500mV or more. Much of what happens in the supplies appear as high impedance, then the
the circuit depends on the supply characteristics. If operational amplifier supply current may be supplied
+VScan sink the current, one of the upper input by the input source via the current steering diodes.
steering diodes conducts and directs current to +VS. This state is not a normal bias condition; the amplifier
Excessively high current levels can flow with most likely will not operate normally. If the supplies
increasingly higher VIN. As a result, the datasheet are low impedance, then the current through the
specifications recommend that applications limit the steering diodes can become quite high. The current
input current to 10mA. level depends on the ability of the input source to
deliver current, and any resistance in the input path.
If the supply is not capable of sinking the current, VIN
may begin sourcing current to the operational If there is an uncertainty about the ability of the
amplifier, and then take over as the source of positive supply to absorb this current, external zener diodes
supply voltage. The danger in this case is that the may be added to the supply pins as shown in
voltage can rise to levels that exceed the operational Figure 35. The zener voltage must be selected such
amplifier absolute maximum ratings. that the diode does not turn on during normal
operation.
Another common question involves what happens to
the amplifier if an input signal is applied to the input However, its zener voltage should be low enough so
while the power supplies +VSand/or –VSare at 0V. that the zener diode conducts if the supply pin begins
to rise above the safe operating supply voltage level.
(1) VIN = +VS+ 500mV.
(2) TVS: +VS(max) > VTVSBR (Min) > +VS
(3) Suggested value approximately 1kΩ.
Figure 35. Equivalent Internal ESD Circuitry and Its Relation to a Typical Circuit Application
Copyright © 2010, Texas Instruments Incorporated 17
Product Folder Link(s): OPA141 OPA2141 OPA4141
PACKAGE OPTION ADDENDUM
www.ti.com 16-Aug-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
OPA141AID ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
OPA141AIDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS
& no Sb/Br) Call TI Level-2-260C-1 YEAR
OPA141AIDGKT ACTIVE VSSOP DGK 8 250 Green (RoHS
& no Sb/Br) Call TI Level-2-260C-1 YEAR
OPA141AIDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
OPA2141AID ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
OPA2141AIDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAUAGLevel-2-260C-1 YEAR
OPA2141AIDGKT ACTIVE VSSOP DGK 8 250 Green (RoHS
& no Sb/Br) CU NIPDAUAGLevel-2-260C-1 YEAR
OPA2141AIDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
OPA4141AID ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
OPA4141AIDR ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
OPA4141AIPW ACTIVE TSSOP PW 14 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
OPA4141AIPWR ACTIVE TSSOP PW 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
PACKAGE OPTION ADDENDUM
www.ti.com 16-Aug-2012
Addendum-Page 2
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
OPA141AIDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
OPA141AIDGKT VSSOP DGK 8 250 180.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
OPA141AIDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
OPA2141AIDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
OPA2141AIDGKT VSSOP DGK 8 250 180.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
OPA2141AIDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
OPA4141AIDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
OPA4141AIPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Aug-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
OPA141AIDGKR VSSOP DGK 8 2500 367.0 367.0 35.0
OPA141AIDGKT VSSOP DGK 8 250 210.0 185.0 35.0
OPA141AIDR SOIC D 8 2500 367.0 367.0 35.0
OPA2141AIDGKR VSSOP DGK 8 2500 367.0 367.0 35.0
OPA2141AIDGKT VSSOP DGK 8 250 210.0 185.0 35.0
OPA2141AIDR SOIC D 8 2500 367.0 367.0 35.0
OPA4141AIDR SOIC D 14 2500 367.0 367.0 38.0
OPA4141AIPWR TSSOP PW 14 2000 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Aug-2012
Pack Materials-Page 2
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