DESCRIPTION
The development board is in a half bridge topology with onboard
gate drives, featuring the EPC8000 family of high frequency en-
hancement mode (eGaN®) eld eect transistors (FETs). The pur-
pose of these development boards is to simplify the evaluation
process of the EPC8000 family of eGaN FETs by including all the
critical components on a single board that can be easily connected
into any existing converter.
The development board is 2” x 1.5” and contains two eGaN FETs in a
half bridge conguration using the Texas Instruments LM5113 gate
SYMBOL PARAMETER CONDITIONS MIN MAX UNITS
VDD Gate Drive Input Supply Range 7 12 V
When using 40 V devices; EPC8004, EPC8007, EPC8008 28* V
VIN Bus Input Voltage Range When using 65 V devices; EPC8002, EPC8005, EPC8009 45* V
When using 100 V devices; EPC8003, EPC8010 70* V
When using 40 V devices; EPC8004, EPC8007, EPC8008 40 V
VOUT Switch Node Output Voltage When using 65 V devices; EPC8002, EPC8005, EPC8009 65 V
When using 100 V devices; EPC8003, EPC8010 100 V
When using 40 V device EPC8004 4.4 A
When using 40 V device EPC8007 3.5* A
When using 40 V device EPC8008 2.2* A
IOUT Switch Node Output Current When using 65 V device EPC8002 1.6* A
When using 65 V device EPC8005 2.2* A
When using 65 V device EPC8009 3.5* A
When using 100 V device EPC8003 2.2* A
When using 100 V device EPC8010 3.2* A
VPWM PWM Logic Input Voltage Threshold Input ‘High’ 3.5 6 V
Input ‘Low’ 0 1.5 V
Minimum ‘High’ State Input Pulse Width VPWM rise and fall time < 10ns 20 ns
Minimum ‘Low’ State Input Pulse Width VPWM rise and fall time < 10ns 50†ns
driver, supply and bypass capacitors. The board contains all critical
components and layout for optimal switching performance. There
are also various probe points to facilitate simple waveform mea-
surement and eciency calculation. A complete block diagram of
the circuit is given in Figure 1.
For more information on the EPC8000 family of eGaN FETs, please
refer to the datasheets available from EPC at www.epc-co.com. The
datasheet should be read in conjunction with this quick start guide.
Demonstration Board Notication
The EPC boards are intended for product evaluation purposes only and is not intended for commercial use. As an evaluation tool, it is not
designed for compliance with the European Union directive on electromagnetic compatibility or any other such directives or regulations. As
board builds are at times subject to product availability, it is possible that boards may contain components or assembly materials that are not
RoHS compliant. Ecient Power Conversion Corporation (EPC) makes no guarantee that the purchased board is 100% RoHS compliant. No
Licenses are implied or granted under any patent right or other intellectual property whatsoever. EPC assumes no liability for applications
assistance, customer product design, software performance, or infringement of patents or any other intellectual property rights of any kind.
EPC reserves the right at any time, without notice, to change said circuitry and specications.
Quick Start Procedure
The development board is easy to set up to evaluate the performance of the eGaN FET. Refer to Figure 2 for proper connect and measurement
setup and follow the procedure below:
1. With power o, connect the input power supply bus to +VIN (J5, J6) and ground / return to –VIN (J7, J8).
2. With power o, connect the switch node of the half bridge OUT (J3, J4) to your circuit as required.
3. With power o, connect the gate drive input to +VDD (J1, Pin-1) and ground return to –VDD (J1, Pin-2).
4. With power o, connect the input PWM control signal to PWM (J2, Pin-1) and ground return to any of the remaining J2 pins.
5. Turn on the gate drive supply – make sure the supply is between 7 V and 12 V range.
6. Turn on the bus voltage to the required value (do not exceed the absolute maximum voltage on VOUT as indicated in the table below:
7. Turn on the controller / PWM input source and probe switching node to see switching operation.
8. Once operational, adjust the bus voltage and load PWM control within the operating range and observe the output switching behavior,
eciency and other parameters.
9. For shutdown, please follow steps in reverse.
NOTE. When measuring the high frequency content switch node (OUT), care must be taken to avoid long ground leads. Measure the switch node (OUT) by placing the oscilloscope
probe tip through the large via on the switch node (designed for this purpose) and grounding the probe directly across the GND terminals provided. See Figure 3 for proper scope
probe technique.
THERMAL CONSIDERATIONS
The development board showcases the EPC8000 family of eGaN FET. Although the electrical performance surpasses that for traditional silicon
devices, their relatively smaller size does magnify the thermal management requirements. The development board is intended for bench evaluation
with low ambient temperature and convection cooling. The addition of heat-sinking and forced air cooling can signicantly increase the current rat-
ing of these devices, but care must be taken to not exceed the absolute maximum die temperature of 125°C.
NOTE. The development board does not have any current or thermal protection on board.
www.epc-co.com
EPC Products are distributed exclusively through Digi-Key.
www.digikey.com
Contact us:
www.epc-co.com
Renee Yawger
WW Marketing
Oce: +1.908.475.5702
Mobile: +1.908.619.9678
renee.yawger@epc-co.com
Stephen Tsang
Sales, Asia
Mobile: +852.9408.8351
stephen.tsang@epc-co.com
Bhasy Nair
Global FAE Support
Oce: +1.972.805.8585
Mobile: +1.469.879.2424
bhasy.nair@epc-co.com
Peter Cheng
FAE Support, Asia
Mobile: +886.938.009.706
peter.cheng@epc-co.com
Demonstration Board
EPC9022/23/24/25/27/28/29/30
Quick Start Guide
Half Bridge with Gate Drive for EPC8000 Family
a. EPC9022, 65 V
b. EPC9023, 100 V
c. EPC9024, 40 V
d. EPC9025, 65 V
e. EPC9027, 40 V
f. EPC9028, 40 V
g. EPC9029, 65 V
h. EPC9030, 100 V
Figure 4: Typical Waveforms for VIN = 28 V to 3.3 V/4 A (5 MHz) Buck converter
CH2: (VOUT) Switch node voltage –– CH4: VPWM Input voltage
Figure 1: Block Diagram of Development Board
Figure 2: Proper Connection and Measurement Setup
Figure 3: Proper Measurement of Switch Node – OUT
VDD
VIN
OUT
PWM
Input
Half-Bridge with Bypass
Gate Drive Supply
Logic and
Dead-time
Adjust
Gate Drive
Regulator
LM5113
Gate
Driver
EPC
EFFICIENT POWER CONVERSION
7 V – 12 V
VDD Supply
PWM Input
External Circuit
VIN Supply
See Table 1
for max
VIN
++
+
––
–
IIN
V
A
Gate Drive Supply
(Note Polarity)
(For Eciency
Measurement)
Switch Node
Do not use probe ground lead
Do not let
probe tip
touch the
low-side die!
Place probe
tip on pad
Minimize loop
* Assumes inductive load, maximum current depends on die temperature – actual maximum current with be subject to switching frequency, bus voltage and thermals.
† Limited by time needed to ‘refresh’ high side bootstrap supply voltage.
Table 1: Performance Summary (TA = 25°C)
DESCRIPTION
The development board is in a half bridge topology with onboard
gate drives, featuring the EPC8000 family of high frequency en-
hancement mode (eGaN®) eld eect transistors (FETs). The pur-
pose of these development boards is to simplify the evaluation
process of the EPC8000 family of eGaN FETs by including all the
critical components on a single board that can be easily connected
into any existing converter.
The development board is 2” x 1.5” and contains two eGaN FETs in a
half bridge conguration using the Texas Instruments LM5113 gate
SYMBOL PARAMETER CONDITIONS MIN MAX UNITS
VDD Gate Drive Input Supply Range 7 12 V
40 V devices; EPC9024, EPC9027, EPC9028 28* V
VIN Bus Input Voltage Range 65 V devices; EPC9022, EPC9025, EPC9029 45* V
100 V devices; EPC9023, EPC9030 70* V
40 V devices; EPC9024, EPC9027, EPC9028 40 V
VOUT Switch Node Output Voltage 65 V device EPC9022, EPC9025, EPC9029 65 V
100 V devices; EPC9023, EPC9030 100 V
40 V device EPC9024 4.4* A
40 V device EPC9027 3.5* A
40 V device EPC9028 2.2* A
IOUT Switch Node Output Current 65 V device EPC9022 1.6* A
65 V device EPC9025 2.2* A
65 V device EPC9029 3.5* A
100 V device EPC9023 2.2* A
100 V device EPC9030 3.2* A
VPWM PWM Logic Input Voltage Threshold Input ‘High’ 3.5 6 V
Input ‘Low’ 0 1.5 V
FMIN Minimum Switching Frequency Bootstrap Capacitor Limited 500 kHz
Minimum ‘High’ State Input Pulse Width VPWM rise and fall time < 10ns 20 ns
Minimum ‘Low’ State Input Pulse Width VPWM rise and fall time < 10ns 50†ns
driver, supply and bypass capacitors. The board contains all critical
components and layout for optimal switching performance. There
are also various probe points to facilitate simple waveform mea-
surement and eciency calculation. A complete block diagram of
the circuit is given in Figure 1.
For more information on the EPC8000 family of eGaN FETs, please
refer to the datasheets available from EPC at www.epc-co.com. The
datasheet should be read in conjunction with this quick start guide.
Demonstration Board Notication
The EPC boards are intended for product evaluation purposes only and is not intended for commercial use. As an evaluation tool, it is not
designed for compliance with the European Union directive on electromagnetic compatibility or any other such directives or regulations. As
board builds are at times subject to product availability, it is possible that boards may contain components or assembly materials that are not
RoHS compliant. Ecient Power Conversion Corporation (EPC) makes no guarantee that the purchased board is 100% RoHS compliant. No
Licenses are implied or granted under any patent right or other intellectual property whatsoever. EPC assumes no liability for applications
assistance, customer product design, software performance, or infringement of patents or any other intellectual property rights of any kind.
EPC reserves the right at any time, without notice, to change said circuitry and specications.
Quick Start Procedure
The development board is easy to set up to evaluate the performance of the eGaN FET. Refer to Figure 2 for proper connect and measurement
setup and follow the procedure below:
1. With power o, connect the input power supply bus to +VIN (J5, J6) and ground / return to –VIN (J7, J8).
2. With power o, connect the switch node of the half bridge OUT (J3, J4) to your circuit as required.
3. With power o, connect the gate drive input to +VDD (J1, Pin-1) and ground return to –VDD (J1, Pin-2).
4. With power o, connect the input PWM control signal to PWM (J2, Pin-1) and ground return to any of the remaining J2 pins.
5. Turn on the gate drive supply – make sure the supply is between 7 V and 12 V range.
6. Turn on the bus voltage to the required value (do not exceed the absolute maximum voltage on VOUT as indicated in the table below:
7. Turn on the controller / PWM input source and probe switching node to see switching operation.
8. Once operational, adjust the bus voltage and load PWM control within the operating range and observe the output switching behavior,
eciency and other parameters.
9. For shutdown, please follow steps in reverse.
NOTE. When measuring the high frequency content switch node (OUT), care must be taken to avoid long ground leads. Measure the switch node (OUT) by placing the oscilloscope
probe tip through the large via on the switch node (designed for this purpose) and grounding the probe directly across the GND terminals provided. See Figure 3 for proper scope
probe technique.
THERMAL CONSIDERATIONS
The development board showcases the EPC8000 family of eGaN FET. Although the electrical performance surpasses that for traditional silicon
devices, their relatively smaller size does magnify the thermal management requirements. The development board is intended for bench evaluation
with low ambient temperature and convection cooling. The addition of heat-sinking and forced air cooling can signicantly increase the current rat-
ing of these devices, but care must be taken to not exceed the absolute maximum die temperature of 125°C.
NOTE. The development board does not have any current or thermal protection on board.
www.epc-co.com
EPC Products are distributed exclusively through Digi-Key.
www.digikey.com
Contact us:
www.epc-co.com
Renee Yawger
WW Marketing
Oce: +1.908.475.5702
Mobile: +1.908.619.9678
renee.yawger@epc-co.com
Stephen Tsang
Sales, Asia
Mobile: +852.9408.8351
stephen.tsang@epc-co.com
Bhasy Nair
Global FAE Support
Oce: +1.972.805.8585
Mobile: +1.469.879.2424
bhasy.nair@epc-co.com
Peter Cheng
FAE Support, Asia
Mobile: +886.938.009.706
peter.cheng@epc-co.com
Demonstration Board
EPC9022/23/24/25/27/28/29/30
Quick Start Guide
Half Bridge with Gate Drive for EPC8000 Family
a. EPC9022, 65 V
b. EPC9023, 100 V
c. EPC9024, 40 V
d. EPC9025, 65 V
e. EPC9027, 40 V
f. EPC9028, 40 V
g. EPC9029, 65 V
h. EPC9030, 100 V
Figure 4: Typical Waveforms for VIN = 28 V to 3.3 V/4 A (5 MHz) Buck converter
CH2: (VOUT) Switch node voltage –– CH4: VPWM Input voltage
Figure 1: Block Diagram of Development Board
Figure 2: Proper Connection and Measurement Setup
Figure 3: Proper Measurement of Switch Node – OUT
VDD
VIN
OUT
PWM
Input
Half-Bridge with Bypass
Gate Drive Supply
Logic and
Dead-time
Adjust
Gate Drive
Regulator
LM5113
Gate
Driver
EPC
EFFICIENT POWER CONVERSION
7 V – 12 V
VDD Supply
PWM Input
External Circuit
VIN Supply
<28 V
VIN
++
+
––
–
IIN
V
A
Gate Drive Supply
(Note Polarity)
(For Eciency
Measurement)
Switch Node
Do not use probe ground lead
Do not let
probe tip
touch the
low-side die!
Place probe
tip on pad
Minimize loop
* Assumes inductive load, maximum current depends on die temperature – actual maximum current with be subject to switching frequency, bus voltage and thermals.
† Limited by time needed to ‘refresh’ high side bootstrap supply voltage.
Table 1: Performance Summary (TA = 25°C)
DESCRIPTION
The development board is in a half bridge topology with onboard
gate drives, featuring the EPC8000 family of high frequency en-
hancement mode (eGaN®) eld eect transistors (FETs). The pur-
pose of these development boards is to simplify the evaluation
process of the EPC8000 family of eGaN FETs by including all the
critical components on a single board that can be easily connected
into any existing converter.
The development board is 2” x 1.5” and contains two eGaN FETs in a
half bridge conguration using the Texas Instruments LM5113 gate
SYMBOL PARAMETER CONDITIONS MIN MAX UNITS
VDD Gate Drive Input Supply Range 7 12 V
When using 40 V devices; EPC8004, EPC8007, EPC8008 28* V
VIN Bus Input Voltage Range When using 65 V devices; EPC8002, EPC8005, EPC8009 45* V
When using 100 V devices; EPC8003, EPC8010 70* V
When using 40 V devices; EPC8004, EPC8007, EPC8008 40 V
VOUT Switch Node Output Voltage When using 65 V devices; EPC8002, EPC8005, EPC8009 65 V
When using 100 V devices; EPC8003, EPC8010 100 V
When using 40 V device EPC8004 4.4 A
When using 40 V device EPC8007 3.5* A
When using 40 V device EPC8008 2.2* A
IOUT Switch Node Output Current When using 65 V device EPC8002 1.6* A
When using 65 V device EPC8005 2.2* A
When using 65 V device EPC8009 3.5* A
When using 100 V device EPC8003 2.2* A
When using 100 V device EPC8010 3.2* A
VPWM PWM Logic Input Voltage Threshold Input ‘High’ 3.5 6 V
Input ‘Low’ 0 1.5 V
Minimum ‘High’ State Input Pulse Width VPWM rise and fall time < 10ns 20 ns
Minimum ‘Low’ State Input Pulse Width VPWM rise and fall time < 10ns 50†ns
driver, supply and bypass capacitors. The board contains all critical
components and layout for optimal switching performance. There
are also various probe points to facilitate simple waveform mea-
surement and eciency calculation. A complete block diagram of
the circuit is given in Figure 1.
For more information on the EPC8000 family of eGaN FETs, please
refer to the datasheets available from EPC at www.epc-co.com. The
datasheet should be read in conjunction with this quick start guide.
Demonstration Board Notication
The EPC boards are intended for product evaluation purposes only and is not intended for commercial use. As an evaluation tool, it is not
designed for compliance with the European Union directive on electromagnetic compatibility or any other such directives or regulations. As
board builds are at times subject to product availability, it is possible that boards may contain components or assembly materials that are not
RoHS compliant. Ecient Power Conversion Corporation (EPC) makes no guarantee that the purchased board is 100% RoHS compliant. No
Licenses are implied or granted under any patent right or other intellectual property whatsoever. EPC assumes no liability for applications
assistance, customer product design, software performance, or infringement of patents or any other intellectual property rights of any kind.
EPC reserves the right at any time, without notice, to change said circuitry and specications.
Quick Start Procedure
The development board is easy to set up to evaluate the performance of the eGaN FET. Refer to Figure 2 for proper connect and measurement
setup and follow the procedure below:
1. With power o, connect the input power supply bus to +VIN (J5, J6) and ground / return to –VIN (J7, J8).
2. With power o, connect the switch node of the half bridge OUT (J3, J4) to your circuit as required.
3. With power o, connect the gate drive input to +VDD (J1, Pin-1) and ground return to –VDD (J1, Pin-2).
4. With power o, connect the input PWM control signal to PWM (J2, Pin-1) and ground return to any of the remaining J2 pins.
5. Turn on the gate drive supply – make sure the supply is between 7 V and 12 V range.
6. Turn on the bus voltage to the required value (do not exceed the absolute maximum voltage on VOUT as indicated in the table below:
7. Turn on the controller / PWM input source and probe switching node to see switching operation.
8. Once operational, adjust the bus voltage and load PWM control within the operating range and observe the output switching behavior,
eciency and other parameters.
9. For shutdown, please follow steps in reverse.
NOTE. When measuring the high frequency content switch node (OUT), care must be taken to avoid long ground leads. Measure the switch node (OUT) by placing the oscilloscope
probe tip through the large via on the switch node (designed for this purpose) and grounding the probe directly across the GND terminals provided. See Figure 3 for proper scope
probe technique.
THERMAL CONSIDERATIONS
The development board showcases the EPC8000 family of eGaN FET. Although the electrical performance surpasses that for traditional silicon
devices, their relatively smaller size does magnify the thermal management requirements. The development board is intended for bench evaluation
with low ambient temperature and convection cooling. The addition of heat-sinking and forced air cooling can signicantly increase the current rat-
ing of these devices, but care must be taken to not exceed the absolute maximum die temperature of 125°C.
NOTE. The development board does not have any current or thermal protection on board.
www.epc-co.com
EPC Products are distributed exclusively through Digi-Key.
www.digikey.com
Contact us:
www.epc-co.com
Renee Yawger
WW Marketing
Oce: +1.908.475.5702
Mobile: +1.908.619.9678
renee.yawger@epc-co.com
Stephen Tsang
Sales, Asia
Mobile: +852.9408.8351
stephen.tsang@epc-co.com
Bhasy Nair
Global FAE Support
Oce: +1.972.805.8585
Mobile: +1.469.879.2424
bhasy.nair@epc-co.com
Peter Cheng
FAE Support, Asia
Mobile: +886.938.009.706
peter.cheng@epc-co.com
Demonstration Board
EPC9022/23/24/25/27/28/29/30
Quick Start Guide
Half Bridge with Gate Drive for EPC8000 Family
a. EPC9022, 65 V
b. EPC9023, 100 V
c. EPC9024, 40 V
d. EPC9025, 65 V
e. EPC9027, 40 V
f. EPC9028, 40 V
g. EPC9029, 65 V
h. EPC9030, 100 V
Figure 4: Typical Waveforms for VIN = 28 V to 3.3 V/4 A (5 MHz) Buck converter
CH2: (VOUT) Switch node voltage –– CH4: VPWM Input voltage
Figure 1: Block Diagram of Development Board
Figure 2: Proper Connection and Measurement Setup
Figure 3: Proper Measurement of Switch Node – OUT
VDD
VIN
OUT
PWM
Input
Half-Bridge with Bypass
Gate Drive Supply
Logic and
Dead-time
Adjust
Gate Drive
Regulator
LM5113
Gate
Driver
EPC
EFFICIENT POWER CONVERSION
7 V – 12 V
VDD Supply
PWM Input
External Circuit
VIN Supply
See Table 1
for max
VIN
++
+
––
–
IIN
V
A
Gate Drive Supply
(Note Polarity)
(For Eciency
Measurement)
Switch Node
Do not use probe ground lead
Do not let
probe tip
touch the
low-side die!
Place probe
tip on pad
Minimize loop
* Assumes inductive load, maximum current depends on die temperature – actual maximum current with be subject to switching frequency, bus voltage and thermals.
† Limited by time needed to ‘refresh’ high side bootstrap supply voltage.
Table 1: Performance Summary (TA = 25°C)
DESCRIPTION
The development board is in a half bridge topology with onboard
gate drives, featuring the EPC8000 family of high frequency en-
hancement mode (eGaN®) eld eect transistors (FETs). The pur-
pose of these development boards is to simplify the evaluation
process of the EPC8000 family of eGaN FETs by including all the
critical components on a single board that can be easily connected
into any existing converter.
The development board is 2” x 1.5” and contains two eGaN FETs in a
half bridge conguration using the Texas Instruments LM5113 gate
SYMBOL PARAMETER CONDITIONS MIN MAX UNITS
VDD Gate Drive Input Supply Range 7 12 V
40 V devices; EPC9024, EPC9027, EPC9028 28* V
VIN Bus Input Voltage Range 65 V devices; EPC9022, EPC9025, EPC9029 45* V
100 V devices; EPC9023, EPC9030 70* V
40 V devices; EPC9024, EPC9027, EPC9028 40 V
VOUT Switch Node Output Voltage 65 V device EPC9022, EPC9025, EPC9029 65 V
100 V devices; EPC9023, EPC9030 100 V
40 V device EPC9024 4.4* A
40 V device EPC9027 3.5* A
40 V device EPC9028 2.2* A
IOUT Switch Node Output Current 65 V device EPC9022 1.6* A
65 V device EPC9025 2.2* A
65 V device EPC9029 3.5* A
100 V device EPC9023 2.2* A
100 V device EPC9029 3.2* A
VPWM PWM Logic Input Voltage Threshold Input ‘High’ 3.5 6 V
Input ‘Low’ 0 1.5 V
FMIN Minimum Switching Frequency Bootstrap Capacitor Limited 500 kHz
Minimum ‘High’ State Input Pulse Width VPWM rise and fall time < 10ns 20 ns
Minimum ‘Low’ State Input Pulse Width VPWM rise and fall time < 10ns 50†ns
driver, supply and bypass capacitors. The board contains all critical
components and layout for optimal switching performance. There
are also various probe points to facilitate simple waveform mea-
surement and eciency calculation. A complete block diagram of
the circuit is given in Figure 1.
For more information on the EPC8000 family of eGaN FETs, please
refer to the datasheets available from EPC at www.epc-co.com. The
datasheet should be read in conjunction with this quick start guide.
Demonstration Board Notication
The EPC boards are intended for product evaluation purposes only and is not intended for commercial use. As an evaluation tool, it is not
designed for compliance with the European Union directive on electromagnetic compatibility or any other such directives or regulations. As
board builds are at times subject to product availability, it is possible that boards may contain components or assembly materials that are not
RoHS compliant. Ecient Power Conversion Corporation (EPC) makes no guarantee that the purchased board is 100% RoHS compliant. No
Licenses are implied or granted under any patent right or other intellectual property whatsoever. EPC assumes no liability for applications
assistance, customer product design, software performance, or infringement of patents or any other intellectual property rights of any kind.
EPC reserves the right at any time, without notice, to change said circuitry and specications.
Quick Start Procedure
The development board is easy to set up to evaluate the performance of the eGaN FET. Refer to Figure 2 for proper connect and measurement
setup and follow the procedure below:
1. With power o, connect the input power supply bus to +VIN (J5, J6) and ground / return to –VIN (J7, J8).
2. With power o, connect the switch node of the half bridge OUT (J3, J4) to your circuit as required.
3. With power o, connect the gate drive input to +VDD (J1, Pin-1) and ground return to –VDD (J1, Pin-2).
4. With power o, connect the input PWM control signal to PWM (J2, Pin-1) and ground return to any of the remaining J2 pins.
5. Turn on the gate drive supply – make sure the supply is between 7 V and 12 V range.
6. Turn on the bus voltage to the required value (do not exceed the absolute maximum voltage on VOUT as indicated in the table below:
7. Turn on the controller / PWM input source and probe switching node to see switching operation.
8. Once operational, adjust the bus voltage and load PWM control within the operating range and observe the output switching behavior,
eciency and other parameters.
9. For shutdown, please follow steps in reverse.
NOTE. When measuring the high frequency content switch node (OUT), care must be taken to avoid long ground leads. Measure the switch node (OUT) by placing the oscilloscope
probe tip through the large via on the switch node (designed for this purpose) and grounding the probe directly across the GND terminals provided. See Figure 3 for proper scope
probe technique.
THERMAL CONSIDERATIONS
The development board showcases the EPC8000 family of eGaN FET. Although the electrical performance surpasses that for traditional silicon
devices, their relatively smaller size does magnify the thermal management requirements. The development board is intended for bench evaluation
with low ambient temperature and convection cooling. The addition of heat-sinking and forced air cooling can signicantly increase the current rat-
ing of these devices, but care must be taken to not exceed the absolute maximum die temperature of 125°C.
NOTE. The development board does not have any current or thermal protection on board.
www.epc-co.com
EPC Products are distributed exclusively through Digi-Key.
www.digikey.com
Contact us:
www.epc-co.com
Renee Yawger
WW Marketing
Oce: +1.908.475.5702
Mobile: +1.908.619.9678
renee.yawger@epc-co.com
Stephen Tsang
Sales, Asia
Mobile: +852.9408.8351
stephen.tsang@epc-co.com
Bhasy Nair
Global FAE Support
Oce: +1.972.805.8585
Mobile: +1.469.879.2424
bhasy.nair@epc-co.com
Peter Cheng
FAE Support, Asia
Mobile: +886.938.009.706
peter.cheng@epc-co.com
Demonstration Board
EPC9022/23/24/25/27/28/29/30
Quick Start Guide
Half Bridge with Gate Drive for EPC8000 Family
a. EPC9022, 65 V
b. EPC9023, 100 V
c. EPC9024, 40 V
d. EPC9025, 65 V
e. EPC9027, 40 V
f. EPC9028, 40 V
g. EPC9029, 65 V
h. EPC9030, 100 V
Figure 4: Typical Waveforms for VIN = 28 V to 3.3 V/4 A (5 MHz) Buck converter
CH2: (VOUT) Switch node voltage –– CH4: VPWM Input voltage
Figure 1: Block Diagram of Development Board
Figure 2: Proper Connection and Measurement Setup
Figure 3: Proper Measurement of Switch Node – OUT
VDD
VIN
OUT
PWM
Input
Half-Bridge with Bypass
Gate Drive Supply
Logic and
Dead-time
Adjust
Gate Drive
Regulator
LM5113
Gate
Driver
EPC
EFFICIENT POWER CONVERSION
7 V – 12 V
VDD Supply
PWM Input
External Circuit
VIN Supply
<28 V
VIN
++
+
––
–
IIN
V
A
Gate Drive Supply
(Note Polarity)
(For Eciency
Measurement)
Switch Node
Do not use probe ground lead
Do not let
probe tip
touch the
low-side die!
Place probe
tip on pad
Minimize loop
* Assumes inductive load, maximum current depends on die temperature – actual maximum current with be subject to switching frequency, bus voltage and thermals.
† Limited by time needed to ‘refresh’ high side bootstrap supply voltage.
Table 1: Performance Summary (TA = 25°C)
Item Qty Reference Part Description Manufacturer / Part #
1 3 C4, C10, C11 Capacitor, 1uF, 10%, 25V, X5R Murata, GRM188R61E105KA12D
2 2 C6, C7 Capacitor, 100pF, 5%, 50V, NP0 Kemet, C0402C101K5GACTU
3 1 C12 Capacitor, 22nF, 10%, 25V, X5R TDK, C1005X5R1E223K050BA
4 1 C14 Capacitor, 0.1uF, 10%, 25V, X5R TDK, C1005X5R1E104K
5 3 C16, C17, C18 Capacitor, - SEE TABLE 3 SEE TABLE 3
6 1 C13 Capacitor, 1uF, 10%, 25V, X5R Murata, GRM188R61E105KA12D
7 1 C21 Capacitor, - SEE TABLE 3 SEE TABLE 3
8 2 D1, D2 Schottky Diode, 30V Diodes Inc., SDM03U40-7
9 3 J1, J2, J9 Connector 2pins of Tyco, 4-103185-0
10 6 J3, J4, J5, J6, J7, J8 Connector FCI, 68602-224HLF
11 2 Q1, Q2 eGaN® FET - SEE TABLE 3 SEE TABLE 3
12 1 R1 Resistor, 10.0K, 5%, 1/8W Stackpole, RMCF0603FT10K0
13 2 R2, R15 Resistor, 0 Ohm, 1/8W Stackpole, RMCF0603ZT0R00
14 2 R4,R5 Resistor, 7.5 Ohm, 5%, 1/16W Stackpole, RMCF0603JT7R50
15 2 TP1, TP2 Test Point Keystone Elect, 5015
16 1 U1 I.C., Logic Fairchild, NC7SZ00L6X
17 1 U2 I.C., Gate driver Texas Instruments, LM5113
18 1 U3 I.C., Regulator Microchip, MCP1703T-5002E/MC
19 1 U4 I.C., Logic Fairchild, NC7SZ08L6X
20 0 HS1 Optional Heatsink HeatSink15mmX15mm
21 0 R14, R22 Optional Resistor
22 0 P1,P2 Optional Potentiometer PV37Y
Board Number Item Qty Reference Part Description Manufacturer / Part #
5 3 C16, C17, C18
Capacitor, 0.01uF, 20%, 100V, X7R
TDK, C1005X7S2A103M050BB
EPC9022 7 1 C21 Capacitor, 1uF, 10%, 100V, X7R
TDK, CGA4J3X7S2A105K125A
11 2 Q1, Q2 eGaN® FET EPC8002
5 3 C16, C17, C18
Capacitor, 0.01uF, 20%, 100V, X7R
TDK, C1005X7S2A103M050BB
EPC9023 7 1 C21 Capacitor, 1uF, 10%, 100V, X7R TDK, CGA4J3X7S2A105K125A
11 2 Q1, Q2 eGaN® FET EPC8003
5 3 C16, C17, C18 Capacitor, 0.1uF, 20%, 50V, X5R TDK, C1005X5R1H104K050BB
EPC9024 7 1 C21 Capacitor, 4.7uF, 10%, 50V, X5R TDK, C2012X5R1H475K125AB
11 2 Q1, Q2 eGaN® FET EPC8004
5 3 C16, C17, C18
Capacitor, 0.01uF, 20%, 100V, X7R
TDK, C1005X7S2A103M050BB
EPC9025 7 1 C21 Capacitor, 1uF, 10%, 100V, X7R TDK, CGA4J3X7S2A105K125A
11 2 Q1, Q2 eGaN® FET EPC8005
5 3 C16, C17, C18 Capacitor, 0.1uF, 20%, 50V, X5R TDK, C1005X5R1H104K050BB
EPC9027 7 1 C21 Capacitor, 4.7uF, 10%, 50V, X5R TDK, C2012X5R1H475K125AB
11 2 Q1, Q2 eGaN® FET EPC8007
5 3 C16, C17, C18 Capacitor, 0.1uF, 20%, 50V, X5R TDK, C1005X5R1H104K050BB
EPC9028 7 1 C21 Capacitor, 4.7uF, 10%, 50V, X5R TDK, C2012X5R1H475K125AB
11 2 Q1, Q2 eGaN® FET EPC8008
5 3 C16, C17, C18
Capacitor, 0.01uF, 20%, 100V, X7R
TDK, C1005X7S2A103M050BB
EPC9029 7 1 C21 Capacitor, 1uF, 10%, 100V, X7R TDK, CGA4J3X7S2A105K125A
11 2 Q1, Q2 eGaN® FET EPC8009
5 3 C16, C17, C18
Capacitor, 0.01uF, 20%, 100V, X7R
TDK, C1005X7S2A103M050BB
EPC9030 7 1 C21 Capacitor, 1uF, 10%, 100V, X7R TDK, CGA4J3X7S2A105K125A
11 2 Q1, Q2 eGaN® FET EPC8010
1
1
2
2
3
3
4
4
5
5
6
6
DD
CC
BB
AA
Figure 5: Development Board Schematic
See Table 3 on variable components
VCC
7 - 12 Vdc
C4
1uF, 25V
C10
1uF, 25V
1
2
J1
CON2
R1
10k
PWM1
GND
3
A
1
B
2
Y4
VDD 6
55
U1
NC7SZ00L6X
28V Max
SW OUT
Return
1
TP3
CON1
C16
C12
22nF, 25V
C13
1uF, 25V
1
2
3
4
J8
CON4
1
2
3
4
J7
CON4
1
2
3
4
J3
CON4
1
2
3
4
J4
CON4
1
2
3
4
J6
CON4
1
2
3
4
J5
CON4
C11
1uF, 25V
1
TP2
Keystone 5015
1
TP1
Keystone 5015
R2
Zero
R14
Optional
R15
Zero
VDD
HB
HOH
HOL
HI
LI
VSS
LOL
GND
HS
LOH
U2
LM5113TME
R5
7.5
C7
100pf
D2
SDM03U40
R4
7.5
C6
100pf
D1
SDM03U40
PWM2
VCC
OUT 1
NC 2
NC 3
GND 4
NC
5
NC
6
NC
7
IN
8
GND
9
U3
MCP1703
1
2
J2
CON2
1
2
J9
CON2
2
P1
Opt.
2
P2
Optional
GND
A
B
Y
VDD
U4
NC7SZ08L6X
Q1
See Table
Q2
See Table
C17
C18
See Table
C14
100nF, 25V
R22
Optional
J11
HS1
Table 2 : Bill of Material
Table 3: Variable BOM Components
Item Qty Reference Part Description Manufacturer / Part #
1 3 C4, C10, C11 Capacitor, 1uF, 10%, 25V, X5R Murata, GRM188R61E105KA12D
2 2 C6, C7 Capacitor, 100pF, 5%, 50V, NP0 Kemet, C0402C101K5GACTU
3 1 C12 Capacitor, 22nF, 10%, 25V, X5R TDK, C1005X5R1E223K050BA
4 1 C14 Capacitor, 0.1uF, 10%, 25V, X5R TDK, C1005X5R1E104K
5 3 C16, C17, C18 Capacitor, - SEE TABLE 3 SEE TABLE 3
6 1 C13 Capacitor, 1uF, 10%, 25V, X5R Murata, GRM188R61E105KA12D
7 1 C21 Capacitor, - SEE TABLE 3 SEE TABLE 3
8 2 D1, D2 Schottky Diode, 30V Diodes Inc., SDM03U40-7
9 3 J1, J2, J9 Connector 2pins of Tyco, 4-103185-0
10 6 J3, J4, J5, J6, J7, J8 Connector FCI, 68602-224HLF
11 2 Q1, Q2 eGaN® FET - SEE TABLE 3 SEE TABLE 3
12 1 R1 Resistor, 10.0K, 5%, 1/8W Stackpole, RMCF0603FT10K0
13 2 R2, R15 Resistor, 0 Ohm, 1/8W Stackpole, RMCF0603ZT0R00
14 2 R4,R5 Resistor, 7.5 Ohm, 5%, 1/16W Stackpole, RMCF0603JT7R50
15 2 TP1, TP2 Test Point Keystone Elect, 5015
16 1 U1 I.C., Logic Fairchild, NC7SZ00L6X
17 1 U2 I.C., Gate driver Texas Instruments, LM5113
18 1 U3 I.C., Regulator Microchip, MCP1703T-5002E/MC
19 1 U4 I.C., Logic Fairchild, NC7SZ08L6X
20 0 HS1 Optional Heatsink HeatSink15mmX15mm
21 0 R14, R22 Optional Resistor
22 0 P1,P2 Optional Potentiometer PV37Y
Board Number Item Qty Reference Part Description Manufacturer / Part #
5 3 C16, C17, C18 Capacitor, 0.01uF, 20%, 100V, X5R TDK, C1005X7S2A103M050BB
EPC9022 7 1 C21 Capacitor, 1uF, 10%, 100V, X7R TDK, C1005X5R1H104K050BB
11 2 Q1, Q2 eGaN® FET EPC8002
5 3 C16, C17, C18 Capacitor, 0.01uF, 20%, 100V, X5R TDK, C1005X7S2A103M050BB
EPC9023 7 1 C21 Capacitor, 1uF, 10%, 100V, X7R TDK, CGA4J3X7S2A105K125A
11 2 Q1, Q2 eGaN® FET EPC8003
5 3 C16, C17, C18 Capacitor, 0.1uF, 20%, 50V, X5R TDK, C1005X5R1H104K050BB
EPC9024 7 1 C21 Capacitor, 4.7uF, 10%, 50V, X5R TDK, C2012X5R1H475K125AB
11 2 Q1, Q2 eGaN® FET EPC8004
5 3 C16, C17, C18 Capacitor, 0.01uF, 20%, 100V, X5R TDK, C1005X7S2A103M050BB
EPC9025 7 1 C21 Capacitor, 1uF, 10%, 100V, X7R TDK, CGA4J3X7S2A105K125A
11 2 Q1, Q2 eGaN® FET EPC8005
5 3 C16, C17, C18 Capacitor, 0.1uF, 20%, 50V, X5R TDK, C1005X5R1H104K050BB
EPC9027 7 1 C21 Capacitor, 4.7uF, 10%, 50V, X5R TDK, C2012X5R1H475K125AB
11 2 Q1, Q2 eGaN® FET EPC8007
5 3 C16, C17, C18 Capacitor, 0.1uF, 20%, 50V, X5R TDK, C1005X5R1H104K050BB
EPC9028 7 1 C21 Capacitor, 4.7uF, 10%, 50V, X5R TDK, C2012X5R1H475K125AB
11 2 Q1, Q2 eGaN® FET EPC8008
5 3 C16, C17, C18 Capacitor, 0.01uF, 20%, 100V, X5R TDK, C1005X7S2A103M050BB
EPC9029 7 1 C21 Capacitor, 1uF, 10%, 100V, X7R TDK, CGA4J3X7S2A105K125A
11 2 Q1, Q2 eGaN® FET EPC8009
5 3 C16, C17, C18 Capacitor, 0.01uF, 20%, 100V, X5R TDK, C1005X7S2A103M050BB
EPC9030 7 1 C21 Capacitor, 1uF, 10%, 100V, X7R TDK, CGA4J3X7S2A105K125A
11 2 Q1, Q2 eGaN® FET EPC8010
1
1
2
2
3
3
4
4
5
5
6
6
DD
CC
BB
AA
Figure 5: Development Board Schematic
See Table 3 on variable components
VCC
7 - 12 Vdc
C4
1uF, 25V
C10
1uF, 25V
1
2
J1
CON2
R1
10k
PWM1
GND
3
A
1
B
2
Y4
VDD 6
55
U1
NC7SZ00L6X
28V Max
SW OUT
Return
1
TP3
CON1
C16
C12
22nF, 25V
C13
1uF, 25V
1
2
3
4
J8
CON4
1
2
3
4
J7
CON4
1
2
3
4
J3
CON4
1
2
3
4
J4
CON4
1
2
3
4
J6
CON4
1
2
3
4
J5
CON4
C11
1uF, 25V
1
TP2
Keystone 5015
1
TP1
Keystone 5015
R2
Zero
R14
Optional
R15
Zero
VDD
HB
HOH
HOL
HI
LI
VSS
LOL
GND
HS
LOH
U2
LM5113TME
R5
7.5
C7
100pF
D2
SDM03U40
R4
7.5
C6
100pF
D1
SDM03U40
PWM2
VCC
OUT 1
NC 2
NC 3
GND 4
NC
5
NC
6
NC
7
IN
8
GND
9
U3
MCP1703
1
2
J2
CON2
1
2
J9
CON2
2
P1
Opt.
2
P2
Optional
GND
A
B
Y
VDD
U4
NC7SZ08L6X
Q1
See Table
Q2
See Table
C17
C18
See Table
C14
100nF, 25V
R22
Optional
J11
HS1
Table 2 : Bill of Material
Table 3: Variable BOM Components
DESCRIPTION
The development board is in a half bridge topology with onboard
gate drives, featuring the EPC8000 family of high frequency en-
hancement mode (eGaN®) eld eect transistors (FETs). The pur-
pose of these development boards is to simplify the evaluation
process of the EPC8000 family of eGaN FETs by including all the
critical components on a single board that can be easily connected
into any existing converter.
The development board is 2” x 1.5” and contains two eGaN FETs in a
half bridge conguration using the Texas Instruments LM5113 gate
SYMBOL PARAMETER CONDITIONS MIN MAX UNITS
VDD Gate Drive Input Supply Range 7 12 V
When using 40 V devices; EPC8004, EPC8007, EPC8008 28* V
VIN Bus Input Voltage Range When using 65 V devices; EPC8002, EPC8005, EPC8009 45* V
When using 100 V devices; EPC8003, EPC8010 70* V
When using 40 V devices; EPC8004, EPC8007, EPC8008 40 V
VOUT Switch Node Output Voltage When using 65 V devices; EPC8002, EPC8005, EPC8009 65 V
When using 100 V devices; EPC8003, EPC8010 100 V
When using 40 V device EPC8004 4.4 A
When using 40 V device EPC8007 3.5* A
When using 40 V device EPC8008 2.2* A
IOUT Switch Node Output Current When using 65 V device EPC8002 1.6* A
When using 65 V device EPC8005 2.2* A
When using 65 V device EPC8009 3.5* A
When using 100 V device EPC8003 2.2* A
When using 100 V device EPC8010 3.2* A
VPWM PWM Logic Input Voltage Threshold Input ‘High’ 3.5 6 V
Input ‘Low’ 0 1.5 V
Minimum ‘High’ State Input Pulse Width VPWM rise and fall time < 10ns 20 ns
Minimum ‘Low’ State Input Pulse Width VPWM rise and fall time < 10ns 50†ns
driver, supply and bypass capacitors. The board contains all critical
components and layout for optimal switching performance. There
are also various probe points to facilitate simple waveform mea-
surement and eciency calculation. A complete block diagram of
the circuit is given in Figure 1.
For more information on the EPC8000 family of eGaN FETs, please
refer to the datasheets available from EPC at www.epc-co.com. The
datasheet should be read in conjunction with this quick start guide.
Demonstration Board Notication
The EPC boards are intended for product evaluation purposes only and is not intended for commercial use. As an evaluation tool, it is not
designed for compliance with the European Union directive on electromagnetic compatibility or any other such directives or regulations. As
board builds are at times subject to product availability, it is possible that boards may contain components or assembly materials that are not
RoHS compliant. Ecient Power Conversion Corporation (EPC) makes no guarantee that the purchased board is 100% RoHS compliant. No
Licenses are implied or granted under any patent right or other intellectual property whatsoever. EPC assumes no liability for applications
assistance, customer product design, software performance, or infringement of patents or any other intellectual property rights of any kind.
EPC reserves the right at any time, without notice, to change said circuitry and specications.
Quick Start Procedure
The development board is easy to set up to evaluate the performance of the eGaN FET. Refer to Figure 2 for proper connect and measurement
setup and follow the procedure below:
1. With power o, connect the input power supply bus to +VIN (J5, J6) and ground / return to –VIN (J7, J8).
2. With power o, connect the switch node of the half bridge OUT (J3, J4) to your circuit as required.
3. With power o, connect the gate drive input to +VDD (J1, Pin-1) and ground return to –VDD (J1, Pin-2).
4. With power o, connect the input PWM control signal to PWM (J2, Pin-1) and ground return to any of the remaining J2 pins.
5. Turn on the gate drive supply – make sure the supply is between 7 V and 12 V range.
6. Turn on the bus voltage to the required value (do not exceed the absolute maximum voltage on VOUT as indicated in the table below:
7. Turn on the controller / PWM input source and probe switching node to see switching operation.
8. Once operational, adjust the bus voltage and load PWM control within the operating range and observe the output switching behavior,
eciency and other parameters.
9. For shutdown, please follow steps in reverse.
NOTE. When measuring the high frequency content switch node (OUT), care must be taken to avoid long ground leads. Measure the switch node (OUT) by placing the oscilloscope
probe tip through the large via on the switch node (designed for this purpose) and grounding the probe directly across the GND terminals provided. See Figure 3 for proper scope
probe technique.
THERMAL CONSIDERATIONS
The development board showcases the EPC8000 family of eGaN FET. Although the electrical performance surpasses that for traditional silicon
devices, their relatively smaller size does magnify the thermal management requirements. The development board is intended for bench evaluation
with low ambient temperature and convection cooling. The addition of heat-sinking and forced air cooling can signicantly increase the current rat-
ing of these devices, but care must be taken to not exceed the absolute maximum die temperature of 125°C.
NOTE. The development board does not have any current or thermal protection on board.
www.epc-co.com
EPC Products are distributed exclusively through Digi-Key.
www.digikey.com
Contact us:
www.epc-co.com
Renee Yawger
WW Marketing
Oce: +1.908.475.5702
Mobile: +1.908.619.9678
renee.yawger@epc-co.com
Stephen Tsang
Sales, Asia
Mobile: +852.9408.8351
stephen.tsang@epc-co.com
Bhasy Nair
Global FAE Support
Oce: +1.972.805.8585
Mobile: +1.469.879.2424
bhasy.nair@epc-co.com
Peter Cheng
FAE Support, Asia
Mobile: +886.938.009.706
peter.cheng@epc-co.com
Demonstration Board
EPC9022/23/24/25/27/28/29/30
Quick Start Guide
Half Bridge with Gate Drive for EPC8000 Family
a. EPC9022, 65 V
b. EPC9023, 100 V
c. EPC9024, 40 V
d. EPC9025, 65 V
e. EPC9027, 40 V
f. EPC9028, 40 V
g. EPC9029, 65 V
h. EPC9030, 100 V
Figure 4: Typical Waveforms for VIN = 28 V to 3.3 V/4 A (5 MHz) Buck converter
CH2: (VOUT) Switch node voltage –– CH4: VPWM Input voltage
Figure 1: Block Diagram of Development Board
Figure 2: Proper Connection and Measurement Setup
Figure 3: Proper Measurement of Switch Node – OUT
VDD
VIN
OUT
PWM
Input
Half-Bridge with Bypass
Gate Drive Supply
Logic and
Dead-time
Adjust
Gate Drive
Regulator
LM5113
Gate
Driver
EPC
EFFICIENT POWER CONVERSION
7 V – 12 V
VDD Supply
PWM Input
External Circuit
VIN Supply
See Table 1
for max
VIN
++
+
––
–
IIN
V
A
Gate Drive Supply
(Note Polarity)
(For Eciency
Measurement)
Switch Node
Do not use probe ground lead
Do not let
probe tip
touch the
low-side die!
Place probe
tip on pad
Minimize loop
* Assumes inductive load, maximum current depends on die temperature – actual maximum current with be subject to switching frequency, bus voltage and thermals.
† Limited by time needed to ‘refresh’ high side bootstrap supply voltage.
Table 1: Performance Summary (TA = 25°C)
