NOTE. The development board does not have any current or thermal protection on board. The development board showcases the EPC8000 family of eGaN FET. Although the electrical performance surpasses that for traditional silicon devices, their relatively smaller size does magnify the thermal management requirements. The development board is intended for bench evaluation with low ambient temperature and convection cooling. The addition of heat-sinking and forced air cooling can significantly increase the current rating of these devices, but care must be taken to not exceed the absolute maximum die temperature of 125C. Figure 4: Typical Waveforms for VIN = 28 V to 3.3 V/4 A (5 MHz) Buck converter CH2: (VOUT) Switch node voltage -- CH4: VPWM Input voltage Figure 3: Proper Measurement of Switch Node - OUT Place probe tip on pad Minimize loop THERMAL CONSIDERATIONS Do not let probe tip touch the low-side die! NOTE. When measuring the high frequency content switch node (OUT), care must be taken to avoid long ground leads. Measure the switch node (OUT) by placing the oscilloscope probe tip through the large via on the switch node (designed for this purpose) and grounding the probe directly across the GND terminals provided. See Figure 3 for proper scope probe technique. 7. Turn on the controller / PWM input source and probe switching node to see switching operation. 8. Once operational, adjust the bus voltage and load PWM control within the operating range and observe the output switching behavior, efficiency and other parameters. 9. For shutdown, please follow steps in reverse. a. EPC9022, 65 V b. EPC9023, 100 V c. EPC9024, 40 V g. EPC9029, 65 V h. EPC9030, 100 V Figure 2: Proper Connection and Measurement Setup EFFICIENT POWER CONVERSION EPC Figure 1: Block Diagram of Development Board With power off, connect the input power supply bus to +VIN (J5, J6) and ground / return to -VIN (J7, J8). With power off, connect the switch node of the half bridge OUT (J3, J4) to your circuit as required. With power off, connect the gate drive input to +VDD (J1, Pin-1) and ground return to -VDD (J1, Pin-2). With power off, connect the input PWM control signal to PWM (J2, Pin-1) and ground return to any of the remaining J2 pins. Turn on the gate drive supply - make sure the supply is between 7 V and 12 V range. Turn on the bus voltage to the required value (do not exceed the absolute maximum voltage on VOUT as indicated in the table below: The development board is easy to set up to evaluate the performance of the eGaN FET. Refer to Figure 2 for proper connect and measurement setup and follow the procedure below: PWM Input - (For Efficiency Measurement) PWM Input VDD Logic and Dead-time Adjust - VIN V LM5113 Gate Driver Gate Drive Gate Drive Supply Regulator External Circuit OUT VIN Half-Bridge with Bypass Switch Node + IIN VIN Supply See Table 1 + for max A + Gate Drive Supply (Note Polarity) VDD Supply - 7 V - 12 V Renee Yawger WW Marketing Office: +1.908.475.5702 Mobile: +1.908.619.9678 renee.yawger@epc-co.com Bhasy Nair Global FAE Support Office: +1.972.805.8585 Mobile: +1.469.879.2424 bhasy.nair@epc-co.com Stephen Tsang Sales, Asia Mobile: +852.9408.8351 stephen.tsang@epc-co.com Peter Cheng FAE Support, Asia Mobile: +886.938.009.706 peter.cheng@epc-co.com Quick Start Procedure www.epc-co.com Demonstration Board EPC9022/23/24/25/27/28/29/30 Quick Start Guide Half Bridge with Gate Drive for EPC8000 Family The development board is 2" x 1.5" and contains two eGaN FETs in a half bridge configuration using the Texas Instruments LM5113 gate VDD Demonstration Board Notification The EPC boards are intended for product evaluation purposes only and is not intended for commercial use. As an evaluation tool, it is not designed for compliance with the European Union directive on electromagnetic compatibility or any other such directives or regulations. As board builds are at times subject to product availability, it is possible that boards may contain components or assembly materials that are not RoHS compliant. Efficient Power Conversion Corporation (EPC) makes no guarantee that the purchased board is 100% RoHS compliant. No Licenses are implied or granted under any patent right or other intellectual property whatsoever. EPC assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or any other intellectual property rights of any kind. EPC reserves the right at any time, without notice, to change said circuitry and specifications. www.epc-co.com The development board is in a half bridge topology with onboard gate drives, featuring the EPC8000 family of high frequency enhancement mode (eGaN(R)) field effect transistors (FETs). The purpose of these development boards is to simplify the evaluation process of the EPC8000 family of eGaN FETs by including all the critical components on a single board that can be easily connected into any existing converter. SYMBOL EPC Products are distributed exclusively through Digi-Key. www.digikey.com 1. 2. 3. 4. 5. 6. d. EPC9025, 65 V e. EPC9027, 40 V f. EPC9028, 40 V Do not use probe ground lead Contact us: DESCRIPTION PARAMETER driver, supply and bypass capacitors. The board contains all critical components and layout for optimal switching performance. There are also various probe points to facilitate simple waveform measurement and efficiency calculation. A complete block diagram of the circuit is given in Figure 1. For more information on the EPC8000 family of eGaN FETs, please refer to the datasheets available from EPC at www.epc-co.com. The datasheet should be read in conjunction with this quick start guide. Table 1: Performance Summary (TA = 25C) CONDITIONS Gate Drive Input Supply Range VIN Bus Input Voltage Range VOUT Switch Node Output Voltage IOUT Switch Node Output Current VPWM PWM Logic Input Voltage Threshold Minimum `High' State Input Pulse Width Minimum `Low' State Input Pulse Width When using 40 V devices; EPC8004, EPC8007, EPC8008 When using 65 V devices; EPC8002, EPC8005, EPC8009 When using 100 V devices; EPC8003, EPC8010 When using 40 V devices; EPC8004, EPC8007, EPC8008 When using 65 V devices; EPC8002, EPC8005, EPC8009 When using 100 V devices; EPC8003, EPC8010 When using 40 V device EPC8004 When using 40 V device EPC8007 When using 40 V device EPC8008 When using 65 V device EPC8002 When using 65 V device EPC8005 When using 65 V device EPC8009 When using 100 V device EPC8003 When using 100 V device EPC8010 Input `High' Input `Low' VPWM rise and fall time < 10ns VPWM rise and fall time < 10ns * Assumes inductive load, maximum current depends on die temperature - actual maximum current with be subject to switching frequency, bus voltage and thermals. Limited by time needed to `refresh' high side bootstrap supply voltage. MIN MAX UNITS 7 12 28* 45* 70* 40 65 100 4.4 3.5* 2.2* 1.6* 2.2* 3.5* 2.2* 3.2* 6 1.5 V V V V V V V A A A A A A A A V V ns ns 3.5 0 20 50 NOTE. The development board does not have any current or thermal protection on board. The development board showcases the EPC8000 family of eGaN FET. Although the electrical performance surpasses that for traditional silicon devices, their relatively smaller size does magnify the thermal management requirements. The development board is intended for bench evaluation with low ambient temperature and convection cooling. The addition of heat-sinking and forced air cooling can significantly increase the current rating of these devices, but care must be taken to not exceed the absolute maximum die temperature of 125C. Figure 4: Typical Waveforms for VIN = 28 V to 3.3 V/4 A (5 MHz) Buck converter CH2: (VOUT) Switch node voltage -- CH4: VPWM Input voltage Figure 3: Proper Measurement of Switch Node - OUT Place probe tip on pad Minimize loop THERMAL CONSIDERATIONS Do not let probe tip touch the low-side die! NOTE. When measuring the high frequency content switch node (OUT), care must be taken to avoid long ground leads. Measure the switch node (OUT) by placing the oscilloscope probe tip through the large via on the switch node (designed for this purpose) and grounding the probe directly across the GND terminals provided. See Figure 3 for proper scope probe technique. 7. Turn on the controller / PWM input source and probe switching node to see switching operation. 8. Once operational, adjust the bus voltage and load PWM control within the operating range and observe the output switching behavior, efficiency and other parameters. 9. For shutdown, please follow steps in reverse. Figure 2: Proper Connection and Measurement Setup EFFICIENT POWER CONVERSION g. EPC9029, 65 V h. EPC9030, 100 V Figure 1: Block Diagram of Development Board With power off, connect the input power supply bus to +VIN (J5, J6) and ground / return to -VIN (J7, J8). With power off, connect the switch node of the half bridge OUT (J3, J4) to your circuit as required. With power off, connect the gate drive input to +VDD (J1, Pin-1) and ground return to -VDD (J1, Pin-2). With power off, connect the input PWM control signal to PWM (J2, Pin-1) and ground return to any of the remaining J2 pins. Turn on the gate drive supply - make sure the supply is between 7 V and 12 V range. Turn on the bus voltage to the required value (do not exceed the absolute maximum voltage on VOUT as indicated in the table below: The development board is easy to set up to evaluate the performance of the eGaN FET. Refer to Figure 2 for proper connect and measurement setup and follow the procedure below: PWM Input EPC - (For Efficiency Measurement) PWM Input VDD Logic and Dead-time Adjust - VIN V LM5113 Gate Driver Gate Drive Gate Drive Supply Regulator External Circuit OUT VIN Half-Bridge with Bypass Switch Node + IIN VIN Supply + <28 V A + Gate Drive Supply (Note Polarity) VDD Supply - 7 V - 12 V Bhasy Nair Global FAE Support Office: +1.972.805.8585 Mobile: +1.469.879.2424 bhasy.nair@epc-co.com Stephen Tsang Sales, Asia Mobile: +852.9408.8351 stephen.tsang@epc-co.com Peter Cheng FAE Support, Asia Mobile: +886.938.009.706 peter.cheng@epc-co.com Quick Start Procedure Renee Yawger WW Marketing Office: +1.908.475.5702 Mobile: +1.908.619.9678 renee.yawger@epc-co.com Demonstration Board EPC9022/23/24/25/27/28/29/30 Quick Start Guide Half Bridge with Gate Drive for EPC8000 Family Demonstration Board Notification The EPC boards are intended for product evaluation purposes only and is not intended for commercial use. As an evaluation tool, it is not designed for compliance with the European Union directive on electromagnetic compatibility or any other such directives or regulations. As board builds are at times subject to product availability, it is possible that boards may contain components or assembly materials that are not RoHS compliant. Efficient Power Conversion Corporation (EPC) makes no guarantee that the purchased board is 100% RoHS compliant. No Licenses are implied or granted under any patent right or other intellectual property whatsoever. EPC assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or any other intellectual property rights of any kind. EPC reserves the right at any time, without notice, to change said circuitry and specifications. www.epc-co.com The development board is in a half bridge topology with onboard gate drives, featuring the EPC8000 family of high frequency enhancement mode (eGaN(R)) field effect transistors (FETs). The purpose of these development boards is to simplify the evaluation process of the EPC8000 family of eGaN FETs by including all the critical components on a single board that can be easily connected into any existing converter. The development board is 2" x 1.5" and contains two eGaN FETs in a half bridge configuration using the Texas Instruments LM5113 gate SYMBOL VDD EPC Products are distributed exclusively through Digi-Key. www.digikey.com 1. 2. 3. 4. 5. 6. d. EPC9025, 65 V e. EPC9027, 40 V f. EPC9028, 40 V www.epc-co.com a. EPC9022, 65 V b. EPC9023, 100 V c. EPC9024, 40 V Do not use probe ground lead Contact us: DESCRIPTION PARAMETER driver, supply and bypass capacitors. The board contains all critical components and layout for optimal switching performance. There are also various probe points to facilitate simple waveform measurement and efficiency calculation. A complete block diagram of the circuit is given in Figure 1. For more information on the EPC8000 family of eGaN FETs, please refer to the datasheets available from EPC at www.epc-co.com. The datasheet should be read in conjunction with this quick start guide. CONDITIONS Table 1: Performance Summary (TA = 25C) MIN MAX UNITS Gate Drive Input Supply Range VIN Bus Input Voltage Range VOUT Switch Node Output Voltage IOUT Switch Node Output Current VPWM PWM Logic Input Voltage Threshold FMIN Minimum Switching Frequency Minimum `High' State Input Pulse Width Minimum `Low' State Input Pulse Width 7 40 V devices; EPC9024, EPC9027, EPC9028 65 V devices; EPC9022, EPC9025, EPC9029 100 V devices; EPC9023, EPC9030 40 V devices; EPC9024, EPC9027, EPC9028 65 V device EPC9022, EPC9025, EPC9029 100 V devices; EPC9023, EPC9030 40 V device EPC9024 40 V device EPC9027 40 V device EPC9028 65 V device EPC9022 65 V device EPC9025 65 V device EPC9029 100 V device EPC9023 100 V device EPC9030 Input `High' Input `Low' Bootstrap Capacitor Limited VPWM rise and fall time < 10ns VPWM rise and fall time < 10ns * Assumes inductive load, maximum current depends on die temperature - actual maximum current with be subject to switching frequency, bus voltage and thermals. Limited by time needed to `refresh' high side bootstrap supply voltage. 3.5 0 500 20 50 12 28* 45* 70* 40 65 100 4.4* 3.5* 2.2* 1.6* 2.2* 3.5* 2.2* 3.2* 6 1.5 V V V V V V V A A A A A A A A V V kHz ns ns NOTE. The development board does not have any current or thermal protection on board. The development board showcases the EPC8000 family of eGaN FET. Although the electrical performance surpasses that for traditional silicon devices, their relatively smaller size does magnify the thermal management requirements. The development board is intended for bench evaluation with low ambient temperature and convection cooling. The addition of heat-sinking and forced air cooling can significantly increase the current rating of these devices, but care must be taken to not exceed the absolute maximum die temperature of 125C. Figure 4: Typical Waveforms for VIN = 28 V to 3.3 V/4 A (5 MHz) Buck converter CH2: (VOUT) Switch node voltage -- CH4: VPWM Input voltage Figure 3: Proper Measurement of Switch Node - OUT Minimize loop THERMAL CONSIDERATIONS d. EPC9025, 65 V e. EPC9027, 40 V f. EPC9028, 40 V g. EPC9029, 65 V h. EPC9030, 100 V With power off, connect the input power supply bus to +VIN (J5, J6) and ground / return to -VIN (J7, J8). With power off, connect the switch node of the half bridge OUT (J3, J4) to your circuit as required. With power off, connect the gate drive input to +VDD (J1, Pin-1) and ground return to -VDD (J1, Pin-2). With power off, connect the input PWM control signal to PWM (J2, Pin-1) and ground return to any of the remaining J2 pins. Turn on the gate drive supply - make sure the supply is between 7 V and 12 V range. Turn on the bus voltage to the required value (do not exceed the absolute maximum voltage on VOUT as indicated in the table below: Place probe tip on pad Do not let probe tip touch the low-side die! NOTE. When measuring the high frequency content switch node (OUT), care must be taken to avoid long ground leads. Measure the switch node (OUT) by placing the oscilloscope probe tip through the large via on the switch node (designed for this purpose) and grounding the probe directly across the GND terminals provided. See Figure 3 for proper scope probe technique. 7. Turn on the controller / PWM input source and probe switching node to see switching operation. 8. Once operational, adjust the bus voltage and load PWM control within the operating range and observe the output switching behavior, efficiency and other parameters. 9. For shutdown, please follow steps in reverse. Do not use probe ground lead Figure 2: Proper Connection and Measurement Setup EFFICIENT POWER CONVERSION Figure 1: Block Diagram of Development Board EPC PWM Input - (For Efficiency Measurement) PWM Input Logic and Dead-time Adjust LM5113 Gate Driver Gate Drive Gate Drive Supply Regulator OUT VIN Half-Bridge with Bypass External Circuit - VIN V VIN Supply Switch Node + See Table 1 + for max IIN A + Gate Drive Supply (Note Polarity) VDD Supply - Contact us: Bhasy Nair Global FAE Support Office: +1.972.805.8585 Mobile: +1.469.879.2424 bhasy.nair@epc-co.com Renee Yawger WW Marketing Office: +1.908.475.5702 Mobile: +1.908.619.9678 renee.yawger@epc-co.com DESCRIPTION Demonstration Board EPC9022/23/24/25/27/28/29/30 Quick Start Guide www.epc-co.com Peter Cheng FAE Support, Asia Mobile: +886.938.009.706 peter.cheng@epc-co.com Stephen Tsang Sales, Asia Mobile: +852.9408.8351 stephen.tsang@epc-co.com a. EPC9022, 65 V b. EPC9023, 100 V c. EPC9024, 40 V 1. 2. 3. 4. 5. 6. The development board is easy to set up to evaluate the performance of the eGaN FET. Refer to Figure 2 for proper connect and measurement setup and follow the procedure below: VDD 7 V - 12 V Quick Start Procedure www.epc-co.com The development board is in a half bridge topology with onboard gate drives, featuring the EPC8000 family of high frequency enhancement mode (eGaN(R)) field effect transistors (FETs). The purpose of these development boards is to simplify the evaluation process of the EPC8000 family of eGaN FETs by including all the critical components on a single board that can be easily connected into any existing converter. Half Bridge with Gate Drive for EPC8000 Family The development board is 2" x 1.5" and contains two eGaN FETs in a half bridge configuration using the Texas Instruments LM5113 gate SYMBOL VDD EPC Products are distributed exclusively through Digi-Key. www.digikey.com Demonstration Board Notification The EPC boards are intended for product evaluation purposes only and is not intended for commercial use. As an evaluation tool, it is not designed for compliance with the European Union directive on electromagnetic compatibility or any other such directives or regulations. As board builds are at times subject to product availability, it is possible that boards may contain components or assembly materials that are not RoHS compliant. Efficient Power Conversion Corporation (EPC) makes no guarantee that the purchased board is 100% RoHS compliant. No Licenses are implied or granted under any patent right or other intellectual property whatsoever. EPC assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or any other intellectual property rights of any kind. PARAMETER driver, supply and bypass capacitors. The board contains all critical components and layout for optimal switching performance. There are also various probe points to facilitate simple waveform measurement and efficiency calculation. A complete block diagram of the circuit is given in Figure 1. For more information on the EPC8000 family of eGaN FETs, please refer to the datasheets available from EPC at www.epc-co.com. The datasheet should be read in conjunction with this quick start guide. Table 1: Performance Summary (TA = 25C) CONDITIONS MIN Gate Drive Input Supply Range PWM Logic Input Voltage Threshold VPWM Switch Node Output Current IOUT Switch Node Output Voltage VOUT Bus Input Voltage Range VIN Minimum `High' State Input Pulse Width Minimum `Low' State Input Pulse Width EPC reserves the right at any time, without notice, to change said circuitry and specifications. 7 When using 40 V devices; EPC8004, EPC8007, EPC8008 When using 65 V devices; EPC8002, EPC8005, EPC8009 When using 100 V devices; EPC8003, EPC8010 When using 40 V devices; EPC8004, EPC8007, EPC8008 When using 65 V devices; EPC8002, EPC8005, EPC8009 When using 100 V devices; EPC8003, EPC8010 When using 40 V device EPC8004 When using 40 V device EPC8007 When using 40 V device EPC8008 When using 65 V device EPC8002 When using 65 V device EPC8005 When using 65 V device EPC8009 When using 100 V device EPC8003 When using 100 V device EPC8010 Input `High' Input `Low' VPWM rise and fall time < 10ns VPWM rise and fall time < 10ns 3.5 0 20 50 MAX 12 28* 45* 70* 40 65 100 4.4 3.5* 2.2* 1.6* 2.2* 3.5* 2.2* 3.2* 6 1.5 UNITS V V V V V V V A A A A A A A A V V ns ns * Assumes inductive load, maximum current depends on die temperature - actual maximum current with be subject to switching frequency, bus voltage and thermals. Limited by time needed to `refresh' high side bootstrap supply voltage. NOTE. The development board does not have any current or thermal protection on board. The development board showcases the EPC8000 family of eGaN FET. Although the electrical performance surpasses that for traditional silicon devices, their relatively smaller size does magnify the thermal management requirements. The development board is intended for bench evaluation with low ambient temperature and convection cooling. The addition of heat-sinking and forced air cooling can significantly increase the current rating of these devices, but care must be taken to not exceed the absolute maximum die temperature of 125C. Figure 4: Typical Waveforms for VIN = 28 V to 3.3 V/4 A (5 MHz) Buck converter CH2: (VOUT) Switch node voltage -- CH4: VPWM Input voltage Figure 3: Proper Measurement of Switch Node - OUT Minimize loop THERMAL CONSIDERATIONS d. EPC9025, 65 V e. EPC9027, 40 V f. EPC9028, 40 V g. EPC9029, 65 V h. EPC9030, 100 V With power off, connect the input power supply bus to +VIN (J5, J6) and ground / return to -VIN (J7, J8). With power off, connect the switch node of the half bridge OUT (J3, J4) to your circuit as required. With power off, connect the gate drive input to +VDD (J1, Pin-1) and ground return to -VDD (J1, Pin-2). With power off, connect the input PWM control signal to PWM (J2, Pin-1) and ground return to any of the remaining J2 pins. Turn on the gate drive supply - make sure the supply is between 7 V and 12 V range. Turn on the bus voltage to the required value (do not exceed the absolute maximum voltage on VOUT as indicated in the table below: Place probe tip on pad Do not let probe tip touch the low-side die! NOTE. When measuring the high frequency content switch node (OUT), care must be taken to avoid long ground leads. Measure the switch node (OUT) by placing the oscilloscope probe tip through the large via on the switch node (designed for this purpose) and grounding the probe directly across the GND terminals provided. See Figure 3 for proper scope probe technique. 7. Turn on the controller / PWM input source and probe switching node to see switching operation. 8. Once operational, adjust the bus voltage and load PWM control within the operating range and observe the output switching behavior, efficiency and other parameters. 9. For shutdown, please follow steps in reverse. Do not use probe ground lead Figure 2: Proper Connection and Measurement Setup EFFICIENT POWER CONVERSION Figure 1: Block Diagram of Development Board PWM Input EPC - (For Efficiency Measurement) PWM Input Logic and Dead-time Adjust LM5113 Gate Driver Gate Drive Gate Drive Supply Regulator OUT VIN Half-Bridge with Bypass External Circuit - VIN V VIN Supply Switch Node + + <28 V IIN A + Gate Drive Supply (Note Polarity) VDD Supply - Contact us: Bhasy Nair Global FAE Support Office: +1.972.805.8585 Mobile: +1.469.879.2424 bhasy.nair@epc-co.com Renee Yawger WW Marketing Office: +1.908.475.5702 Mobile: +1.908.619.9678 renee.yawger@epc-co.com DESCRIPTION Demonstration Board EPC9022/23/24/25/27/28/29/30 Quick Start Guide www.epc-co.com Peter Cheng FAE Support, Asia Mobile: +886.938.009.706 peter.cheng@epc-co.com Stephen Tsang Sales, Asia Mobile: +852.9408.8351 stephen.tsang@epc-co.com a. EPC9022, 65 V b. EPC9023, 100 V c. EPC9024, 40 V 1. 2. 3. 4. 5. 6. The development board is easy to set up to evaluate the performance of the eGaN FET. Refer to Figure 2 for proper connect and measurement setup and follow the procedure below: VDD 7 V - 12 V Quick Start Procedure www.epc-co.com The development board is in a half bridge topology with onboard gate drives, featuring the EPC8000 family of high frequency enhancement mode (eGaN(R)) field effect transistors (FETs). The purpose of these development boards is to simplify the evaluation process of the EPC8000 family of eGaN FETs by including all the critical components on a single board that can be easily connected into any existing converter. Half Bridge with Gate Drive for EPC8000 Family The development board is 2" x 1.5" and contains two eGaN FETs in a half bridge configuration using the Texas Instruments LM5113 gate SYMBOL VDD EPC Products are distributed exclusively through Digi-Key. www.digikey.com Demonstration Board Notification The EPC boards are intended for product evaluation purposes only and is not intended for commercial use. As an evaluation tool, it is not designed for compliance with the European Union directive on electromagnetic compatibility or any other such directives or regulations. As board builds are at times subject to product availability, it is possible that boards may contain components or assembly materials that are not RoHS compliant. Efficient Power Conversion Corporation (EPC) makes no guarantee that the purchased board is 100% RoHS compliant. No Licenses are implied or granted under any patent right or other intellectual property whatsoever. EPC assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or any other intellectual property rights of any kind. PARAMETER driver, supply and bypass capacitors. The board contains all critical components and layout for optimal switching performance. There are also various probe points to facilitate simple waveform measurement and efficiency calculation. A complete block diagram of the circuit is given in Figure 1. For more information on the EPC8000 family of eGaN FETs, please refer to the datasheets available from EPC at www.epc-co.com. The datasheet should be read in conjunction with this quick start guide. Table 1: Performance Summary (TA = 25C) MIN MAX UNITS CONDITIONS Gate Drive Input Supply Range Minimum Switching Frequency Minimum `High' State Input Pulse Width Minimum `Low' State Input Pulse Width FMIN PWM Logic Input Voltage Threshold VPWM Switch Node Output Current IOUT Switch Node Output Voltage VOUT Bus Input Voltage Range VIN EPC reserves the right at any time, without notice, to change said circuitry and specifications. 7 40 V devices; EPC9024, EPC9027, EPC9028 65 V devices; EPC9022, EPC9025, EPC9029 100 V devices; EPC9023, EPC9030 40 V devices; EPC9024, EPC9027, EPC9028 65 V device EPC9022, EPC9025, EPC9029 100 V devices; EPC9023, EPC9030 40 V device EPC9024 40 V device EPC9027 40 V device EPC9028 65 V device EPC9022 65 V device EPC9025 65 V device EPC9029 100 V device EPC9023 100 V device EPC9029 Input `High' Input `Low' Bootstrap Capacitor Limited VPWM rise and fall time < 10ns VPWM rise and fall time < 10ns 3.5 0 500 20 50 12 28* 45* 70* 40 65 100 4.4* 3.5* 2.2* 1.6* 2.2* 3.5* 2.2* 3.2* 6 1.5 V V V V V V V A A A A A A A A V V kHz ns ns * Assumes inductive load, maximum current depends on die temperature - actual maximum current with be subject to switching frequency, bus voltage and thermals. Limited by time needed to `refresh' high side bootstrap supply voltage. TDK, C1005X5R1E223K050BA 4 1 C14 Capacitor, 0.1uF, 10%, 25V, X5R TDK, C1005X5R1E104K 5 3 C16, C17, C18 Capacitor, - SEE TABLE 3 6 1 C13 Capacitor, 1uF, 10%, 25V, X5R 7 1 C21 Capacitor, - SEE TABLE 3 8 2 D1, D2 Schottky Diode, 30V Diodes Inc., SDM03U40-7 9 3 J1, J2, J9 Connector 2pins of Tyco, 4-103185-0 10 6 J3, J4, J5, J6, J7, J8 Connector FCI, 68602-224HLF 11 2 Q1, Q2 eGaN(R) FET - SEE TABLE 3 SEE TABLE 3 12 1 R1 Resistor, 10.0K, 5%, 1/8W Stackpole, RMCF0603FT10K0 13 2 R2, R15 Resistor, 0 Ohm, 1/8W Stackpole, RMCF0603ZT0R00 Stackpole, RMCF0603JT7R50 C16 C17 C18 J11 Murata, GRM188R61E105KA12D 2 R4,R5 Resistor, 7.5 Ohm, 5%, 1/16W 2 TP1, TP2 Test Point Keystone Elect, 5015 16 1 U1 I.C., Logic Fairchild, NC7SZ00L6X 17 1 U2 I.C., Gate driver Texas Instruments, LM5113 18 1 U3 I.C., Regulator Microchip, MCP1703T-5002E/MC VDD LOH 19 1 U4 I.C., Logic Fairchild, NC7SZ08L6X 20 0 HS1 Optional Heatsink HeatSink15mmX15mm 21 0 R14, R22 Optional Resistor 22 0 P1,P2 Optional Potentiometer C21 Capacitor, 4.7uF, 10%, 50V, X5R TDK, C2012X5R1H475K125AB 11 2 Q1, Q2 eGaN(R) FET 5 3 C16, C17, C18 Capacitor, 0.01uF, 20%, 100V, X7R TDK, C1005X7S2A103M050BB 7 1 C21 Capacitor, 1uF, 10%, 100V, X7R TDK, CGA4J3X7S2A105K125A 11 2 Q1, Q2 eGaN(R) FET 5 3 C16, C17, C18 Capacitor, 0.1uF, 20%, 50V, X5R TDK, C1005X5R1H104K050BB 7 1 C21 Capacitor, 4.7uF, 10%, 50V, X5R TDK, C2012X5R1H475K125AB 11 2 Q1, Q2 eGaN(R) FET 5 3 C16, C17, C18 Capacitor, 0.1uF, 20%, 50V, X5R TDK, C1005X5R1H104K050BB 7 1 C21 Capacitor, 4.7uF, 10%, 50V, X5R TDK, C2012X5R1H475K125AB 11 2 Q1, Q2 eGaN(R) FET 5 3 C16, C17, C18 Capacitor, 0.01uF, 20%, 100V, X7R TDK, C1005X7S2A103M050BB 7 1 C21 Capacitor, 1uF, 10%, 100V, X7R TDK, CGA4J3X7S2A105K125A 11 2 Q1, Q2 eGaN(R) FET 5 3 C16, C17, C18 Capacitor, 0.01uF, 20%, 100V, X7R TDK, C1005X7S2A103M050BB 7 1 C21 Capacitor, 1uF, 10%, 100V, X7R TDK, CGA4J3X7S2A105K125A 11 2 Q1, Q2 eGaN(R) FET VDD U4 A GND 4 R2 Zero 4 2 4 Y GND R1 10k R14 3 B 2 U1 A 1 NC7SZ00L6X 5 5 6 VDD MCP1703 NC NC NC C10 1uF, 25V 6 7 U3 IN 8 5 R15 Zero CON2 1 2 7 - 12 Vdc J1 J2 1 2 CON2 J9 1 2 CON2 B EPC8010 1 EPC8008 EPC8009 1uF, 25V Optional R22 NC GND 2 3 NC 1 OUT 2 EPC8007 A EPC9030 EPC8005 PWM1 EPC9029 GND EPC9028 EPC8004 9 EPC9027 3 1 1 7 D TDK, C1005X5R1H104K050BB C7 100pf Capacitor, 0.1uF, 20%, 50V, X5R 7.5 C16, C17, C18 Optional 3 EPC8003 SDM03U40 R5 5 C6 100pf eGaN(R) FET D2 Q1, Q2 7.5 2 2 11 P2 Optional TDK, CGA4J3X7S2A105K125A PWM2 Capacitor, 1uF, 10%, 100V, X7R C C21 SDM03U40 R4 1 D1 7 Y TDK, C1005X7S2A103M050BB GND Capacitor, 0.01uF, 20%, 100V, X7R NC7SZ08L6X C16, C17, C18 2 3 P1 Opt. 5 EPC8002 B eGaN(R) FET C13 100nF, 25V C14 22nF, 25V C12 VCC Q1, Q2 C4 1uF, 25V 2 C11 1uF, 25V 11 VCC TDK, CGA4J3X7S2A105K125A 3 TDK, C1005X7S2A103M050BB Capacitor, 1uF, 10%, 100V, X7R HS Capacitor, 0.01uF, 20%, 100V, X7R C21 HOL C16, C17, C18 1 EPC9025 Manufacturer / Part # HI 3 7 EPC9024 Part Description LI 5 EPC9022 EPC9023 Reference HB Item HOH Table 3: Variable BOM Components VSS PV37Y LOL 4 U2 LM5113TME 14 Board Number See Table J4 CON4 SW OUT HS1 1 5 Q2 J3 CON4 See Table Q1 1 2 3 4 TP2 Keystone 5015 SEE TABLE 3 15 Qty D C B SEE TABLE 3 6 Capacitor, 22nF, 10%, 25V, X5R 5 C12 See Table 3 on variable components 1 Figure 5: Development Board Schematic 3 J8 CON4 Kemet, C0402C101K5GACTU TP1 Keystone 5015 Capacitor, 100pF, 5%, 50V, NP0 Return C6, C7 J7 CON4 2 TP3 1 CON1 2 See Table Murata, GRM188R61E105KA12D J6 CON4 Capacitor, 1uF, 10%, 25V, X5R J5 CON4 C4, C10, C11 28V Max A 3 4 3 2 1 1 6 Manufacturer / Part # 1 Part Description 1 2 3 4 Reference 4 3 2 1 Qty 1 2 3 4 Item 4 3 2 1 Table 2 : Bill of Material 3 Qty C12 C6, C7 C4, C10, C11 Reference Capacitor, - SEE TABLE 3 Capacitor, 0.1uF, 10%, 25V, X5R Capacitor, 22nF, 10%, 25V, X5R Capacitor, 100pF, 5%, 50V, NP0 Capacitor, 1uF, 10%, 25V, X5R Part Description TDK, C1005X5R1E104K TDK, C1005X5R1E223K050BA Kemet, C0402C101K5GACTU Murata, GRM188R61E105KA12D Manufacturer / Part # Murata, GRM188R61E105KA12D Part Description TDK, C1005X5R1H104K050BB TDK, C1005X7S2A103M050BB 1 2 3 4 Item 2 C14 Capacitor, 1uF, 10%, 25V, X5R SEE TABLE 3 Reference Capacitor, 1uF, 10%, 100V, X7R Capacitor, 0.01uF, 20%, 100V, X5R 4 3 2 1 1 1 C16, C17, C18 Capacitor, - SEE TABLE 3 Diodes Inc., SDM03U40-7 C16, C17, C18 1 2 3 4 2 1 C13 Schottky Diode, 30V 2pins of Tyco, 4-103185-0 Qty C21 4 3 2 1 3 3 C21 Connector FCI, 68602-224HLF 3 1 2 3 4 4 1 D1, D2 Connector SEE TABLE 3 Item 1 eGaN(R) FET TDK, C1005X7S2A103M050BB 4 3 2 1 5 1 J1, J2, J9 eGaN(R) FET - SEE TABLE 3 Stackpole, RMCF0603FT10K0 5 Q1, Q2 Capacitor, 0.01uF, 20%, 100V, X5R TDK, CGA4J3X7S2A105K125A 1 6 2 J3, J4, J5, J6, J7, J8 Resistor, 10.0K, 5%, 1/8W Stackpole, RMCF0603ZT0R00 Keystone Elect, 5015 7 2 C16, C17, C18 Capacitor, 1uF, 10%, 100V, X7R EPC8003 1 7 3 Q1, Q2 Resistor, 0 Ohm, 1/8W Stackpole, RMCF0603JT7R50 11 3 C21 eGaN(R) FET TDK, C1005X5R1H104K050BB HB 8 6 R1 Resistor, 7.5 Ohm, 5%, 1/16W 5 1 Q1, Q2 Capacitor, 0.1uF, 20%, 50V, X5R TDK, C2012X5R1H475K125AB VDD 9 2 R2, R15 Test Point 7 2 C16, C17, C18 Capacitor, 4.7uF, 10%, 50V, X5R EPC8004 LOH 10 1 R4,R5 11 3 C21 eGaN(R) FET TDK, C1005X7S2A103M050BB HOH 11 2 TP1, TP2 5 1 Q1, Q2 Capacitor, 0.01uF, 20%, 100V, X5R TDK, CGA4J3X7S2A105K125A LOL 12 2 Fairchild, NC7SZ00L6X 7 2 C16, C17, C18 Capacitor, 1uF, 10%, 100V, X7R EPC8005 VSS 13 2 I.C., Logic Texas Instruments, LM5113 11 3 C21 eGaN(R) FET TDK, C1005X5R1H104K050BB HS 14 U1 I.C., Gate driver Microchip, MCP1703T-5002E/MC 5 1 Q1, Q2 Capacitor, 0.1uF, 20%, 50V, X5R TDK, C2012X5R1H475K125AB HOL 15 1 U2 I.C., Regulator Fairchild, NC7SZ08L6X 7 2 C16, C17, C18 Capacitor, 4.7uF, 10%, 50V, X5R EPC8007 LI 16 1 U3 I.C., Logic HeatSink15mmX15mm 11 3 C21 eGaN(R) FET TDK, C1005X5R1H104K050BB HI 17 1 U4 Optional Heatsink 5 1 Q1, Q2 Capacitor, 0.1uF, 20%, 50V, X5R TDK, C2012X5R1H475K125AB GND 18 1 HS1 Optional Resistor PV37Y 7 2 C16, C17, C18 Capacitor, 4.7uF, 10%, 50V, X5R EPC8008 9 19 0 R14, R22 Optional Potentiometer 11 3 C21 eGaN(R) FET TDK, C1005X7S2A103M050BB PWM1 20 0 P1,P2 5 1 Q1, Q2 Capacitor, 0.01uF, 20%, 100V, X5R TDK, CGA4J3X7S2A105K125A EPC8009 D D Figure 5: Development Board Schematic See Table 3 on variable components Table 2 : Bill of Material 21 0 SEE TABLE 3 22 7 2 C16, C17, C18 Capacitor, 1uF, 10%, 100V, X7R Table 3: Variable BOM Components 11 3 C21 eGaN(R) FET TDK, C1005X7S2A103M050BB 6 5 4 3 J8 CON4 TP1 Keystone 5015 C C6 100pF D2 J4 CON4 J7 CON4 C7 100pF R15 Zero See Table 7.5 Q2 Optional 7.5 2 P2 Optional Y GND GND See Table J11 SW OUT D1 1uF, 25V SDM03U40 R4 NC7SZ08L6X C13 See Table 22nF, 25V J5 CON4 TP2 Keystone 5015 MCP1703 C16 C17 C18 U2 LM5113TME J3 CON4 100nF, 25V C14 2 P1 Opt. B TP3 1 CON1 SDM03U40 R5 R14 VDD U4 A R2 Zero Manufacturer / Part # 5 1 Q1, Q2 Capacitor, 0.01uF, 20%, 100V, X5R TDK, CGA4J3X7S2A105K125A 4 Board Number 7 2 C16, C17, C18 Capacitor, 1uF, 10%, 100V, X7R EPC8010 Y Optional NC7SZ00L6X EPC9022 11 3 C21 eGaN(R) FET 4 EPC8002 5 1 Q1, Q2 GND EPC9023 7 2 GND EPC9024 EPC9025 EPC9027 EPC9028 EPC9029 EPC9030 11 NC J6 CON4 5 2 1 NC 5 Q1 5 3 2 C12 B R22 2 B 6 1 2 CON2 J9 1 2 CON2 B PWM2 C 28V Max VDD R1 10k U1 A VCC 1 J2 NC HS1 NC CON2 7 C4 1uF, 25V NC 3 A OUT C11 1uF, 25V 6 C10 1uF, 25V VCC 1 U3 IN 1 2 8 J1 A 6 5 4 3 2 1 7 - 12 Vdc Return NOTE. The development board does not have any current or thermal protection on board. The development board showcases the EPC8000 family of eGaN FET. Although the electrical performance surpasses that for traditional silicon devices, their relatively smaller size does magnify the thermal management requirements. The development board is intended for bench evaluation with low ambient temperature and convection cooling. The addition of heat-sinking and forced air cooling can significantly increase the current rating of these devices, but care must be taken to not exceed the absolute maximum die temperature of 125C. Figure 4: Typical Waveforms for VIN = 28 V to 3.3 V/4 A (5 MHz) Buck converter CH2: (VOUT) Switch node voltage -- CH4: VPWM Input voltage Figure 3: Proper Measurement of Switch Node - OUT Place probe tip on pad Minimize loop THERMAL CONSIDERATIONS Do not let probe tip touch the low-side die! NOTE. When measuring the high frequency content switch node (OUT), care must be taken to avoid long ground leads. Measure the switch node (OUT) by placing the oscilloscope probe tip through the large via on the switch node (designed for this purpose) and grounding the probe directly across the GND terminals provided. See Figure 3 for proper scope probe technique. 7. Turn on the controller / PWM input source and probe switching node to see switching operation. 8. Once operational, adjust the bus voltage and load PWM control within the operating range and observe the output switching behavior, efficiency and other parameters. 9. For shutdown, please follow steps in reverse. a. EPC9022, 65 V b. EPC9023, 100 V c. EPC9024, 40 V g. EPC9029, 65 V h. EPC9030, 100 V Figure 2: Proper Connection and Measurement Setup EFFICIENT POWER CONVERSION EPC Figure 1: Block Diagram of Development Board With power off, connect the input power supply bus to +VIN (J5, J6) and ground / return to -VIN (J7, J8). With power off, connect the switch node of the half bridge OUT (J3, J4) to your circuit as required. With power off, connect the gate drive input to +VDD (J1, Pin-1) and ground return to -VDD (J1, Pin-2). With power off, connect the input PWM control signal to PWM (J2, Pin-1) and ground return to any of the remaining J2 pins. Turn on the gate drive supply - make sure the supply is between 7 V and 12 V range. Turn on the bus voltage to the required value (do not exceed the absolute maximum voltage on VOUT as indicated in the table below: The development board is easy to set up to evaluate the performance of the eGaN FET. Refer to Figure 2 for proper connect and measurement setup and follow the procedure below: PWM Input - (For Efficiency Measurement) PWM Input VDD Logic and Dead-time Adjust - VIN V LM5113 Gate Driver Gate Drive Gate Drive Supply Regulator External Circuit OUT VIN Half-Bridge with Bypass Switch Node + IIN VIN Supply See Table 1 + for max A + Gate Drive Supply (Note Polarity) VDD Supply - 7 V - 12 V Renee Yawger WW Marketing Office: +1.908.475.5702 Mobile: +1.908.619.9678 renee.yawger@epc-co.com Bhasy Nair Global FAE Support Office: +1.972.805.8585 Mobile: +1.469.879.2424 bhasy.nair@epc-co.com Stephen Tsang Sales, Asia Mobile: +852.9408.8351 stephen.tsang@epc-co.com Peter Cheng FAE Support, Asia Mobile: +886.938.009.706 peter.cheng@epc-co.com Quick Start Procedure www.epc-co.com Demonstration Board EPC9022/23/24/25/27/28/29/30 Quick Start Guide Half Bridge with Gate Drive for EPC8000 Family The development board is 2" x 1.5" and contains two eGaN FETs in a half bridge configuration using the Texas Instruments LM5113 gate VDD Demonstration Board Notification The EPC boards are intended for product evaluation purposes only and is not intended for commercial use. As an evaluation tool, it is not designed for compliance with the European Union directive on electromagnetic compatibility or any other such directives or regulations. As board builds are at times subject to product availability, it is possible that boards may contain components or assembly materials that are not RoHS compliant. Efficient Power Conversion Corporation (EPC) makes no guarantee that the purchased board is 100% RoHS compliant. No Licenses are implied or granted under any patent right or other intellectual property whatsoever. EPC assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or any other intellectual property rights of any kind. EPC reserves the right at any time, without notice, to change said circuitry and specifications. www.epc-co.com The development board is in a half bridge topology with onboard gate drives, featuring the EPC8000 family of high frequency enhancement mode (eGaN(R)) field effect transistors (FETs). The purpose of these development boards is to simplify the evaluation process of the EPC8000 family of eGaN FETs by including all the critical components on a single board that can be easily connected into any existing converter. SYMBOL EPC Products are distributed exclusively through Digi-Key. www.digikey.com 1. 2. 3. 4. 5. 6. d. EPC9025, 65 V e. EPC9027, 40 V f. EPC9028, 40 V Do not use probe ground lead Contact us: DESCRIPTION PARAMETER driver, supply and bypass capacitors. The board contains all critical components and layout for optimal switching performance. There are also various probe points to facilitate simple waveform measurement and efficiency calculation. A complete block diagram of the circuit is given in Figure 1. For more information on the EPC8000 family of eGaN FETs, please refer to the datasheets available from EPC at www.epc-co.com. The datasheet should be read in conjunction with this quick start guide. Table 1: Performance Summary (TA = 25C) CONDITIONS Gate Drive Input Supply Range VIN Bus Input Voltage Range VOUT Switch Node Output Voltage IOUT Switch Node Output Current VPWM PWM Logic Input Voltage Threshold Minimum `High' State Input Pulse Width Minimum `Low' State Input Pulse Width When using 40 V devices; EPC8004, EPC8007, EPC8008 When using 65 V devices; EPC8002, EPC8005, EPC8009 When using 100 V devices; EPC8003, EPC8010 When using 40 V devices; EPC8004, EPC8007, EPC8008 When using 65 V devices; EPC8002, EPC8005, EPC8009 When using 100 V devices; EPC8003, EPC8010 When using 40 V device EPC8004 When using 40 V device EPC8007 When using 40 V device EPC8008 When using 65 V device EPC8002 When using 65 V device EPC8005 When using 65 V device EPC8009 When using 100 V device EPC8003 When using 100 V device EPC8010 Input `High' Input `Low' VPWM rise and fall time < 10ns VPWM rise and fall time < 10ns * Assumes inductive load, maximum current depends on die temperature - actual maximum current with be subject to switching frequency, bus voltage and thermals. Limited by time needed to `refresh' high side bootstrap supply voltage. MIN MAX UNITS 7 12 28* 45* 70* 40 65 100 4.4 3.5* 2.2* 1.6* 2.2* 3.5* 2.2* 3.2* 6 1.5 V V V V V V V A A A A A A A A V V ns ns 3.5 0 20 50