1
FEATURES
THS4022
DandDGNPackage
(TopView)
THS4021
DandDGNPackage
(TopView)
11
22
33
44
88
77
66
55
1OUTNULL
1IN–IN–
1IN+IN+
–VCC
VCC–
VCC+
NULL
2OUTVCC+
2IN–OUT
2IN+NC
NC-Nointernalconnection
CrossSectionViewShowing
PowerPADOption(DGN)
DESCRIPTION
1
10
100
Vn − Voltage Noise − nV//Hz
In − Current Noise − pA//Hz
Vn
In
f − Frequency − Hz
10 100 1k 100k10k
G001
VCC = ± 15 V and ± 5 V
TA = 25°C
THS4021
THS4022
SLOS265C – SEPTEMBER 1999 – REVISED JULY 2007www.ti.com
350-MHz LOW-NOISE HIGH-SPEED AMPLIFIERS
23
•Ultralow 1.5-nV/ √Hz Voltage Noise•High Speed:
– 350-MHz Bandwidth (G = 10, – 3 dB)– 470-V/ μs Slew Rate– 40-ns Settling Time (0.1%)•Stable at a Gain of 10 ( – 9) or Greater•High Output Drive, I
O
= 100 mA (typ)•Excellent Video Performance:– 17-MHz Bandwidth (0.1 dB, G = 10)– 0.02% Differential Gain– 0.08 °Differential Phase
VOLTAGE AND CURRENT NOISE•Very Low Distortion:
vs– THD = – 68 dBc (f = 1 MHz, R
L
= 150 Ω)
FREQUENCY•Wide Range of Power Supplies:– V
CC
= ± 5 V to ± 15 V•Available in Standard SOIC or MSOPPowerPAD™ Package•Evaluation Module Available
The THS4021 and THS4022 are ultralow voltagenoise, high-speed voltage feedback amplifiers thatare ideal for applications requiring low voltage noise,including communication and imaging. Thesingle-amplifier THS4021 and the dual-amplifierTHS4022 offer very good ac performance with350-MHz bandwidth, 470-V/ μs slew rate, and 40-nssettling time (0.1%). The THS4021 and THS4022 arestable at gains of 10 ( – 9) or greater. These amplifiershave a high drive capability of 100 mA and draw only7.8-mA supply current per channel. With totalharmonic distortion (THD) of – 68 dBc at f = 1 MHz,
Figure 1.the THS4021 and THS4022 are ideally suited forapplications requiring low distortion.
RELATED DEVICES
DEVICE DESCRIPTION
THS4011/4012 290-MHz Low-Distortion High-Speed AmplifiersTHS4031/4032 100-MHz Low-Noise High-Speed AmplifiersTHS4061/4062 180-MHz High-Speed Amplifiers
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2PowerPAD is a trademark of Texas Instruments.3All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 1999 – 2007, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
www.ti.com
FUNCTIONAL BLOCK DIAGRAMS
OUT
8
6
1
IN–
IN+
2
3
Null
S0273-01
1OUT
1IN–
1IN+
VCC
2OUT
2IN–
2IN+
–VCC
S0274-01
THS4021
THS4022
SLOS265C – SEPTEMBER 1999 – REVISED JULY 2007
CAUTION: The THS4021 and THS4022 provide ESD protection circuitry. However, permanent damage can still occur if this deviceis subjected to high-energy electrostatic discharges. Proper ESD precautions are recommended to avoid any performancedegradation or loss of functionality.
AVAILABLE OPTIONS
(1)
PACKAGED DEVICESNUMBER OF EVALUATIONPLASTICT
A
MSOP SYMBOLPLASTIC MSOP
(2)CHANNELS MODULESMALL OUTLINE
(2)
(DGN)(D)
1 THS4021CD THS4021CDGN ACK THS4021EVM0°C to 70 °C
2 THS4022CD THS4022CDGN ACA THS4022EVM1 THS4021ID THS4021CIDGN ACL –– 40 °C to 85 °C
2 THS4022ID THS4022CIDGN ACB –
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TIWeb site at www.ti.com .(2) The D and DGN packages are available taped and reeled. Add an R suffix to the device type (for example, THS4021CDGN).
Figure 2. THS4021 — Single Channel
Figure 3. THS4022 — Dual Channel
2Submit Documentation Feedback Copyright © 1999 – 2007, Texas Instruments Incorporated
Product Folder Link(s): THS4021 THS4022
www.ti.com
ABSOLUTE MAXIMUM RATINGS
(1)
DISSIPATION RATINGS
RECOMMENDED OPERATING CONDITIONS
ELECTRICAL CHARACTERISTICS
THS4021
THS4022
SLOS265C – SEPTEMBER 1999 – REVISED JULY 2007
over operating free-air temperature range (unless otherwise noted)
VALUE UNIT
V
CC
Supply voltage ± 16.5 VV
I
Input voltage ± V
CC
VI
O
Output current 150 mAV
IO
Differential input voltage ± 4 VContinuous total power dissipation See Dissipation Ratings tableT
J
Maximum junction temperature 150 °COperating free-air temperature: C-suffix 0 to 70T
A
°CI-suffix – 40 to 85T
stg
Storage temperature – 65 to 150 °CLead temperature 1,6 mm (1/16 inch) from case for 10 seconds 300 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operatingconditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
θ
JA
θ
JC
T
A
= 25 °CPACKAGE
(°C/W) ( °C/W) POWER RATING
D
(1)
167 38.3 740 mWDGN
(2)
58.4 4.7 2.14 W
(1) This data was taken using the JEDEC standard low-K test PCB. For the JEDEC proposed high-K test PCB, the θ
JA
is 95 °C/W with apower rating at T
A
= 25 °C of 1.32 W.(2) This data was taken using 2-oz. (0.071-mm thick) trace and copper pad on a 3-in. ×3-in. (7.62-cm ×7.62-cm) PCB, with the devicesoldered directly to the board. For further information, see the Application Information section of this data sheet.
MIN NOM MAX UNIT
Dual supply ± 4.5 ± 16V
CC+
and V
CC –
Supply voltage VSingle supply 9 32C-suffix 0 70T
A
Operating free-air temperature °CI-suffix – 40 85
at T
A
= 25 °C, V
CC
= ± 15 V, R
L
= 150 Ω(unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Dynamic Performance
V
CC
= ± 15 V 350Gain = 10V
CC
= ± 5 V 280Small-signal bandwidth( – 3 dB)
V
CC
= ± 15 V 80Gain = 20V
CC
= ± 5 V 70BW MHzV
CC
= ± 15 V 17Bandwidth for 0 1-dB flatness Gain = 10V
CC
= ± 5 V 17V
O(pp)
= 20 V, V
CC
= ± 15 V 3.7Full power bandwidth
(1)
V
O(pp)
= 5 V, V
CC
= ± 5 V 11.8V
CC
= ± 15 V, 10-V step 470SR Slew rate
(2)
Gain = 10 V/ μsV
CC
= ± 5 V, 5-V step 370
(1) Full-power bandwidth = slew rate / 2 πV
O(Peak)
.(2) Slew rate is measured from an output level range of 25% to 75%.
Copyright © 1999 – 2007, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Link(s): THS4021 THS4022
www.ti.com
THS4021
THS4022
SLOS265C – SEPTEMBER 1999 – REVISED JULY 2007
ELECTRICAL CHARACTERISTICS (continued)at T
A
= 25 °C, V
CC
= ± 15 V, R
L
= 150 Ω(unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
CC
= ± 15 V, 5-V step 40Settling time to 0.1% Gain = – 10V
CC
= ± 5 V, 2-V step 50t
s
nsV
CC
= ± 15 V, 5-V step 145Settling time to 0.01% Gain = – 10V
CC
= ± 5 V, 2-V step 150
Noise/Distortion Performance
R
L
= 150 Ω– 68V
O(pp)
= 2 V, f = 1 MHz,gain = 2, V
CC
= ± 15 V
R
L
= 1 k Ω– 77THD Total harmonic distortion dBcR
L
= 150 Ω– 69V
O(pp)
= 2 V, f = 1 MHz,gain = 2, V
CC
= ± 5 V
R
L
= 1 k Ω– 78V
n
Input voltage noise V
CC
= ± 5 V or ± 15 V, f > 10 kHz 1.5 nV/ √HzI
n
Input current noise V
CC
= ± 5 V or ± 15 V, f > 10 kHz 2 pA/ √HzV
CC
= ± 15 0.02%Gain = 2, NTSC, 40 IREDifferential gain error
modulation, ± 100 IRE ramp
V
CC
= ± 5 V 0.02%V
CC
= ± 15 0.08Gain = 2, NTSC, 40 IREDifferential phase error °modulation, ± 100 IRE ramp
V
CC
= ± 5 V 0.06Channel-to-channel crosstalkX
T
V
CC
= ± 5 V or ± 15 V, f = 1 MHz – 60 dB(THS4022 only)
DC Performance
T
A
= 25 °C 40 60V
CC
= ± 15 V, V
O
= ± 10 V,R
L
= 1 k Ω
T
A
= full range 35Open-loop gain V/mVT
A
= 25 °C 20 35V
CC
= ± 5 V, V
O
= ± 2.5 V,R
L
= 250 Ω
T
A
= full range 15T
A
= 25 °C 0.5 2V
OS
Input offset voltage mVT
A
= full range 3Offset voltage drift T
A
= full range 15 μV/ °CV
CC
= ± 5 V or ± 15 V T
A
= 25 °C 3 6I
IB
Input bias current μAT
A
= full range 6T
A
= 25 °C 30 250I
OS
Input offset current nAT
A
= full range 400Offset current drift T
A
= full range 0.3 nA/ °C
Input Characteristics
V
CC
= ± 15 V ± 13.8 ± 14.3Common-mode input voltageV
ICR
Vrange
V
CC
= ± 5 V ± 3.8 ± 4.3CMRR Common-mode rejection ratio V
CC
= ± 15 V, V
ICR
= ± 12 V, T
A
= full range 74 95 dBr
i
Input resistance 1 M Ω
C
i
Input capacitance 1.5 pF
Output Characteristics
V
CC
= ± 15 V R
L
= 250 Ω± 12 ± 12.5V
CC
= ± 5 V R
L
= 150 Ω± 3 ± 3.3V
O
Output voltage swing VV
CC
= ± 15 V ± 13 ± 13.5R
L
= 1 k ΩV
CC
= ± 5 V ± 3.4 ± 3.8V
CC
= ± 15 V 80 100I
O
Output current R
L
= 20 ΩmAV
CC
= ± 5 V 50 75I
SC
Short-circuit current
(3)
V
CC
= ± 15 V 150 mAR
O
Output resistance
(3)
Open loop 13 Ω
(3) Observe power dissipation ratings to keep the junction temperature below the absolute maximum rating when the output is heavilyloaded or shorted. See the Absolute Maximum Ratings table of this data sheet for more information.
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Product Folder Link(s): THS4021 THS4022
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TYPICAL CHARACTERISTICS
−80
−70
−60
−50
−40
−30
−20
−10
0
10
Crosstalk − dB
f − Frequency − Hz
1M 10M 1G100M
G002
VCC = ± 15 V
Gain = 10
RF = 220 Ω
RL = 150 Ω
−20
0
20
40
60
80
100
120
Open Loop Gain − dB
f − Frequency − Hz
1k 10k 1G1M 10M
30
−90
−120
−150
−180
−60
−30
0
Phase − 5
G003
100k 100M
VCC = ± 5 V & ±15 V
Gain
Phase
−110
−90
−70
−50
−30
−10
0 5 10 15 20
Distortion − dBc
VO − Output Voltage − V G005
VCC = ± 15 V
RL = 1 kΩ
G = 10
f = 1 MHz
2nd Harmonic
3rd Harmonic
−110
−90
−70
−50
−30
−10
0 5 10 15 20
Distortion − dBc
VO − Output Voltage − V G006
VCC = ± 15 V
RL = 150 Ω
G = 10
f = 1 MHz
2nd Harmonic
3rd Harmonic
−100
−90
−80
−70
−60
−50
−40
THD − Total Harmonic Distortion − dBc
f − Frequency − Hz
100k 10M1M
G004
VCC = ± 15 V
Gain = 10
VO(PP) = 2 V
RL = 150 Ω
RL = 1 kΩ
THS4021
THS4022
SLOS265C – SEPTEMBER 1999 – REVISED JULY 2007
ELECTRICAL CHARACTERISTICS (continued)at T
A
= 25 °C, V
CC
= ± 15 V, R
L
= 150 Ω(unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Power Supply
Dual supply ± 4.5 ± 16.5Supply voltage operatingV
CC
Vrange
Single supply 9 33T
A
= 25 °C 7.8 10V
CC
= ± 15 V
T
A
= full range 11I
CC
Supply current (per amplifier) mAT
A
= 25 °C 6.7 9V
CC
= ± 5 V
T
A
= full range 10.5PSRR Power-supply rejection ratio V
CC
= ± 5 V or ± 15 V, T
A
= full range 80 95 dB
CROSSTALK OPEN LOOP GAIN AND PHASE RESPONSEvs vsFREQUENCY FREQUENCY
Figure 4. Figure 5.
TOTAL HARMONIC DISTORTION DISTORTION DISTORTIONvs vs vsFREQUENCY OUTPUT VOLTAGE OUTPUT VOLTAGE
Figure 6. Figure 7. Figure 8.
Copyright © 1999 – 2007, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Link(s): THS4021 THS4022
www.ti.com
−100
−90
−80
−70
−60
−50
Distortion − dBc
f − Frequency − Hz
100k 10M1M
G007
2nd Harmonic
3rd Harmonic
VCC = ± 15 V
RL = 1 kΩ
G = 10
VO(PP) = 2 V
−100
−90
−80
−70
−60
−50
Distortion − dBc
f − Frequency − Hz
100k 10M1M
G008
VCC = ± 5 V
RL = 1 kΩ
G = 10
VO(PP) = 2 V 2nd Harmonic
3rd Harmonic
−100
−90
−80
−70
−60
−50
Distortion − dBc
f − Frequency − Hz
100k 10M1M
G009
VCC = ± 15 V
RL = 150 Ω
G = 10
VO(PP) = 2 V
2nd Harmonic
3rd Harmonic
−100
−90
−80
−70
−60
−50
−40
Distortion − dBc
f − Frequency − Hz
100k 10M1M
G010
VCC = ± 5 V
RL = 150 Ω
G = 10
VO(PP) = 2 V 2nd Harmonic
3rd Harmonic
10
15
20
25
Output Amplitude − dB
f − Frequency − Hz
10k 1G1M
G011
100k 10M 100M
VCC = ± 15 V
Gain = 10
RL = 150 Ω
VO(PP) = 400 mV
RF = 150 Ω
RF = 220 Ω
10
15
20
25
Output Amplitude − dB
f − Frequency − Hz
10k 1G1M
G012
100k 10M 100M
VCC = ± 5 V
Gain = 10
RL = 150 Ω
VO(PP) = 400 mV
RF = 220 Ω
RF = 150 Ω
−0.6
−0.4
−0.2
0.0
0.2
0.4
0.6
0.8
0 50 100 150 200 250 300 350 400
VO − Output Voltage − V
t − Time − ns G015
VCC = ± 5 V
Gain = 10
RF = 220 Ω
RL = 150 Ω
10
15
20
25
30
Output Amplitude − dB
f − Frequency − Hz
100k 1G1M
G013
10M 100M
RF = 6.2 kΩ
RF = 220 Ω
VCC = ±15 V
Gain = 20
RL = 150 Ω
VO(PP) = 400 mV
RF = 1 kΩ
10
15
20
25
30
Output Amplitude − dB
f − Frequency − Hz
100k 1G1M
G014
10M 100M
RF = 6.2 kΩ
RF = 220 Ω
VCC = ±5 V
Gain = 20
RL = 150 Ω
VO(PP) = 400 mV
RF = 1 kΩ
THS4021
THS4022
SLOS265C – SEPTEMBER 1999 – REVISED JULY 2007
TYPICAL CHARACTERISTICS (continued)
DISTORTION DISTORTION DISTORTIONvs vs vsFREQUENCY FREQUENCY FREQUENCY
Figure 9. Figure 10. Figure 11.
DISTORTION OUTPUT AMPLITUDE OUTPUT AMPLITUDEvs vs vsFREQUENCY FREQUENCY FREQUENCY
Figure 12. Figure 13. Figure 14.
OUTPUT AMPLITUDE OUTPUT AMPLITUDEvs vsFREQUENCY FREQUENCY 1-V STEP RESPONSE
Figure 15. Figure 16. Figure 17.
6Submit Documentation Feedback Copyright © 1999 – 2007, Texas Instruments Incorporated
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−0.6
−0.4
−0.2
0.0
0.2
0.4
0.6
0.8
0 50 100 150 200 250 300 350 400
VO − Output Voltage − V
t − Time − ns G017
VCC = ± 15 V
Gain = 10
RF = 220 Ω
RL = 150 Ω
−3
−2
−1
0
1
2
3
0 50 100 150 200 250 300 350 400
VO − Output Voltage − V
t − Time − ns G016
VCC = ± 5 V
Gain = −10
RF = 220 Ω
RL = 150 Ω
−6
−4
−2
0
2
4
6
0 100 200 300 400 500
VO − Output Voltage − V
t − Time − ns G018
VCC = ± 15 V
Gain = 10
RF = 220 Ω
RL = 150
−0.30
−0.25
−0.20
−0.15
−0.10
−0.05
−40 −20 0 20 40 60 80 100
VIO − Input Offset Voltage − mV
TA − Free-Air Temperature − °CG019
VCC = ± 15 V
VCC = ± 5 V
3.00
3.05
3.10
3.15
3.20
3.25
3.30
−40 −20 0 20 40 60 80 100
IIB − Input Bias Current − µA
TA − Free-Air Temperature − °CG020
VCC = ± 5 V & ±15 V
2
4
6
8
10
12
14
5 7 9 11 13 15
|VO| − Output Voltage − |V|
+VCC − Supply Voltage − V G021
TA = 25°C
RL = 150 Ω
RL = 1 kΩ
3
5
7
9
11
13
15
5 7 9 11 13 15
VICR − Common−Mode Input Voltage − +V
+VCC − Supply Voltage − V G022
TA = 25°C
0
2
4
6
8
10
12
14
−40 −20 0 20 40 60 80 100
|VO| − Output Voltage − |V|
TA − Free-Air Temperature − °CG023
VCC = ± 5 V
RL = 150 Ω
VCC = ± 5 V
RL = 1 kΩ
VCC = ± 15 V
RL = 250 Ω
VCC = ± 15 V
RL = 1 kΩ
5
6
7
8
9
10
11
5 7 9 11 13 15
ICC − Supply Current − mA
+VCC − Supply Voltage − V G024
TA=85°C
TA=−40°C
TA=25°C
THS4021
THS4022
SLOS265C – SEPTEMBER 1999 – REVISED JULY 2007
TYPICAL CHARACTERISTICS (continued)
5-V STEP RESPONSE 1-V STEP RESPONSE 10-V STEP RESPONSE
Figure 18. Figure 19. Figure 20.
INPUT OFFSET VOLTAGE INPUT BIAS CURRENT OUTPUT VOLTAGEvs vs vsFREE-AIR TEMPERATURE FREE-AIR TEMPERATURE SUPPLY VOLTAGE
Figure 21. Figure 22. Figure 23.
COMMON-MODE INPUT VOLTAGE OUTPUT VOLTAGE SUPPLY CURRENTvs vs vsSUPPLY VOLTAGE FREE-AIR TEMPERATURE SUPPLY VOLTAGE
Figure 24. Figure 25. Figure 26.
Copyright © 1999 – 2007, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Link(s): THS4021 THS4022
www.ti.com
−80
−70
−60
−50
−40
−30
−20
−10
0
PSRR − Power Supply Rejection Ratio − dB
f − Frequency − Hz
100k 1G1M
G026
10M 100M
VCC = ±15 V & ±5 V
−VCC
+VCC
Vn − Voltage Noise − nV//Hz
f − Frequency − Hz
10 100 1k 100k
1
10
100
G025
10k
In − Current Noise − pA//Hz
VCC = ± 15 V and ± 5 V
TA = 25°C
Vn
In
−60
−50
−40
−30
−20
−10
0
CMRR − Common-Mode Rejection Ratio − dB
f − Frequency − Hz
100k 1G1M
G027
10M 100M
VCC = ±15 V or ±5 V
RF = 20 kΩ
VI(PP) = 2 V
THS4021
THS4022
SLOS265C – SEPTEMBER 1999 – REVISED JULY 2007
TYPICAL CHARACTERISTICS (continued)
VOLTAGE AND CURRENT NOISE POWER SUPPLY REJECTION RATIO COMMON MODE REJECTION RATIOvs vs vsFREQUENCY FREQUENCY FREQUENCY
Figure 27. Figure 28. Figure 29.
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Product Folder Link(s): THS4021 THS4022
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APPLICATION INFORMATION
Theory of Operation
Noise Calculations and Noise Figure
THS4021
THS4022
SLOS265C – SEPTEMBER 1999 – REVISED JULY 2007
The THS402x is a high-speed operational amplifier configured in a voltage feedback architecture. It is built usinga 30-V, dielectrically isolated, complementary bipolar process with NPN and PNP transistors possessing f
T
ofseveral GHz. This results in an exceptionally high-performance amplifier that has a wide bandwidth, high slewrate, fast settling time, and low distortion. A simplified schematic is shown in Figure 30 .
Figure 30. THS4021 Simplified Schematic
Noise can cause errors on very small signals. This is especially true when amplifying small signals, wheresignal-to-noise ratio (SNR) is very important. The noise model for the THS402x is shown in Figure 31. Thismodel includes all of the noise sources as follows:•e
n
= Amplifier internal voltage noise (nV/ √Hz)•IN+ = Noninverting current noise (pA/ √Hz)•IN – = Inverting current noise (pA/ √Hz)•e
Rx
= Thermal voltage noise associated with each resistor (e
Rx
= 4 kTR
x
)
Copyright © 1999 – 2007, Texas Instruments Incorporated Submit Documentation Feedback 9
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www.ti.com
_
+
RF
RS
RG
eRg
eRf
eRs en
IN+
Noiseless
IN–
eni eno
S0277-01
eni +ǒenǓ2)ǒIN+ RSǓ2)ǒIN− ǒRFøRGǓǓ2)4 kTRs)4 kTǒRFøRGǓ
Ǹ
eno +eni AV+eniǒ1)RF
RGǓ(noninverting case)
NF +10logȧ
ȧ
ȱ
Ȳ
e2
ni
ǒeRsǓ2ȧ
ȧ
ȳ
ȴ
THS4021
THS4022
SLOS265C – SEPTEMBER 1999 – REVISED JULY 2007
Figure 31. Noise Model
The total equivalent input noise density (e
ni
) is calculated by using the following equation:
where:
k = Boltzmann ’ s constant = 1.380658 ×10
– 23
T = Temperature in degrees Kelvin (273 + °C)R
F
|| R
G
= Parallel resistance of R
F
and R
G
To get the equivalent output noise of the amplifier, just multiply the equivalent input noise density (e
ni
) by theoverall amplifier gain (A
V
).
As the previous equations show, to keep noise at a minimum, small value resistors should be used. As theclosed-loop gain is increased (by reducing R
G
), the input noise is reduced considerably because of the parallelresistance term. This leads to the general conclusion that the most dominant noise sources are the sourceresistor (R
S
) and the internal amplifier noise voltage (e
n
). Because noise is summed in a root-mean-squaresmethod, noise sources smaller than 25% of the largest noise source can be effectively ignored. This can greatlysimplify the formula and make noise calculations much easier to calculate.
For more information on noise analysis, see the Noise Analysis in Operational Amplifier Circuits applicationreport (SLVA043 ).
This brings up another noise measurement usually preferred in RF applications, the noise figure (NF). Noisefigure is a measure of noise degradation caused by the amplifier. The value of the source resistance must bedefined and is typically 50 Ωin RF applications.
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www.ti.com
NF +10logȧ
ȧ
ȧ
ȧ
ȧ
ȱ
Ȳ
1)ǒǒenǓ2)ǒIN+ RSǓ2Ǔ
4 kTRS
ȧ
ȧ
ȧ
ȧ
ȧ
ȳ
ȴ
0
2
4
6
8
10
12
14
16
Source Resistance − Ω
Noise Figure − dB
10 100 1k 10k
G028
f = 10 kHz
TA = 25°C
THS4021
THS4022
SLOS265C – SEPTEMBER 1999 – REVISED JULY 2007
Because the dominant noise components are generally the source resistance and the internal amplifier noisevoltage, we can approximate noise figure as:
Figure 32 shows the noise figure graph for the THS402x.
NOISE FIGURE
vsSOURCE RESISTANCE
Figure 32. Noise Figure vs Source Resistance
Copyright © 1999 – 2007, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Link(s): THS4021 THS4022
www.ti.com
Driving a Capacitive Load
+
_
THS402x
CLOAD
1kW
Input
Output
50 W
20 W
S0278-01
Offset Nulling
_
+
THS402x
VCC–
VCC+
0.1 Fm
0.1 Fm
10kW
S0279-01
THS4021
THS4022
SLOS265C – SEPTEMBER 1999 – REVISED JULY 2007
Driving capacitive loads with high-performance amplifiers is not a problem as long as certain precautions aretaken. The first is to realize that the THS402x has been internally compensated to maximize its bandwidth andslew-rate performance. When the amplifier is compensated in this manner, capacitive loading directly on theoutput decreases the device phase margin, leading to high-frequency ringing or oscillations. Therefore, forcapacitive loads of greater than 10 pF, it is recommended that a resistor be placed in series with the output ofthe amplifier, as shown in Figure 33 . A minimum value of 20 Ωshould work well for most applications. Forexample, in 75- Ωtransmission systems, setting the series resistor value to 75 Ωboth isolates any capacitanceloading and provides the proper line impedance matching at the source end.
Figure 33. Driving a Capacitive Load
The THS402x has very low input offset voltage for a high-speed amplifier. However, if additional correction isrequired, an offset nulling function has been provided on the THS4021. The input offset can be adjusted byplacing a potentiometer between terminals 1 and 8 of the device and tying the wiper to the negative supply. Thisis shown in Figure 34 .
Figure 34. Offset Nulling Schematic
12 Submit Documentation Feedback Copyright © 1999 – 2007, Texas Instruments Incorporated
Product Folder Link(s): THS4021 THS4022
www.ti.com
Offset Voltage
+
–
VIO
RG
RS
RF
IIB–
VOS
IIB+
+
–
S0280-01
( ) RF
V V I R 1 I R
OS IO IB S IB F
RG
æ ö
= ± ± ´ + ± ´
ç ÷
+ -
ç ÷
è ø
General Configurations
VI
VO
C1
+
–
RGRF
R1
S0281-01
3dB
1
f
2 R1C1
-=p
OF
I G
VR1
1
V R 1 sR1C1
æ öæ ö
= +
ç ÷ç ÷
ç ÷ +
è ø
è ø
THS4021
THS4022
SLOS265C – SEPTEMBER 1999 – REVISED JULY 2007
The output offset voltage (V
OO
) is the sum of the input offset voltage (V
IO
) and both input bias currents (I
IB
) timesthe corresponding gains. The schematic and formula of Figure 35 can be used to calculate the output offsetvoltage.
Figure 35. Output Offset Voltage Model
When receiving low-level signals, limiting the bandwidth of the incoming signals into the system is often required.The simplest way to accomplish this is to place an RC filter at the noninverting terminal of the amplifier (seeFigure 36 ).
Figure 36. Single-Pole Low-Pass Filter
Copyright © 1999 – 2007, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Link(s): THS4021 THS4022
www.ti.com
Circuit Layout Considerations
THS4021
THS4022
SLOS265C – SEPTEMBER 1999 – REVISED JULY 2007
To achieve the levels of high-frequency performance of the THS402x, follow proper printed-circuit boardhigh-frequency design techniques. A general set of guidelines is given as follows. In addition, a THS402xevaluation board is available to use as a guide for layout or for evaluating the device performance.•Ground planes — It is highly recommended that a ground plane be used on the board to provide allcomponents with a low-inducance ground connection. However, in the areas of the amplifier inputs andoutput, the ground plane can be removed to minimize the stray capacitance.•Proper power-supply decoupling — Use a 6.8- μF tantalum capacitor in parallel with a 0.1- μF ceramic capacitoron each supply terminal. It may be possible to share the tantalum among several amplifiers depending on theapplication, but a 0.1- μF ceramic capacitor should always be used on the supply terminal of every amplifier.In addition, the 0.1- μF capacitor should be placed as close as possible to the supply terminal. As this distanceincreases, the inductance in the connecting trace makes the capacitor less effective. The designer shouldstrive for distances of less than 0.1 inch (2.54 mm) between the device power terminals and the ceramiccapacitors.
•Sockets — Sockets are not recommended for high-speed operational amplifiers. The additional leadinductance in the socket pins often produces stability problems. Surface-mount packages soldered directly tothe PCB is the best implementation.•Short trace runs/compact part placements — Optimum high-frequency performance is achieved when strayseries inductance has been minimized. To realize this, the circuit layout should be made as compact aspossible, thereby minimizing the length of all trace runs. Particular attention should be paid to the invertinginput of the amplifier. Its length should be kept as short as possible. This helps to minimize stray capacitanceat the input of the amplifier.•Surface-mount passive components — Using surface-mount passive components is recommended forhigh-frequency amplifier circuits for several reasons. First, because of the extremely low lead inductance ofsurface-mount components, the problem with stray series inductance is greatly reduced. Second, the smallsize of surface-mount components naturally leads to a more compact layout, thereby minimizing both strayinductance and capacitance. If leaded components are used, it is recommended that the lead lengths be keptas short as possible.
14 Submit Documentation Feedback Copyright © 1999 – 2007, Texas Instruments Incorporated
Product Folder Link(s): THS4021 THS4022
www.ti.com
General Thermal Pad Design Considerations
DIE
SideView(a)
EndView(b) BottomView(c)
DIE
Thermal
Pad
M0031-01
Thermalpadarea=68mils 70mils(1.73mm 1.78mm)with5vias.´ ´
Viadiameter=13mils(0.33mm).
M0032-02
THS4021
THS4022
SLOS265C – SEPTEMBER 1999 – REVISED JULY 2007
The THS402x is available packaged in a thermally-enhanced DGN package, which is a member of thePowerPAD family of packages. This package is constructed using a downset leadframe upon which the die ismounted [see Figure 37 (a) and Figure 37 (b)]. This arrangement results in the lead frame being exposed as athermal pad on the underside of the package [see Figure 37 (c)]. Because this thermal pad has direct thermalcontact with the die, excellent thermal performance can be achieved by providing a good thermal path away fromthe thermal pad.
The PowerPAD package allows for both assembly and thermal management in one manufacturing operation.During the surface-mount solder operation (when the leads are being soldered), the thermal pad can also besoldered to a copper area underneath the package. Through the use of thermal paths within this copper area,heat can be conducted away from the package into either a ground plane or other heat dissipating device.
The PowerPAD package represents a design breakthrough, combining the small area and ease of the surfacemount assembly method to eliminate the previously difficult mechanical methods of heatsinking.
NOTE: The thermal pad is electrically isolated from all terminals in the package.
Figure 37. Views of Thermally Enhanced DGN Package
Although there are many ways to heatsink this device properly, the following steps illustrate the recommendedapproach.
Figure 38. Thermal Pad PCB Etch and Via Pattern
1. Prepare the PCB with a top side etch pattern as shown in Figure 38 . There should be etch for the leads aswell as etch for the thermal pad.2. Place five holes in the area of the thermal pad. These holes should be 13 mils (0.33 mm) in diameter. Keepthem small so that solder wicking through the holes is not a problem during reflow.3. Additional vias may be placed anywhere along the thermal plane outside of the thermal pad area. These viashelp dissipate the heat generated by the THS402xDGN IC. These additional vias may be larger than the13-mil (0.33-mm) diameter vias directly under the thermal pad. They can be larger because they are not inthe thermal pad area to be soldered, so wicking is not a problem.4. Connect all holes to the internal ground plane.5. When connecting these holes to the ground plane, do not use the typical web or spoke via connectionmethodology. Web connections have a high thermal resistance connection that is useful for slowing the heattransfer during soldering operations. This makes the soldering of vias that have plane connections easier. Inthis application, however, low thermal resistance is desired for the most efficient heat transfer. Therefore, theholes under the THS402xDGN package should connect to the internal ground plane with a completeconnection around the entire circumference of the plated-through hole.6. The top-side solder mask should leave the terminals of the package and the thermal pad area with its fiveholes exposed. The bottom-side solder mask should cover the five holes of the thermal pad area. Thisprevents solder from being pulled away from the thermal pad area during the reflow process.
Copyright © 1999 – 2007, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Link(s): THS4021 THS4022
www.ti.com
PD+ǒTMAX–TA
qJA Ǔ
TA − Free-Air Temperature − °C
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
−40 −20 0 20 40 60 80 100
Maximum Power Dissipation − W
G029
DGN Package
θJA = 58.4°C/W
2 oz. Trace And Copper Pad
With Solder
DGN Package
θJA = 158°C/W
2 oz. Trace And
Copper Pad
Without Solder
SOIC Package
High-K Test PCB
θJA = 98°C/W
SOIC Package
Low-K Test PCB
θJA = 167°C/W
TJ = 150°C
THS4021
THS4022
SLOS265C – SEPTEMBER 1999 – REVISED JULY 2007
7. Apply solder paste to the exposed thermal pad area and all of the IC terminals.8. With these preparatory steps in place, the THS402xDGN IC is simply placed in position and run through thesolder reflow operation as any standard surface-mount component. This results in a part that is properlyinstalled.
The actual thermal performance achieved with the THS402xDGN in its PowerPAD package depends on theapplication. In the example above, if the size of the internal ground plane is approximately 3 inches ×3 inches(7.62 cm ×7.62 cm), then the expected thermal coefficient, θ
JA
, is about 58.4 °C/W. For comparison, thenon-PowerPAD version of the THS402x IC (SOIC) is shown. For a given θ
JA
, the maximum power dissipation isshown in Figure 39 and is calculated by the following formula:
where:
P
D
= Maximum power dissipation of THS402x IC (watts)T
MAX
= Absolute maximum junction temperature (150 °C)T
A
= Free-ambient air temperature ( °C)θ
JA
=θ
JC
+θ
CA
θ
JC
= Thermal coefficient from junction to caseθ
CA
= Thermal coefficient from case to ambient air ( °C/W)MAXIMUM POWER DISSIPATION
vsFREE-AIR TEMPERATURE
NOTE: Results are with no air flow and PCB size = 3 in. ×3 in. (7.62 cm ×7.62 cm).Figure 39. Maximum Power Dissipation vs Free-Air Temperature
More-complete details of the thermal pad installation process and thermal management techniques can be foundin the PowerPAD Thermally Enhanced Package application report (SLMA002 ).
16 Submit Documentation Feedback Copyright © 1999 – 2007, Texas Instruments Incorporated
Product Folder Link(s): THS4021 THS4022
www.ti.com
|VO| − RMS Output Voltage − V
0
20
40
60
80
100
120
140
160
180
200
012345
|IO| − Maximum RMS Output Current − mA
G030
Package With
θJA < = 120°C/W
SO-8 Package
θJA = 167°C/W
Low-K Test PCB
VCC = ± 5 V
Tj = 150°C
TA = 50°C
Maximum Output
Current Limit Line
Safe Operating
Area
|VO| − RMS Output Voltage − V
0 3 6 9 12 15
|IO| − Maximum RMS Output Current − mA
G031
10
1k
100
TJ = 150°C
TA = 50°CVCC = ± 15 V
Maximum Output
Current Limit Line
SO-8 Package
θJA = 98°C/W
High-K Test PCB
DGN Package
θJA = 58.4°C/W
SO-8 Package
θJA = 167°C/W
Low-K Test PCB Safe Operating
Area
THS4021
THS4022
SLOS265C – SEPTEMBER 1999 – REVISED JULY 2007
The next consideration is the package constraints. The two sources of heat within an amplifier are quiescentpower and output power. The designer should never forget about the quiescent heat generated within the device,especially with multiamplifier devices. Because these devices have linear output stages (Class A-B), most of theheat dissipation is at low output voltages with high output currents. Figure 40 through Figure 43 show this effect,along with the quiescent heat, with an ambient air temperature of 50 °C. Obviously, as the ambient temperatureincreases, the limit lines shown drop accordingly. The area under each respective limit line is considered the safeoperating area. Any condition above this line exceeds the amplifier limits and failure may result. When using V
CC= ± 5 V, there is generally not a heat problem, even with SOIC packages. But, when using V
CC
= ± 15 V, the SOICpackage is severely limited in the amount of heat it can dissipate. The other key factor when looking at thesegraphs is how the devices are mounted on the PCB. The PowerPAD devices are extremely useful for heatdissipation. But the device should always be soldered to a copper plane to use fully the heat dissipationproperties of the thermal pad. The SOIC package, on the other hand, is highly dependent on how it is mountedon the PCB. As more trace and copper area is placed around the device, θ
JA
decreases and the heat dissipationcapability increases. The currents and voltages shown in these graphs are for the total package. For thedual-amplifier package (THS4022), the sum of the RMS output currents and voltages should be used to choosethe proper package. The graphs shown assume that both amplifier outputs are identical.
THS4021 THS4021MAXIMUM RMS OUTPUT CURRENT MAXIMUM RMS OUTPUT CURRENTvs vsRMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS
Figure 40. Figure 41.
Copyright © 1999 – 2007, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Link(s): THS4021 THS4022
www.ti.com
|VO| − RMS Output Voltage − V
0
20
40
60
80
100
120
140
160
180
200
012345
|IO| − Maximum RMS Output Current − mA
G032
Package With
θJA ≤ 60°C/W
SO-8 Package
θJA = 98°C/W
High-K Test PCB
VCC = ± 5 V
TJ = 150°C
TA = 50°C
Both Channels
Maximum Output
Current Limit Line
SO-8 Package
θJA = 167°C/W
Low-K Test PCB
Safe Operating Area
|VO| − RMS Output Voltage − V
0 3 6 9 12 15
|IO| − Maximum RMS Output Current − mA
G033
1
1k
10
100
Maximum Output
Current Limit Line
VCC = ± 15 V
TJ = 150°C
TA = 50°C
Both Channels
SO-8 Package
θJA = 167°C/W
Low-K Test PCB
DGN Package
θJA = 58.4°C/W
Safe Operating Area
SO-8 Package
θJA = 98°C/W
High-K Test PCB
THS4021
THS4022
SLOS265C – SEPTEMBER 1999 – REVISED JULY 2007
THS4022 THS4022MAXIMUM RMS OUTPUT CURRENT MAXIMUM RMS OUTPUT CURRENTvs vsRMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS
Figure 42. Figure 43.
18 Submit Documentation Feedback Copyright © 1999 – 2007, Texas Instruments Incorporated
Product Folder Link(s): THS4021 THS4022
www.ti.com
Evaluation Board
_
+
THS4021
VCC–
VCC+
C1
6.8 Fm
C4
0.1 Fm
C2
6.8 Fm
C3
0.1 Fm
R4
1kW
R2
49.9 W
R3
49.9 W
R5
49.9 W
IN–
IN+
NULL
OUT
NULL
+
+
S0282-01
THS4021
THS4022
SLOS265C – SEPTEMBER 1999 – REVISED JULY 2007
Evaluation boards are available for the THS4021 (literature number SLOP129 ) and THS4022 (literature numberSLOP231 ). These boards have been configured for very low parasitic capacitance in order to realize the fullperformance of the amplifier. A schematic of the THS4021 evaluation board is shown in Figure 44 . The circuitryhas been designed so that the amplifier may be used in either an inverting or noninverting configuration. Formore information, see the THS4021 High-Speed Operational Amplifier Evaluation Module user ’ s guide(SLOU063 ) or the THS4022 Dual High-Speed Operational Amplifier Evaluation Module user ’ s guide (SLOU064 ).To order the evaluation board, contact your local TI sales office or distributor or visit the Texas Instruments Website at www.ti.com .
Figure 44. THS4021 Evaluation Board
Copyright © 1999 – 2007, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Link(s): THS4021 THS4022
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
THS4021CD ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4021CDG4 ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4021CDGN ACTIVE MSOP-
Power
PAD
DGN 8 80 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4021CDGNG4 ACTIVE MSOP-
Power
PAD
DGN 8 80 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4021CDGNR ACTIVE MSOP-
Power
PAD
DGN 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4021CDGNRG4 ACTIVE MSOP-
Power
PAD
DGN 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4021ID ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4021IDG4 ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4021IDGN ACTIVE MSOP-
Power
PAD
DGN 8 80 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4021IDGNG4 ACTIVE MSOP-
Power
PAD
DGN 8 80 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4021IDGNR ACTIVE MSOP-
Power
PAD
DGN 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4021IDGNRG4 ACTIVE MSOP-
Power
PAD
DGN 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4021IDR ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4021IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4022CD ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4022CDG4 ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4022CDGN ACTIVE MSOP-
Power
PAD
DGN 8 80 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4022CDGNG4 ACTIVE MSOP-
Power
PAD
DGN 8 80 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4022CDGNR ACTIVE MSOP-
Power
PAD
DGN 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4022CDGNRG4 ACTIVE MSOP-
Power
PAD
DGN 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 17-Jun-2008
Addendum-Page 1
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
THS4022ID ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4022IDG4 ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4022IDGN ACTIVE MSOP-
Power
PAD
DGN 8 80 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4022IDGNG4 ACTIVE MSOP-
Power
PAD
DGN 8 80 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4022IDGNR ACTIVE MSOP-
Power
PAD
DGN 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4022IDGNRG4 ACTIVE MSOP-
Power
PAD
DGN 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 17-Jun-2008
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
THS4021IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
THS4022CDGNR MSOP-
Power
PAD
DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
THS4022IDGNR MSOP-
Power
PAD
DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Oct-2010
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
THS4021IDR SOIC D 8 2500 346.0 346.0 29.0
THS4022CDGNR MSOP-PowerPAD DGN 8 2500 346.0 346.0 29.0
THS4022IDGNR MSOP-PowerPAD DGN 8 2500 346.0 346.0 29.0
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Oct-2010
Pack Materials-Page 2
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Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products Applications
Amplifiers amplifier.ti.com Audio www.ti.com/audio
Data Converters dataconverter.ti.com Automotive www.ti.com/automotive
DLP® Products www.dlp.com Communications and www.ti.com/communications
Telecom
DSP dsp.ti.com Computers and www.ti.com/computers
Peripherals
Clocks and Timers www.ti.com/clocks Consumer Electronics www.ti.com/consumer-apps
Interface interface.ti.com Energy www.ti.com/energy
Logic logic.ti.com Industrial www.ti.com/industrial
Power Mgmt power.ti.com Medical www.ti.com/medical
Microcontrollers microcontroller.ti.com Security www.ti.com/security
RFID www.ti-rfid.com Space, Avionics & www.ti.com/space-avionics-defense
Defense
RF/IF and ZigBee® Solutions www.ti.com/lprf Video and Imaging www.ti.com/video
Wireless www.ti.com/wireless-apps
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