1/40January 2004
M29W160ET
M29W160EB
16 Mbit (2Mb x8 or 1Mb x16, Boot Block)
3V Suppl y Flash M emo ry
FEATURES SUM M ARY
SUPPLY VOLT AGE
–V
CC = 2.7V to 3.6V for Program, Erase
and Read
ACCESS TI MES: 70, 90ns
PROGRAMMING TIME
10µs per Byte/Word typical
35 MEMORY BL OCKS
1 Boot Block (Top or Bottom Location)
2 Paramete r and 32 Main Blocks
PROGRAM/ERASE CONTROLLER
Embedded Byte/ Word Program
algorithms
ERASE SUSPEND and RESUME MODES
Read and Program another Block during
Erase Su spend
UNLOCK BYPASS PROGRAM COMMAND
Faster Produc tion/Batc h Progra mming
TEMPO RARY BLOCK UNPROTECTION
MODE
COMMON FLASH INTERFAC E
64 bit Security Code
LOW POWER CONSUM PTION
Standby and Autom atic Standby
100, 000 PROGRA M /ERAS E CYCLES per
BLOCK
ELECTRO NIC SIG N ATURE
Manufacturer Code: 0020h
Top Device C ode M29 W160ET: 22C4h
Bottom Device Code M29W160EB: 2249h
Figure 1. Packages
TSOP48 (N)
12 x 20mm
TFBGA48 (ZA)
6 x 8mm
FBGA
M29W160ET, M29W160EB
2/40
TABLE OF C ONTENT S
FEATUR ES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SUM MARY DESCRIPT ION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 1. Signa l Na mes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 3. TSOP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 4. TFBGA Connect ions (Top view through packag e) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 5. Block Add resses (x8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 6. Block Add resses (x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
SIGNA L DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Address Inputs (A0-A19). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
D ata Inputs/Ou tputs (DQ0-DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0
D ata Inputs/Ou tputs (DQ8-DQ14 ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
D ata Input/Output or Address Input (DQ15A-1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
C hip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Out put Enabl e (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Wri t e Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Reset/Bl ock Temporary Unprotect (RP).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
R eady/Busy Output (RB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Byte/Word Organization Select (BYTE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
VCC Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
VSS Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1
Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1
Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1
Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1
Autom at ic Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1
Special Bus Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Ele ctronic Signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Block Protection and Blocks Unp rotection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 2. Bus Operations, BYTE = V IL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 3. Bus Operations, BYTE = V IH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
R ead/Res et Comm and.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Auto Se lect Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Unlock Bypass C ommand. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Unlock Bypass Program Com mand. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Unlock Bypass R eset Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
3/40
M29W160ET, M29W160EB
C hip Erase Comm and. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3
Blo ck Erase Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Erase S uspend Com ma nd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Erase Resume Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4
R ead CFI Query Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 4. Com m ands, 16-bi t mode, BYTE = VIH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 5. Com m ands, 8-bit mode, BY TE = VIL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 6. Program, Erase Times and Program, Erase Endurance Cycles . . . . . . . . . . . . . . . . . . . 17
STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Data Polling Bit (DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 7
Toggl e Bit (DQ6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Error Bit (DQ5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Erase Timer Bit (DQ3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Alternative Toggle Bit (DQ2).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 8
Table 7. Status Register Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 8
Figure 7. Data Pol ling Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 8. Data Toggle Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 9
MAXIMU M RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 8. Absolute Maximum Rati ngs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 9. Operating a nd AC Measurement Cond iti ons. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 9. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 10.A C Measurem ent Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 10. Dev ice Capacitanc e. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 11. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1
Figure 11.Read M ode A C Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 12. Read AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Figure 12.Write AC Wa veforms, Write Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 13. Write AC Cha racteristics, Write Enable Contro lled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 13.Write AC Waveforms, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 14. Write AC Characteristics, Chip Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 14.Reset/Block Temporary Unprotect AC Wa veforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 15. Reset/Block Temporary Unprotect AC Chara cteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 25
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 15.TSOP48 – 48 lead Plastic T hin S ma ll Outline, 12 x 20mm, Packa ge Outline. . . . . . . . . 26
Table 16. TSOP48 – 48 lead Plastic T hin S m all Outline, 12 x 20mm, Pack age Mecha nical Data . 26
Figure 16.TF B GA48 6x 8m m - 6x8 ball array, 0.80 mm pitch, Pack age Outline . . . . . . . . . . . . . . . 27
Table 17. TF B GA48 6x 8m m - 6x8 ball array, 0.80 mm pitch, Package Mech anical Data. . . . . . . . 27
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 18. Orde ring Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
M29W160ET, M29W160EB
4/40
APPENDIX A.BLOCK ADDRESS TABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 19. Top Boot Block Addresses, M29W160ET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 20. Bottom Boot Block Addresses, M29W1 60EB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
APPENDIX B.COMMON FLASH INTERFACE (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 21. Query Structure Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Table 22. CFI Query Identification String. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Table 23. CFI Query System Interface Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 24. Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Table 25. P rimary Algorithm-S pecific Extended Query Tabl e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 26. Security Code Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3
APPENDIX C.BLOCK PROTECTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Programmer Tech nique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4
In-System Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4
Table 27. Programmer Techni que Bus Operations, BYTE = V IH or VIL . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 17.Programmer Equipment Block Protect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 18.P rogram mer Equipment Chip Unprotect Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 19.In-System Equipment Block Protect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 20.In-System Equipment Chip Unprotect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
REVISION HISTO RY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 28. Document Revi sion History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5/40
M29W160ET, M29W160EB
SUMMARY DESCRIPTION
The M29W160E is a 16 Mbit (2Mb x8 or 1Mb x16)
non-volatile memory that can be read, erased and
reprogrammed. These operations can be per-
formed using a single low voltage (2.7 to 3.6V)
supply. On power-up the memory defaults to its
Read mode where it can be read in the same way
as a ROM or E P ROM .
The memory is divided into blocks that can be
erased independently so i t is p ossible to pres erve
valid data while old data is erased. Each block can
be protected independently to prevent accidental
Program or Erase commands from modifying the
memory. P rogram and Er ase com m ands are wri t-
ten to the Com mand Interface of the mem ory. An
on-chip Program/Erase Controller simplifies the
process of pr ogramming or erasing the memory by
taking care of all of the special operations that are
required to update the memory contents.
The end of a program or erase operation can be
detected and any error conditions identified. The
command set required to control the memory is
consistent with JEDEC standards.
The b locks in the memory are asymmetrically ar-
ranged, see Figures 5 and 6, Block Addresses.
The first or last 64 KBytes have been di vi ded into
four additional blocks. The 16 KByte Boot Block
can be used for small initialization code to s tart the
microprocessor, the two 8 KByte Parameter
Blocks can be us ed for parameter storage and the
remaining 32K is a small Main Block where the ap-
plication may be stored.
Chip Enabl e, Output Enable and Write Enable sig-
nals control the bus operation of the memory.
They allow simple connection to most micropro-
cessors, often without additional logic.
The memory is offered TSOP48 (12 x 20mm ) and
TFBGA48 (0.8mm pitch) packages. The memory
is s upp lied with all the bits erased (set to ’1’).
Figure 2. Logic Diagram Tabl e 1. Signal Names
AI06849B
20
A0-A19
W
DQ0-DQ14
VCC
M29W160ET
M29W160EB
E
VSS
15
G
RP
DQ15A–1
RB
BYTE
A0-A19 Address Inputs
DQ0-DQ7 Data Inputs/Outputs
DQ8-DQ14 Data Inputs/Outputs
DQ15A–1 Data Input/Output or Address Input
EChip Enable
GOutput Enable
WWrite Enable
RP Reset/Block Temporary Unprotect
RB Ready/Busy Output
BYTE Byte/Word Organization Select
VCC Supply Vo ltage
VSS Ground
NC Not Connected Internally
M29W160ET, M29W160EB
6/40
Figu re 3. TSOP Conne ct i on s
DQ3
DQ9
DQ2
A6 DQ0
W
A3
RB
DQ6
A8
A9 DQ13
A17
A10 DQ14
A2
DQ12
DQ10
DQ15A–1
VCC
DQ4
DQ5
A7
DQ7
NC
NC
AI06850
M29W160ET
M29W160EB
12
1
13
24 25
36
37
48
DQ8
NC
A19
A1
A18
A4
A5
DQ1
DQ11
G
A12
A13
A16
A11
BYTE
A15
A14 VSS
E
A0
RP
VSS
7/40
M29W160ET, M29W160EB
Figure 4. TFBGA Connections ( Top vi ew throug h package)
AI02985B
654321
VSS
DQ15
A–1
A15
A14
A12
A13
DQ3
DQ11
DQ10
A18
NC
RB
DQ1
DQ9
DQ8
DQ0
A6
A17
A7
G
E
A0
A4
A3
DQ2
DQ6
DQ13
DQ14
A10
A8
A9
DQ4
VCC
DQ12
DQ5
A19
NC
RP
W
A11
DQ7
A1
A2
VSS
A5 NC
A16
BYTE
G
F
E
B
A
D
C
H
M29W160ET, M29W160EB
8/40
Figure 5. Block Addresses (x8)
Note: Also see Appendix A, T ables 19 and 20 for a f ul l lis t i ng of the Bl ock Addresses .
AI06851
16 KByte
1FFFFFh
1FC000h
64 KByte
01FFFFh
010000h
64 KByte
00FFFFh
000000h
M29W160ET
Top Boot Block Addresses (x8)
32 KByte
1F7FFFh
1F0000h
64 KByte
1E0000h
1EFFFFh
Total of 31
64 KByte Blocks
16 KByte
1FFFFFh
1F0000h 64 KByte
64 KByte
003FFFh
000000h
M29W160EB
Bottom Boot Block Addresses (x8)
32 KByte
1EFFFFh
01FFFFh 64 KByte
1E0000h
010000h
Total of 31
64 KByte Blocks
00FFFFh
008000h
8 KByte
8 KByte
1FBFFFh
1FA000h
1F9FFFh
1F8000h
8 KByte
8 KByte
007FFFh
006000h
005FFFh
004000h
9/40
M29W160ET, M29W160EB
Figure 6. Block Addresses (x16)
Note: Also see Appendix A, T ables 19 and 20 for a f ul l lis t i ng of the Bl ock Addresses .
AI06852
8 KWord
FFFFFh
FE000h
32 KWord
0FFFFh
08000h
32 KWord
07FFFh
00000h
M29W160ET
Top Boot Block Addresses (x16)
16 KWord
FBFFFh
F8000h
32 KWord
F0000h
F7FFFh
Total of 31
32 KWord Blocks
8 KWord
FFFFFh
F8000h 32 KWord
32 KWord
01FFFh
00000h
M29W160EB
Bottom Boot Block Addresses (x16)
16 KWord
F7FFFh
0FFFFh 32 KWord
F0000h
08000h
Total of 31
32 KWord Blocks
07FFFh
04000h
4 KWord
4 KWord
FDFFFh
FD000h
FCFFFh
FC000h
4 KWord
4 KWord
03FFFh
03000h
02FFFh
02000h
M29W160ET, M29W160EB
10/40
SIGNAL DESCRIPTIONS
See Figure 2, L ogic Diag ram, and T able 1, Sign al
Names, for a brief overview of the s ignals connect-
ed to this d evice .
Address Inputs (A0-A19). The Address Inputs
sele ct the cell s in the memory a rray to access d ur-
ing Bus Read operations. During Bus Wri te opera-
tions they control the commands sent to the
Command Interface of the Program/Erase Con-
troller.
Data Inputs/Outputs (DQ0-DQ7). The Data In-
puts/Outputs out put the data stored at the selected
address during a Bus Read operation. Duri ng Bus
Write operations they represent the commands
sent to the Command Interface of the Program/
Erase Controller.
Data Inputs/Outputs (DQ8-DQ14). The Data In-
puts/Outputs out put the data stored at the selected
address during a Bus Read operati on when BYTE
is High, VIH. When BYTE is Low, VIL, these pins
are not used and are high impedance. During Bus
Write operations the Command Register does not
use these bits . When reading t he Status Register
these bits should be ignored.
Data Input/Output or Address Input (DQ15A-1).
When BYTE is High, VIH, this pin behaves as a
Data Input/Output pin (as DQ8-DQ14). When
BYTE is Low, VIL, t his pin beh aves as an address
pin; DQ15A–1 Low will select t he LSB of the Word
on the other addresses, DQ15A–1 Hi gh will select
the MSB . Throughout the text consider references
to the Data Input/Output to include this pin when
BYTE is High and references to the Address In-
puts to inclu de this pin when BYT E is Low except
when stated explicitly otherwise.
Chip Enable (E). The Chip Enable, E, activates
the memor y, allowing Bus Read and Bus Write op-
erations to be performed. When Chip Enable is
High, VIH, all other pins are ignored.
Output Enable (G). The Output Enable, G, con-
trols the B us Read operat ion of the memory.
Write Enable (W). T he Write Enable, W, controls
the Bus Write operation of the memory’s Com-
ma nd Inte r face.
Reset/Block Temporary Unprotect ( RP). The
Reset/Block Temporary Unprotect pin can be
used to apply a Hardware Reset to t he memory or
to temporarily unprot ect al l Blocks that have b een
protected.
A Hardware Reset is achieved by holding Reset/
Block Temporary Unprotect Low, VIL, for at least
tPLPX. After Reset/Block Temporary Unprotect
goes High, V IH, the memory will be ready for Bus
Read and Bus Write operations after tPHEL or
tRHEL, whichever occurs last. See the Ready/ Busy
Output section, Table 15 and Figure 14, Reset/
Temporary Unprot ect AC Charact eris tics for more
details.
Holding RP at VID will temporarily unprotect the
protected Blocks in the memory. Program and
Erase operations on all blocks will be possible.
The transition from VIH to VID must be sl ower than
tPHPHH.
Ready/Busy Output (RB). The Ready/Busy pin
is an open-drain output that can be used to identify
when the device is performing a P rogr am or Erase
operation. During Program or Erase operations
Ready/Busy is Low, V OL. Read y/Busy is high-im-
pedance during Read mode, Auto Select mode
and Erase Suspend m ode.
After a Hardware Reset, Bus Read and Bus Write
operations cannot begin until Ready/Busy be-
comes h igh-impeda nc e. See Tabl e 15 a nd Fi gure
14, Reset/Temporary Unprotect AC Characteris-
tics.
The use of an open-drain output allows t he Ready/
Busy pins from several memories to be connected
to a single pull-up resistor. A Low will then i ndicate
that one, or more, of the me mories is busy.
Byte/Word Organization Select (BYTE). The
Byte/Word Organization Select pin is used to
switch bet ween the 8-bit and 16-bit Bus m odes of
the memory. When Byte/Word Organization Se-
lect is Low, VIL, the memory is in 8-bit mode, when
it is Hig h, VIH, the memory is in 16-bit mode.
VCC Supply Voltage. The VCC Supply Voltage
supplies the power for all operations (Read, Pro-
gram, Erase etc.).
The Command Interface is disabl ed when the VCC
Supply Voltage is less than the Lockout Voltage,
VLKO. This prevents Bus Write operations from ac-
cidentally damaging the data during power up,
power down and power surges. If the Program/
Erase Controller is programming or erasing during
this time then the operation aborts and t he memo-
ry contents being altered wi ll be invalid.
A 0.1µF capacitor should be connected between
the V CC Supply Voltage pin and the VSS Ground
pin to decoupl e the current surges from the power
supply. The PCB track widths must be sufficient to
carry the currents required during program and
erase operat ions, ICC3.
VSS Ground. The VSS Ground is the referenc e for
all v ol tage measurements. T he two VSS pins of the
device m ust be connected to the system ground.
11/40
M29W160ET, M29W160EB
BUS OPERATIONS
There are five s tandard bus operations that control
the device. The se are Bus Read, Bus Wri te, Out-
put Disable, Standby and Autom at ic Standby. See
Tables 2 and 3, Bus Operations, for a summary.
Typically glitches of less than 5ns on Chip Enab le
or Write Enable are ignored by the memory and do
not affect bus operations.
Bus Read. Bus Read operations read from the
memory cells, or specific registers in the Com-
mand Interface. A valid Bus Read operation in-
volves setting the desired address on the Address
Inputs, appl ying a Low s ig nal, VIL, to C hip Enable
and Output Enable and keeping Write Enable
High, VIH. The Data Inputs/Ou tputs will outp ut the
value, see Figure 11, Read Mode AC Waveforms,
and Table 12, Read AC Characteristics, for details
of when the output becomes valid.
Bus Write. Bus Write operations write to the
Command Interface. A valid Bus Write operation
begins by setting the desired address on the Ad-
dress Inputs. The Address Inputs are latched by
the Command Interface on the falling edge of Chip
Enable or Write Enable, whichever occurs last.
The Dat a Input s/O utputs a re latc hed by the Com-
mand Interface on the ri si ng edge of Chip Enab le
or Write Enable, whichever occurs first. Output En-
able must remain High, V IH, du ring the whole B us
Write operation. See Figures 12 and 13, Write AC
Waveforms, and Tables 13 and 14, Write AC
Characteristics, for details of the timing require-
ments.
Outp ut Disable. The Data Inputs/Outputs are in
the high impedance state when Output Enable is
High, VIH.
Standby. When Chip Enable is High, VIH, the
memory enters Standby mode and the Data In-
puts/Outputs pins are placed in the high-imped-
ance state. To reduce the Supply Current to the
Standby Supply Current, ICC2, Chip Enable should
be held within VCC ± 0.2V. For the Standby current
level see Table 11, DC C harac teristics.
During program or erase operations the memory
will continue to use the Program/Erase Supply
Current, ICC3, for Program or Erase operations un-
til t he operation com pletes .
Automatic Standby. If CMOS levels (VCC ± 0.2V)
are used to driv e the bus and the bus is inactive for
150ns or more the memory enters Automatic
Standby where the internal Supply Current is re-
duced to the Standby Supply Current, ICC2. The
Data Inputs/Outputs will still output data if a Bus
Read operation is in progress.
Special Bus Operations. Additional bus opera-
tions can be pe rform ed to read t he E lectronic Sig-
nature and also to apply and remove Block
Protection. These bus operat ions are intended f or
use by programming eq uipment a nd are not usu-
ally used in applications. They require VID to be
applied to some pins.
Electronic Sign atur e. The memory has two
codes, the manufacturer code and the device
code, that can be read to identify the memory.
These co des can be re ad by app lying the signals
listed in T able s 2 and 3, Bus Operations.
Block Protection and Blocks Unprotection.
Each block can be separately protected against
accidental Program or Erase. Protected blocks
can be unprotected t o allow dat a to be changed.
There are two methods available for protecting
and unprotecting the blocks, one for use on pro-
gramming equipment and the other for in-system
use. Block Protect and Blocks Unprotect opera-
tions are described in Appendix C.
Table 2. Bus Operations, BYTE = VIL
No te: X = VIL or VIH.
Operation E G W Address Inputs
DQ15A–1, A0-A19 Data Inputs/Outputs
DQ14-DQ8 DQ7-DQ0
Bus Read VIL VIL VIH Cell Address Hi-Z Data Output
Bus Write VIL VIH VIL Command Address Hi-Z Data Input
Output Disable X VIH VIH X Hi-Z Hi-Z
Standby VIH X X X Hi-Z Hi-Z
Read Manufacturer
Code VIL VIL VIH A0 = VIL, A1 = VIL, A9 = VID,
Others VIL or VIH Hi-Z 20h
Read Device Code VIL VIL VIH A0 = VIH, A1 = VIL, A 9 = VID,
Others VIL or VIH Hi-Z C4h (M29W160ET)
49h (M29W160EB)
M29W160ET, M29W160EB
12/40
Table 3. Bus Operations, BYTE = VIH
No te: X = VIL or VIH.
COMMAND INTERFACE
All Bus Write operations t o the me mory are in ter-
preted by the Command Interface. Commands
consist of one or more sequential Bus Write oper-
ations. Failure to observe a valid sequence of Bus
Write operations will result in the memory return-
ing to Read mode. The long command sequences
are imposed to maximize data security.
The address used for the commands changes de-
pending on whether the mem ory is in 16-bit or 8-
bit mode. See eith er Table 4, o r 5, de pendin g on
the configuration that is being used, for a summary
of the c om m ands.
Read/Rese t Command . The Read/Reset com-
mand returns the memory t o its Read m ode where
it behaves like a ROM or EPROM, unless other-
wise stated. It also reset s the errors in th e Status
Register. Either one or three Bus Write operations
can be used to is sue the Read/Reset command.
The Read/Reset Command can be issued, be-
tween Bus Write cycles before the start of a pro-
gram or erase operation, to return the device to
read mode. Onc e the program or erase operation
has started the Read/Res et comm and is no longer
accepted. The Read/Reset command will not
abort an Erase operation when issued while in
Erase Suspend.
Auto Select Command. The Auto Select com-
mand i s us ed to read the Man ufacturer C ode, t he
Device Code and the Block Protection Status.
Three consecutive Bus Write operations are re-
quired to issue the Auto Select command. Once
the Auto Select command is issued the memory
remains in Auto Select mode until a Read/Reset
command is issued. Read CFI Query and Read/
Reset commands are accepted in Auto Select
mode, all other commands are ignored .
From the Auto Select mode the Manufacturer
Code can be read using a Bus Read operation
with A 0 = VIL and A1 = VIL. The other address bits
may be set to e ither VIL or VIH. The Manufacturer
Code for STMicroelectronics is 0020h.
The Device Code can be read using a Bus Read
operation with A0 = VIH and A1 = VIL. The other
address bits ma y be set to either V IL or VIH. The
Device Code for the M29W160ET is 22C4h and
for the M29W160EB i s 2249h.
Th e Bloc k Pr ot ect i on Status of each block can be
read using a Bus Read operation with A0 = VIL,
A1 = VIH, and A 12-A1 9 s p ecifyi ng th e ad dres s of
th e block. The other address bit s may b e set t o ei-
ther VIL or VIH. I f the address ed block is pro tected
then 01h is output on Data Inputs/Outputs DQ0-
DQ7, otherwise 00h is output.
Progr a m Command. The Program command
can be used to program a value to one address in
the memory array at a time. The command re-
quires four Bus Write operations, the final write op-
eration latches the address and data, and starts
the Program/ Erase Controller.
If the address falls in a protected block then the
Program command is ignored, the data remains
unchanged. The Status Register is never read and
no error condition is giv en.
During the program operation the me mory will ig-
nore all comm ands. I t is not possible to iss ue any
command t o abort or pause the operation. Typical
program times are given in T able 6. Bus Read op-
erations during the program operation will output
the Status Register on the Data Inputs/Outputs.
See the section on the Status Register for more
details.
After the program operation has completed the
memory returns to t he Read mode, unless an error
Operation E G W Address Inputs
A0-A19 Data Inputs/Outputs
DQ15A–1, DQ14-DQ0
Bus Read VIL VIL VIH Cell Address Data Output
Bus Write VIL VIH VIL Command Address Data Input
Output Disable X VIH VIH XHi-Z
Standby VIH XXX Hi-Z
Read Manufacturer
Code VIL VIL VIH A0 = VIL, A1 = VIL, A9 = VID,
Others VIL or VIH 0020h
Read Device Code VIL VIL VIH A0 = VIH, A1 = VIL, A 9 = VID,
Others VIL or VIH 22C4h (M29W160ET)
2249h (M29W160EB)
13/40
M29W160ET, M29W160EB
has occurred. Wh en an error occurs the memory
continues to output the Status Register. A Read/
Reset comma nd must be issued to reset the error
condition and return to Read mode.
Note that t he Program command cannot change a
bit set at ’0’ back to ’1’. One of the Erase Com-
mands must be used to set all the bits in a block or
in the whole memory from ’0’ to ’1’.
Unlock Bypass Comman d. The Unlock Bypass
command is used in conjunction with the Unlock
Bypass Program c ommand to program the memo-
ry. When the access time to the device is long (as
with some EPROM programmers) considerable
time saving can be made by using these com-
mands. Three Bus Write operations are required
to issue the Unl oc k Bypass comm and.
Once the Unlock Bypass command has been is-
sued the memo ry will only accept the Unlock By-
pass Program command and the Unlock Bypass
Reset command. The memory can be read as if in
Read mode.
Unlock Bypass Program Comman d. The Un-
lock Bypass Program command can be used to
program one address in memory at a time. The
command re quires two Bus Write operations, the
final write operation latches t he address and dat a,
and starts the Program/Erase Controller.
The Program operation using the Unlock Bypass
Program c om mand behaves identicall y to the Pro-
gram operation using the Program command. A
protected block cannot be program m ed; the oper-
ation cannot be aborted and the Status Register is
read. Errors must be reset using the Read/Reset
command, w hich l eaves the de vice in Unlo ck By-
pass Mode. See the Program com mand for details
on the behavior.
Unlock Bypass Reset Comman d. The Unlock
Bypass Re se t command c an be used t o return to
Read/Reset mode from Unlock Bypass Mode.
Two Bus Write operations are required to issue the
Unlock Bypass Reset command. Read/Reset
command does not exit from Unlock Bypass
Mode.
Chip Erase Command. The Chip Erase com-
mand can be used to erase the entire chip. Six Bus
Write operations are required to issue the Chip
Erase Command and start the Program/Erase
Controller.
If any blocks are protected th en these are ignored
and all the other blocks are erased. If all of the
blo cks are p rote cted the Chip Erase o perat ion a p-
pears to start but will terminate within about 100µs,
leaving the data unchange d. No error co ndition is
given when protected blocks are ignored.
During the erase operation the memory will ignore
all commands. It is not pos sible to issue any com -
mand to abort the operation. Typical chip erase
times are given in Table 6. All Bus Read opera-
tions during the Chip Erase operation will output
the Status Register on the Data Inputs/Outputs.
See the section on the Status Register for more
details.
After the Chip Erase operation has completed t he
memory will return to the Read Mode, unless an
error has occurred. When an error occurs the
memory will continue to output the Status Regis-
ter. A Read/ Reset command must be issued to re-
set the error c ondition and return to Read Mode.
The Chip Erase Command sets all of the bits in un-
protected blocks of the memory to ’1’. All previous
data is lost.
Block Erase Command. The Block Erase com-
mand can be used to erase a list of one or more
blocks. Six Bus Write operations are required to
select the first block in the list. Each additional
block in the list can be selected by repeating the
sixth Bus Wr ite operation using the address of the
additional block. The Bloc k Erase operat ion starts
the Program/Erase Controller about 50µs af ter the
last Bus Write operation. Once the Program/Erase
Controller starts it is not possible to select any
more blocks. Each additional block must therefore
be selected within 50µs of the last block. The 50µs
timer r es tarts when an additional block is selected.
The Status Register can be read after the sixth
Bus Write operati on. See the Stat us Register sec-
tion for details on how to identify if the Program/
Erase Controller has started the Block Erase oper-
ation.
If any select ed blocks are protected then these are
ignored and all the other selected blocks are
erased. If all of the selected blocks are protected
the Block Erase operation appears to start but will
terminate within about 100µs, l eaving the data un-
changed. No error condition is given when protect-
ed blocks are ignore d.
During the Block Eras e ope ration th e me mory will
ignore all commands except the Erase Suspend
co mmand. Typical b lock e ra se tim es are g iven in
Table 6. Al l Bus Read operations during the Block
Eras e o peration will o ut p ut the S t a tus R eg i st er o n
the Data Inputs/Outputs. See the section on the
Status Regi st er for more details.
After the Block Erase operat ion has complet ed the
memory will return to the Read Mode, unless an
error has occurred. When an error occurs the
memory will continue to output the Status Regis-
ter. A Read/ Reset command must be issued to re-
set the error condition and return to Read mode.
The Block Erase Command sets all of the bits in
the unprotected selec ted blocks to ’1’. All previous
data in the selected blocks is lost.
Erase Suspend Command . The Erase Suspend
Comman d m ay be used to temporari ly s uspend a
M29W160ET, M29W160EB
14/40
Block Erase operation and return the memory to
Read mode. The command requires one Bus
Write operation.
The Prog ram/Eras e Controlle r will suspend within
the Erase Suspend Latency Time (ref er t o Table 6
for va lue) of the Era se Suspend Command being
issued. Once the Program/Erase Controller has
stopped the memory will be set to Read mode and
the Erase will be suspended. If the Erase Suspend
command is issued during the period when the
memory is waiting for an additional block (before
the Program/Erase Controller starts) then the
Erase is susp ended i mmedi ate ly and wi ll start im-
mediately when the Erase Resume Command is
issued. It is not possible to select any further
blo cks to erase a fte r the Era se Resume.
During Erase Suspend it is possible to Read and
Program cells in blocks that are not being erased;
both Read and Program operations behave as
normal on these blocks. If any attempt is made to
program in a protected bloc k or in the suspended
block then the Program command is ignored and
the data remains unchanged. The St atus Register
is not read and no error condi tion is given. Read-
ing from blocks that are being erased will output
the Status Register.
It is also possible to issue the Auto Select, Read
CFI Query and Unlock Bypass commands during
an Erase Suspend. The Read/Reset command
must be i ssued to return the devi ce to Read Array
mode before the Resume command will be ac-
cepted.
Erase Resum e Command . The Erase Resume
command must be used to restart the Program/
Erase Controller from Erase Suspend. An erase
can be suspended and resum ed more than onc e.
Read CFI Query Comman d. The Read CFI
Query Command is used to read data from the
Common Flash Interface (CFI) Memory Area. This
command is valid when the device i s in the Read
Array mod e, or wh en the dev ice is in A uto Se lect
mode.
One Bus Write cycle is required to issue the Read
CFI Query Command. Once the command is is-
sued subsequen t Bus Read ope ratio ns read from
the Common Flash Interface Memory Area .
The Read/Reset command must be issued to re-
turn the device to the previous mode (the Read Ar-
ray mode or Auto Select mode). A se cond Read/
Reset comma nd wo uld be needed if the dev ice is
to be put in the Read Array mode from Aut o Select
mode.
See Appendix B, Tables 21, 22, 23, 24, 25 and 26
for details on the information contained in the
Common Flash Interface (CF I) memory area.
15/40
M29W160ET, M29W160EB
Table 4. Co m mand s, 16-bit mode, BY TE = VIH
Note : X Don’t Care, PA Program Add ress, PD Program Data, BA Any addre ss in the Block.
All values in th e table are i n hexadec i m al .
Th e Com ma nd In terf ace o nly us es A –1, A0-A 10 a nd DQ 0-DQ7 t o ver ify t he comm an ds; A1 1-A1 9, DQ8- DQ1 4 a nd DQ 15 ar e Don’t
Care. DQ15A–1 is A–1 when B Y T E is VIL or DQ15 when BYTE is VIH.
Read/Reset. Aft er a Read/Rese t c om m and, read the mem ory as normal un til another comm and i s issued.
Auto Selec t. Af ter an Au to S elect c om mand, read Manu facturer ID, De vice ID or Block Prot ection S tatus.
Pro gram, Unl ock By pass Progra m, Ch ip E rase, Blo ck Eras e . Afte r thes e com man ds rea d t he Stat us Reg ist er unt il the Prog ram/
Erase Controller completes and the memory returns to Read Mode. Add additional Blocks during Block Erase Command with additional
Bus Write Operations until T i m eout Bit is set.
Unlo ck By p as s. After th e Unlock Bypas s co mmand i ssue Unlock Bypass Program or Unl ock Bypass Re set comm ands.
Unlo ck By p as s Re set. After the Unlock Bypass Reset command read the memory as normal until another command is issued.
Erase Suspend. After the Erase Suspend command read non-erasing memory blocks as normal, issue Auto Select and Program com-
ma nds on non-erasing blocks as nor m al .
Erase Resume. Aft er t he Eras e Resum e comm and the susp ended Erase o peration resum es, re ad the Status Register unt i l th e Pro-
gram/E rase Cont ro l l er com pl ete s an d t h e m em ory returns to Re ad Mo de.
CFI Qu e r y. Com m and i s vali d when devi ce is ready to rea d array dat a or when device i s i n A uto Select mode.
Command
Length
Bus Write Operations
1st 2nd 3rd 4th 5th 6th
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Read/Reset 1X F0
3555 AA 2AA 55 X F0
Auto Select 3 555 AA 2AA 55 555 90
Program 4 555 AA 2AA 55 555 A0 PA PD
Unlock Bypass 3 555 AA 2AA 55 555 20
Unlock Bypass
Program 2X A0PAPD
Unlock Bypass Reset 2 X 90 X 00
Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2 AA 55 555 10
Block Erase 6+ 555 AA 2AA 55 555 80 555 AA 2AA 55 BA 30
Erase Suspend 1 X B0
Erase Resume 1 X 30
Read CFI Query 1 55 98
M29W160ET, M29W160EB
16/40
Table 5. Commands, 8-bit mode, BYTE = V IL
Note : X Don’t Care, PA Program Add ress, PD Program Data, BA Any addre ss in the Block.
All values in th e table are i n hexadec i m al .
Th e Com ma nd In terf ace o nly us es A –1, A0-A 10 a nd DQ 0-DQ7 t o ver ify t he comm an ds; A1 1-A1 9, DQ8- DQ1 4 a nd DQ 15 ar e Don’t
Care. DQ15A–1 is A–1 when B Y T E is VIL or DQ15 when BYTE is VIH.
Read/Reset. Aft er a Read/Rese t c om m and, read the mem ory as normal un til another comm and i s issued.
Auto Selec t. Af ter an Au to S elect c om mand, read Manu facturer ID, De vice ID or Block Prot ection S tatus.
Pro gram, Unl ock By pass Progra m, Ch ip E rase, Blo ck Eras e . Afte r thes e com man ds rea d t he Stat us Reg ist er unt il the Prog ram/
Erase Controller completes and the memory returns to Read Mode. Add additional Blocks during Block Erase Command with additional
Bus Write Operations until T i m eout Bit is set.
Unlo ck Bypass. After the Unlock Bypass comm and issue Unloc k Bypass Program or Unlo ck By pass Reset com m ands.
Unlo ck Bypass Re set. After the Unlock Bypass Reset command read the memory as normal until another command is issued.
Erase Suspend. After the Erase Suspend command read non-erasing memory blocks as normal, issue Auto Select and Program com-
ma nds on non-erasing blocks as nor m al .
Erase Resume. Aft er t he Eras e Resum e comm and the susp ended Erase o peration resum es, re ad the Status Register unt i l th e Pro-
gram/E rase Cont ro l l er com pl ete s an d t h e m em ory returns to Re ad Mo de.
CFI Qu e r y. Com m and i s vali d when devi ce is ready to rea d array dat a or when device i s i n A uto Select mode.
Command
Length
Bus Write Operations
1st 2nd 3rd 4th 5th 6th
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Read/Reset 1X F0
3 AAA AA 555 55 X F0
Auto Select 3 AAA AA 555 55 AAA 90
Program 4 AAA AA 555 55 AAA A0 PA PD
Unlock Bypass 3 AAA AA 555 55 AAA 20
Unlock Bypass
Program 2X A0PAPD
Unlock Bypass Reset 2 X 90 X 00
Chip Erase 6 AAA AA 555 55 AAA 80 AAA AA 555 55 AAA 10
Block Erase 6+ AAA AA 555 55 AAA 80 AAA AA 555 55 BA 30
Erase Suspend 1 X B0
Erase Resume 1 X 30
Read CFI Query 1 AA 98
17/40
M29W160ET, M29W160EB
Table 6. Progra m, Erase Tim es and Progra m , Erase Endu ran ce Cycle s
Note: 1. Typ i cal values m easured at room t em perature and nominal voltages.
2. Sam ple d, but no t 100% tes ted.
3. Max imum valu e m easured at worst cas e condi tions for both temperatu re and VCC after 100,000 program/erase cycles .
4. Max imum valu e m easured at worst cas e condi tions for both temperatu re and VCC.
STATUS REGIST ER
Bus Read operations from any address always
read the Status Register during Program and
Erase operations. It is al so read during Erase Sus-
pend when an address within a block being erased
is acce sse d.
The bits in the Stat us Regist er are sum marized in
Table 7, Status Regist er Bits.
Data Pollin g Bit (DQ7). The Data Polling Bit can
be used to identify whether the Program/Erase
Controller has successfully completed its opera-
tion or if it has responded to an Erase Suspend.
The Data Polling Bit is output on DQ7 when the
Status Register is re ad.
During Program operations the Data Polling Bit
outputs the complement of the bit being pro-
grammed to DQ7. After successful completion of
the Program operation the memory returns to
Read mode and Bus Read oper ations from t he ad-
dress just programmed output DQ7, not its com-
plement.
During Erase ope rations the Data Po lling Bi t out-
puts ’0’, the complement of the erased state of
DQ7. Aft er suc cessful completi on of the Erase op-
eration the memory returns to Read Mode.
In Erase Suspend mode the Data Polling Bit will
output a ’1’ during a Bus Read operation within a
block being erased. The Data Polling Bit will
change f rom a ’0’ to a ’1’ when the Program/Erase
Controller has suspended the Erase operation.
Figure 7, Data Polling Flowcha rt, gives an exam-
ple of how to use the Data Polling B it. A Valid Ad-
dress is the address being programmed or an
address within the block being erased.
Toggle Bit (DQ6). The Toggle Bit can be used to
identify whether the Program/Er as e Controll er has
successfully compl eted its operation or if it has re-
sponded to an Erase Suspend. The Toggle Bit is
output on DQ6 when the Status Register is read.
During Program and Erase operations the Toggle
Bit changes f rom ’0 ’ to ’ 1’ to ’ 0’, et c., with succes-
sive Bus Read operations at any address. After
successful completion of the operation the memo-
ry returns to Read mode.
During Erase Suspend mode the Toggle Bit will
output when addressing a cel l within a block being
erased. The Toggle Bit will stop toggli ng when the
Program/Erase Controller has suspended the
Erase operation.
If any attempt is ma de to erase a prote cted bl ock,
the o peration is aborted, no error i s s ig nalled and
DQ6 toggles for approximately 100µs. If any at-
tempt is made to program a protected block or a
suspended b lock, the operation is abort ed, no er-
ror is signalled and DQ6 toggles for approximately
1µs.
Figure 8 , Data Toggle Flowchart, g ives an e xam-
ple of how to u se the Data Toggle Bit.
Error Bi t (DQ5). The Error Bit can be used to
identify errors detected by the Program/Erase
Controller. The Erro r Bit is set to ’1’ when a Pro-
gram, Block Erase or Chip Erase operation fails to
write the correct data to the memory. If the Error
Bit is set a Rea d/Re se t comm and must be issued
before other commands are issued. The Error bit
is output on DQ5 when the Status Register is read.
Parameter Min Typ (1,2) Max(2) Unit
Chip Erase 29 120 (3) s
Block Erase (64 KBytes) 0.8 6 (4) s
Erase Suspend Latency Time 20 25 (4) µs
Program (Byte or Word) 13 200 (3) µs
Chip Program (Byte by Byte) 26 120 (3) s
Chip Program (Word by Word) 13 60 (3) s
Program/Erase Cycles (per Block) 100,000 cycles
Data Retention 20 years
M29W160ET, M29W160EB
18/40
Note that t he Program command cannot change a
bit set to ’ 0’ back to ’1’ and attempting to do so will
set DQ5 to ‘1’. A Bus Read operation to that ad-
dres s w ill s h ow th e b it is s ti ll ‘0’. On e of the Eras e
commands must be used to set all the bits in a
block or in the whole memory from ’0’ to ’1
Erase Timer Bit (DQ3). The Erase Timer Bit can
be used to identify the start of Program/Erase
Controller operation during a Block Erase com-
mand. Once the Program/Erase Controller starts
erasing the Erase Ti mer Bit is set to ’1’. Before the
Program/Erase Controller starts the Erase Timer
Bit is set to ’0’ and add itional blocks to be erased
may be written to the Command Interface. The
Erase Timer Bit is output on DQ3 when the Status
Register is read.
Alternative T og gle Bit (DQ2). The Alternative
Toggle Bit can be used to monitor the Program/
Erase controller during Erase operations. The Al-
ternative Toggle Bit is output on DQ2 when the
Status Register is re ad.
During Chip Erase and Block Erase operations the
Toggle Bit changes fro m0’ to ’1’ to ’0’, etc., with
successive Bus Re ad operations from addresses
within the blocks being erased. A protected block
is treated the same as a block not being erased.
Once t he operation completes the memory returns
to Read mode.
During Erase Suspend the Alternative Toggle Bit
changes from ’0’ to ’1’ to ’0’, etc. with successive
Bus Read operations from addresses within the
blocks being erased. Bus Read operations to ad-
dresses within blocks not bei ng erased wi ll ou tput
the memory cell data as i f in Read mode.
After an Erase operation that caus es t he Error Bit
to be set the Alternative Toggle Bit can be used to
identify which block or blocks have caused the er-
ror. The Altern ative Toggle Bit changes from ’0to
’1’ to ’0’, etc. with successive Bus Read Opera-
tions from addresses within blocks that have not
erased correctly. The Alte rnative Toggle Bit does
not change if the addressed block has erased cor-
rectly.
Table 7. Statu s Register Bits
Note: Unspecified data bits sh ould be ignored.
Operation Address DQ7 DQ6 DQ5 DQ3 DQ2 RB
Program Any Address DQ7 Toggle 0 0
Program During Erase
Suspend Any Address DQ7 Toggle 0 0
Program Error Any Address DQ7 Toggle 1 0
Chip Erase Any Address 0 Toggle 0 1 Toggle 0
Block Erase before
timeout Erasing Block 0 Toggle 0 0 Toggle 0
Non-Erasing Block 0 Toggle 0 0 No Toggle 0
Block Erase Erasing Block 0 Toggle 0 1 Toggle 0
Non-Erasing Block 0 Toggle 0 1 No Toggle 0
Erase Suspend Erasing Block 1 No Toggle 0 Toggle 1
Non-Erasing Block Data read as normal 1
Erase Error Good Block Address 0 Toggle 1 1 No Toggle 0
Faulty Block Address 0 Toggle 1 1 Toggle 0
19/40
M29W160ET, M29W160EB
Figu re 7. Da ta Po lling Flo wc h a rt Fi gure 8. Dat a Toggle Fl owchar t
MAX I MUM RA T I N G
Stressing the device ab ove t he rating listed in t he
Absolute Maximum Ratings" table may cause per-
manent damag e to the dev ice. Exposure to Abso-
lute Maximum Rating conditions for extended
periods may affect device reliability. These are
stress ratings only and operation of the device at
these or any other conditions above those indicat-
ed in the Operating sections of this specification is
not implied. Refer also to the STMicroelectronics
SURE Program and other relevant quality docu-
ments.
Table 8. Absolute Maximum Ratings
Note: 1. Mini m um voltage m ay undershoo t t o –2V during t ransition and for less t han 20ns dur i ng trans i tions.
2. Max imum voltage may overshoot to V CC +2V during trans i t i on and for less tha n 20ns during trans i t io ns.
READ DQ5 & DQ7
at VALID ADDRESS
START
READ DQ7
at VALID ADDRESS
FAIL PASS
AI03598
DQ7
=
DATA YES
NO
YES
NO
DQ5
= 1
DQ7
=
DATA YES
NO
READ DQ6
START
READ DQ6
TWICE
FAIL PASS
AI01370C
DQ6
=
TOGGLE NO
NO
YES
YES
DQ5
= 1
NO
YES
DQ6
=
TOGGLE
READ
DQ5 & DQ6
Symbol Parameter Min Max Unit
TBIAS Temperature Under Bias –50 125 °C
TSTG Storage Temperature 65 150 °C
VIO Input or Output Voltage (1,2) –0.6 VCC +0.6 V
VCC Supply Voltage –0.6 4 V
VID Identification Voltage –0.6 13.5 V
M29W160ET, M29W160EB
20/40
DC AND AC PARAMETERS
This section summarizes the operating measure-
ment cond iti ons, and the DC and AC characteris-
tics of the device. The p arameters in the D C and
AC characteristics Tables that fo llow, are derived
from tests performed under the Measurement
Conditions sum marized in Table 9, Operating and
AC Measurement Conditions. Designers should
check t hat the operating cond itions in their circuit
match the operating conditions when relying on
the quot ed parameters.
Table 9. Operating and AC Measurem en t Conditions
Figure 9. AC Measurement I/O Wavefo rm Figure 10. AC Measure ment Lo ad Circuit
Table 10. Device Capacitance
Note: Sampled only, no t 100% test ed.
Parameter
M29W160E
Unit70 90
Min Max Min Max
VCC Supply Voltage 2.7 3.6 2.7 3.6 V
Ambient Operati ng Temperatur e –40 85 –40 85 °C
Load Capacitance (CL)30 30 pF
Input Rise and Fall Times 10 10 ns
Input Pulse Voltages 0 to VCC 0 to VCC V
Input and Output Timing Ref. Voltages VCC/2 VCC/2 V
AI04498
VCC
0V
VCC/2
AI04499
CL
CL includes JIG capacitance
DEVICE
UNDER
TEST
25k
VCC
25k
VCC
0.1µF
Symbol Parameter Test Condition Min Max Unit
CIN Input Capacitance VIN = 0V 6pF
COUT Output Capacitance VOUT = 0V 12 pF
21/40
M29W160ET, M29W160EB
Table 11. DC Characteristics
Note: 1. Sampled only, not 100% tested.
Symbol Parameter Test Condition Min Typ Max Unit
ILI Input Leakage Current 0V VIN VCC ±1 µA
ILO Output Leak age Curren t 0V VOUT VCC ±1 µA
ICC1 Supply Curre nt (Read) E = VIL, G = VIH,
f = 6MHz 4.5 10 mA
ICC2 Supply Curre nt (Standby) E = VCC ±0.2V,
RP = VCC ±0.2V 35 100 µA
ICC3 (1) Su pply Curre nt
(Program/Erase) Program/Erase
Controller active 20 mA
VIL Input Low Voltage –0.5 0.8 V
VIH Input High Voltage 0.7VCC VCC +0.3 V
VOL Output Low Vo ltage IOL = 1.8mA 0.45 V
VOH Output High Voltage IOH = –100µAVCC –0.4 V
VID Identification Voltage 11.5 12.5 V
IID Identification Current A9 = VID 100 µA
VLKO Program/Erase Lockout
Supply Voltage 1.8 2.3 V