M29W160ET70N6F - STMicroelectronics

1/40January 2004

M29W160ET

M29W160EB

16 Mbit (2Mb x8 or 1Mb x16, Boot Block)

3V Suppl y Flash M emo ry

FEATURES SUM M ARY

■SUPPLY VOLT AGE

–V

CC = 2.7V to 3.6V for Program, Erase

and Read

■ACCESS TI MES: 70, 90ns

■PROGRAMMING TIME

– 10µs per Byte/Word typical

■35 MEMORY BL OCKS

– 1 Boot Block (Top or Bottom Location)

– 2 Paramete r and 32 Main Blocks

■PROGRAM/ERASE CONTROLLER

– Embedded Byte/ Word Program

algorithms

■ERASE SUSPEND and RESUME MODES

– Read and Program another Block during

Erase Su spend

■UNLOCK BYPASS PROGRAM COMMAND

– Faster Produc tion/Batc h Progra mming

■TEMPO RARY BLOCK UNPROTECTION

MODE

■COMMON FLASH INTERFAC E

– 64 bit Security Code

■LOW POWER CONSUM PTION

– Standby and Autom atic Standby

■100, 000 PROGRA M /ERAS E CYCLES per

BLOCK

■ELECTRO NIC SIG N ATURE

– Manufacturer Code: 0020h

– Top Device C ode M29 W160ET: 22C4h

– Bottom Device Code M29W160EB: 2249h

Figure 1. Packages

TSOP48 (N)

12 x 20mm

TFBGA48 (ZA)

6 x 8mm

FBGA

M29W160ET, M29W160EB

2/40

TABLE OF C ONTENT S

FEATUR ES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 1. Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

SUM MARY DESCRIPT ION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Table 1. Signa l Na mes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 3. TSOP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 4. TFBGA Connect ions (Top view through packag e) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 5. Block Add resses (x8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 6. Block Add resses (x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

SIGNA L DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Address Inputs (A0-A19). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

D ata Inputs/Ou tputs (DQ0-DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0

D ata Inputs/Ou tputs (DQ8-DQ14 ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

D ata Input/Output or Address Input (DQ15A-1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

C hip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Out put Enabl e (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Wri t e Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Reset/Bl ock Temporary Unprotect (RP).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

R eady/Busy Output (RB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Byte/Word Organization Select (BYTE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

VCC Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

VSS Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1

Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1

Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1

Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1

Autom at ic Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1

Special Bus Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Ele ctronic Signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Block Protection and Blocks Unp rotection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 2. Bus Operations, BYTE = V IL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 3. Bus Operations, BYTE = V IH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

R ead/Res et Comm and.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Auto Se lect Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Unlock Bypass C ommand. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Unlock Bypass Program Com mand. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Unlock Bypass R eset Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

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M29W160ET, M29W160EB

C hip Erase Comm and. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3

Blo ck Erase Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Erase S uspend Com ma nd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Erase Resume Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4

R ead CFI Query Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 4. Com m ands, 16-bi t mode, BYTE = VIH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 5. Com m ands, 8-bit mode, BY TE = VIL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 6. Program, Erase Times and Program, Erase Endurance Cycles . . . . . . . . . . . . . . . . . . . 17

STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Data Polling Bit (DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 7

Toggl e Bit (DQ6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Error Bit (DQ5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Erase Timer Bit (DQ3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Alternative Toggle Bit (DQ2).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 8

Table 7. Status Register Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 8

Figure 7. Data Pol ling Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 8. Data Toggle Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 9

MAXIMU M RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 8. Absolute Maximum Rati ngs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 9. Operating a nd AC Measurement Cond iti ons. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 9. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 10.A C Measurem ent Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 10. Dev ice Capacitanc e. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 11. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1

Figure 11.Read M ode A C Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 12. Read AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Figure 12.Write AC Wa veforms, Write Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 13. Write AC Cha racteristics, Write Enable Contro lled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 13.Write AC Waveforms, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 14. Write AC Characteristics, Chip Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 14.Reset/Block Temporary Unprotect AC Wa veforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 15. Reset/Block Temporary Unprotect AC Chara cteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 25

PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 15.TSOP48 – 48 lead Plastic T hin S ma ll Outline, 12 x 20mm, Packa ge Outline. . . . . . . . . 26

Table 16. TSOP48 – 48 lead Plastic T hin S m all Outline, 12 x 20mm, Pack age Mecha nical Data . 26

Figure 16.TF B GA48 6x 8m m - 6x8 ball array, 0.80 mm pitch, Pack age Outline . . . . . . . . . . . . . . . 27

Table 17. TF B GA48 6x 8m m - 6x8 ball array, 0.80 mm pitch, Package Mech anical Data. . . . . . . . 27

PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 18. Orde ring Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

M29W160ET, M29W160EB

4/40

APPENDIX A.BLOCK ADDRESS TABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 19. Top Boot Block Addresses, M29W160ET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 20. Bottom Boot Block Addresses, M29W1 60EB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

APPENDIX B.COMMON FLASH INTERFACE (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 21. Query Structure Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Table 22. CFI Query Identification String. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Table 23. CFI Query System Interface Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 24. Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Table 25. P rimary Algorithm-S pecific Extended Query Tabl e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 26. Security Code Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3

APPENDIX C.BLOCK PROTECTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Programmer Tech nique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4

In-System Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4

Table 27. Programmer Techni que Bus Operations, BYTE = V IH or VIL . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 17.Programmer Equipment Block Protect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 18.P rogram mer Equipment Chip Unprotect Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 19.In-System Equipment Block Protect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 20.In-System Equipment Chip Unprotect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

REVISION HISTO RY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 28. Document Revi sion History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

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M29W160ET, M29W160EB

SUMMARY DESCRIPTION

The M29W160E is a 16 Mbit (2Mb x8 or 1Mb x16)

non-volatile memory that can be read, erased and

reprogrammed. These operations can be per-

formed using a single low voltage (2.7 to 3.6V)

supply. On power-up the memory defaults to its

Read mode where it can be read in the same way

as a ROM or E P ROM .

The memory is divided into blocks that can be

erased independently so i t is p ossible to pres erve

valid data while old data is erased. Each block can

be protected independently to prevent accidental

Program or Erase commands from modifying the

memory. P rogram and Er ase com m ands are wri t-

ten to the Com mand Interface of the mem ory. An

on-chip Program/Erase Controller simplifies the

process of pr ogramming or erasing the memory by

taking care of all of the special operations that are

required to update the memory contents.

The end of a program or erase operation can be

detected and any error conditions identified. The

command set required to control the memory is

consistent with JEDEC standards.

The b locks in the memory are asymmetrically ar-

ranged, see Figures 5 and 6, Block Addresses.

The first or last 64 KBytes have been di vi ded into

four additional blocks. The 16 KByte Boot Block

can be used for small initialization code to s tart the

microprocessor, the two 8 KByte Parameter

Blocks can be us ed for parameter storage and the

remaining 32K is a small Main Block where the ap-

plication may be stored.

Chip Enabl e, Output Enable and Write Enable sig-

nals control the bus operation of the memory.

They allow simple connection to most micropro-

cessors, often without additional logic.

The memory is offered TSOP48 (12 x 20mm ) and

TFBGA48 (0.8mm pitch) packages. The memory

is s upp lied with all the bits erased (set to ’1’).

Figure 2. Logic Diagram Tabl e 1. Signal Names

AI06849B

A0-A19

DQ0-DQ14

VCC

M29W160ET

M29W160EB

VSS

DQ15A–1

BYTE

A0-A19 Address Inputs

DQ0-DQ7 Data Inputs/Outputs

DQ8-DQ14 Data Inputs/Outputs

DQ15A–1 Data Input/Output or Address Input

EChip Enable

GOutput Enable

WWrite Enable

RP Reset/Block Temporary Unprotect

RB Ready/Busy Output

BYTE Byte/Word Organization Select

VCC Supply Vo ltage

VSS Ground

NC Not Connected Internally

M29W160ET, M29W160EB

6/40

Figu re 3. TSOP Conne ct i on s

DQ3

DQ9

DQ2

A6 DQ0

DQ6

A9 DQ13

A17

A10 DQ14

DQ12

DQ10

DQ15A–1

VCC

DQ4

DQ5

DQ7

AI06850

M29W160ET

M29W160EB

24 25

DQ8

A19

A18

DQ1

DQ11

A12

A13

A16

A11

BYTE

A15

A14 VSS

VSS

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M29W160ET, M29W160EB

Figure 4. TFBGA Connections ( Top vi ew throug h package)

AI02985B

654321

VSS

DQ15

A–1

A15

A14

A12

A13

DQ3

DQ11

DQ10

A18

DQ1

DQ9

DQ8

DQ0

A17

DQ2

DQ6

DQ13

DQ14

A10

DQ4

VCC

DQ12

DQ5

A19

A11

DQ7

VSS

A5 NC

A16

BYTE

M29W160ET, M29W160EB

8/40

Figure 5. Block Addresses (x8)

Note: Also see Appendix A, T ables 19 and 20 for a f ul l lis t i ng of the Bl ock Addresses .

AI06851

16 KByte

1FFFFFh

1FC000h

64 KByte

01FFFFh

010000h

64 KByte

00FFFFh

000000h

M29W160ET

Top Boot Block Addresses (x8)

32 KByte

1F7FFFh

1F0000h

64 KByte

1E0000h

1EFFFFh

Total of 31

64 KByte Blocks

16 KByte

1FFFFFh

1F0000h 64 KByte

64 KByte

003FFFh

000000h

M29W160EB

Bottom Boot Block Addresses (x8)

32 KByte

1EFFFFh

01FFFFh 64 KByte

1E0000h

010000h

Total of 31

64 KByte Blocks

00FFFFh

008000h

8 KByte

1FBFFFh

1FA000h

1F9FFFh

1F8000h

8 KByte

007FFFh

006000h

005FFFh

004000h

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M29W160ET, M29W160EB

Figure 6. Block Addresses (x16)

Note: Also see Appendix A, T ables 19 and 20 for a f ul l lis t i ng of the Bl ock Addresses .

AI06852

8 KWord

FFFFFh

FE000h

32 KWord

0FFFFh

08000h

32 KWord

07FFFh

00000h

M29W160ET

Top Boot Block Addresses (x16)

16 KWord

FBFFFh

F8000h

32 KWord

F0000h

F7FFFh

Total of 31

32 KWord Blocks

8 KWord

FFFFFh

F8000h 32 KWord

32 KWord

01FFFh

00000h

M29W160EB

Bottom Boot Block Addresses (x16)

16 KWord

F7FFFh

0FFFFh 32 KWord

F0000h

08000h

Total of 31

32 KWord Blocks

07FFFh

04000h

4 KWord

FDFFFh

FD000h

FCFFFh

FC000h

4 KWord

03FFFh

03000h

02FFFh

02000h

M29W160ET, M29W160EB

10/40

SIGNAL DESCRIPTIONS

See Figure 2, L ogic Diag ram, and T able 1, Sign al

Names, for a brief overview of the s ignals connect-

ed to this d evice .

Address Inputs (A0-A19). The Address Inputs

sele ct the cell s in the memory a rray to access d ur-

ing Bus Read operations. During Bus Wri te opera-

tions they control the commands sent to the

Command Interface of the Program/Erase Con-

troller.

Data Inputs/Outputs (DQ0-DQ7). The Data In-

puts/Outputs out put the data stored at the selected

address during a Bus Read operation. Duri ng Bus

Write operations they represent the commands

sent to the Command Interface of the Program/

Erase Controller.

Data Inputs/Outputs (DQ8-DQ14). The Data In-

puts/Outputs out put the data stored at the selected

address during a Bus Read operati on when BYTE

is High, VIH. When BYTE is Low, VIL, these pins

are not used and are high impedance. During Bus

Write operations the Command Register does not

use these bits . When reading t he Status Register

these bits should be ignored.

Data Input/Output or Address Input (DQ15A-1).

When BYTE is High, VIH, this pin behaves as a

Data Input/Output pin (as DQ8-DQ14). When

BYTE is Low, VIL, t his pin beh aves as an address

pin; DQ15A–1 Low will select t he LSB of the Word

on the other addresses, DQ15A–1 Hi gh will select

the MSB . Throughout the text consider references

to the Data Input/Output to include this pin when

BYTE is High and references to the Address In-

puts to inclu de this pin when BYT E is Low except

when stated explicitly otherwise.

Chip Enable (E). The Chip Enable, E, activates

the memor y, allowing Bus Read and Bus Write op-

erations to be performed. When Chip Enable is

High, VIH, all other pins are ignored.

Output Enable (G). The Output Enable, G, con-

trols the B us Read operat ion of the memory.

Write Enable (W). T he Write Enable, W, controls

the Bus Write operation of the memory’s Com-

ma nd Inte r face.

Reset/Block Temporary Unprotect ( RP). The

Reset/Block Temporary Unprotect pin can be

used to apply a Hardware Reset to t he memory or

to temporarily unprot ect al l Blocks that have b een

protected.

A Hardware Reset is achieved by holding Reset/

Block Temporary Unprotect Low, VIL, for at least

tPLPX. After Reset/Block Temporary Unprotect

goes High, V IH, the memory will be ready for Bus

Read and Bus Write operations after tPHEL or

tRHEL, whichever occurs last. See the Ready/ Busy

Output section, Table 15 and Figure 14, Reset/

Temporary Unprot ect AC Charact eris tics for more

details.

Holding RP at VID will temporarily unprotect the

protected Blocks in the memory. Program and

Erase operations on all blocks will be possible.

The transition from VIH to VID must be sl ower than

tPHPHH.

Ready/Busy Output (RB). The Ready/Busy pin

is an open-drain output that can be used to identify

when the device is performing a P rogr am or Erase

operation. During Program or Erase operations

Ready/Busy is Low, V OL. Read y/Busy is high-im-

pedance during Read mode, Auto Select mode

and Erase Suspend m ode.

After a Hardware Reset, Bus Read and Bus Write

operations cannot begin until Ready/Busy be-

comes h igh-impeda nc e. See Tabl e 15 a nd Fi gure

14, Reset/Temporary Unprotect AC Characteris-

tics.

The use of an open-drain output allows t he Ready/

Busy pins from several memories to be connected

to a single pull-up resistor. A Low will then i ndicate

that one, or more, of the me mories is busy.

Byte/Word Organization Select (BYTE). The

Byte/Word Organization Select pin is used to

switch bet ween the 8-bit and 16-bit Bus m odes of

the memory. When Byte/Word Organization Se-

lect is Low, VIL, the memory is in 8-bit mode, when

it is Hig h, VIH, the memory is in 16-bit mode.

VCC Supply Voltage. The VCC Supply Voltage

supplies the power for all operations (Read, Pro-

gram, Erase etc.).

The Command Interface is disabl ed when the VCC

Supply Voltage is less than the Lockout Voltage,

VLKO. This prevents Bus Write operations from ac-

cidentally damaging the data during power up,

power down and power surges. If the Program/

Erase Controller is programming or erasing during

this time then the operation aborts and t he memo-

ry contents being altered wi ll be invalid.

A 0.1µF capacitor should be connected between

the V CC Supply Voltage pin and the VSS Ground

pin to decoupl e the current surges from the power

supply. The PCB track widths must be sufficient to

carry the currents required during program and

erase operat ions, ICC3.

VSS Ground. The VSS Ground is the referenc e for

all v ol tage measurements. T he two VSS pins of the

device m ust be connected to the system ground.

11/40

M29W160ET, M29W160EB

BUS OPERATIONS

There are five s tandard bus operations that control

the device. The se are Bus Read, Bus Wri te, Out-

put Disable, Standby and Autom at ic Standby. See

Tables 2 and 3, Bus Operations, for a summary.

Typically glitches of less than 5ns on Chip Enab le

or Write Enable are ignored by the memory and do

not affect bus operations.

Bus Read. Bus Read operations read from the

memory cells, or specific registers in the Com-

mand Interface. A valid Bus Read operation in-

volves setting the desired address on the Address

Inputs, appl ying a Low s ig nal, VIL, to C hip Enable

and Output Enable and keeping Write Enable

High, VIH. The Data Inputs/Ou tputs will outp ut the

value, see Figure 11, Read Mode AC Waveforms,

and Table 12, Read AC Characteristics, for details

of when the output becomes valid.

Bus Write. Bus Write operations write to the

Command Interface. A valid Bus Write operation

begins by setting the desired address on the Ad-

dress Inputs. The Address Inputs are latched by

the Command Interface on the falling edge of Chip

Enable or Write Enable, whichever occurs last.

The Dat a Input s/O utputs a re latc hed by the Com-

mand Interface on the ri si ng edge of Chip Enab le

or Write Enable, whichever occurs first. Output En-

able must remain High, V IH, du ring the whole B us

Write operation. See Figures 12 and 13, Write AC

Waveforms, and Tables 13 and 14, Write AC

Characteristics, for details of the timing require-

ments.

Outp ut Disable. The Data Inputs/Outputs are in

the high impedance state when Output Enable is

High, VIH.

Standby. When Chip Enable is High, VIH, the

memory enters Standby mode and the Data In-

puts/Outputs pins are placed in the high-imped-

ance state. To reduce the Supply Current to the

Standby Supply Current, ICC2, Chip Enable should

be held within VCC ± 0.2V. For the Standby current

level see Table 11, DC C harac teristics.

During program or erase operations the memory

will continue to use the Program/Erase Supply

Current, ICC3, for Program or Erase operations un-

til t he operation com pletes .

Automatic Standby. If CMOS levels (VCC ± 0.2V)

are used to driv e the bus and the bus is inactive for

150ns or more the memory enters Automatic

Standby where the internal Supply Current is re-

duced to the Standby Supply Current, ICC2. The

Data Inputs/Outputs will still output data if a Bus

Read operation is in progress.

Special Bus Operations. Additional bus opera-

tions can be pe rform ed to read t he E lectronic Sig-

nature and also to apply and remove Block

Protection. These bus operat ions are intended f or

use by programming eq uipment a nd are not usu-

ally used in applications. They require VID to be

applied to some pins.

Electronic Sign atur e. The memory has two

codes, the manufacturer code and the device

code, that can be read to identify the memory.

These co des can be re ad by app lying the signals

listed in T able s 2 and 3, Bus Operations.

Block Protection and Blocks Unprotection.

Each block can be separately protected against

accidental Program or Erase. Protected blocks

can be unprotected t o allow dat a to be changed.

There are two methods available for protecting

and unprotecting the blocks, one for use on pro-

gramming equipment and the other for in-system

use. Block Protect and Blocks Unprotect opera-

tions are described in Appendix C.

Table 2. Bus Operations, BYTE = VIL

No te: X = VIL or VIH.

Operation E G W Address Inputs

DQ15A–1, A0-A19 Data Inputs/Outputs

DQ14-DQ8 DQ7-DQ0

Bus Read VIL VIL VIH Cell Address Hi-Z Data Output

Bus Write VIL VIH VIL Command Address Hi-Z Data Input

Output Disable X VIH VIH X Hi-Z Hi-Z

Standby VIH X X X Hi-Z Hi-Z

Read Manufacturer

Code VIL VIL VIH A0 = VIL, A1 = VIL, A9 = VID,

Others VIL or VIH Hi-Z 20h

Read Device Code VIL VIL VIH A0 = VIH, A1 = VIL, A 9 = VID,

Others VIL or VIH Hi-Z C4h (M29W160ET)

49h (M29W160EB)

M29W160ET, M29W160EB

12/40

Table 3. Bus Operations, BYTE = VIH

No te: X = VIL or VIH.

COMMAND INTERFACE

All Bus Write operations t o the me mory are in ter-

preted by the Command Interface. Commands

consist of one or more sequential Bus Write oper-

ations. Failure to observe a valid sequence of Bus

Write operations will result in the memory return-

ing to Read mode. The long command sequences

are imposed to maximize data security.

The address used for the commands changes de-

pending on whether the mem ory is in 16-bit or 8-

bit mode. See eith er Table 4, o r 5, de pendin g on

the configuration that is being used, for a summary

of the c om m ands.

Read/Rese t Command . The Read/Reset com-

mand returns the memory t o its Read m ode where

it behaves like a ROM or EPROM, unless other-

wise stated. It also reset s the errors in th e Status

can be used to is sue the Read/Reset command.

The Read/Reset Command can be issued, be-

tween Bus Write cycles before the start of a pro-

gram or erase operation, to return the device to

read mode. Onc e the program or erase operation

has started the Read/Res et comm and is no longer

accepted. The Read/Reset command will not

abort an Erase operation when issued while in

Erase Suspend.

Auto Select Command. The Auto Select com-

mand i s us ed to read the Man ufacturer C ode, t he

Device Code and the Block Protection Status.

Three consecutive Bus Write operations are re-

quired to issue the Auto Select command. Once

the Auto Select command is issued the memory

remains in Auto Select mode until a Read/Reset

command is issued. Read CFI Query and Read/

Reset commands are accepted in Auto Select

mode, all other commands are ignored .

From the Auto Select mode the Manufacturer

Code can be read using a Bus Read operation

with A 0 = VIL and A1 = VIL. The other address bits

may be set to e ither VIL or VIH. The Manufacturer

Code for STMicroelectronics is 0020h.

The Device Code can be read using a Bus Read

operation with A0 = VIH and A1 = VIL. The other

address bits ma y be set to either V IL or VIH. The

Device Code for the M29W160ET is 22C4h and

for the M29W160EB i s 2249h.

Th e Bloc k Pr ot ect i on Status of each block can be

read using a Bus Read operation with A0 = VIL,

A1 = VIH, and A 12-A1 9 s p ecifyi ng th e ad dres s of

th e block. The other address bit s may b e set t o ei-

ther VIL or VIH. I f the address ed block is pro tected

then 01h is output on Data Inputs/Outputs DQ0-

DQ7, otherwise 00h is output.

Progr a m Command. The Program command

can be used to program a value to one address in

the memory array at a time. The command re-

quires four Bus Write operations, the final write op-

eration latches the address and data, and starts

the Program/ Erase Controller.

If the address falls in a protected block then the

Program command is ignored, the data remains

unchanged. The Status Register is never read and

no error condition is giv en.

During the program operation the me mory will ig-

nore all comm ands. I t is not possible to iss ue any

command t o abort or pause the operation. Typical

program times are given in T able 6. Bus Read op-

erations during the program operation will output

the Status Register on the Data Inputs/Outputs.

See the section on the Status Register for more

details.

After the program operation has completed the

memory returns to t he Read mode, unless an error

Operation E G W Address Inputs

A0-A19 Data Inputs/Outputs

DQ15A–1, DQ14-DQ0

Bus Read VIL VIL VIH Cell Address Data Output

Bus Write VIL VIH VIL Command Address Data Input

Output Disable X VIH VIH XHi-Z

Standby VIH XXX Hi-Z

Read Manufacturer

Code VIL VIL VIH A0 = VIL, A1 = VIL, A9 = VID,

Others VIL or VIH 0020h

Read Device Code VIL VIL VIH A0 = VIH, A1 = VIL, A 9 = VID,

Others VIL or VIH 22C4h (M29W160ET)

2249h (M29W160EB)

13/40

M29W160ET, M29W160EB

has occurred. Wh en an error occurs the memory

continues to output the Status Register. A Read/

Reset comma nd must be issued to reset the error

condition and return to Read mode.

Note that t he Program command cannot change a

bit set at ’0’ back to ’1’. One of the Erase Com-

mands must be used to set all the bits in a block or

in the whole memory from ’0’ to ’1’.

Unlock Bypass Comman d. The Unlock Bypass

command is used in conjunction with the Unlock

Bypass Program c ommand to program the memo-

ry. When the access time to the device is long (as

with some EPROM programmers) considerable

time saving can be made by using these com-

mands. Three Bus Write operations are required

to issue the Unl oc k Bypass comm and.

Once the Unlock Bypass command has been is-

sued the memo ry will only accept the Unlock By-

pass Program command and the Unlock Bypass

Reset command. The memory can be read as if in

Read mode.

Unlock Bypass Program Comman d. The Un-

lock Bypass Program command can be used to

program one address in memory at a time. The

command re quires two Bus Write operations, the

final write operation latches t he address and dat a,

and starts the Program/Erase Controller.

The Program operation using the Unlock Bypass

Program c om mand behaves identicall y to the Pro-

gram operation using the Program command. A

protected block cannot be program m ed; the oper-

ation cannot be aborted and the Status Register is

read. Errors must be reset using the Read/Reset

command, w hich l eaves the de vice in Unlo ck By-

pass Mode. See the Program com mand for details

on the behavior.

Unlock Bypass Reset Comman d. The Unlock

Bypass Re se t command c an be used t o return to

Read/Reset mode from Unlock Bypass Mode.

Two Bus Write operations are required to issue the

Unlock Bypass Reset command. Read/Reset

command does not exit from Unlock Bypass

Mode.

Chip Erase Command. The Chip Erase com-

mand can be used to erase the entire chip. Six Bus

Write operations are required to issue the Chip

Erase Command and start the Program/Erase

Controller.

If any blocks are protected th en these are ignored

and all the other blocks are erased. If all of the

blo cks are p rote cted the Chip Erase o perat ion a p-

pears to start but will terminate within about 100µs,

leaving the data unchange d. No error co ndition is

given when protected blocks are ignored.

During the erase operation the memory will ignore

all commands. It is not pos sible to issue any com -

mand to abort the operation. Typical chip erase

times are given in Table 6. All Bus Read opera-

tions during the Chip Erase operation will output

the Status Register on the Data Inputs/Outputs.

See the section on the Status Register for more

details.

After the Chip Erase operation has completed t he

memory will return to the Read Mode, unless an

error has occurred. When an error occurs the

memory will continue to output the Status Regis-

ter. A Read/ Reset command must be issued to re-

set the error c ondition and return to Read Mode.

The Chip Erase Command sets all of the bits in un-

protected blocks of the memory to ’1’. All previous

data is lost.

Block Erase Command. The Block Erase com-

mand can be used to erase a list of one or more

blocks. Six Bus Write operations are required to

select the first block in the list. Each additional

block in the list can be selected by repeating the

sixth Bus Wr ite operation using the address of the

additional block. The Bloc k Erase operat ion starts

the Program/Erase Controller about 50µs af ter the

last Bus Write operation. Once the Program/Erase

Controller starts it is not possible to select any

more blocks. Each additional block must therefore

be selected within 50µs of the last block. The 50µs

timer r es tarts when an additional block is selected.

The Status Register can be read after the sixth

Bus Write operati on. See the Stat us Register sec-

tion for details on how to identify if the Program/

Erase Controller has started the Block Erase oper-

ation.

If any select ed blocks are protected then these are

ignored and all the other selected blocks are

erased. If all of the selected blocks are protected

the Block Erase operation appears to start but will

terminate within about 100µs, l eaving the data un-

changed. No error condition is given when protect-

ed blocks are ignore d.

During the Block Eras e ope ration th e me mory will

ignore all commands except the Erase Suspend

co mmand. Typical b lock e ra se tim es are g iven in

Table 6. Al l Bus Read operations during the Block

Eras e o peration will o ut p ut the S t a tus R eg i st er o n

the Data Inputs/Outputs. See the section on the

Status Regi st er for more details.

After the Block Erase operat ion has complet ed the

memory will return to the Read Mode, unless an

error has occurred. When an error occurs the

memory will continue to output the Status Regis-

ter. A Read/ Reset command must be issued to re-

set the error condition and return to Read mode.

The Block Erase Command sets all of the bits in

the unprotected selec ted blocks to ’1’. All previous

data in the selected blocks is lost.

Erase Suspend Command . The Erase Suspend

Comman d m ay be used to temporari ly s uspend a

M29W160ET, M29W160EB

14/40

Block Erase operation and return the memory to

Read mode. The command requires one Bus

Write operation.

The Prog ram/Eras e Controlle r will suspend within

the Erase Suspend Latency Time (ref er t o Table 6

for va lue) of the Era se Suspend Command being

issued. Once the Program/Erase Controller has

stopped the memory will be set to Read mode and

the Erase will be suspended. If the Erase Suspend

command is issued during the period when the

memory is waiting for an additional block (before

the Program/Erase Controller starts) then the

Erase is susp ended i mmedi ate ly and wi ll start im-

mediately when the Erase Resume Command is

issued. It is not possible to select any further

blo cks to erase a fte r the Era se Resume.

During Erase Suspend it is possible to Read and

Program cells in blocks that are not being erased;

both Read and Program operations behave as

normal on these blocks. If any attempt is made to

program in a protected bloc k or in the suspended

block then the Program command is ignored and

the data remains unchanged. The St atus Register

is not read and no error condi tion is given. Read-

ing from blocks that are being erased will output

the Status Register.

It is also possible to issue the Auto Select, Read

CFI Query and Unlock Bypass commands during

an Erase Suspend. The Read/Reset command

must be i ssued to return the devi ce to Read Array

mode before the Resume command will be ac-

cepted.

Erase Resum e Command . The Erase Resume

command must be used to restart the Program/

Erase Controller from Erase Suspend. An erase

can be suspended and resum ed more than onc e.

Read CFI Query Comman d. The Read CFI

Query Command is used to read data from the

Common Flash Interface (CFI) Memory Area. This

command is valid when the device i s in the Read

Array mod e, or wh en the dev ice is in A uto Se lect

mode.

One Bus Write cycle is required to issue the Read

CFI Query Command. Once the command is is-

sued subsequen t Bus Read ope ratio ns read from

the Common Flash Interface Memory Area .

The Read/Reset command must be issued to re-

turn the device to the previous mode (the Read Ar-

ray mode or Auto Select mode). A se cond Read/

Reset comma nd wo uld be needed if the dev ice is

to be put in the Read Array mode from Aut o Select

mode.

See Appendix B, Tables 21, 22, 23, 24, 25 and 26

for details on the information contained in the

Common Flash Interface (CF I) memory area.

15/40

M29W160ET, M29W160EB

Table 4. Co m mand s, 16-bit mode, BY TE = VIH

Note : X Don’t Care, PA Program Add ress, PD Program Data, BA Any addre ss in the Block.

All values in th e table are i n hexadec i m al .

Th e Com ma nd In terf ace o nly us es A –1, A0-A 10 a nd DQ 0-DQ7 t o ver ify t he comm an ds; A1 1-A1 9, DQ8- DQ1 4 a nd DQ 15 ar e Don’t

Care. DQ15A–1 is A–1 when B Y T E is VIL or DQ15 when BYTE is VIH.

Read/Reset. Aft er a Read/Rese t c om m and, read the mem ory as normal un til another comm and i s issued.

Auto Selec t. Af ter an Au to S elect c om mand, read Manu facturer ID, De vice ID or Block Prot ection S tatus.

Pro gram, Unl ock By pass Progra m, Ch ip E rase, Blo ck Eras e . Afte r thes e com man ds rea d t he Stat us Reg ist er unt il the Prog ram/

Erase Controller completes and the memory returns to Read Mode. Add additional Blocks during Block Erase Command with additional

Bus Write Operations until T i m eout Bit is set.

Unlo ck By p as s. After th e Unlock Bypas s co mmand i ssue Unlock Bypass Program or Unl ock Bypass Re set comm ands.

Unlo ck By p as s Re set. After the Unlock Bypass Reset command read the memory as normal until another command is issued.

Erase Suspend. After the Erase Suspend command read non-erasing memory blocks as normal, issue Auto Select and Program com-

ma nds on non-erasing blocks as nor m al .

Erase Resume. Aft er t he Eras e Resum e comm and the susp ended Erase o peration resum es, re ad the Status Register unt i l th e Pro-

gram/E rase Cont ro l l er com pl ete s an d t h e m em ory returns to Re ad Mo de.

CFI Qu e r y. Com m and i s vali d when devi ce is ready to rea d array dat a or when device i s i n A uto Select mode.

Command

Length

Bus Write Operations

1st 2nd 3rd 4th 5th 6th

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Read/Reset 1X F0

3555 AA 2AA 55 X F0

Auto Select 3 555 AA 2AA 55 555 90

Program 4 555 AA 2AA 55 555 A0 PA PD

Unlock Bypass 3 555 AA 2AA 55 555 20

Unlock Bypass

Program 2X A0PAPD

Unlock Bypass Reset 2 X 90 X 00

Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2 AA 55 555 10

Block Erase 6+ 555 AA 2AA 55 555 80 555 AA 2AA 55 BA 30

Erase Suspend 1 X B0

Erase Resume 1 X 30

Read CFI Query 1 55 98

M29W160ET, M29W160EB

16/40

Table 5. Commands, 8-bit mode, BYTE = V IL

Note : X Don’t Care, PA Program Add ress, PD Program Data, BA Any addre ss in the Block.

All values in th e table are i n hexadec i m al .

Th e Com ma nd In terf ace o nly us es A –1, A0-A 10 a nd DQ 0-DQ7 t o ver ify t he comm an ds; A1 1-A1 9, DQ8- DQ1 4 a nd DQ 15 ar e Don’t

Care. DQ15A–1 is A–1 when B Y T E is VIL or DQ15 when BYTE is VIH.

Read/Reset. Aft er a Read/Rese t c om m and, read the mem ory as normal un til another comm and i s issued.

Auto Selec t. Af ter an Au to S elect c om mand, read Manu facturer ID, De vice ID or Block Prot ection S tatus.

Pro gram, Unl ock By pass Progra m, Ch ip E rase, Blo ck Eras e . Afte r thes e com man ds rea d t he Stat us Reg ist er unt il the Prog ram/

Erase Controller completes and the memory returns to Read Mode. Add additional Blocks during Block Erase Command with additional

Bus Write Operations until T i m eout Bit is set.

Unlo ck Bypass. After the Unlock Bypass comm and issue Unloc k Bypass Program or Unlo ck By pass Reset com m ands.

Unlo ck Bypass Re set. After the Unlock Bypass Reset command read the memory as normal until another command is issued.

Erase Suspend. After the Erase Suspend command read non-erasing memory blocks as normal, issue Auto Select and Program com-

ma nds on non-erasing blocks as nor m al .

Erase Resume. Aft er t he Eras e Resum e comm and the susp ended Erase o peration resum es, re ad the Status Register unt i l th e Pro-

gram/E rase Cont ro l l er com pl ete s an d t h e m em ory returns to Re ad Mo de.

CFI Qu e r y. Com m and i s vali d when devi ce is ready to rea d array dat a or when device i s i n A uto Select mode.

Command

Length

Bus Write Operations

1st 2nd 3rd 4th 5th 6th

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Read/Reset 1X F0

3 AAA AA 555 55 X F0

Auto Select 3 AAA AA 555 55 AAA 90

Program 4 AAA AA 555 55 AAA A0 PA PD

Unlock Bypass 3 AAA AA 555 55 AAA 20

Unlock Bypass

Program 2X A0PAPD

Unlock Bypass Reset 2 X 90 X 00

Chip Erase 6 AAA AA 555 55 AAA 80 AAA AA 555 55 AAA 10

Block Erase 6+ AAA AA 555 55 AAA 80 AAA AA 555 55 BA 30

Erase Suspend 1 X B0

Erase Resume 1 X 30

Read CFI Query 1 AA 98

17/40

M29W160ET, M29W160EB

Table 6. Progra m, Erase Tim es and Progra m , Erase Endu ran ce Cycle s

Note: 1. Typ i cal values m easured at room t em perature and nominal voltages.

2. Sam ple d, but no t 100% tes ted.

3. Max imum valu e m easured at worst cas e condi tions for both temperatu re and VCC after 100,000 program/erase cycles .

4. Max imum valu e m easured at worst cas e condi tions for both temperatu re and VCC.

STATUS REGIST ER

Bus Read operations from any address always

read the Status Register during Program and

Erase operations. It is al so read during Erase Sus-

pend when an address within a block being erased

is acce sse d.

The bits in the Stat us Regist er are sum marized in

Table 7, Status Regist er Bits.

Data Pollin g Bit (DQ7). The Data Polling Bit can

be used to identify whether the Program/Erase

Controller has successfully completed its opera-

tion or if it has responded to an Erase Suspend.

The Data Polling Bit is output on DQ7 when the

Status Register is re ad.

During Program operations the Data Polling Bit

outputs the complement of the bit being pro-

grammed to DQ7. After successful completion of

the Program operation the memory returns to

Read mode and Bus Read oper ations from t he ad-

dress just programmed output DQ7, not its com-

plement.

During Erase ope rations the Data Po lling Bi t out-

puts ’0’, the complement of the erased state of

DQ7. Aft er suc cessful completi on of the Erase op-

eration the memory returns to Read Mode.

In Erase Suspend mode the Data Polling Bit will

output a ’1’ during a Bus Read operation within a

block being erased. The Data Polling Bit will

change f rom a ’0’ to a ’1’ when the Program/Erase

Controller has suspended the Erase operation.

Figure 7, Data Polling Flowcha rt, gives an exam-

ple of how to use the Data Polling B it. A Valid Ad-

dress is the address being programmed or an

address within the block being erased.

Toggle Bit (DQ6). The Toggle Bit can be used to

identify whether the Program/Er as e Controll er has

successfully compl eted its operation or if it has re-

sponded to an Erase Suspend. The Toggle Bit is

output on DQ6 when the Status Register is read.

During Program and Erase operations the Toggle

Bit changes f rom ’0 ’ to ’ 1’ to ’ 0’, et c., with succes-

sive Bus Read operations at any address. After

successful completion of the operation the memo-

ry returns to Read mode.

During Erase Suspend mode the Toggle Bit will

output when addressing a cel l within a block being

erased. The Toggle Bit will stop toggli ng when the

Program/Erase Controller has suspended the

Erase operation.

If any attempt is ma de to erase a prote cted bl ock,

the o peration is aborted, no error i s s ig nalled and

DQ6 toggles for approximately 100µs. If any at-

tempt is made to program a protected block or a

suspended b lock, the operation is abort ed, no er-

ror is signalled and DQ6 toggles for approximately

1µs.

Figure 8 , Data Toggle Flowchart, g ives an e xam-

ple of how to u se the Data Toggle Bit.

Error Bi t (DQ5). The Error Bit can be used to

identify errors detected by the Program/Erase

Controller. The Erro r Bit is set to ’1’ when a Pro-

gram, Block Erase or Chip Erase operation fails to

write the correct data to the memory. If the Error

Bit is set a Rea d/Re se t comm and must be issued

before other commands are issued. The Error bit

is output on DQ5 when the Status Register is read.

Parameter Min Typ (1,2) Max(2) Unit

Chip Erase 29 120 (3) s

Block Erase (64 KBytes) 0.8 6 (4) s

Erase Suspend Latency Time 20 25 (4) µs

Program (Byte or Word) 13 200 (3) µs

Chip Program (Byte by Byte) 26 120 (3) s

Chip Program (Word by Word) 13 60 (3) s

Program/Erase Cycles (per Block) 100,000 cycles

Data Retention 20 years

M29W160ET, M29W160EB

18/40

Note that t he Program command cannot change a

bit set to ’ 0’ back to ’1’ and attempting to do so will

set DQ5 to ‘1’. A Bus Read operation to that ad-

dres s w ill s h ow th e b it is s ti ll ‘0’. On e of the Eras e

commands must be used to set all the bits in a

block or in the whole memory from ’0’ to ’1’

Erase Timer Bit (DQ3). The Erase Timer Bit can

be used to identify the start of Program/Erase

Controller operation during a Block Erase com-

mand. Once the Program/Erase Controller starts

erasing the Erase Ti mer Bit is set to ’1’. Before the

Program/Erase Controller starts the Erase Timer

Bit is set to ’0’ and add itional blocks to be erased

may be written to the Command Interface. The

Erase Timer Bit is output on DQ3 when the Status

Alternative T og gle Bit (DQ2). The Alternative

Toggle Bit can be used to monitor the Program/

Erase controller during Erase operations. The Al-

ternative Toggle Bit is output on DQ2 when the

Status Register is re ad.

During Chip Erase and Block Erase operations the

Toggle Bit changes fro m ’0’ to ’1’ to ’0’, etc., with

successive Bus Re ad operations from addresses

within the blocks being erased. A protected block

is treated the same as a block not being erased.

Once t he operation completes the memory returns

to Read mode.

During Erase Suspend the Alternative Toggle Bit

changes from ’0’ to ’1’ to ’0’, etc. with successive

Bus Read operations from addresses within the

blocks being erased. Bus Read operations to ad-

dresses within blocks not bei ng erased wi ll ou tput

the memory cell data as i f in Read mode.

After an Erase operation that caus es t he Error Bit

to be set the Alternative Toggle Bit can be used to

identify which block or blocks have caused the er-

ror. The Altern ative Toggle Bit changes from ’0’ to

’1’ to ’0’, etc. with successive Bus Read Opera-

tions from addresses within blocks that have not

erased correctly. The Alte rnative Toggle Bit does

not change if the addressed block has erased cor-

rectly.

Table 7. Statu s Register Bits

Note: Unspecified data bits sh ould be ignored.

Operation Address DQ7 DQ6 DQ5 DQ3 DQ2 RB

Program Any Address DQ7 Toggle 0 – – 0

Program During Erase

Suspend Any Address DQ7 Toggle 0 – – 0

Program Error Any Address DQ7 Toggle 1 – – 0

Chip Erase Any Address 0 Toggle 0 1 Toggle 0

Block Erase before

timeout Erasing Block 0 Toggle 0 0 Toggle 0

Non-Erasing Block 0 Toggle 0 0 No Toggle 0

Block Erase Erasing Block 0 Toggle 0 1 Toggle 0

Non-Erasing Block 0 Toggle 0 1 No Toggle 0

Erase Suspend Erasing Block 1 No Toggle 0 – Toggle 1

Non-Erasing Block Data read as normal 1

Erase Error Good Block Address 0 Toggle 1 1 No Toggle 0

Faulty Block Address 0 Toggle 1 1 Toggle 0

19/40

M29W160ET, M29W160EB

Figu re 7. Da ta Po lling Flo wc h a rt Fi gure 8. Dat a Toggle Fl owchar t

MAX I MUM RA T I N G

Stressing the device ab ove t he rating listed in t he

Absolute Maximum Ratings" table may cause per-

manent damag e to the dev ice. Exposure to Abso-

lute Maximum Rating conditions for extended

periods may affect device reliability. These are

stress ratings only and operation of the device at

these or any other conditions above those indicat-

ed in the Operating sections of this specification is

not implied. Refer also to the STMicroelectronics

SURE Program and other relevant quality docu-

ments.

Table 8. Absolute Maximum Ratings

Note: 1. Mini m um voltage m ay undershoo t t o –2V during t ransition and for less t han 20ns dur i ng trans i tions.

2. Max imum voltage may overshoot to V CC +2V during trans i t i on and for less tha n 20ns during trans i t io ns.

READ DQ5 & DQ7

at VALID ADDRESS

START

READ DQ7

at VALID ADDRESS

FAIL PASS

AI03598

DQ7

DATA YES

YES

DQ5

= 1

DQ7

DATA YES

READ DQ6

START

READ DQ6

TWICE

FAIL PASS

AI01370C

DQ6

TOGGLE NO

YES

DQ5

= 1

YES

DQ6

TOGGLE

READ

DQ5 & DQ6

Symbol Parameter Min Max Unit

TBIAS Temperature Under Bias –50 125 °C

TSTG Storage Temperature –65 150 °C

VIO Input or Output Voltage (1,2) –0.6 VCC +0.6 V

VCC Supply Voltage –0.6 4 V

VID Identification Voltage –0.6 13.5 V

M29W160ET, M29W160EB

20/40

DC AND AC PARAMETERS

This section summarizes the operating measure-

ment cond iti ons, and the DC and AC characteris-

tics of the device. The p arameters in the D C and

AC characteristics Tables that fo llow, are derived

from tests performed under the Measurement

Conditions sum marized in Table 9, Operating and

AC Measurement Conditions. Designers should

check t hat the operating cond itions in their circuit

match the operating conditions when relying on

the quot ed parameters.

Table 9. Operating and AC Measurem en t Conditions

Figure 9. AC Measurement I/O Wavefo rm Figure 10. AC Measure ment Lo ad Circuit

Table 10. Device Capacitance

Note: Sampled only, no t 100% test ed.

Parameter

M29W160E

Unit70 90

Min Max Min Max

VCC Supply Voltage 2.7 3.6 2.7 3.6 V

Ambient Operati ng Temperatur e –40 85 –40 85 °C

Load Capacitance (CL)30 30 pF

Input Rise and Fall Times 10 10 ns

Input Pulse Voltages 0 to VCC 0 to VCC V

Input and Output Timing Ref. Voltages VCC/2 VCC/2 V

AI04498

VCC

VCC/2

AI04499

CL includes JIG capacitance

DEVICE

UNDER

TEST

25kΩ

VCC

25kΩ

VCC

0.1µF

Symbol Parameter Test Condition Min Max Unit

CIN Input Capacitance VIN = 0V 6pF

COUT Output Capacitance VOUT = 0V 12 pF

21/40

M29W160ET, M29W160EB

Table 11. DC Characteristics

Note: 1. Sampled only, not 100% tested.

Symbol Parameter Test Condition Min Typ Max Unit

ILI Input Leakage Current 0V ≤ VIN ≤ VCC ±1 µA

ILO Output Leak age Curren t 0V ≤ VOUT ≤ VCC ±1 µA

ICC1 Supply Curre nt (Read) E = VIL, G = VIH,

f = 6MHz 4.5 10 mA

ICC2 Supply Curre nt (Standby) E = VCC ±0.2V,

RP = VCC ±0.2V 35 100 µA

ICC3 (1) Su pply Curre nt

(Program/Erase) Program/Erase

Controller active 20 mA

VIL Input Low Voltage –0.5 0.8 V

VIH Input High Voltage 0.7VCC VCC +0.3 V

VOL Output Low Vo ltage IOL = 1.8mA 0.45 V

VOH Output High Voltage IOH = –100µAVCC –0.4 V

VID Identification Voltage 11.5 12.5 V

IID Identification Current A9 = VID 100 µA

VLKO Program/Erase Lockout

Supply Voltage 1.8 2.3 V

M29W160ET, M29W160EB

22/40

Figure 11. Read Mode AC Waveforms

Table 12. Read AC Characteristics

Note: 1. Sampled only, not 100% tested.

Symbol Alt Parameter Test Condition M29W160E Unit

70 90

tAVAV tRC Address Valid to Next Address Valid E = VIL,

G = VIL Min 70 90 ns

tAVQV tACC Address Valid to Output Valid E = VIL,

G = VIL Max 70 90 ns

tELQX (1) tLZ Chip Enable Low to Output Transition G = VIL Min 0 0 ns

tELQV tCE Chip Enable Low to Output Valid G = VIL Max 70 90 ns

tGLQX (1) tOLZ Output Enable Low to Output Transition E = VIL Min 0 0 ns

tGLQV tOE Output Enable Low to Output Valid E = VIL Max 30 35 ns

tEHQZ (1) tHZ Chip Enable High to Output Hi-Z G = VIL Max 25 30 ns

tGHQZ (1) tDF Output Enab le High to Output Hi-Z E = VIL Max 25 30 ns

tEHQX

tGHQX

tAXQX tOH Chip Enable, Output Enable or Address

Transition to Output Transition Min 0 0 ns

tELBL

tELBH tELFL

tELFH Chip Enable to BYTE Low or High Max 5 5 ns

tBLQZ tFLQZ BYTE Low to Output Hi-Z Max 25 30 ns

tBHQV tFHQV BYTE High to Output Valid Max 30 40 ns

AI02922

tAVAV

tAVQV tAXQX

tELQX tEHQZ

tGLQV

tGLQX tGHQX

VALID

A0-A19/

A–1

DQ0-DQ7/

DQ8-DQ15

tELQV tEHQX

tGHQZ

VALID

tBHQV

tELBL/tELBH tBLQZ

BYTE

23/40

M29W160ET, M29W160EB

Figure 12. Write AC Waveform s, Write Enable Controlle d

Table 13. Write AC Characteristics, Write Enable Controlle d

Note: 1. Sampled only, not 100% tested.

Symbol Alt Parameter M29W160E Unit

70 90

tAVAV tWC Address Valid to Next Address V alid Min 70 90 ns

tELWL tCS Chip Enable Low to Write Enable Low Min 0 0 ns

tWLWH tWP Write Enable Low to Write Enable High Min 45 50 ns

tDVWH tDS Input Valid to Write Enable High Min 45 50 ns

tWHDX tDH Write Enable High to Input Transition Min 0 0 ns

tWHEH tCH Write Enable High to Chip Enable High Min 0 0 ns

tWHWL tWPH Write Enable High to Write Enable Low Min 30 30 ns

tAVWL tAS Address Valid to Write Enable Low Min 0 0 ns

tWLAX tAH Write Enable Low to Address Transition Min 45 50 ns

tGHWL Output Enable High to Write Enable Low Min 0 0 ns

tWHGL tOEH Write Enable High to Output Enable Low Min 0 0 ns

tWHRL (1) tBUSY Program/Erase Valid to RB Low Max 30 35 ns

tVCHEL tVCS VCC High to Chip Enable Low Min 50 50 µs

AI02923

A0-A19/

A–1

DQ0-DQ7/

DQ8-DQ15

VALID

VCC

tVCHEL

tWHEH

tWHWL

tELWL

tAVWL

tWHGL

tWLAX

tWHDX

tAVAV

tDVWH

tWLWHtGHWL

tWHRL

M29W160ET, M29W160EB

24/40

Figure 13. Write AC Waveforms, Chip Enable Control led

Table 14. Write AC Characteristics, Chip Enable Controlled

Note: 1. Sampled only, not 100% tested.

Symbol Alt Parameter M29W160E Unit

70 90

tAVAV tWC Address Valid to Next Address V alid Min 70 90 ns

tWLEL tWS Write Enable Low to Chip Enable Low Min 0 0 ns

tELEH tCP Chip Enable Low to Chip Enable High Min 45 50 ns

tDVEH tDS Input Valid to Chip Enable High Min 45 50 ns

tEHDX tDH Chip Enable High to Input Transition Min 0 0 ns

tEHWH tWH Chip Enable High to Write Enable High Min 0 0 ns

tEHEL tCPH Chip Enab le High to Chip Enable Low Min 30 30 ns

tAVEL tAS Address Valid to Chip Enable Low Min 0 0 ns

tELAX tAH Chip Enable Low to Address Transition Min 45 50 ns

tGHEL Output Enable High Chip Enable Low Min 0 0 ns

tEHGL tOEH Chip Enable High to Output Enable Low Min 0 0 ns

tEHRL (1) tBUSY Program/Erase Valid to RB Low Max 30 35 ns

tVCHWL tVCS VCC High to Write Enable Low Min 50 50 µs

AI02924

A0-A19/

A–1

DQ0-DQ7/

DQ8-DQ15

VALID

VCC

tVCHWL

tEHWH

tEHEL

tWLEL

tAVEL

tEHGL

tELAX

tEHDX

tAVAV

tDVEH

tELEHtGHEL

tEHRL

25/40

M29W160ET, M29W160EB

Figure 14. Reset/Block Tem porary Unp rotec t AC Waveforms

Table 15. Reset/Block Temporary Unprotect AC Characteristics

Note: 1. Sampled only, not 100% tested.

Symbol Alt Parameter M29W160E Unit

70 90

tPHWL (1)

tPHEL

tPHGL (1) tRH RP High to Write Enable Low, Chip Enable Low,

Output Enable Low Min 50 50 ns

tRHWL (1)

tRHEL (1)

tRHGL (1) tRB RB High to Write Enable Low, Chip Enable Low,

Output Enable Low Min 0 0 ns

tPLPX tRP RP Pulse Width Min 500 500 ns

tPLYH (1) tREADY RP Low to Read Mode Max 10 10 µs

tPHPHH (1) tVIDR RP Rise Time to VID Min 500 500 ns

AI02931B

RP tPLPX

tPHWL, tPHEL, tPHGL

tPLYH

tPHPHH

E, G

tRHWL, tRHEL, tRHGL

M29W160ET, M29W160EB

26/40

PACKAGE MECHANICAL

Figure 15. TS O P4 8 – 48 lead Plastic Thin Small Outline, 12 x 20mm, Pa ckage Outline

No te : Drawing is not to scal e.

Table 16. TSOP48 – 48 lead Plastic Thin Sma ll Outline, 12 x 20mm, Packag e Me chanica l Data

Symbol millimeters inches

Typ Min Max Typ Min Max

A 1.200 0.0472

A1 0.100 0.050 0.150 0.0039 0.0020 0.0059

A2 1.000 0.950 1.050 0.0394 0.0374 0.0413

B 0.220 0.170 0.270 0.0087 0.0067 0.0106

C 0.100 0.210 0.0039 0.0083

CP 0.080 0.0031

D1 12.000 11.900 12.100 0.4724 0.4685 0.4764

E 20.000 19.800 20.200 0.7874 0.7795 0.7953

E1 18.400 18.300 18.500 0.7244 0.7205 0.7283

e 0.500 – – 0.0197 – –

L 0.600 0.500 0.700 0.0236 0.0197 0.0276

L1 0.800 0.0315

α305305

TSOP-G

DIE

LA1 α

27/40

M29W160ET, M29W160EB

Figure 16. TFBGA48 6x8mm - 6x8 ball array, 0.80 mm pitch, Package Outline

Table 17. TFBGA48 6x8mm - 6x8 ball array, 0.80 mm pitch, Package Mech anical Data

Symbol millimeters inches

Typ Min Max Typ Min Max

A 1.200 0.0472

A1 0.260 0.0102

A2 0.900 0.0354

b 0.350 0.450 0.0138 0.0177

D 6.000 5.900 6.100 0.2362 0.2323 0.2402

D1 4.000 – – 0.1575 – –

ddd 0.100 0.0039

E 8.000 7.900 8.100 0.3150 0.3110 0.3189

E1 5.600 – – 0.2205 – –

e 0.800 – – 0.0315 – –

FD 1.000 – – 0.0394 – –

FE 1.200 – – 0.0472 – –

SD 0.400 – – 0.0157 – –

SE 0.400 – – 0.0157 – –

E1E

BGA-Z32

ddd

FE SD

BALL "A1"

M29W160ET, M29W160EB

28/40

PART NUMBERING

Table 18. Ordering Information Scheme

Devices are shipped from the factory wit h the memory cont ent bits erased to ’1’.

For a list of available opt ions (Speed, Package, etc.) or for further information on any aspect of this device,

please contact the ST Sales Office nearest to you.

Example: M29W160EB 90 N 6 T

Device Type

M29

Operating Voltage

W = VCC = 2.7 to 3.6V

Device Function

160E = 16 Mbit (x8/x16), Boot Block

Array Matrix

T = Top Boot

B = Bottom Boot

Speed

70 = 70 ns

90 = 90 ns

Package

N = TSOP48: 12 x 20 mm

ZA = TFBGA48: 6x8 mm, 0.80mm pitch

Temperature Range

6 = –40 to 85 °C

Option

Blank = Standard Packing

T = Tape and Reel Packing

E = Lead-free Package, Standard Packing

F = Lead-free Package, Tape & Reel Packing

29/40

M29W160ET, M29W160EB

APPENDIX A. BLOCK ADDRESS TABLE

Table 19. Top Boot Blo ck Add resse s,

M29W160ET T able 20. Botto m Boot Bloc k Addresses,

M29W160EB

#Size

(KBytes) Add ress R ange

(x8) Ad dress Range

(x16)

34 16 1FC000h-1FFFFFh FE000h-FFFFFh

33 8 1FA000h-1FBFFFh FD000h-FDFFFh

32 8 1F8000h-1F9FFFh FC000h-FCFFFh

31 32 1F0000h-1F7FFFh F8000h-FBFFFh

30 64 1E0000h-1EFFFFh F0000h-F7FFFh

29 64 1D0000h-1DFFFFh E8000h-EFFFFh

28 64 1C0000h-1CFFFFh E0000h-E7FFFh

27 64 1B0000h-1BFFFFh D8000h-DFFFFh

26 64 1A0000h-1AFFFFh D0000h-D7FFFh

25 64 190000h-19FFFFh C8000h-CFFFFh

24 64 180000h-18FFFFh C0000h-C7FFFh

23 64 170000h-17FFFFh B8000h-BFFFFh

22 64 160000h-16FFFFh B0000h-B7FFFh

21 64 150000h-15FFFFh A8000h-AFFFFh

20 64 140000h-14FFFFh A0000h-A7FFFh

19 64 130000h-13FFFFh 98000h-9FFFFh

18 64 120000h-12FFFFh 90000h-97FFFh

17 64 110000h-11FFFFh 88000h-8FFFFh

16 64 100000h-10FFFFh 80000h-87FFFh

15 64 0F0000h-0FFFFFh 78000h-7FFFFh

14 64 0E0000h-0EFFFFh 70000h-77FFFh

13 64 0D0000h-0DFFFFh 68000h-6FFFFh

12 64 0C0000h-0CFFFFh 60000h-67FFFh

11 64 0B0000h-0BFFFFh 58000h-5FFFFh

10 64 0A0000h-0AFFFFh 50000h-57FFFh

9 64 090000h-09FFFFh 48000h-4FFFFh

8 64 080000h-08FFFFh 40000h-47FFFh

7 64 070000h-07FFFFh 38000h-3FFFFh

6 64 060000h-06FFFFh 30000h-37FFFh

5 64 050000h-05FFFFh 28000h-2FFFFh

4 64 040000h-04FFFFh 20000h-27FFFh

3 64 030000h-03FFFFh 18000h-1FFFFh

2 64 020000h-02FFFFh 10000h-17FFFh

1 64 010000h-01FFFFh 08000h-0FFFFh

0 64 000000h-00FFFFh 00000h-07FFFh

#Size

(KBytes) Address Range

(x8) Add ress Rang e

(x16)

34 64 1F0000h-1FFFFFh F8000h-FFFFFh

33 64 1E0000h-1EFFFFh F0000h-F7FFFh

32 64 1D0000h-1DFFFFh E8000h-EFFFFh

31 64 1C0000h-1CFFFFh E0000h-E7FFFh

30 64 1B0000h-1BFFFFh D8000h-DFFFFh

29 64 1A0000h-1AFFFFh D0000h-D7FFFh

28 64 190000h-19FFFFh C8000h-CFFFFh

27 64 180000h-18FFFFh C0000h-C7FFFh

26 64 170000h-17FFFFh B8000h-BFFFFh

25 64 160000h-16FFFFh B0000h-B7FFFh

24 64 150000h-15FFFFh A8000h-AFFFFh

23 64 140000h-14FFFFh A0000h-A7FFFh

22 64 130000h-13FFFFh 98000h-9FFFFh

21 64 120000h-12FFFFh 90000h-97FFFh

20 64 110000h-11FFFFh 88000h-8FFFFh

19 64 100000h-10FFFFh 80000h-87FFFh

18 64 0F0000h-0FFFFFh 78000h-7FFFFh

17 64 0E0000h-0EFFFFh 70000h-77FFFh

16 64 0D0000h-0DFFFFh 68000h-6FFFFh

15 64 0C0000h-0CFFFFh 60000h-67FFFh

14 64 0B0000h-0BFFFFh 58000h-5FFFFh

13 64 0A0000h-0AFFFFh 50000h-57FFFh

12 64 090000h-09FFFFh 48000h-4FFFFh

11 64 080000h-08FFFFh 40000h-47FFFh

10 64 070000h-07FFFFh 38000h-3FFFFh

9 64 060000h-06FFFFh 30000h-37FFFh

8 64 050000h-05FFFFh 28000h-2FFFFh

7 64 040000h-04FFFFh 20000h-27FFFh

6 64 030000h-03FFFFh 18000h-1FFFFh

5 64 020000h-02FFFFh 10000h-17FFFh

4 64 010000h-01FFFFh 08000h-0FFFFh

3 32 008000h-00FFFFh 04000h-07FFFh

2 8 006000h-007FFFh 03000h-03FFFh

1 8 004000h-005FFFh 02000h-02FFFh

0 16 000000h-003FFFh 00000h-01FFFh

M29W160ET, M29W160EB

30/40

APPENDIX B. COMMON FLASH INTERFACE (CFI)

The Common Flash Interface is a JEDEC ap-

proved, standardized data structure that can be

read from the Flash memory device. It allows a

system sof tware to query the devi c e to determine

various electrical and timing parameters, density

information and functions su pported by the mem-

ory. The system can interface easily with the de-

vice, enabling th e software to upgrade itself when

necessary.

When the CFI Query Command is issued the de-

vice enters CFI Query mode and the data structure

is read from the memory. Tables 21, 22, 23, 24, 25

and 26 show the addresses used to retrieve the

data.

The CFI data structure also contains a security

area where a 64 bi t unique security number is writ-

ten (see Table 26, Security Code area). This area

can be accessed only in Read mode by the final

user. It is imposs ible to change t he secu ri ty num-

ber after it ha s been written by ST. Issue a Read

command to return to Read mode.

Note: The Common Flash In terface is onl y avail-

able for Temperature range 6 (–40 to 85° C).

Table 21. Query Structure Overview

N ote: Que ry dat a ar e always pr esent ed on t h e l owes t or der dat a outpu t s.

Table 22. CFI Query Identification String

Note: Query data are always presented on the lowest order data outputs (DQ7-DQ0) only. DQ8-DQ15 are ‘0’.

Address Sub-section Name Description

x16 x8

10h 20h CFI Query Identification String Command set ID and algorithm data offset

1Bh 36h System Interface Information Device timing & voltage information

27h 4Eh Device Geometry Definition Flash device layout

40h 80h Primary Algorithm-specific Extended

Query table Additional information specific to the Primary

Algorithm (optional)

61h C2h Security Code Area 64 bit unique device number

Address Data Description Value

x16 x8

10h 20h 0051h "Q"

11h 22h 0052h Query Unique ASCII String "QRY" "R"

12h 24h 0059h "Y"

13h 26h 0002h Primary Algorithm Command Set and Control Interface ID code 16 bit

ID code defining a specific algori thm AMD

Compatible

14h 28h 0000h

15h 2Ah 0040h Address for Primary Algorithm extended Query table (see Table 24) P = 40h

16h 2Ch 0000h

17h 2Eh 0000h Alternate Vendor Command Set and Control Interface ID Code second

vendor - specified algorithm supported NA

18h 30h 0000h

19h 32h 0000h Address for Alternate Algorithm extended Query table NA

1Ah 34h 0000h

31/40

M29W160ET, M29W160EB

Table 23. CFI Query System In terface Information

Address Data Description Value

x16 x8

1Bh 36h 0027h VCC Logic Supply Minimum Program/Erase voltage

bit 7 to 4BCD value in volts

bit 3 to 0BCD value in 100 mV 2.7V

1Ch 38h 0036h VCC Logic Supply Maximum Program/Erase voltage

bit 7 to 4BCD value in volts

bit 3 to 0BCD value in 100 mV 3.6V

1Dh 3Ah 0000h VPP [Programming] Supply Minimum Program/Erase voltage NA

1Eh 3Ch 0000h VPP [Programming] Supply Maximum Program/Erase voltage NA

1Fh 3Eh 0004h Typical timeout per single Byte/Word program = 2n µs 16µs

20h 40h 0000h Typical timeout for minimum size write buffer program = 2n µs NA

21h 42h 000Ah Typical timeout per individual block erase = 2n ms 1s

22h 44h 0000h Typical timeout for full chip erase = 2n ms NA

23h 46h 0004h Maximum timeout for Byte/Word program = 2n times typical 256µs

24h 48h 0000h Maximum timeout for write buffer program = 2n times typical NA

25h 4Ah 0003h Maximum timeout per individual block erase = 2n times typical 8s

26h 4Ch 0000h Maximum timeout for chip erase = 2n times typical NA

M29W160ET, M29W160EB

32/40

Table 24. Device Geometry Definition

Address Data Description Value

x16 x8

27h 4Eh 0015h Device Size = 2n in number of Bytes 2 MByte

28h

29h 50h

52h 0002h

0000h Flash Device Interface Code description x8, x16

Async.

2Ah

2Bh 54h

56h 0000h

0000h Maximum number of Bytes in multi-Byte program or page = 2n NA

2Ch 58h 0004h Number of Erase Block Regions within the device.

It specifies the number of regions within the device containing

contiguous Erase Blocks of the same size. 4

2Dh

2Eh 5Ah

5Ch 0000h

0000h Region 1 Information

Number of identical size erase block = 0000h+1 1

2Fh

30h 5Eh

60h 0040h

0000h Region 1 Information

Block size in Region 1 = 0040h * 256 Byte 16 KByte

31h

32h 62h

64h 0001h

0000h Region 2 Information

Number of identical size erase block = 0001h+1 2

33h

34h 66h

68h 0020h

0000h Region 2 Information

Block size in Region 2 = 0020h * 256 Byte 8 KByte

35h

36h 6Ah

6Ch 0000h

0000h Region 3 Information

Number of identical size erase block = 0000h+1 1

37h

38h 6Eh

70h 0080h

0000h Region 3 Information

Block size in Region 3 = 0080h * 256 Byte 32 KByte

39h

3Ah 72h

74h 001Eh

0000h Region 4 Information

Number of identical-size erase block = 001Eh+1 31

3Bh

3Ch 76h

78h 0000h

0001h Region 4 Information

Block size in Region 4 = 0100h * 256 Byte 64 KByte

33/40

M29W160ET, M29W160EB

Table 25. Primary Algorithm- Speci fic Extended Qu ery Ta ble

Table 26. Security Code Area

Address Data Description Value

x16 x8

40h 80h 0050h

Primary Algorithm extended Query table unique ASCII string “PRI”

"P"

41h 82h 0052h "R"

42h 84h 0049h "I"

43h 86h 0031h Major version number, ASCII "1"

44h 88h 0030h Minor version number, ASCII "0"

45h 8Ah 0000h Address Sensitive Unlock (bits 1 to 0)

00 = required, 01= not required

Silicon Revision Number (bits 7 to 2)

Yes

46h 8Ch 0002h Erase Suspend

00 = not supported, 01 = Read only, 02 = Read and Write 2

47h 8Eh 0001h Block Protection

00 = not supported, x = number of blocks in per group 1

48h 90h 0001h Temporary Block Unprotect

00 = not supported, 01 = supported Yes

49h 92h 0004h Block Protect /Unprotect

04 = M29W400B 4

4Ah 94h 0000h Simultaneous Operations, 00 = not supported No

4Bh 96h 0000h Burst Mode, 00 = not supported, 01 = supported No

4Ch 98h 0000h Page Mode, 00 = not supported, 01 = 4 page Word, 02 = 8 page Word No

Address Data Description

x16 x8

61h C3h, C2h XXXX

64 bit: unique device number

62h C5h, C4h XXXX

63h C7h, C6h XXXX

64h C9h, C8h XXXX

M29W160ET, M29W160EB

34/40

APPENDIX C. BLOCK PRO TECTION

Block protection can be used to prevent any oper-

ation from modifying the data stored in the Flash

memory. Eac h Block can be protected individually.

Once protected, Program and Erase operations

on the block fail to c hange the data .

There are three techniques that can be used to

control Block Protection, these are the Program-

mer technique, the In- System technique and Tem-

porary Unprotection. Temporary Unprotection is

controlled by the Reset/Block Temporary Unpro-

tection pin, RP; this is des cribed in the S ign al De-

scriptions section.

Unlike the Command Interface of the Program/

Erase Controller, t he techniques for protec ting and

unprotecting blocks could change betwe en differ-

ent Flash memory suppli ers.

Programme r Technique

The Programmer technique uses high (VID) volt-

age levels on some of the bus pins. These cannot

be achieved using a standard microprocessor bus,

therefore the technique is recommended only for

use in Programming Equipment.

To protect a block follow the flowc hart in Figure 17,

Programmer Equipment Block Protect Flowchart.

During the Block Protect algorithm, the A19-A12

Address Inputs indicate the address of the block to

be protected. The block wil l be correctly pr otected

only if A19-A12 remain valid and stable, and if

Chip Enable is kept Low, VIL, all along t he Protect

and Verify phases.

The Chip Unpr otect algorithm is used to unprotect

all the memory bl oc ks at the same time. Thi s algo-

rithm can only be used if all of t he bl ocks are pro-

tected first. T o unprotect the c hip follow Fi gure 18,

Programmer Equipment Chip Unprotect Flow-

chart. Table 27, Programmer Technique Bus Op-

erations, gives a s um m ary of each operation.

The timing on these flowcharts is critical. Care

should be taken t o ensure t hat, where a pause is

specified, it is followed as clos ely as possible. Do

not abort the procedure before reaching the end.

Chip Unprotect can take several seconds and a

user message should be provided to show that the

operation is progressing.

In-System Technique

The In-System technique requires a high voltage

level on the Reset/Blocks Temporary Unprotect

pin, RP . This can be achieved without viol ating the

maximum rati ngs of the component s on the micro-

processor bus, therefore this technique is suitable

for use a fter the Flash memory has been fitted to

th e syste m.

To protect a block follow the flowc hart in Figure 19,

In-System Block Protect Flowchart. To unprotect

the whole chip it is necessary to protect all of the

blocks f i rst, then all the blocks can be unprotected

at the same time. To unprotect the chip follow Fig-

ure 20, I n-System Chip Unprotect Flowchart.

The timing on these flowcharts is critical. Care

should be taken t o ensure t hat, where a pause is

specified, it is followed as clos ely as possible. Do

not allow the m icroprocessor to s ervice interrupts

that will upset the ti ming and do not abort the pro-

cedure before reaching the end. Chip Unprotect

can take several seconds and a user message

should be provided to show that the operation is

progressing.

Table 27. Program mer Tech niqu e Bus Op erations , BYTE = VIH or VIL

Operation E G W Address Inputs

A0-A19 Data Input s/Out puts

DQ15 A–1, DQ14 -DQ0

Block Protect VIL VID VIL Pulse A9 = VID, A12-A19 Block Address

Others = X X

Chip Unprotect VID VID VIL Pulse A9 = VID, A12 = VIH, A15 = VIH

Others = X X

Block Protection

Verify VIL VIL VIH A0 = VIL, A1 = VIH, A6 = VIL, A9 = VID,

A12-A19 Block Address

Others = X

Pass = XX01h

Retry = XX00h

Block Unprotection

Verify VIL VIL VIH A0 = VIL, A1 = VIH, A6 = VIH, A9 = VID,

A12-A19 Block Address

Others = X

Retry = XX01h

Pass = XX00h

35/40

M29W160ET, M29W160EB

Figu re 17 . Programm er E quipm ent Bl oc k P rot ect Flow chart

Note : 1. Ad dress In puts A1 9-A1 2 g ive the a ddres s of the bloc k t hat is to be prot ecte d. I t is im pera t ive t hat they r emain s table d urin g th e

operation.

2. During the Protect and Verify phases of the algorithm, Chip Enable E must be kep t Low, VIL.

ADDRESS = BLOCK ADDRESS

AI03469b

G, A9 = VID,

E = VIL

n = 0

Wait 4µs

Wait 100µs

W = VIL(1)

W = VIH

E, G = VIH,

A0, A6 = VIL,

A1 = VIH

A9 = VIH

E, G = VIH

++n

= 25

START

FAIL

PASS

YES

DATA

01hYES

W = VIH

E = VIL(1)

Wait 4µs

G = VIL

Wait 60ns

Read DATA

Verify Protect Set-upEnd

A9 = VIH

E, G = VIH

M29W160ET, M29W160EB

36/40

Figure 1 8. Programmer Equipment Chip Unprotect Flowchart

PROTECT ALL BLOCKS

AI03470

A6, A12, A15 = VIH(1)

E, G, A9 = VID

DATA

W = VIH

E, G = VIH

ADDRESS = CURRENT BLOCK ADDRESS

A0 = VIL, A1, A6 = VIH

Wait 10ms

00h

INCREMENT

CURRENT BLOCK

n = 0

CURRENT BLOCK = 0

Wait 4µs

W = VIL

++n

= 1000

START

YES

YESNO

NO LAST

BLOCK

YES

E = VIL

Wait 4µs

G = VIL

Wait 60ns

Read DATA

FAIL PASS

Verify Unprotect Set-upEnd

A9 = VIH

E, G = VIH A9 = VIH

E, G = VIH

37/40

M29W160ET, M29W160EB

Figure 19. In-System Equipment Blo ck Protect Flowchart

AI03471

WRITE 60h

ADDRESS = BLOCK ADDRESS

A0 = VIL, A1 = VIH, A6 = VIL

n = 0

Wait 100µs

WRITE 40h

ADDRESS = BLOCK ADDRESS

A0 = VIL, A1 = VIH, A6 = VIL

RP = VIH ++n

= 25

START

FAIL

PASS

YES

DATA

01hYES

RP = VIH

Wait 4µs

Verify Protect Set-upEnd

READ DATA

ADDRESS = BLOCK ADDRESS

A0 = VIL, A1 = VIH, A6 = VIL

RP = VID

ISSUE READ/RESET

COMMAND

ISSUE READ/RESET

COMMAND

WRITE 60h

ADDRESS = BLOCK ADDRESS

A0 = VIL, A1 = VIH, A6 = VIL

M29W160ET, M29W160EB

38/40

Figure 20. In-System Equipment Chip Unprotect Flowchart

AI03472

WRITE 60h

ANY ADDRESS WITH

A0 = VIL, A1 = VIH, A6 = VIH

n = 0

CURRENT BLOCK = 0

Wait 10ms

WRITE 40h

ADDRESS = CURRENT BLOCK ADDRESS

A0 = VIL, A1 = VIH, A6 = VIH

RP = VIH

++n

= 1000

START

FAIL PASS

YES

DATA

00h

YESNO

RP = VIH

Wait 4µs

READ DATA

ADDRESS = CURRENT BLOCK ADDRESS

A0 = VIL, A1 = VIH, A6 = VIH

RP = VID

ISSUE READ/RESET

COMMAND

ISSUE READ/RESET

COMMAND

PROTECT ALL BLOCKS

INCREMENT

CURRENT BLOCK

LAST

BLOCK

YES

WRITE 60h

ANY ADDRESS WITH

A0 = VIL, A1 = VIH, A6 = VIH

Verify Unprotect Set-upEnd

39/40

M29W160ET, M29W160EB

RE VISION HISTORY

Table 28. Document Revi sion History

Date Version Revision Details

06-Aug-2002 -01 First Issue: originates from M29W160D datasheet dated 24-Jun-2002

27-Nov-2002 1.1 9x8mm FBGA48 package replaced by 6x8mm. VDD(min) reduced for -70ns speed class.

Erase Suspend Latency Time (typical and maximum) added to Program, Erase Times

and Program, Erase Endurance Cycles table. Logic Diagram corrected.

03-Dec-2002 1.2 Package information corrected in ordering information table.

21-Mar-2003 2.0 Document promoted to full Datasheet status. Block Protect and Chip Unprotect

algorithms specified in Appendix C, BLOCK PROTECTION.

27-Jun-2003 2.1 TSOP48 package information updated (see Figure 15 and Table 16).

26-Jan-2004 3.0 Block Erase Command clarified.

M29W160ET, M29W160EB

40/40

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