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PGA112

PGA113

PGA117

PGA116

FEATURES APPLICATIONS

DESCRIPTION

10kW

ADC

G=1 RF

Output

Stage

SPI

Interface

SCLK

DIO

VOUT

DVDD

AVDD

GND

VREF

MSP430

Microcontroller

+3V

+5V

VREF

PGA112

PGA113

V /CH0

CAL 2

CH1

CAL3

CAL4

CAL1

CAL2

0.1VCAL

0.9VCAL

10kW

80kW

MUX

CAL2/3

0.1 F

BYPASS

0.1 F

BYPASS

0.1 F

BYPASS

PGA112

, ,

PGA113PGA116

PGA117

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............................................................................................................................................ SBOS424B – MARCH 2008 – REVISED SEPTEMBER 2008

Zer ø -DriftPROGRAMMABLE GAIN AMPLIFIER with MUX

•Remote e-Meter Reading23

•Rail-to-Rail Input/Output

•Automatic Gain Control•Offset: 25 µV (typ), 100 µV (max)

•Portable Data Acquisition•Zer ø Drift: 0.35 µV/ ° C (typ), 1.2 µV/ ° C (max)

•PC-Based Signal Acquisition Systems•Low Noise: 12nV/ √Hz

•Test and Measurement•Input Offset Current: ± 5nA max (+25 ° C)

•Programmable Logic Controllers•Gain Error: 0.1% max (G ≤32),

•Battery-Powered Instruments0.3% max (G > 32)

•Handheld Test Equipment•Binary Gains: 1, 2, 4, 8, 16, 32, 64, 128(PGA112, PGA116)•Scope Gains: 1, 2, 5, 10, 20, 50, 100, 200

The PGA112 and PGA113 (binary/scope gains) offer(PGA113, PGA117)

two analog inputs, a three-pin SPI interface, and•Gain Switching Time: 200ns

software shutdown in an MSOP-10 package. The•Two Channel MUX: PGA112, PGA113

PGA116 and PGA117 (binary/scope gains) offer 1010 Channel MUX: PGA116, PGA117

analog inputs, a four-pin SPI interface withdaisy-chain capability, and hardware and software•Four Internal Calibration Channels

shutdown in a TSSOP-20 package.•Amplifier Optimized for Driving CDAC ADCs

All versions provide internal calibration channels for•Output Swing: 50mV to Supply Rails

system-level calibration. The channels are tied to•AV

and DV

for Mixed Voltage Systems

GND, 0.9V

CAL

, 0.1V

CAL

, and V

REF

, respectively. V

CAL

,•I

= 1.1mA (typ)

an external voltage connected to Channel 0, is usedas the system calibration reference. Binary gains are:•Software/Hardware Shutdown: I

≤4µA (typ)

1, 2, 4, 8, 16, 32, 64, and 128; scope gains are: 1, 2,•Temperature Range: – 40 ° C to +125 ° C

5, 10, 20, 50, 100, and 200.•SPI™ Interface (10MHz) with Daisy-ChainCapability

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2SPI is a trademark of Motorola.3All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Copyright © 2008, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.

ABSOLUTE MAXIMUM RATINGS

(1)

PGA112 , , PGA113PGA116 , PGA117

SBOS424B – MARCH 2008 – REVISED SEPTEMBER 2008 ............................................................................................................................................

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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled withappropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be moresusceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

PACKAGE AND MODEL COMPARISON

SHUTDOWN# OF MUX GAINS SPIDEVICE INPUTS (Eight Each) DAISY-CHAIN HARDWARE SOFTWARE PACKAGE

PGA112 Two Binary No No üMSOP-10PGA113 Two Scope No No üMSOP-10PGA116 10 Binary üüüTSSOP-20PGA117 10 Scope üüüTSSOP-20

ORDERING INFORMATION

(1)

DESCRIPTION PACKAGE PACKAGEPRODUCT (Gains/Channels) PACKAGE-LEAD DESIGNATOR MARKING

PGA112 Binary

(2)

/2 Channels MSOP-10 DGS P112PGA113 Scope

(3)

/2 Channels MSOP-10 DGS P113PGA116 Binary

(2)

/10 Channels TSSOP-20 PW PGA116PGA117 Scope

(3)

/10 Channels TSSOP-20 PW PGA117

(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TIweb site at www.ti.com .(2) Binary gains: 1, 2, 4, 8, 16, 32, 64, and 128.(3) Scope gains: 1, 2, 5, 10, 20, 50, 100, and 200.

Over operating free-air temperature range, unless otherwise noted.

PGA112, PGA113, PGA116, PGA117 UNIT

Supply Voltage +7 VSignal Input Terminals, Voltage

(2)

GND – 0.5 to (AV

) + 0.5 VSignal Input Terminals, Current

(2)

± 10 mAOutput Short-Circuit ContinuousOperating Temperature – 40 to +125 ° CStorage Temperature – 65 to +150 ° CJunction Temperature +150 ° CHuman Body Model (HBM) 3000 VESD Ratings: Charged Device Model (CDM) 1000 VMachine Model (MM) 300 V

(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods maydegrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyondthose specified is not implied.(2) Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5V beyond the supply rails shouldbe current limited to 10mA or less.

Product Folder Link(s): PGA112 PGA113 PGA116 PGA117

ELECTRICAL CHARACTERISTICS: V

= AV

= DV

= +5V

PGA112 , , PGA113PGA116 , PGA117

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............................................................................................................................................ SBOS424B – MARCH 2008 – REVISED SEPTEMBER 2008

Boldface limits apply over the specified temperature range, T

= – 40 ° C to +125 ° C.At T

= +25 ° C, R

= 10k Ω//C

= 100pF connected to DV

/2, and V

REF

= GND, unless otherwise noted.

PGA112, PGA113, PGA116, PGA117

PARAMETER CONDITIONS MIN TYP MAX UNIT

OFFSET VOLTAGE

Input Offset Voltage V

= DV

= +5V, V

REF

= V

= AV

/2, V

= 2.5V ± 25 ± 100 µV

= DV

= +5V, V

REF

= V

= AV

/2, V

= 4.5V ± 75 ± 325 µV

vs Temperature, – 40 ° C to +125 ° C dV

/dT AV

= DV

= +5V, V

= 2.5V 0.35 1.2 µV/ ° C

vs Temperature, – 40 ° C to +85 ° C AV

= DV

= +5V, V

= 2.5V 0.15 0.9 µV/ ° C

vs Temperature, – 40 ° C to +125 ° C AV

= DV

= +5V, V

= 4.5V 0.6 1.8 µV/ ° C

vs Temperature, – 40 ° C to +85 ° C AV

= DV

= +5V, V

= 4.5V 0.3 1.3 µV/ ° C

= DV

= +2.2V to +5.5V, V

= 0.5V,vs Power Supply PSRR 5 20 µV/VV

REF

= V

= AV

= DV

= +2.2V to +5.5V, V

= 0.5V,Over Temperature, – 40 ° C to +125 ° C 5 40 µV/VV

REF

= V

= AV

INPUT ON-CHANNEL CURRENT

Input On-Channel Current (Ch0, Ch1) I

REF

= V

= AV

/2 ± 1.5 ± 5 nA

Over Temperature, – 40 ° C to +125 ° C V

REF

= V

= AV

/2 See Typical Characteristics nA

INPUT VOLTAGE RANGE

Input Voltage Range

(1)

GND – 0.1 AV

+ 0.1 V

Overvoltage Input Range No Output Phase Reversal

(2)

GND – 0.3 AV

+ 0.3 V

INPUT IMPEDANCE (Channel On)

(3)

Channel Input Capacitance C

2 pF

Channel Switch Resistance R

150 Ω

Amplifier Input Capacitance C

AMP

3 pF

Amplifier Input Resistance R

AMP

Input Resistance to GND 10 G Ω

CAL

/CH0 R

CAL1 or CAL2 Selected 100 k Ω

GAIN SELECTIONS

Nominal Gains Binary gains: 1, 2, 4, 8, 16, 32, 64, 128 1 128

Scope gains: 1, 2, 5, 10, 20, 50, 100, 200 1 200

DC Gain Error G = 1 V

OUT

= GND + 85mV to DV

– 85mV 0.006 0.1 %

1 < G ≤32 V

OUT

= GND + 85mV to DV

– 85mV 0.1 %

G≥50 V

OUT

= GND + 85mV to DV

– 85mV 0.3 %

DC Gain Drift G = 1 V

OUT

= GND + 85mV to DV

– 85mV 0.5 ppm/ ° C

1 < G ≤32 V

OUT

= GND + 85mV to DV

– 85mV 2 ppm/ ° C

G≥50 V

OUT

= GND + 85mV to DV

– 85mV 6 ppm/ ° C

Op Amp + Input = 0.9V

CAL

,CAL2 DC Gain Error

(4)

0.02 %V

REF

= V

CAL

= AV

/2, G = 1

Op Amp + Input = 0.9V

CAL

,CAL2 DC Gain Drift

(4)

2 ppm/ ° CV

REF

= V

CAL

= AV

/2, G = 1

Op Amp + Input = 0.1V

CAL

,CAL3 DC Gain Error

(4)

0.02 %V

REF

= V

CAL

= AV

/2, G = 1

Op Amp + Input = 0.1V

CAL

,CAL3 DC Gain Drift

(4)

2 ppm/ ° CV

REF

= V

CAL

= AV

/2, G = 1

INPUT IMPEDANCE (Channel Off)

(3)

Input Impedance C

See Figure 1 2 pF

INPUT OFF-CHANNEL CURRENT

REF

= GND, V

OFF-CHANNEL

= AV

/2,Input Off-Channel Current (Ch0, Ch1)

(5)

LKG

± 0.05 ± 1 nAV

ON-CHANNEL

= AV

/2 – 0.1V

REF

= GND, V

OFF-CHANNEL

= AV

/2,Over Temperature, – 40 ° C to +125 ° C See Typical CharacteristicsV

ON-CHANNEL

= AV

/2 – 0.1V

Channel-to-Channel Crosstalk 130 dB

(1) Gain error is a function of the input voltage. Gain error outside of the range (GND + 85mV ≤V

OUT

≤DV

– 85mV) increases to 0.5%(typical).

(2) Input voltages beyond this range must be current limited to < |10mA| through the input protection diodes on each channel to preventpermanent destruction of the device.(3) See Figure 1 .(4) Total V

OUT

error must be computed using input offset voltage error multiplied by gain. Includes op amp G = 1 error.(5) Maximum specification limitation limited by final test time and capability.

Product Folder Link(s): PGA112 PGA113 PGA116 PGA117

PGA112 , , PGA113PGA116 , PGA117

SBOS424B – MARCH 2008 – REVISED SEPTEMBER 2008 ............................................................................................................................................

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ELECTRICAL CHARACTERISTICS: V

= AV

= DV

= +5V (continued)Boldface limits apply over the specified temperature range, T

= – 40 ° C to +125 ° C.At T

= +25 ° C, R

= 10k Ω//C

= 100pF connected to DV

/2, and V

REF

= GND, unless otherwise noted.

PGA112, PGA113, PGA116, PGA117

PARAMETER CONDITIONS MIN TYP MAX UNIT

OUTPUT

Voltage Output Swing from Rail I

OUT

= ± 0.25mA, AV

≥DV

(6)

GND + 0.05 DV

– 0.05 V

OUT

= ± 5mA, AV

≥DV

(6)

GND + 0.25 DV

– 0.25 V

DC Output Nonlinearity V

OUT

= GND + 85mV to DV

– 85mV

(7)

0.0015 %FSR

Short-Circuit Current I

– 30/+60 mA

Capacitive Load Drive C

LOAD

See Typical Characteristics

NOISE

Input Voltage Noise Density e

f > 10kHz, C

= 100pF, V

= 5V 12 nV/ √Hz

f > 10kHz, C

= 100pF, V

= 2.2V 22 nV/ √Hz

Input Voltage Noise e

f = 0.1Hz to 10Hz, C

= 100pF, V

= 5V 0.362 µV

f = 0.1Hz to 10Hz, C

= 100pF, V

= 2.2V 0.736 µV

Input Current Density I

f = 10kHz, C

= 100pF 400 fA/ √Hz

SLEW RATE

Slew Rate SR See Table 1 V/ µs

SETTLING TIME

Settling Time t

See Table 1 µs

FREQUENCY RESPONSE

Frequency Response See Table 1 MHz

THD + NOISE

G = 1, f = 1kHz, V

OUT

= 4V

at 2.5V

, C

= 100pF 0.003 %

G = 10, f = 1kHz, V

OUT

= 4V

at 2.5V

, C

= 100pF 0.005 %

G = 50, f = 1kHz, V

OUT

= 4V

at 2.5V

, C

= 100pF 0.03 %

G = 128, f = 1kHz, V

OUT

= 4V

at 2.5V

, C

= 100pF 0.08 %

G = 200, f = 1kHz, V

OUT

= 4V

at 2.5V

, C

= 100pF 0.1 %

G = 1, f = 20kHz, V

OUT

= 4V

at 2.5V

, C

= 100pF 0.02 %

G = 10, f = 20kHz, V

OUT

= 4V

at 2.5V

, C

= 100pF 0.01 %

G = 50, f = 20kHz, V

OUT

= 4V

at 2.5V

, C

= 100pF 0.03 %

G = 128, f = 20kHz, V

OUT

= 4V

at 2.5V

, C

= 100pF 0.08 %

G = 200, f = 20kHz, V

OUT

= 4V

at 2.5V

, C

= 100pF 0.11 %

POWER SUPPLY

Operating Voltage Range

(6)

2.2 5.5 V

Quiescent Current Analog I

= 0, G = 1, V

OUT

= V

REF

0.33 0.45 mA

Over Temperature, – 40 ° C to +125 ° C 0.45 mA

= 0, G = 1, V

OUT

= V

REF

, SCLK at 10MHz,Quiescent Current Digital

(8) (9) (10)

0.75 1.2 mACS = Logic 0, DIO or DIN = Logic 0

= 0, G = 1, V

OUT

= V

REF

, SCLK at 10MHz,Over Temperature, – 40 ° C to +125 ° C

(8) (9) (10)

1.2 mACS = Logic 0, DIO or DIN = Logic 0

Shutdown Current Analog + Digital

(8) (9)

SDA

+ I

SDD

= 0, V

OUT

= V

REF

, G = 1, SCLK Idle 4 µA

= 0, V

OUT

= 0, G = 1, SCLK at 10MHz,

245 µACS = Logic 0, DIO or DIN = Logic 0

POWER-ON RESET (POR)

Digital interface disabled and Command Register set to PORPOR Trip Voltage 1.6 Vvalues for DV

< POR Trip Voltage

(6) When AV

is less than DV

, the output is clamped to AV

+ 300mV.(7) Measurement limited by noise in test equipment and test time.(8) Does not include current into or out of the V

REF

pin. Internal R

and R

are always connected between V

OUT

and V

REF

.(9) Digital logic levels: DIO or DIN = logic 0. 10 µA internal pull-down current source.(10) Includes current from op amp output structure.

Product Folder Link(s): PGA112 PGA113 PGA116 PGA117

RSW

RAMP

Mux

Switch

CCH CAMP VOUT

CHx

(Input)

VREF

Break-Before-Make

PGA112 , , PGA113PGA116 , PGA117

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............................................................................................................................................ SBOS424B – MARCH 2008 – REVISED SEPTEMBER 2008

ELECTRICAL CHARACTERISTICS: V

= AV

= DV

= +5V (continued)Boldface limits apply over the specified temperature range, T

= – 40 ° C to +125 ° C.At T

= +25 ° C, R

= 10k Ω//C

= 100pF connected to DV

/2, and V

REF

= GND, unless otherwise noted.

PGA112, PGA113, PGA116, PGA117

PARAMETER CONDITIONS MIN TYP MAX UNIT

TEMPERATURE RANGE

Specified Range – 40 +125 ° C

Operating Range – 40 +125 ° C

Thermal Resistance θ

MSOP-10 164 ° C/W

DIGITAL INPUTS (SCLK, CS, DIO, DIN)

Logic Low 0 0.3DV

Input Leakage Current (SCLK and CS only) – 1 +1 µA

Weak Pull-Down Current (DIO, DIN only) 10 µA

Logic High 0.7DV

Hysteresis 700 mV

DIGITAL OUTPUT (DIO, DOUT)

Logic High I

= – 3mA (sourcing) DV

– 0.4 DV

Logic Low I

= +3mA (sinking) GND GND + 0.4 V

CHANNEL AND GAIN TIMING

Channel Select Time 0.2 µs

Gain Select Time 0.2 µs

SHUTDOWN MODE TIMING

Enable Time 4.0 µs

OUT

goes high-impedance, R

and R

remain connectedDisable Time 2.0 µsbetween V

OUT

and V

REF

POWER-ON-RESET (POR) TIMING

POR Power-Up Time DV

≥2V 40 µs

POR Power-Down Time DV

≤1.5V 5 µs

Table 1. Frequency Response versus Gain (C

= 100pF, R

= 10k Ω)0.1% 0.01% 0.1% 0.01%TYPICAL SLEW SLEW SETTLING SETTLING TYPICAL SLEW SLEW SETTLING SETTLING– 3dB RATE- RATE- TIME: TIME: SCOPE – 3dB RATE- RATE- TIME: TIME:BINARY FREQUENCY FALL RISE 4V

GAIN FREQUENCY FALL RISE 4V

PPGAIN (V/V) (MHz) (V/ µs) (V/ µs) ( µs) ( µs) (V/V) (MHz) (V/ µs) (V/ µs) ( µs) ( µs)

1 10 8 3 2 2.55 1 10 8 3 2 2.55

2 3.8 9 6.4 2 2.6 2 3.8 9 6.4 2 2.6

4 2 12.8 10.6 2 2.6 5 1.8 12.8 10.6 2 2.6

8 1.8 12.8 10.6 2 2.6 10 1.8 12.8 10.6 2.2 2.6

16 1.6 12.8 12.8 2.3 2.6 20 1.3 12.8 9.1 2.3 2.8

32 1.8 12.8 13.3 2.3 3 50 0.9 9.1 7.1 2.4 3.8

64 0.6 4 3.5 3 6 100 0.38 4 3.5 4.4 7

128 0.35 2.5 2.5 4.8 8 200 0.23 2.3 2 6.9 10

Figure 1. Equivalent Input Circuit

Product Folder Link(s): PGA112 PGA113 PGA116 PGA117

SPI TIMING: V

= AV

= DV

= +2.2V to +5V

PGA112 , , PGA113PGA116 , PGA117

SBOS424B – MARCH 2008 – REVISED SEPTEMBER 2008 ............................................................................................................................................

www.ti.com

Boldface limits apply over the specified temperature range, T

= – 40 ° C to +125 ° C.At T

= +25 ° C, R

= 10k Ω//C

= 100pF connected to DV

/2, and V

REF

= GND, unless otherwise noted.

PGA112, PGA113,PGA116, PGA117

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Input Capacitance (SCLK, CS, and DIO pins) 1 pFInput Rise/Fall Time

(1)

RFI

2µs( CS, SCLK, and DIO pins)Output Rise/Fall Time (DIO pin)

(1)

RFO

LOAD

= 60pF 10 nsCS High Time ( CS pin)

(1)

CSH

40 nsSCLK Edge to CS Fall Setup Time

(1)

CSO

10 nsCS Fall to First SCLK Edge Setup Time t

CSSC

10 nsSCLK Frequency

(2)

SCLK

10 MHzSCLK High Time

(3)

40 nsSCLK Low Time

(3)

40 nsSCLK Last Edge to CS Rise Setup Time

(1)

SCCS

10 nsCS Rise to SCLK Edge Setup Time

(1)

CS1

10 nsDIN Setup Time t

10 nsDIN Hold Time t

10 nsSCLK to DOUT Valid Propagation Delay

(1)

25 nsCS Rise to DOUT Forced to Hi-Z

(1)

SOZ

20 ns

(1) Ensured by design; not production tested.(2) When using devices in daisy-chain mode, the maximum clock frequency for SCLK is limited by SCLK rise/fall time, DIN setup time, andDOUT propagation delay. See Figure 63 . Based on this limitation, the maximum SCLK frequency for daisy-chain mode is 9.09MHz.(3) t

and t

must not be less than 1/SCLK (max).

Product Folder Link(s): PGA112 PGA113 PGA116 PGA117

SPI TIMING DIAGRAMS

SCLK

DIN

DOUT

Hi-Z Hi-Z

tCSH

tSCCS

tLO

tCSSC

tSU tHD

tDO tSOZ

tHI

tCS1 tCS0

1/fSCLK

SCLK

DIN

DOUT

tCSSC

tHI tLO

tSCCS tCS1

tSOZ

tDO

tCS0

tSU tHD

1/fSCLK

Hi-Z Hi-Z

tCSH

PGA112 , , PGA113PGA116 , PGA117

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............................................................................................................................................ SBOS424B – MARCH 2008 – REVISED SEPTEMBER 2008

Figure 2. SPI Mode 0, 0

Figure 3. SPI Mode 1, 1

Product Folder Link(s): PGA112 PGA113 PGA116 PGA117

PIN CONFIGURATIONS

DVDD

DIO

SCLK

GND

AVDD

CH1

V /CH0

CAL

VREF

VOUT

PGA112

PGA113

PGA112 , , PGA113PGA116 , PGA117

SBOS424B – MARCH 2008 – REVISED SEPTEMBER 2008 ............................................................................................................................................

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MSOP-10

DGS PACKAGE

(TOP VIEW)

PGA112, PGA113 TERMINAL FUNCTIONS

MSOP

PACKAGE

PIN # NAME DESCRIPTION

1 AV

Analog supply voltage (+2.2V to +5.5V)2 CH1 Input MUX channel 1Input MUX channel 0 and V

CAL

input. For system calibration purposes, connect this pin to alow-impedance external reference voltage to use internal calibration channels. The four internal3 V

CAL

/CH0 calibration channels are connected to GND, 0.9V

CAL

, 0.1V

CAL

, and V

REF

, respectively. V

CAL

is loadedwith 100k Ω(typical) when internal calibration channels CAL2 or CAL3 are selected. Otherwise,V

CAL

/CH0 appears as high impedance.Reference input pin. Connect external reference for V

OUT

offset shift or to midsupply for midsupply4 V

REF

referenced systems. V

REF

must be connected to a low-impedance reference capable of sourcing andsinking at least 2mA or V

REF

must be connected to GND.5 V

OUT

Analog voltage output. When AV

< DV

, V

OUT

is clamped to AV

+ 300mV.6 GND Ground pin7 SCLK Clock input for SPI serial interface8 DIO Data input/output for SPI serial interface. DIO contains a weak, 10 µA internal pull-down current source.9 CS Chip select line for SPI serial interfaceDigital and op amp output stage supply voltage (+2.2V to +5.5V). Useful in multi-supply systems toprevent overvoltage/lockup condition on an analog-to-digital (ADC) input (for example, a microcontroller10 DV

with an ADC running on +3V and the PGA powered from +5V). Digital I/O levels to be relative to DV

.DV

should be bypassed with a 0.1 µF ceramic capacitor, and DV

must supply the current for thedigital portion of the PGA as well as the load current for the op amp output stage.

Product Folder Link(s): PGA112 PGA113 PGA116 PGA117

AVDD

CH5

CH4

CH3

CH2

CH1

V /CH0

CAL

VREF

VOUT

CH7

CH6

DVDD

DOUT

DIN

SCLK

GND

ENABLE

CH9

CH8

PGA116

PGA117

PGA112 , , PGA113PGA116 , PGA117

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............................................................................................................................................ SBOS424B – MARCH 2008 – REVISED SEPTEMBER 2008

TSSOP-20

PW PACKAGE

(TOP VIEW)

PGA116, PGA117 TERMINAL FUNCTIONS

TSSOP

PACKAGE

PIN # NAME DESCRIPTION

1 AV

Analog supply voltage (+2.2V to +5.5V)2 CH5 Input MUX channel 53 CH4 Input MUX channel 44 CH3 Input MUX channel 35 CH2 Input MUX channel 26 CH1 Input MUX channel 1Input MUX channel 0 and V

CAL

input. For system calibration purposes, connect this pin to alow-impedance external reference voltage to use internal calibration channels. The four internal7 V

CAL

/CH0 calibration channels are connected to GND, 0.9V

CAL

, 0.1V

CAL

, and V

REF

, respectively. V

CAL

is loadedwith 100k Ω(typical) when internal calibration channels CAL2 or CAL3 are selected. Otherwise,V

CAL

/CH0 appears as high impedance.Reference input pin. Connect external reference for V

OUT

offset shift or to midsupply for midsupply8 V

REF

referenced systems. V

REF

must be connected to a low-impedance reference capable of sourcing andsinking at least 2mA or to GND.9 V

OUT

Analog voltage output. When AV

< DV

, V

OUT

is clamped to AV

+ 300mV.10 CH7 Input MUX channel 711 CH8 Input MUX channel 812 CH9 Input MUX channel 913 ENABLE Hardware enable pin. Logic low puts the part into Shutdown mode (I

< 1 µA).14 GND Ground pin15 SCLK Clock input for SPI serial interfaceData input for SPI serial interface. DIN contains a weak, 10 µA internal pull-down current source to16 DIN

allow for ease of daisy-chain configurations.Data output for SPI serial interface. DOUT goes to high-Z state when CS goes high for standard SPI17 DOUT

interface.18 CS Chip select line for SPI serial interfaceDigital and op amp output stage supply voltage (+2.2V to +5.5V). Useful in multi-supply systems toprevent overvoltage/lockup condition on an ADC input (for example, a microcontroller with an ADC19 DV

running on +3V and the PGA powered from +5V). Digital I/O levels to be relative to DV

. DV

shouldbe bypassed with a 0.1 µF ceramic capacitor, and DV

must supply the current for the digital portion ofthe PGA as well as the load current for the op amp output stage.20 CH6 Input MUX channel 6

Product Folder Link(s): PGA112 PGA113 PGA116 PGA117

TYPICAL APPLICATION CIRCUITS

10kW

ADC

G=1 RF

Output

Stage

SPI

Interface

SCLK

DIO

VOUT

DVDD

AVDD

GND

VREF

MSP430

Microcontroller

+3V

+5V

VREF

PGA112

PGA113

V /CH0

CAL 2

CH1

CAL3

CAL4

CAL1

CAL2

0.1VCAL

0.9VCAL

10kW

80kW

MUX

CAL2/3

0.1 F

BYPASS

0.1 F

BYPASS

0.1 F

BYPASS

10kW

G=1 RF

Output

Stage

SPI

Interface

SCLK

ENABLE

DIN

VOUT

DVDD

AVDD

GND

VREF

8 13

DOUT17

+5V

VREF

PGA116

PGA117

CH8 12

CH9

CH7 11

CH6 10

CH5 20

CH4 2

CH3 3

CH2 4

CH1 5

V /CH0

CAL 6

CAL3

CAL4

CAL1

CAL2

0.1VCAL

0.9VCAL

10kW

80kW

MUX

CAL2/3

0.1 F

BYPASS

ADC

MSP430

Microcontroller

+3V

0.1 F

BYPASS

0.1 F

BYPASS

PGA112 , , PGA113PGA116 , PGA117

SBOS424B – MARCH 2008 – REVISED SEPTEMBER 2008 ............................................................................................................................................

www.ti.com

Figure 4. PGA112, PGA113 (MSOP-10)

Figure 5. PGA116, PGA117 (TSSOP-20)

Product Folder Link(s): PGA112 PGA113 PGA116 PGA117

TYPICAL CHARACTERISTICS

-80

OffsetVoltage( V)m

Population

-90

-100

-70

-60

-10

-20

-30

-40

-50

100

V =2.5V

-260.0

OffsetVoltage( V)m

Population

-325.0

-227.5

-195.0

-32.5

-65.0

-97.5

-130.0

-162.5

32.5

292.5

260.0

65.0

97.5

130.0

227.5

195.0

162.5

V =4.5V

325.0

-292.5

-0.72

OffsetVoltageDrift( V/ C)m °

Population

-0.81

-0.90

-0.63

-0.54

-0.09

-0.18

-0.27

-0.36

-0.45

0.09

0.81

0.90

0.72

0.18

0.27

0.36

0.63

0.54

0.45

V =2.5V

-1.04

OffsetVoltageDrift( V/ C)m °

Population

-1.30

-0.91

-0.78

-0.13

-0.26

-0.39

-0.52

-0.65

0.13

1.17

1.04

0.26

0.39

0.52

0.91

0.78

0.65

1.30

V =4.5V

-1.17

-1.44

OffsetVoltageDrift( V/ C)m °

Population

-1.80

-1.26

-1.08

-0.18

-0.36

-0.54

-0.72

-0.90

0.18

1.62

1.44

0.36

0.54

0.72

1.26

1.08

0.90

1.80

V =4.5V

-1.62

-0.96

OffsetVoltageDrift( V/ C)m °

Population

-1.08

-1.20

-0.84

-0.72

-0.12

-0.24

-0.36

-0.48

-0.60

0.12

1.08

1.20

0.96

0.24

0.36

0.48

0.84

0.72

0.60

V =2.5V

PGA112 , , PGA113PGA116 , PGA117

www.ti.com

............................................................................................................................................ SBOS424B – MARCH 2008 – REVISED SEPTEMBER 2008

At T

= +25 ° C, AV

= DV

= 5V, R

= 10k Ωconnected to DV

/2, V

REF

= GND, and C

= 100pF, unless otherwise noted.

OFFSET VOLTAGE OFFSET VOLTAGE

Figure 6. Figure 7.

OFFSET VOLTAGE DRIFT OFFSET VOLTAGE DRIFT( – 40 ° C to +85 ° C) ( – 40 ° C TO +85 ° C)

Figure 8. Figure 9.

OFFSET VOLTAGE DRIFT OFFSET VOLTAGE DRIFT( – 40 ° C to +125 ° C) ( – 40 ° C TO +125 ° C)

Figure 10. Figure 11.

Product Folder Link(s): PGA112 PGA113 PGA116 PGA117

0 1 5

InputVoltage(V)

100

InputOffsetVoltage( V)m

32 4

V (V)

OUT

DCOutputNonlinearityError(%FSR)

0.0010

0.0008

0.0006

0.0004

0.0002

0.0004

0.0006

0.0008

0.0010

0.50 5.01.0 1.5

G=128

G=16

G=2

G=1

2.0 2.5 3.0 3.5 4.0 4.5

AV =DV =+5V

DD DD

-0.08

GainError(%)

Population

-0.09

-0.10

-0.07

-0.06

-0.01

-0.02

-0.03

-0.04

-0.05

0.01

0.09

0.08

0.02

0.03

0.04

0.07

0.06

0.05

0.10

-0.08

GainError(%)

Population

-0.09

-0.10

-0.07

-0.06

-0.01

-0.02

-0.03

-0.04

-0.05

0.01

0.09

0.08

0.02

0.03

0.04

0.07

0.06

0.05

0.10

GainErrorDrift( )ppm/ C°

Population

G=1

0.10

0.05

0.15

0.20

0.45

0.40

0.35

0.30

0.25

0.50

0.55

0.95

0.90

0.60

0.65

0.70

0.85

0.80

0.75

1.00

-0.240

GainError(%)

Population

-0.270

-0.300

-0.210

-0.180

-0.030

-0.060

-0.090

-0.120

-0.150

0.030

0.270

0.240

0.060

0.090

0.120

0.210

0.180

0.150

0.300

PGA112 , , PGA113PGA116 , PGA117

SBOS424B – MARCH 2008 – REVISED SEPTEMBER 2008 ............................................................................................................................................

www.ti.com

TYPICAL CHARACTERISTICS (continued)At T

= +25 ° C, AV

= DV

= 5V, R

= 10k Ωconnected to DV

/2, V

REF

= GND, and C

= 100pF, unless otherwise noted.

INPUT OFFSET VOLTAGE vs INPUT VOLTAGE PGA112/PGA116 NONLINEARITY

Figure 12. Figure 13.

GAIN ERROR (G = 1) GAIN ERROR (1 < G ≤32)

Figure 14. Figure 15.

GAIN ERROR DRIFTGAIN ERROR (G ≥50) ( – 40 ° C to +125 ° C)

Figure 16. Figure 17.

Product Folder Link(s): PGA112 PGA113 PGA116 PGA117

1.0

GainErrorDrift(ppm/ C)°

Population

0.5

1.5

2.0

4.5

4.0

3.5

3.0

2.5

5.0

5.5

9.5

9.0

6.0

6.5

7.0

8.5

8.0

7.5

10.0

G 50³

0.50

GainErrorDrift(ppm/ C)°

Population

0.25

0.75

1.00

2.25

2.00

1.75

1.50

1.25

2.50

2.75

4.75

4.50

3.00

3.25

3.50

4.25

4.00

3.75

5.00

1 G 32< £

-0.08

GainError(%)

Population

-0.10

-0.07

-0.06

-0.01

-0.02

-0.03

-0.04

-0.05

0.01

0.09

0.08

0.02

0.03

0.04

0.07

0.06

0.05

0.10

-0.09

-0.08

GainError(%)

Population

-0.10

-0.07

-0.06

-0.01

-0.02

-0.03

-0.04

-0.05

0.01

0.09

0.08

0.02

0.03

0.04

0.07

0.06

0.05

0.10

-0.09

-1.6

GainErrorDrift(ppm/ C)°

Population

-2.0

-1.4

-1.2

-0.2

-0.4

-0.6

-0.8

-1.0

0.2

1.8

1.6

0.4

0.6

0.8

1.4

1.2

1.0

2.0

-1.8

-1.6

GainErrorDrift(ppm/ C)°

Population

-2.0

-1.4

-1.2

-0.2

-0.4

-0.6

-0.8

-1.0

0.2

1.8

1.6

0.4

0.6

0.8

1.4

1.2

1.0

>2.0

-1.8

2.0

PGA112 , , PGA113PGA116 , PGA117

www.ti.com

............................................................................................................................................ SBOS424B – MARCH 2008 – REVISED SEPTEMBER 2008

TYPICAL CHARACTERISTICS (continued)At T

= +25 ° C, AV

= DV

= 5V, R

= 10k Ωconnected to DV

/2, V

REF

= GND, and C

= 100pF, unless otherwise noted.

GAIN ERROR DRIFT GAIN ERROR DRIFT( – 40 ° C to +125 ° C) ( – 40 ° C to +125 ° C)

Figure 18. Figure 19.

CAL2 GAIN ERROR CAL3 GAIN ERROR

Figure 20. Figure 21.

CAL2 GAIN ERROR DRIFT CAL3 GAIN ERROR DRIFT( – 40 ° C to +125 ° C) ( – 40 ° C to +125 ° C)

Figure 22. Figure 23.

Product Folder Link(s): PGA112 PGA113 PGA116 PGA117

2.5s/div

250nV/div

V =2.2V

2.5s/div

100nV/div

V =5V

1 10 100 1k 100k

Frequency(Hz)

100

VoltageNoise(nV/ )ÖHz

10k

100

CurrentNoise(fA/ )ÖHz

VoltageNoise,V =5V

VoltageNoise,V =2.2V

CurrentNoise,V =5V

500

200

Frequency(Hz)

THD+N(%)

0.1

0.01

0.001

0.0001

10010 100k1k 10k

G=128

G=64 G=32 G=16

G=8

G=2

G=1 G=4

Frequency(Hz)

THD+N(%)

0.1

0.01

0.001

0.0001

10010 100k1k 10k

G=128

G=64 G=32 G=16

G=8

G=4

G=2

G=1

Frequency(Hz)

THD+N(%)

0.1

0.01

0.001

0.0001

10010 100k1k 10k

G=1

G=200 G=100 G=50 G=20

G=10

G=2 G=5

PGA112 , , PGA113PGA116 , PGA117

SBOS424B – MARCH 2008 – REVISED SEPTEMBER 2008 ............................................................................................................................................

www.ti.com

TYPICAL CHARACTERISTICS (continued)At T

= +25 ° C, AV

= DV

= 5V, R

= 10k Ωconnected to DV

/2, V

REF

= GND, and C

= 100pF, unless otherwise noted.

0.1Hz TO 10Hz NOISE 0.1Hz TO 10Hz NOISE

Figure 24. Figure 25.

PGA112, PGA116 THD + NOISE vs FREQUENCYSPECTRAL NOISE DENSITY (V

OUT

= 2V

)

Figure 26. Figure 27.

PGA112, PGA116 THD + NOISE vs FREQUENCY PGA113, PGA117 THD + NOISE vs FREQUENCY(V

OUT

= 4V

) (V

OUT

= 2V

)

Figure 28. Figure 29.

Product Folder Link(s): PGA112 PGA113 PGA116 PGA117

Frequency(Hz)

THD+N(%)

0.1

0.01

0.001

0.0001

10010 100k1k 10k

G=200 G=100 G=50 G=20

G=10

G=2

G=1

G=5

Temperature( C)°

I (mA)

0.8

0.4

0.3

0.2

0.1

75-25-50 100 1250 25 50

0.5

0.6

0.7

V =5.5V

V =2.2V

Digital

Analog

f =10MHz

SCLK

SupplyVoltage(V)

I +I (mA)

QA QD

1.2

1.0

0.8

0.6

0.4

0.2

4.52.52.0 5.0 5.53.0 3.5 4.0

SCLK=10MHz

SCLK=5MHz

SCLK=2MHz

SCLK=500kHz

-50 -25 0 125

Temperature( C)°

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

ShutdownI ( A)m

25 50 75 100

Digital

Analog

0 10 20 30 40 50 60 70 80 90 100

OutputCurrent(mA)

5.5

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

OutputVoltage(V)

V =5.5V

G=1

+125 C°

+25 C°

- °40 C

02 4 6 8 10 12 14 16 18 24

OutputCurrent(mA)

2.2

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

OutputVoltage(V)

V =2.2V

G=1

+125 C°+25 C°

- °40 C

PGA112 , , PGA113PGA116 , PGA117

www.ti.com

............................................................................................................................................ SBOS424B – MARCH 2008 – REVISED SEPTEMBER 2008

TYPICAL CHARACTERISTICS (continued)At T

= +25 ° C, AV

= DV

= 5V, R

= 10k Ωconnected to DV

/2, V

REF

= GND, and C

= 100pF, unless otherwise noted.

PGA113, PGA117 THD + NOISE vs FREQUENCY QUIESCENT CURRENT(V

OUT

= 4V

) vs TEMPERATURE

Figure 30. Figure 31.

TOTAL QUIESCENT CURRENT SHUTDOWN QUIESCENT CURRENTvs SUPPLY VOLTAGE vs TEMPERATURE

Figure 32. Figure 33.

OUTPUT VOLTAGE OUTPUT VOLTAGEvs OUTPUT CURRENT vs OUTPUT CURRENT

Figure 34. Figure 35.

Product Folder Link(s): PGA112 PGA113 PGA116 PGA117

1k 10k 10M

Frequency(Hz)

2.5

2.0

1.5

1.0

0.5

OutputVoltage(V)

100k 1M

G=1

G=8

G=4

G=2

AV =DV =2.2V

DD DD

1k 10k 10M

Frequency(Hz)

2.5

2.0

1.5

1.0

0.5

OutputVoltage(V)

100k 1M

G=128

G=16

G=64

G=32

AV = 2.2V

DD DV =

100 1k 10k 10M

Frequency(Hz)

OutputVoltage(V)

100k 1M

G=1

G=8

G=4

G=2

AV =DV =5.5V

DD DD

100 1k 10k 10M

Frequency(Hz)

OutputVoltage(V)

100k 1M

G=128

G=16

G=64

G=32

AV =DV =5.5V

DD DD

1k 10k 100k 1M 10M

Frequency(Hz)

2.5

2.0

1.5

1.0

0.5

OutputVoltage(V)

G=10

G=2

G=1

G=5

AV =DV

DD DD =2.2V

1k 10k 100k 1M 10M

Frequency(Hz)

2.5

2.0

1.5

1.0

0.5

OutputVoltage(V)

G=100

G=20

G=200

G=50

AV =DV

DD DD =2.2V

PGA112 , , PGA113PGA116 , PGA117

SBOS424B – MARCH 2008 – REVISED SEPTEMBER 2008 ............................................................................................................................................

www.ti.com

TYPICAL CHARACTERISTICS (continued)At T

= +25 ° C, AV

= DV

= 5V, R

= 10k Ωconnected to DV

/2, V

REF

= GND, and C

= 100pF, unless otherwise noted.

PGA112, PGA116 OUTPUT VOLTAGE SWING vs PGA112, PGA116 OUTPUT VOLTAGE SWING vsFREQUENCY FREQUENCY

Figure 36. Figure 37.

PGA112, PGA116 OUTPUT VOLTAGE SWING vs PGA112, PGA116 OUTPUT VOLTAGE SWING vsFREQUENCY FREQUENCY

Figure 38. Figure 39.

PGA113, PGA117 OUTPUT VOLTAGE SWING vs PGA113, PGA117 OUTPUT VOLTAGE SWING vsFREQUENCY FREQUENCY

Figure 40. Figure 41.

Product Folder Link(s): PGA112 PGA113 PGA116 PGA117

100 1k 10k 100k 1M 10M

Frequency(Hz)

OutputVoltage(V)

G=10

G=2

G=1

G=5

AV =DV

DD DD =5.5V

100 1k 10k 100k 1M 10M

Frequency(Hz)

OutputVoltage(V)

G=20

G=200

G=100

G=50

AV =DV

DD DD =5.5V

0 50 100 200

Gain

SettlingTime( s)m

150

0.01%

0.1%

C =100pF//R =10kW

L L

OUT PP

V =4V

0 100 200 300 400 500 600 700 800

LoadCapacitance(pF)

Overshoot(%)

G=1

G 2>

Channel1toChannel9

InputOff-ChannelCurrent(nA)

-50 -25 0 25 50 75 100 125

Temperature(°C)

0.15

0.10

0.05

0.01

0.15

Channel0InputOff-ChannelCurrent(nA)

CH1to

CH9

CH0

Measurementmadewithchannelpin

connectedtomidsupply

-50 -25 0 25 50 75 100 125

Temperature(°C)

InputOn-ChannelCurrent(nA)

CH1to

CH9

CH0

Measurementmadewithchannelpin

connectedtomidsupply

PGA112 , , PGA113PGA116 , PGA117

www.ti.com

............................................................................................................................................ SBOS424B – MARCH 2008 – REVISED SEPTEMBER 2008

TYPICAL CHARACTERISTICS (continued)At T

= +25 ° C, AV

= DV

= 5V, R

= 10k Ωconnected to DV

/2, V

REF

= GND, and C

= 100pF, unless otherwise noted.

PGA113, PGA117 OUTPUT VOLTAGE SWING vs PGA113, PGA117 OUTPUT VOLTAGE SWING vsFREQUENCY FREQUENCY

Figure 42. Figure 43.

SMALL-SIGNAL OVERSHOOTvs LOAD CAPACITANCE GAIN vs SETTLING TIME

Figure 44. Figure 45.

INPUT ON-CHANNEL CURRENT INPUT OFF-CHANNEL LEAKAGE CURRENTvs TEMPERATURE vs TEMPERATURE

Figure 46. Figure 47.

Product Folder Link(s): PGA112 PGA113 PGA116 PGA117

10 100 1k 10k 10M

Frequency(Hz)

140

130

120

110

100

Crosstalk(dB)

1M100k

0.1 1 10 100 10M

Frequency(Hz)

110

100

PSRR(dB)

1M100k10k1k

G=200

G=50

G=10

G=2

G=1

G 2

2.5 s/divm

G=20

G=10

G=1

100mV

Output

Input

V /G

2.5 s/divm

Output

Input

G=50

G=100,200

100mV

V /G

2.5 s/divm

2V/div

G=10

G=2

G=1

Output

Input

2.5 s/divm

2V/div

Input

G=50

G=100,200

Output

PGA112 , , PGA113PGA116 , PGA117

SBOS424B – MARCH 2008 – REVISED SEPTEMBER 2008 ............................................................................................................................................

www.ti.com

TYPICAL CHARACTERISTICS (continued)At T

= +25 ° C, AV

= DV

= 5V, R

= 10k Ωconnected to DV

/2, V

REF

= GND, and C

= 100pF, unless otherwise noted.

POWER-SUPPLY REJECTION RATIOvs FREQUENCY CROSSTALK vs FREQUENCY

Figure 48. Figure 49.

SMALL-SIGNAL PULSE RESPONSE SMALL-SIGNAL PULSE RESPONSE

Figure 50. Figure 51.

LARGE-SIGNAL PULSE RESPONSE LARGE-SIGNAL PULSE RESPONSE

Figure 52. Figure 53.

Product Folder Link(s): PGA112 PGA113 PGA116 PGA117

25 s/divm

Output(1V/div)

Supply(5V/div)

1ms/div

1V/div

V =5V

R =10k

C =100pF

VIN

VOUT

10 s/divm

2V/div

Output

Active In

Shutdown

Output

Shutdown

Active

2V/div

10 s/divm

Output

Enable

PGA112 , , PGA113PGA116 , PGA117

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............................................................................................................................................ SBOS424B – MARCH 2008 – REVISED SEPTEMBER 2008

TYPICAL CHARACTERISTICS (continued)At T

= +25 ° C, AV

= DV

= 5V, R

= 10k Ωconnected to DV

/2, V

REF

= GND, and C

= 100pF, unless otherwise noted.

POWER-UP/POWER-DOWN TIMING OUTPUT OVERDRIVE PERFORMANCE

Figure 54. Figure 55.

OUTPUT VOLTAGE vs SHUTDOWN MODE PGA116, PGA117 HARDWARE SHUTDOWN MODE

Figure 56. Figure 57.

Product Folder Link(s): PGA112 PGA113 PGA116 PGA117

SERIAL INTERFACE INFORMATION

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

SCLK

DIN

DOUT

SPIMode0,0(CPOL=0,CPHA=0)

SCLK

DIN

DOUT

1 2 3 45 6 7 8 9 10 11 12 13 14 15 16

SPIMode1,1(CPOL=1,CPHA=1)

SERIAL DIGITAL INTERFACE: SPI MODES

10 Am

PGA116

PGA117

DOUT

DIN

PGA112 , , PGA113PGA116 , PGA117

SBOS424B – MARCH 2008 – REVISED SEPTEMBER 2008 ............................................................................................................................................

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Figure 58. SPI Mode 0,0 and Mode 1,1

Table 2. SPI Mode Setting DescriptionMODE CPOL CPHA CPOL DESCRIPTION CPHA DESCRIPTION

0, 0 0 0

(1)

Clock idles low Data are read on the rising edge of clock. Data change on the falling edge of clock.

1, 1 1 1

(2)

Clock idles high Data are read on the rising edge of clock. Data change on the falling edge of clock.

(1) CPHA = 0 means sample on first clock edge (rising or falling) after a valid CS.(2) CPHA = 1 means sample on second clock edge (rising or falling) after a valid CS.

The PGA uses a standard serial peripheral interface(SPI). Both SPI Mode 0,0 and Mode 1,1 aresupported, as shown in Figure 58 and described inTable 2 .

If there are not even-numbered increments of 16clocks (that is, 16, 32, 64, and so forth) between CSgoing low (falling edge) and CS going high (risingedge), the device takes no action. This conditionprovides reliable serial communication. Furthermore,this condition also provides a way to quickly reset theSPI interface to a known starting condition for datasynchronization. Transmitted data are latched

Figure 59. Digital I/O Structure — PGA116/PGA117internally on the rising edge of CS.

On the PGA116/PGA117, CS, DIN, and SCLK areSchmitt-triggered CMOS logic inputs. DIN has a weakinternal pull-down to support daisy-chaincommunications on the PGA116/PGA117. DOUT is aCMOS logic output. When CS is high, the state ofDOUT is high-impedance. When CS is low, DOUT isdriven as illustrated in Figure 59 .

Product Folder Link(s): PGA112 PGA113 PGA116 PGA117

DOUT

SCLK

DIN

MSP430

SCLK

DIN1 DOUT1

U1 CS

SCLK

DIN2 DOUT2

PGA116/PGA117 PGA116/PGA117

10 Am

PGA112

PGA113

DOUT

DIO

DIN

SERIAL DIGITAL INTERFACE: SPI

DOUT

SCLK

DIN

MSP430

SCLK

DIN1 DOUT1

U1 CS

SCLK

DIO

PGA116/PGA117 PGA112/PGA113

PGA112 , , PGA113PGA116 , PGA117

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............................................................................................................................................ SBOS424B – MARCH 2008 – REVISED SEPTEMBER 2008

On the PGA112/PGA113, there are digital output and used (see Table 4 ) to ensure that data are written ordigital input gates both internally connected to the read in the proper sequence. There is a specialDIO pin. DIN is an input-only gate and DOUT is a daisy-chain NOP command (No OPeration) which,digital output that can give a 3-state output. The DIO when presented to the desired device in thepin has a weak 10 µA pull-down current source to daisy-chain, causes no changes in that respectiveprevent the pin from floating in systems with a device. Detailed timing diagrams for daisy-chainhigh-impedance SPI DOUT line. When CS is high, operation are shown in Figure 65 through Figure 67 .the state of the internal DOUT gate ishigh-impedance. When CS is low, the state of DIOdepends on the previous valid SPI communication;either DIO becomes an output to clock out data or itremains an input to receive data. This structure isshown in Figure 60 .

Figure 61. Daisy-Chain Read/Write Configuration

The PGA112/PGA113 can be used as the last devicein a daisy-chain as shown in Figure 62 if write-onlycommunication is acceptable, because thePGA112/PGA113 have no separate DOUT pin toconnect back to the microcontroller DIN pin in orderto read back data in this configuration.

Figure 60. Digital I/O Structure — PGA112/PGA113

DAISY-CHAIN COMMUNICATIONS

To reduce the number of I/O port pins used on amicrocontroller, the PGA116/PGA117 support SPI

Figure 62. Daisy-Chain Write-Only Configurationdaisy-chain communications with full read/writecapability. A two-device daisy-chain configuration isshown in Figure 61 , although any number of devicescan be daisy-chained. The SPI daisy-chaincommunication uses a common SCLK and CS linefor all devices in the daisy chain, rather than eachdevice requiring a separate CS line. The daisy-chainmode of communication routes data serially througheach device in the chain by using its respective DINand DOUT pins as shown. Special commands are

Product Folder Link(s): PGA112 PGA113 PGA116 PGA117

SCLK

DOUT1

DIN2

tRFI

tSU

tMIN =55ns

SCLKMAX =9.09MHz

tMIN =55ns

tDO

tRFI

10ns

25ns

10ns

PGA112 , , PGA113PGA116 , PGA117

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The maximum SCLK frequency that can be used indaisy-chain operation is directly related to SCLKrise/fall times, DIN setup time, and DOUTpropagation delay. Any number of two or moredevices have the same limitations because it is thetiming considerations between adjacent devices thatlimit the clock speed.

Figure 63 analyzes the maximum SCLK frequency fordaisy-chain mode based on the circuit of Figure 61 . Aclock rise and fall time of 10ns is assumed to allowfor extra bus capacitance that could occur as a resultof multiple devices in the daisy-chain.

Figure 63. Daisy-Chain Maximum SCLKFrequency

Product Folder Link(s): PGA112 PGA113 PGA116 PGA117

SPI SERIAL INTERFACE

Hi-Z

SCLK

DIN

DOUT

SPIRead,Mode=1,1

12345678910 11 12 13 14 15 16

0110101

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

00000000

Hi-Z

000000000

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

D7 D0

D6 D5 D4 D3 D2 D1

G3 G2 G1 G0 CH3 CH2 CH1 CH0

D15 D14 D13 D12 D11 D10 D9 D8

DIO

12345678910 11 12 13 14 15 16

D15 D7 D0

Hi-Z

SCLK

DIN

DOUT

SPIWrite,Mode=0,0

D14 D13 D12 D11 D10 D9 D8 D6 D5 D4 D3 D2 D1

DIO

Hi-Z

SCLK

DIN

DOUT

SPIWrite,Mode=1,1

12345678910 11 12 13 14 15 16

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

DIO

12345678910 11 12 13 14 15 16

Hi-Z

SCLK

DIN

DOUT

SPIRead,Mode=0,0

110101

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

D7 D0

00000000Hi-Z

000000000

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

D6 D5 D4 D3 D2 D1

G3 G2 G1 G0 CH3 CH2 CH1 CH0

D15 D14 D13 D12 D11 D10 D9 D8

DIO

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............................................................................................................................................ SBOS424B – MARCH 2008 – REVISED SEPTEMBER 2008

Figure 64. SPI Serial Interface Timing Diagrams

Product Folder Link(s): PGA112 PGA113 PGA116 PGA117

12 3 456 7 8 9 10 11 12 13 14 15 16

Command U2

SCLK

DOUT

DIN1

DOUT

DIN1

DOUT1

DIN2

DOUT1

DIN2

Daisy-Chain SPI Write, Mode = 0,0

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

Command U1

DOUT Hi-Z Pulled Low by DIN Weak Pull-Down

Command U2

12 3 45 6 7 8 9 10 11 12 13 14 15 16

Command U1

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

DOUT Hi-Z Pulled Low by DIN Weak Pull-Down Command U2

Daisy-ChainSPIWrite,Mode=1,1

DOUT

SCLK

DIN

MSP430

SCLK

DIN1 DOUT1

U1 CS

SCLK

DIN2

PGA116/PGA117 PGA116/PGA117

DOUT2

D7 D0

D14D13 D12 D11 D10 D9 D8D6 D5 D4 D3 D2 D1

D15

D7 D0

D15 D14 D13 D12 D11 D10 D9 D8 D6 D5 D4 D3 D2 D1

D7 D0

D15 D14 D13 D12 D11 D10 D9 D8 D6 D5 D4 D3 D2 D1

D7D0

D15 D14 D13 D12 D11 D10 D9 D8 D6 D5 D4 D3 D2 D1 D7 D0

D15 D14 D13 D12 D11 D10 D9 D8 D6 D5 D4 D3 D2 D1

D7 D0

D15 D14 D13 D12 D11 D10 D9 D8 D6 D5 D4 D3 D2 D1

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Figure 65. SPI Daisy-Chain Write Timing Diagrams

Product Folder Link(s): PGA112 PGA113 PGA116 PGA117

12 3 45 6 7 8 9 10 11 12 13 14 15 16

Command U2

SCLK

DOUT

DIN1

DOUT1

DIN2

Daisy-Chain SPI Read, Mode = 0,0

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

Command U1

DOUT Hi-Z Pulled Low by DIN Weak Pull-Down

Command U2

SCLK

DOUT1

DIN2

DOUT2

DIN

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

DataByteU1

12345678910 11 12 13 14 15 16

DataByteU2

DataByteU1

DOUT

SCLK

DIN

MSP430

SCLK

DIN1 DOUT1

Hi-Z

SCLK

DIN2

PGA116/PGA117 PGA116/PGA117

DOUT2

011111

0000000000011111

0000000000

011111

0000000000

G3 CH0

00000000G2 G1 G0 CH3 CH2 CH1

00000000G3 G2 G1 G0 CH3 CH2 CH1 00000000G3 CH0

G2 G1 G0 CH3 CH2 CH1

CH0

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............................................................................................................................................ SBOS424B – MARCH 2008 – REVISED SEPTEMBER 2008

Figure 66. SPI Daisy-Chain Read Timing Diagram (Mode 0,0)

Product Folder Link(s): PGA112 PGA113 PGA116 PGA117

1 2 3 456 7 8 9 10 11 12 13 14 15 16

Command U2

SCLK

DOUT

DIN1

DOUT1

DIN2

Daisy-Chain SPI Read, Mode = 1,1

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

Command U1

DOUT Hi-Z Pulled Low by DIN Weak Pull-Down

Command U2

SCLK

DOUT1

DIN2

DOUT2

DIN

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

DataByteU1

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

DataByteU2

DataByteU1

DOUT

SCLK

DIN

MSP430

SCLK

DIN1 DOUT1

Hi-Z

SCLK

DIN2

PGA116/PGA117 PGA116/PGA117

DOUT2

011111

0000000000011111

0000000000

011111

0000000000

G3 CH0

00000000G2 G1 G0 CH3 CH2 CH1

00000000

00000000G3 CH0

G2 G1 G0 CH3 CH2 CH1 G3 CH0

G2 G1 G0 CH3 CH2 CH1

PGA112 , , PGA113PGA116 , PGA117

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Figure 67. SPI Daisy-Chain Read Timing Diagram (Mode 1,1)

Product Folder Link(s): PGA112 PGA113 PGA116 PGA117

SPI COMMANDS

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Table 3. SPI Commands (PGA112/PGA113)

(1) (2)

THREE-WIRED15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 SPI COMMAND

01101010 00000000READ

0 0 1 0 1 0 1 0 G3 G2 G1 G0 CH3 CH2 CH1 CH0 WRITE

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NOP WRITE

SDN_DIS11100001 00000000

WRITE

1 1 1 0 0 0 0 1 1 1 1 1 0 0 0 1 SDN_EN WRITE

(1) SDN = Shutdown mode. Enter Shutdown mode by issuing an SDN_EN command. Shutdown mode is cleared (returned to the last validwrite configuration) by a SDN_DIS command or by any valid Write command.(2) POR (Power-on-Reset) value of internal Gain/Channel Select Register is all 0s; this value sets Gain = 1, and Channel = V

CAL

/CH0.

Table 4. SPI Daisy-Chain Commands

(1) (2)

DAISY-CHAIND15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 COMMAND

00010000 00000000NOP

11110001 00000000SDN_DIS

11110001 11110001SDN_EN

01111010 00000000READ

0 0 1 1 1 0 1 0 G3 G2 G1 G0 CH3 CH2 CH1 CH0 WRITE

(1) SDN = Shutdown Mode. Shutdown Mode is entered by an SDN_EN command. Shutdown Mode is cleared (returned to the last validwrite configuration) by a SDN_DIS command or by any valid Write command.(2) POR (Power-on-Reset) value of internal Gain/Channel Register is all 0s; this value sets Gain = 1, V

CAL

/CH0 selected.

Table 5. Gain Selection Bits (PGA112/PGA113)

G3 G2 G1 G0 BINARY GAIN SCOPE GAIN

0 0 0 0 1 10 0 0 1 2 20 0 1 0 4 50 0 1 1 8 100 1 0 0 16 200 1 0 1 32 500 1 1 0 64 1000 1 1 1 128 200

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Table 6. Mux Channel Selection Bits

CH3 CH2 CH1 CH0 PGA112, PGA113 PGA116, PGA117

0 0 0 0 VCAL/CH0 VCAL/CH00 0 0 1 CH1 CH10 0 1 0 X

(1)

CH20 0 1 1 X CH30 1 0 0 X CH40 1 0 1 X CH50 1 1 0 X CH60 1 1 1 X CH71 0 0 0 X CH81 0 0 1 X CH91 0 1 0 X X

(1)

1 0 1 1 Factory Reserved Factory Reserved1 1 0 0 CAL1

(2)

CAL1

(2)

1 1 0 1 CAL2

(3)

CAL2

(3)

1 1 1 0 CAL3

(4)

CAL3

(4)

1 1 1 1 CAL4

(5)

CAL4

(5)

(1) X = channel is not used.(2) CAL1: connects to GND.(3) CAL2: connects to 0.9V

CAL

.(4) CAL3: connects to 0.1V

CAL

.(5) CAL4: connects to V

REF

Product Folder Link(s): PGA112 PGA113 PGA116 PGA117

APPLICATION INFORMATION

FUNCTIONAL DESCRIPTION

VIN+

AVDD

GND

VIN-

Reference

Current

OP AMP: INPUT STAGE

InputVoltage(V)

InputOffsetVoltage( V)m

10 62 3 4 5

AV =5V

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PMOS transistors. The result of this transitionappears as a small input offset voltage transition thatis reflected to the output by the selected PGA gain.The PGA112/PGA113 and PGA116/PGA117 are

This transition may be either increasing orsingle-ended input, single-supply, programmable gain

decreasing, and differs from part to part as describedamplifiers (PGAs) with an input multiplexer.

in Figure 69 and Figure 70 . These figures illustrateMultiplexer channel selection and gain selection are

possible differences in input offset voltage betweendone through a standard SPI interface. The

two different devices when used with AV

= +5V.PGA112/PGA113 have a two-channel input MUX and

Because the exact transition region varies fromthe PGA116/PGA117 have a 10-channel input MUX.

device to device, the Electrical Characteristics tableThe PGA112 and PGA116 provide binary gain

specifies an input offset voltage above and below thisselections (1, 2, 4, 8, 16, 32, 64, 128) and the

input transition region.PGA113 and PGA117 provide scope gain selections(1, 2, 5, 10, 20, 50, 100, 200). All models use asplit-supply architecture with an analog supply, AV

,and a digital supply, DV

. This split-supplyarchitecture allows for ease of interface toanalog-to-digital converters (ADCs) andmicrocontrollers in mixed-supply voltage systems,such as where the analog supply is +5V and thedigital supply is +3V. Four internal calibrationchannels are provided for system-level calibration.The channels are tied to GND, 0.9V

CAL

, 0.1V

CAL

, andV

REF

, respectively. V

CAL

, an external voltageconnected to V

CAL

/CH0, acts as the systemcalibration reference. If V

CAL

is the system ADCreference, then gain and offset calibration on theADC are easily accomplished through the PGA usingonly one MUX input. If calibration is not used, thenV

CAL

/CH0 can be used as a standard MUX input. Allfour versions provide a V

REF

pin that can be tied to

Figure 68. PGA Rail-to-Rail Input Stageground or, for ease of scaling, to midsupply insingle-supply systems where midsupply is used as avirtual ground. The PGA112/PGA113 offer asoftware-controlled shutdown feature for low standbypower. The PGA116/PGA117 offer both hardware-and software-controlled shutdown for low standbypower. The PGA112/PGA113 have a three-wire SPIdigital interface; the PGA116/PGA117 have afour-wire SPI digital interface. The PGA116/117 alsohave daisy-chain capability.

The PGA op amp is a rail-to-rail input and output(RRIO) single-supply op amp. The input topologyuses two separate input stages in parallel to achieverail-to-rail input. As Figure 68 shows, there is aPMOS transistor on each input for operation down toground; there is also an NMOS transistor on each

Figure 69. V

versus Input Voltage — Case 1input in parallel for operation to the positive supplyrail. When the common-mode input voltage (that is,the single-ended input, because this PGA isconfigured internally for noninverting gain) crosses alevel that is typically about 1.5V below the positivesupply, there is a transition between the NMOS and

Product Folder Link(s): PGA112 PGA113 PGA116 PGA117

G=1

PGA112

PGA113

VREF

V /2

VIN0 VIN1

VOUT

CH0

CH1 MUX

VOUT0 =G V AV /2 (G 1)´ - ´ -

IN0 DD

(2)

InputVoltage(V)

InputOffsetVoltage( V)m

10 62 3 4 5

AV =5V

OP AMP: GENERAL GAIN EQUATIONS

V =G (V +AV /2) /2 (G 1)

V =G V + /2,where: /2<G V <+ /2

´ -

OUT1 IN1 DD - ´

´ - ´

AV AV AV

OUT1 IN1 DD DD IN1 DD

G=1

VREF

VIN

VOUT

CH1

V =G V´

OUT IN

(1)

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Figure 72. PGA112/PGA113 Configuration forPositive and Negative Excursions AroundMidsupply Virtual Ground

When: G = 1Figure 70. V

versus Input Voltage — Case 2

Then: V

OUT0

= G × V

IN0

Figure 71 shows the basic configuration for using thePGA as a gain block. V

OUT

is the selected

(3)noninverting gain, depending on the model selected,

Where:for either binary or scope gains.

G = 1, 2, 4, 8, 16, 32, 64, and 128 (binary gains)G = 1, 2, 5, 10, 20, 50, 100, and 200 (scopegains)

Table 7 details the internal typical values for the opamp internal feedback resistor (R

) and op ampinternal input resistor (R

) for both binary and scopegains.

Table 7. Typical R

and R

versus Gain

Binary ScopeGain GainFigure 71. PGA Used as a Gain Block

(V/V) R

(Ω) R

(Ω) (V/V) R

(Ω) R

(Ω)

1 0 3.25k 1 0 3.25k2 3.25k 3.25k 2 3.25k 3.25kWhere:

4 9.75k 3.25k 5 13k 3.25kG = 1, 2, 4, 8, 16, 32, 64, and 128 (binary gains)

8 22.75k 3.25k 10 29.25k 3.25kG = 1, 2, 5, 10, 20, 50, 100, and 200 (scope

16 48.75k 3.25k 20 61.75k 3.25kgains)

32 100.75k 3.25k 50 159.25k 3.25kFigure 72 shows the PGA configuration and gain

64 204.75k 3.25k 100 321.75k 3.25kequations for V

REF

= AV

/2. V

OUT0

is V

OUT

when

128 412.75k 3.25k 200 646.75k 3.25kCH0 is selected and V

OUT1

is V

OUT

when CH1 isselected. Notice the V

REF

pin has no effect for G = 1because the internal feedback resistor, R

, is shortedout. This configuration allows for positive andnegative voltage excursions around a midsupplyvirtual ground.

Product Folder Link(s): PGA112 PGA113 PGA116 PGA117

OP AMP: FREQUENCY RESPONSE VERSUS ANALOG MUX

SR(V/ s)=2 f V (1 10 )m p ´ ´

-6

(4)

Example:

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............................................................................................................................................ SBOS424B – MARCH 2008 – REVISED SEPTEMBER 2008

GAIN

The analog input MUX provides two input channelsTable 8 documents how small-signal bandwidth and for the PGA112/PGA113 and 10 input channels forslew rate change correspond to changes in PGA the PGA116/PGA117. The MUX switches aregain. designed to be break-before-make and therebyeliminate any concerns about shorting the two inputFull power bandwidth (that is, the highest frequency

signal sources together.that a sine wave can pass through the PGA for agiven gain) is related to slew rate by Equation 4 : Four internal MUX CAL channels are included in theanalog MUX for ease of system calibration. TheseCAL channels allow ADC gain and offset errors to becalibrated out. This calibration does not remove theWhere:

offset and gain errors of the PGA for gains greaterSR = Slew rate in V/ µs

than 1, but most systems should see a significantf = Frequency in Hz

increase in the ADC accuracy. In addition, these CALV

= Output peak voltage in volts

channels can be used by the ADC to read theminimum and maximum possible voltages from thePGA. With these minimum and maximum levelsknown, the system architecture can be designed toFor G = 8, then SR = 10.6V/ µs (slew rate rise is

indicate an out-of-range condition on the measuredminimum slew rate).

analog input signals if these levels are everFor a 5V system, choose 0.1V < V

OUT

< 4.9V or

measured.V

OUTPP

= 4.8V or V

OUTP

= 2.4V.

To use the CAL channels, V

CAL

/CH0 must beSR (V/ µs) = 2 πf × V

(1 × 10

– 6

permanently connected to the system ADC reference.10.6 = 2 πf (2.4) (1 × 10

– 6

)→f = 702.9kHz

There is a typical 100k Ωload from V

CAL

/CH0 toThis example shows that a G = 8 configuration

ground. Table 9 illustrates how to use the CALcan produce a 4.8V

sine wave with frequency

channels with V

REF

= ground. Table 10 describes howup to 702.9kHz. This computation only shows the

to use the CAL channels with V

REF

= AV

/2. Thetheoretical upper limit of frequency for this

REF

pin must be connected to a source that isexample, but does not indicate the distortion of

low-impedance for both dc and ac in order tothe sine wave. The acceptable distortion depends

maintain gain and nonlinearity accuracy. Worst-caseon the specific application. As a general

current demand on the V

REF

pin occurs when G = 1guideline, maintain two to three times the

because there is a 3.25k Ωresistor between V

OUT

andcalculated slew rate to minimize distortion on the

REF

. For a 5V system with AV

/2 = 2.5V, the V

REFsine wave. For this example, the application

pin buffer must source and sink 2.5V/3.25k Ω= 0.7mAshould only use G = 8, 4.8V

, up to a frequency

minimum for a V

OUT

that can swing from ground torange of 234kHz to 351kHz, depending upon the

+5V.acceptable distortion. For a given gain and slewrate requirement, check for adequate small-signalbandwidth (typical – 3dB frequency) in order toassure that the frequency of the signal can bepassed without attenuation.

Table 8. Frequency Response versus Gain (C

= 100pF, R

GAIN FREQUENCY FALL RISE 4V

PPGAIN (V/V) (MHz) (V/ µs) (V/ µs) ( µs) ( µs) (V/V) (MHz) (V/ µs) (V/ µs) ( µs) ( µs)

1 10 8 3 2 2.55 1 10 8 3 2 2.55

2 3.8 9 6.4 2 2.6 2 3.8 9 6.4 2 2.6

4 2 12.8 10.6 2 2.6 5 1.8 12.8 10.6 2 2.6

8 1.8 12.8 10.6 2 2.6 10 1.8 12.8 10.6 2.2 2.6

16 1.6 12.8 12.8 2.3 2.6 20 1.3 12.8 9.1 2.3 2.8

32 1.8 12.8 13.3 2.3 3 50 0.9 9.1 7.1 2.4 3.8

64 0.6 4 3.5 3 6 100 0.38 4 3.5 4.4 7

128 0.35 2.5 2.5 4.8 8 200 0.23 2.3 2 6.9 10

Product Folder Link(s): PGA112 PGA113 PGA116 PGA117

10kW

ADC

G=1 RF

Output

Stage

SPI

Interface

REF3225

SCLK

DIO

VOUT

DVDD

AVDD

GND VREF

MSP430

Microcontroller

+3V

VREF

PGA112

PGA113

V /CH0

CAL

CH1

CAL3

CAL4

CAL1

CAL2

0.1VCAL

0.9VCAL

10kW

80kW

MUX

CAL2/3

2.5V ADCRef

0.1 F

BYPASS

0.1 F

BYPASS

0.1 F

BYPASS

PGA112 , , PGA113PGA116 , PGA117

SBOS424B – MARCH 2008 – REVISED SEPTEMBER 2008 ............................................................................................................................................

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Figure 73. Using CAL Channels with V

REF

= Ground

Table 9. Using the MUX CAL Channels with V

REF

= GND(AV

= 3V, DV

= 3V, ADC Ref = 2.5V, and V

REF

= GND)

MUX GAIN OP AMP OP AMPFUNCTION SELECT SELECT MUX INPUT (+In) (V

OUT

) DESCRIPTION

Minimum signal level that theMUX, op amp, and ADC canMinimum Signal CAL1 1 GND GND 50mV

read. Op amp V

OUT

is limitedby negative saturation.90% ADC Ref for system0.9 ×Gain Calibration CAL2 1 2.25V 2.25V full-scale or gain calibration(V

CAL

/CH0)

of the ADC.Maximum signal level thatthe MUX, op amp, and ADCcan read. Op amp V

OUT

is0.9 ×Maximum Signal CAL2 2 2.25V 2.95V limited by positive saturation.(V

CAL

/CH0)

System is limited by ADCmax input of 2.5V (ADC Ref= 2.5V).0.1 × 10% ADC Ref for systemOffset Calibration CAL3 1 0.25V 0.25V(V

CAL

/CH0) offset calibration of the ADC.Minimum signal level that theMUX, op amp, and ADC canMinimum Signal CAL4 1 V

REF

GND 50mV

read. Op amp V

OUT

is limitedby negative saturation.

Product Folder Link(s): PGA112 PGA113 PGA116 PGA117

10kW

ADC

G=1 RF

Output

Stage

SPI

Interface

SCLK

DIO

VOUT

DVDD

AVDD

GND VREF

MSP430

Microcontroller

+3V

VREF

PGA112

PGA113

V /CH0

CAL

CH1

CAL3

CAL4

CAL1

CAL2

0.1VCAL

0.9VCAL

10kW

80kW

MUX

CAL2/3

ADCRef

OPA364

10kW

2.7nF

+3V

CL2

0.1 Fm

100kW

+3V

(1.5V)

0.1 F

BYPASS

0.1 F

BYPASS

0.1 F

BYPASS

0.1 F

BYPASS

PGA112 , , PGA113PGA116 , PGA117

www.ti.com

............................................................................................................................................ SBOS424B – MARCH 2008 – REVISED SEPTEMBER 2008

Figure 74. Using CAL Channels with V

REF

= AV

Table 10. Using the MUX CAL Channels with V

REF

= AV

/2(AV

= 3V, DV

= 3V, ADC Ref = 3V, and V

REF

= 1.5V)

MUX GAIN OP AMP OP AMPFUNCTION SELECT SELECT MUX INPUT (+In) (V

OUT

) DESCRIPTION

Minimum signal level that the MUX,Minimum Signal CAL1 1 GND GND 50mV op amp, and ADC can read. Op ampV

OUT

is limited by negative saturation.0.9 × 90% ADC Ref for system full-scale orGain Calibration CAL2 1 2.7V 2.7V(V

CAL

/CH0) gain calibration of the ADC.Maximum signal level that the MUX,0.9 ×Maximum Signal CAL2 4 or 5 2.25V 2.95V op amp, and ADC can read. Op amp(V

CAL

/CH0)

OUT

is limited by positive saturation.0.1 × 10% ADC Ref for system offsetOffset Calibration CAL3 1 0.3V 0.3V(V

CAL

/CH0) calibration of the ADC.V

REF

Check CAL4 1 V

REF

1.5V 1.5V Midsupply voltage used as V

REF

Product Folder Link(s): PGA112 PGA113 PGA116 PGA117

SYSTEM CALIBRATION USING THE PGA

TransferFunction

withOffsetError+GainError

TransferFunction

withGainErrorOnly

IdealTransferFunction

GainError

VFS_ACTUAL

VFS_IDEAL

AnalogInput

DigitalOutput

V 1LSB-

REF_ADC

0000h

0FFFh

OffsetError VZ_IDEAL

VZ_ACTUAL

PGA112 , , PGA113PGA116 , PGA117

SBOS424B – MARCH 2008 – REVISED SEPTEMBER 2008 ............................................................................................................................................

www.ti.com

In practice, the zero input (0V) or full-scale input(V

REF_ADC

– 1LSB) of ADCs cannot always beAnalog-to-digital converters (ADCs) contain two major

measured because of internal offset error and gainerrors that can be easily removed by calibration at a

error. However, if measurements are made very closesystem level. These errors are gain error and offset

to the full-scale input and the zero input, both zeroerror, as shown in Figure 75 .Figure 75 shows a

and full-scale can be calibrated very accurately withtypical transfer function for a 12-bit ADC. The analog

the assumption of linearity from the calibration pointsinput is on the x-axis with a range from 0V to

to the desired end points of the ADC ideal transfer(V

REF_ADC

– 1LSB), where V

REF_ADC

is the ADC

function. For the zero calibration, choosereference voltage. The y-axis is the hexadecimal

10%V

REF_ADC

; this value should be above the internalequivalent of the digital codes that result from ADC

offset error and sufficiently out of the noise floorconversions. The dotted red line represents an ideal

range of the ADC. For the gain calibration, choosetransfer function with 0000h representing 0V analog

90%V

REF_ADC

; this value should be less than theinput and 0FFFh representing an analog input of

internal gain error and sufficiently below the tolerance(V

REF_ADC

– 1LSB). The solid blue line illustrates the

of V

REF

. These key points can be summarized in thisoffset error. Although the solid blue line includes both

way:offset error and gain error, at an analog input of 0Vthe offset error voltage, V

Z_ACTUAL

, can be measured.

For zero calibration:The dashed black line represents the transfer function

•The ADC cannot read the ideal zero because ofwith gain error. The dashed black line is equivalent to

offset errorthe solid blue line without the offset error, and can be

•Must be far enough above ground to be abovemeasured and computed using V

Z_ACTUAL

and

noise floor and ADC offset errorV

Z_IDEAL

. The difference between the dashed black

•Therefore, choose 10%V

REF_ADC

for zeroline and the dotted red line is the gain error. Gain and

calibrationoffset error can be computed by taking zero input andfull-scale input readings. Using these error

For gain calibration:calculations, compute a calibrated ADC reading to

•The ADC cannot read the ideal full-scale becauseremove the ADC gain and offset error.

of gain error•Must be far enough below full-scale to be belowthe V

REF

tolerance and ADC gain error•Therefore, choose 90%V

REF_ADC

for gaincalibration

Figure 75. ADC Offset and Gain Error

Product Folder Link(s): PGA112 PGA113 PGA116 PGA117

V 90=0.9(V )

REF REF_ADC

(5)

V 10=0.1(V )

REF REF_ADC

(6)

V 90=ADC atV 90

MEAS MEASUREMENT REF

(7)

V 10=ADC atV 10

MEAS MEASUREMENT REF

(8)

G =

MEAS

V 90 V 10-

MEAS MEAS

V 90 V 10-

REF REF

(9)

O =V 10 (V 10 G )- ´

MEAS MEAS REF MEAS

(10)

V =AnyV ADC

AD_MEAS IN MEASUREMENT

(11)

V =

ADC_CAL

V O-

AD_MEAS MEAS

GMEAS

(12)

IdealTransferFunction

TransferFunction

withOffsetError+GainError

V =+5V

REF

OffsetError=+4LSB

GainError=+6LSB

0FFFh(4.99878V)

(4.5114751443V)

(0.5056191443V)

0000h(0V)

0V VIN

DigitalOutput(V )

AD_MEAS

0.5V

(0.1 V )´REF_ADC

4.5V

(0.9 V )´REF_ADC

4.99878V

(V 1LSB)

REF_ADC -

PGA112 , , PGA113PGA116 , PGA117

www.ti.com

............................................................................................................................................ SBOS424B – MARCH 2008 – REVISED SEPTEMBER 2008

The 12-bit ADC example in Figure 76 illustrates thetechnique for calibrating an ADC using a10%V

REF_ADC

and 90%V

REF_ADC

reading whereV

REF_ADC

is the ADC reference voltage. Note that the10%V

REF

reading also contains a gain error becauseit is not a V

= 0 calibration point. First, use the

2. Compute the ADC measured gain. The slope of90%V

REF

and 10%V

REF

points to compute the

the curve connecting the measured 10%V

REF

andmeasured gain error. The measured gain error is then

measured 90%V

REF

point is computed andused to remove the gain error from the 10%V

REF

compared to the slope between the idealreading, giving a measured 10%V

REF

number. The

10%V

REF

and ideal 90%V

REF

. This result is themeasured 10%V

REF

number is used to compute the

measured gain.measured offset error.

3. Compute the ADC measured offset. Themeasured offset is computed by taking thedifference between the measured 10%V

REF

andthe (ideal 10%V

REF

) × (measured gain).

4. Compute the calibrated ADC readings.

Any ADC reading can therefore be calibrated byremoving the gain error and offset error. Themeasured offset is subtracted from the ADC readingand then divided by the measured gain to give aFigure 76. 12-Bit Example of ADC Calibration for

corrected reading. If this calibration is performed on aGain and Offset Error

timed basis, relative to the specific application, gainand offset error over temperature are also removedfrom the ADC reading by calibration.The gain error and offset error in ADC readings canbe calibrated by using 10%V

REF_ADC

and

For example; given:90%V

REF_ADC

calibration points. Because the

•12-Bit ADCcalibration is ratiometric to V

REF_ADC

, the exact value

•ADC Gain Error = +6LSBof V

REF_ADC

does not need to be known in the end

•ADC Offset Error = +4LSBapplication.

•ADC Reference (V

REF_ADC

) = +5VFollow these steps to compute a calibrated ADC

•Temperature = +25 ° Creading:

1. Take the ADC reading at V

= 90% × V

REF

and

Table 11 shows the resulting system accuracy.V

= 10% × V

REF

. The ADC readings for10%V

REF

and 90%V

REF

are taken.

Table 11. Bits of System Accuracy

(1)

(to 0.5LSB)

ADC ACCURACY WITHOUT ADC ACCURACY WITH PGA112V

CALIBRATION CALIBRATION

10%V

REF_ADC

8.80 Bits 12.80 Bits90%V

REF_ADC

7.77 Bits 11.06 Bits

(1) Difference in maximum input offset voltage for V

= 10%V

REF_ADC

and V

= 90%V

REF_ADC

is the reason for different accuracies.

Product Folder Link(s): PGA112 PGA113 PGA116 PGA117

APPLICATIONS: GENERAL-PURPOSE INPUT

VOUT

CH1 DVDD

AVDD

VREF

V /2

(+2.5V)

(+5V)

CH0

VIN0

200mVPP

MUX

VREF_ADC

PGA112

PGA113

G=1

+100mV

-100mV

+2.5V

+2.6V

+2.4V

+2.5V

+4.5V

+0.5V

VOUT0

VIN0 VCH0

VIN1

RIG=20

+4.9625V

+37.5mV

VOUT1

PGA112 , , PGA113PGA116 , PGA117

SBOS424B – MARCH 2008 – REVISED SEPTEMBER 2008 ............................................................................................................................................

www.ti.com

Table 12 summarizes the scaling resistor values forSCALING R

, R

, and R

for different ADC Ref voltages.V

REF_ADC

is the reference voltage used for the ADCFigure 77 is an example application that

connected to the PGA112/PGA113 output. It isdemonstrates the flexibility of the PGA for

assumed the ADC input range is 0V to V

REF_ADC

. Thegeneral-purpose input scaling. V

IN0

is a ± 100mV input

Bipolar Input to Single-Supply Scaling section givesthat is ac-coupled into CH0. The PGA112/PGA113 is

the algorithm to compute resistor values forpowered from a +5V supply voltage, V

, and

references not listed in Table 12 . As a generalconfigured with the V

REF

pin connected to V

guideline, R

should be chosen such that the input(+2.5V). V

CH0

is the ± 100mV input, level-shifted and

on-channel current multiplied by R

is less than orcentered on V

/2 (+2.5V). A gain of 20 is applied to

equal to the input offset voltage. This value ensuresCH0, and because of the PGA113 configuration, the

that the scaling network contributes no more erroroutput voltage at V

OUT

is ± 2V centered on V

than the input offset voltage. Individual applications(+2.5V).

may require other design trade-offs.CH1 is set to G = 1; through a resistive divider andscalar network, we can read ± 5V or 0V. This settingprovides bipolar to single-ended input scaling.

Figure 77. General-Purpose Input Scaling

Product Folder Link(s): PGA112 PGA113 PGA116 PGA117

PGA112 , , PGA113PGA116 , PGA117

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............................................................................................................................................ SBOS424B – MARCH 2008 – REVISED SEPTEMBER 2008

Table 12. Bipolar to Single-Ended Input Scaling

(1) (2)

REF_ADC

(V) V

IN1

(V) CH1 INPUT R

(k Ω) R

(Ω) R

(k Ω)

2.5 – 5 0.047613 9.2 4.81k 100 1.2476135 2.4476132.5 – 10 0.050317 3.16 2.4k 100 1.25031710 2.4503173 – 5 0.058003 13.5 5.76k 100 1.4980035 2.9380033 – 10 0.059303 4.02 2.87k 100 1.49930310 2.9393034.096 – 5 0.082224 37 7.87k 100 2.0483045 4.0143844.096 – 10 0.086018 6.49 3.92k 100 2.05209810 4.0181785 – 5 0.093506 24 965 100 2.4935065 4.8935065 – 10 0.095227 9.2 4.81k 100 2.49522710 4.895227

(1) Scaling is based on 0.02(V

REF_ADC

) to 0.98(V

REF_ADC

), using standard 0.1% resistor values.(2) Assumes symmetrical V

and symmetrical scaling for CH1 input minimum and maximum.

Product Folder Link(s): PGA112 PGA113 PGA116 PGA117

Bipolar Input to Single-Supply Scaling

R =

2 R g´ ´

1 g-

9.23077k =W2 10k 0.315789474´ W ´

1 0.315789474-

R =

R R

B A

R +R

B A

4.81k =W

10k 9.23077kW ´ W

10k +9.23077kW W

10kW

4.81kW

9.2kW

CH1Input

(2.447817V,

0.0474093V)

VIN1

(+5V, 5V)-

VREF_ADC

(2.5V)

APPLICATIONS: HIGH GAIN/WIDE

k =k k

0.96=0.98 0.02

VO VO+ VO-

g=

k V´

VO REF_ADC

2 |V | k- ´´ VREF_ADCIN1 VO

0.315789474= 0.96 2.5´

2 5 0.96 2.5- ´´

PGA112 , , PGA113PGA116 , PGA117

SBOS424B – MARCH 2008 – REVISED SEPTEMBER 2008 ............................................................................................................................................

www.ti.com

Note that this process assumes a symmetrical V

IN1and that symmetrical scaling is used for CH1 inputminimum and maximum values. The following stepsgive the algorithm to compute resistor values forreferences not listed in Table 12 .

d. R

can now be computed from the starting valueof R

and the computed value for R

.Step 1: Choose the following:a. V

REF_ADC

= 2.5V (ADC reference voltage)b. | V

IN1

| = 5

(magnitude of V

, assuming scaling is for ± V

IN1

)c. Choose R

as a standard resistor value. Theinput on-channel current multiplied by R

shouldbe less than the input offset voltage, such that R

Bis not a major source of inaccuracy.

= 10k Ω(select as a starting value forresistors)

d. For the most negative V

IN1

, choose thepercentage (in decimal format) of V

REF_ADCdesired at the ADC input.

VO –

= 0.02

(CH1 input = k

VO –

× V

REF_ADC

when V

IN1

= – V

IN1

)e. For the most positive V

IN1

, choose the percentage Figure 78. Bipolar to Single-Ended InputAlgorithm(in decimal format) of V

REF_ADC

desired at theADC input. Since this scaling is based onsymmetry, k

VO+

must be the same percentageaway from V

REF_ADC

at the upper limit as at the BANDWIDTH CONSIDERATIONSlower limit where k

VO –

is computed.

As a result of the combination of wide bandwidth andk

VO+

= 1 – k

VO –

high gain capability of the PGA112/PGA113 andPGA116/PGA117, there are several printed circuitk

VO+

= 1 – 0.02 = 0.98

board (PCB) design and system recommendations toconsider for optimum application performance.(CH1 input = k

VO+

× V

REF_ADC

when V

IN1

= +V

IN1

)

1. Power-supply bypass. Bypass eachStep 2: Compute the following:

power-supply pin separately. Use a ceramica. To simplify analysis, create one constant called

capacitor connected directly from thek

power-supply pin to the ground pin of the IC onthe same PCB plane. Vias can then be used toconnect to ground and voltage planes. Thisconfiguration keeps parasitic inductive paths outb. A constant, g, is created to simplify resistor value

of the local bypass for the PGA. Good analogcomputations.

design practice dictates the use of a large valuetantalum bypass capacitor on the PCB for eachrespective voltage.

c. R

is now selected from the starting value of R

Band the g constant.

Product Folder Link(s): PGA112 PGA113 PGA116 PGA117

APPLICATIONS: DRIVING/INTERFACING TO

10kW

CDACSAR

ADC

G=1 RF

Output

Stage

SPI

Interface

SCLK

DIO

VOUT

DVDD

AVDD

GND

VREF

+3V

+5V

VREF

PGA112

PGA113

(MSOP-10)

V /CH0

CAL 2

CH1

CAL3

CAL4

CAL1

CAL2

0.1VCAL

0.9VCAL

10kW

80kW

MUX

CAL2/3

100W

FILT

CFILT

(1nF)

CSH

40pF

12-BitSettling 500kHz

16-BitSettling 300kHz

0.1 F

BYPASS

0.1 F

BYPASS

0.1 F

BYPASS

PGA112 , , PGA113PGA116 , PGA117

www.ti.com

............................................................................................................................................ SBOS424B – MARCH 2008 – REVISED SEPTEMBER 2008

2. Signal trace routing. Keep V

OUT

and other low Bypass capacitors greater than 100pF areimpedance traces away from MUX channel inputs recommended. Lower impedances and a bypassthat are high impedance. Poor signal routing can capacitor placed directly at the input MUXcause positive feedback, unwanted oscillations, channels keep crosstalk between channels to aor excessive overshoot and ringing on minimum as a result of parasitic capacitivestep-changing signals. If the input signals are coupling from adjacent PCB traces and pin-to-pinparticularly noisy, separate MUX input channels capacitance.with guard traces on either side of the signaltraces. Connect the guard traces to ground nearthe PGA and at the signal entry point into the

ADCSPCB. On multilayer PCBs, ensure that there are

CDAC SAR ADCs contain an input samplingno parallel traces near MUX input traces on

capacitor, C

, to sample the input signal during aadjacent layers; capacitive coupling from other

sample period as shown in Figure 79 . After thelayers can be a problem. Use ground planes to

sample period, C

is removed from the input signal.isolate MUX input signal traces from signal traces

Subsequent comparisons of the charge stored on C

SHon other layers.

are performed during the ADC conversion process.Additionally, group and route the digital signals

To achieve optimal op amp stability, input signalinto the PGA as far away as possible from the

settling, and the demands for charge from the inputanalog MUX input signals. Most digital signals

signal conditioning circuitry, most ADC applicationsare fast rise/fall time signals with low-impedance

are optimized by the use of a resistor (R

FILT

) anddrive capability that can easily couple into the

capacitor (C

FILT

) filter placed between the op amphigh-impedance inputs of the input MUX

output and ADC input. For the PGA112/PGA113, orchannels. This coupling can create unwanted

the PGA116/PGA117, setting C

FILT

= 1nF and R

FILT

=noise that gains up to V

OUT

100 Ωyields optimum system performance forsampling converters operating at speeds up to3. Input MUX channels and source impedance.

500kHz, depending upon the application settling timeInput MUX channels are high-impedance; when

and accuracy requirements.combined with high gain, the channels can pickup unwanted noise. Keep the input signalsources low-impedance ( < 10k Ω). Also, considerbypassing input MUX channels with a ceramicbypass capacitor directly at the MUX input pin.

Figure 79. Driving/Interfacing to ADCs

Product Folder Link(s): PGA112 PGA113 PGA116 PGA117

POWER SUPPLIES

SHUTDOWN AND POWER-ON-RESET (POR)

10kW

ADC

G=1 RF

Output

Stage

SPI

Interface

SCLK

DIO

VOUT

DVDD

AVDD

GND

VREF

MSP430

Microcontroller

+3V

+5V

VREF

PGA112

PGA113

(MSOP-10)

VCAL/CH0 2

CH1

CAL3

CAL4

CAL1

CAL2

0.1VCAL

0.9VCAL

10kW

80kW

MUX

CAL2/3

PGA112 , , PGA113PGA116 , PGA117

SBOS424B – MARCH 2008 – REVISED SEPTEMBER 2008 ............................................................................................................................................

www.ti.com

At initial power-on, the state of the PGA is G = 1 andChannel 0 active. CAUTION: For most applications,Figure 80 shows a typical mixed-supply voltage

set AV

≥DV

to prevent V

OUT

from drivingsystem where the analog supply, AV

, is +5V and

current into AV

and raising the voltage level ofthe digital supply voltage, DV

, is +3V. The analog

.output stage of the PGA and the SPI interface digitalcircuitry are both powered from DV

. Whenconsidering the power required for DV

, use theElectrical Characteristics table and add any load

The PGA112/PGA113 have a software shutdowncurrent anticipated on V

OUT

; this load current must be

mode, and the PGA116/PGA117 offer both aprovided by DV

. This split-supply architecture

hardware and software shutdown mode. When theensures compatible logic levels with the

PGA is shut down, it goes into a low-power standbymicrocontroller. It also ensures that the PGA output

mode. The Electrical Characteristics table details thecannot run the input for the onboard ADC into an

current draw in shutdown mode with and without theovervoltage condition; this condition could cause

SPI interface being clocked. In shutdown mode, R

Fdevice latch-up and system lock-up, and require

and R

remain connected between V

OUT

and V

REF

.power-supply sequencing. Each supply pin should be

When DV

is less than 1.6V, the digital interface isindividually bypassed with a 0.1 µF ceramic capacitor

disabled and the channel and gain selections aredirectly at the device to ground. If there is only one

held to the respective POR states of Gain = 1 andpower supply in the system, AV

and DV

can both

Channel = V

CAL

/CH0. When DV

is above 1.8V, thebe connected to the same supply; however, it is

digital interface is enabled and the POR gain andrecommended to use individual bypass capacitors

channel states remain unchanged until a valid SPIdirectly at each respective supply pin to a single point

communication is received.ground. V

OUT

is diode-clamped to AV

(as shown inFigure 80 ); therefore, set DV

less than or equal toAV

+ 0.3V. DV

and AV

must be within theoperating voltage range of +2.2V to +5.5V.

Figure 80. Split Power-Supply Architecture: AV

≠DV

Product Folder Link(s): PGA112 PGA113 PGA116 PGA117

PACKAGING INFORMATION

Orderable Device Status (1) Package

Type Package

Drawing Pins Package

Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)

PGA112AIDGSR ACTIVE MSOP DGS 10 2500 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

PGA112AIDGSRG4 ACTIVE MSOP DGS 10 2500 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

PGA112AIDGST ACTIVE MSOP DGS 10 250 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

PGA112AIDGSTG4 ACTIVE MSOP DGS 10 250 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

PGA113AIDGSR ACTIVE MSOP DGS 10 2500 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

PGA113AIDGSRG4 ACTIVE MSOP DGS 10 2500 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

PGA113AIDGST ACTIVE MSOP DGS 10 250 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

PGA113AIDGSTG4 ACTIVE MSOP DGS 10 250 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

PGA116AIPW ACTIVE TSSOP PW 20 70 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

PGA116AIPWG4 ACTIVE TSSOP PW 20 70 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

PGA116AIPWR ACTIVE TSSOP PW 20 2000 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

PGA116AIPWRG4 ACTIVE TSSOP PW 20 2000 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

PGA117AIPW ACTIVE TSSOP PW 20 70 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

PGA117AIPWG4 ACTIVE TSSOP PW 20 70 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

PGA117AIPWR ACTIVE TSSOP PW 20 2000 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

PGA117AIPWRG4 ACTIVE TSSOP PW 20 2000 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

PACKAGE OPTION ADDENDUM

www.ti.com 13-Nov-2008

Addendum-Page 1

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

PACKAGE OPTION ADDENDUM

www.ti.com 13-Nov-2008

Addendum-Page 2

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

PGA112AIDGSR MSOP DGS 10 2500 330.0 12.4 5.3 3.3 1.3 8.0 12.0 Q1

PGA112AIDGST MSOP DGS 10 250 180.0 12.4 5.3 3.3 1.3 8.0 12.0 Q1

PGA113AIDGSR MSOP DGS 10 2500 330.0 12.4 5.3 3.3 1.3 8.0 12.0 Q1

PGA113AIDGST MSOP DGS 10 250 180.0 12.4 5.3 3.3 1.3 8.0 12.0 Q1

PGA116AIPWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1

PGA117AIPWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 5-May-2011

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

PGA112AIDGSR MSOP DGS 10 2500 370.0 355.0 55.0

PGA112AIDGST MSOP DGS 10 250 195.0 200.0 45.0

PGA113AIDGSR MSOP DGS 10 2500 370.0 355.0 55.0

PGA113AIDGST MSOP DGS 10 250 195.0 200.0 45.0

PGA116AIPWR TSSOP PW 20 2000 346.0 346.0 33.0

PGA117AIPWR TSSOP PW 20 2000 346.0 346.0 33.0

PACKAGE MATERIALS INFORMATION

www.ti.com 5-May-2011

Pack Materials-Page 2

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