Parallel NOR Flash Embedded Memory
M29W160ET, M29W160EB
Features
Supply voltage
VCC = 2.7–3.6V (program, erase, read)
Access times
70, 90ns
Program time
10µs per byte/word (TYP)
Memory organization
3 parameter and 31 main blocks
1 boot block (top or bottom location)
Program/erase controller
Embedded byte/word program algorithms
Erase suspend and resume capability
Read or program another block during an ERASE
SUSPEND operation
UNLOCK BYPASS PROGRAM COMMAND
Fast buffered/batch programming
Temporary block unprotect mode
Common Flash interface
64-bit security code
Low power consumption: Standby and automatic
mode
100,000 PROGRAM/ERASE cycles per block
Electronic signature
Manufacturer code: 0020h
Top device code M29W160ET: 22C4h
Bottom device code M29W160EB: 2249h
Packages
48-pin TSOP (N) 12mm x 20mm
48-ball TFBGA (ZA) 6mm x 8mm
64-ball FBGA (ZS) 11mm x 13mm
Automotive grade parts available
16Mb: 3V Embedded Parallel NOR Flash
Features
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m29W_160e.pdf - Rev. C 02/18 EN 1Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2012 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
Part Numbering Information
Devices are shipped from the factory with memory content bits erased to 1. For available options, such as pack-
ages or speed, or for further information, contact your Micron sales representative. Part numbers can be verified at
www.micron.com. Feature and specification comparison by device type is available at www.micron.com/products.
Contact the factory for devices not found.
Table 1: Part Number Information
Part Number
Category Category Details Notes
Device Type M29 = Parallel Flash memory
Operating Voltage W = 2.7 to 3.6V
Device function 160E = 16Mb memory array
Configuration T = Top boot
B = Bottom boot
Speed 7A = 70ns 1
70 = 70 ns 2
80 = 80ns 3
90 = 90ns 4
Package N = 48-pin TSOP, 12mm x 20mm
ZA = 48-ball TFBGA, 6mm x 8mm, 0.80mm pitch
ZS = 64-ball Fortified BGA, 11mm x 13mm, 1mm pitch
Temperature Range 6 = –40° to 85°C
3 = –40°C to 125°C
Voltage Extension Blank = Standard option
S = VCC,min extension to 2.5V of VCC and available only with 80ns speed class option
Shipping Options Blank = Standard packing
T = Tape and reel packing
E = RoHS-compliant package, standard packing
F = RoHS-compliant package, tape and reel packing
Notes: 1. Device speed in conjunction with temperature range = 6 to denote automotive grade (–40° to 85°C) parts.
2. Device speed in conjunction with temperature range = 6 to denote industrial grade (–40° to 85°C) parts, or
in conjunction with temperature range = 3 to denote automotive grade (–40° to 125°C) parts.
3. Access time, automotive device, in conjunction with temperature range = 3 and voltage extension = S.
4. Device speed in conjunction with temperature range = 6 to denote industrial grade (–40° to 85°C) parts.
16Mb: 3V Embedded Parallel NOR Flash
Features
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Contents
Important Notes and Warnings ......................................................................................................................... 7
General Description ......................................................................................................................................... 8
Signal Assignments ......................................................................................................................................... 10
Signal Descriptions ......................................................................................................................................... 13
Memory Organization .................................................................................................................................... 15
Memory Configuration ............................................................................................................................... 15
Memory Map, x8 – 16Mb Density ................................................................................................................ 15
Memory Map, x16 – 16Mb Density .............................................................................................................. 16
Bus Operations ............................................................................................................................................... 17
Read .......................................................................................................................................................... 17
Write .......................................................................................................................................................... 17
Standby and Automatic Standby ................................................................................................................. 17
Output Disable ........................................................................................................................................... 17
Commands .................................................................................................................................................... 18
READ Operations ........................................................................................................................................... 19
READ/RESET Command ............................................................................................................................ 19
READ CFI Command .................................................................................................................................. 19
AUTO SELECT Operations .............................................................................................................................. 20
AUTO SELECT Command ........................................................................................................................... 20
Read Device ID ............................................................................................................................................... 20
Block and Chip Protection .............................................................................................................................. 21
BLOCK PROTECT Command ...................................................................................................................... 21
Block Protection Using Programmer Equipment .......................................................................................... 22
In-System Block Protection ......................................................................................................................... 24
BYPASS Operations ......................................................................................................................................... 26
UNLOCK BYPASS Command ...................................................................................................................... 26
UNLOCK BYPASS RESET Command ............................................................................................................ 26
PROGRAM Operations .................................................................................................................................... 26
PROGRAM Command ................................................................................................................................ 26
UNLOCK BYPASS PROGRAM Command ..................................................................................................... 26
ERASE Operations .......................................................................................................................................... 27
CHIP ERASE Command .............................................................................................................................. 27
BLOCK ERASE Command ........................................................................................................................... 27
ERASE SUSPEND Command ....................................................................................................................... 28
ERASE RESUME Command ........................................................................................................................ 28
Status Register ................................................................................................................................................ 29
Data Polling Bit (DQ7) ................................................................................................................................ 29
Toggle Bit (DQ6) ......................................................................................................................................... 29
Error Bit (DQ5) ........................................................................................................................................... 29
Erase Timer Bit (DQ3) ................................................................................................................................. 30
Alternative Toggle Bit (DQ2) ........................................................................................................................ 30
Absolute Ratings and Operating Conditions ..................................................................................................... 33
DC Characteristics .......................................................................................................................................... 35
Read AC Characteristics .................................................................................................................................. 36
Write AC Characteristics ................................................................................................................................. 38
Program/Erase Characteristics ........................................................................................................................ 42
Reset Characteristics ...................................................................................................................................... 43
Package Dimensions ....................................................................................................................................... 44
Revision History ............................................................................................................................................. 47
Rev. C – 2/18 ............................................................................................................................................... 47
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Rev. B – 06/13 ............................................................................................................................................. 47
Rev. A – 07/12 ............................................................................................................................................. 47
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Features
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List of Figures
Figure 1: Logic Diagram ................................................................................................................................... 9
Figure 2: 48-Pin TSOP 160ET/B ...................................................................................................................... 10
Figure 3: 48-Ball TFBGA 160ET/B ................................................................................................................... 11
Figure 4: 64-Ball FBGA 160ET/B ..................................................................................................................... 12
Figure 5: Block Protect Flowchart – Programmer Equipment ........................................................................... 22
Figure 6: Chip Unprotect Flowchart – Programmer Equipment ....................................................................... 23
Figure 7: Block Protect Flowchart – In-System Equipment ............................................................................... 24
Figure 8: Chip Protection Flowchart – In-System Equipment ........................................................................... 25
Figure 9: Data Polling Flowchart .................................................................................................................... 31
Figure 10: Data Toggle Flowchart ................................................................................................................... 32
Figure 11: AC Measurement Load Circuit ....................................................................................................... 34
Figure 12: AC Measurement I/O Waveform ..................................................................................................... 34
Figure 13: Random AC Timing ....................................................................................................................... 37
Figure 14: WE#-Controlled AC Timing ............................................................................................................ 39
Figure 15: CE#-Controlled AC Timing ............................................................................................................. 41
Figure 16: Reset/Block Temporary Unprotect AC Waveforms ........................................................................... 43
Figure 17: 48-Pin TSOP – 12mm x 20mm ........................................................................................................ 44
Figure 18: 48-Ball TFBGA – 6mm x 8mm ......................................................................................................... 45
Figure 19: 64-Ball FBGA – 11mm x 13mm ....................................................................................................... 46
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Features
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List of Tables
Table 1: Part Number Information ................................................................................................................... 2
Table 2: Signal Names ...................................................................................................................................... 9
Table 3: Signal Descriptions ........................................................................................................................... 13
Table 4: x8 Top Boot, Blocks [34:0] .................................................................................................................. 15
Table 5: x8 Bottom Boot, Blocks [34:0] ............................................................................................................ 15
Table 6: x16 Top Boot, Blocks [34:0] ................................................................................................................ 16
Table 7: x16 Bottom Boot, Blocks [34:0] .......................................................................................................... 16
Table 8: Bus Operations ................................................................................................................................. 17
Table 9: Commands – 16-Bit Mode (BYTE# = VIL) ............................................................................................ 18
Table 10: Commands – 8-Bit Mode (BYTE# = VIL) ............................................................................................ 18
Table 11: Read Electronic Signature ............................................................................................................... 20
Table 12: Block and Chip Protection Signal Settings ........................................................................................ 21
Table 13: Status Register Bits .......................................................................................................................... 30
Table 14: Absolute Maximum/Minimum Ratings ............................................................................................ 33
Table 15: Operating Conditions ...................................................................................................................... 33
Table 16: Input/Output Capacitance .............................................................................................................. 34
Table 17: DC Current Characteristics .............................................................................................................. 35
Table 18: DC Voltage Characteristics .............................................................................................................. 35
Table 19: Read AC Characteristics .................................................................................................................. 36
Table 20: WE#-Controlled Write AC Characteristics ......................................................................................... 38
Table 21: CE#-Controlled Write AC Characteristics ......................................................................................... 40
Table 22: Program/Erase Times and Endurance Cycles ................................................................................... 42
Table 23: Reset/Block Temporary Unprotect AC Characteristics ...................................................................... 43
16Mb: 3V Embedded Parallel NOR Flash
Features
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Important Notes and Warnings
Micron Technology, Inc. ("Micron") reserves the right to make changes to information published in this document,
including without limitation specifications and product descriptions. This document supersedes and replaces all
information supplied prior to the publication hereof. You may not rely on any information set forth in this docu-
ment if you obtain the product described herein from any unauthorized distributor or other source not authorized
by Micron.
Automotive Applications. Products are not designed or intended for use in automotive applications unless specifi-
cally designated by Micron as automotive-grade by their respective data sheets. Distributor and customer/distrib-
utor shall assume the sole risk and liability for and shall indemnify and hold Micron harmless against all claims,
costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of
product liability, personal injury, death, or property damage resulting directly or indirectly from any use of non-
automotive-grade products in automotive applications. Customer/distributor shall ensure that the terms and con-
ditions of sale between customer/distributor and any customer of distributor/customer (1) state that Micron
products are not designed or intended for use in automotive applications unless specifically designated by Micron
as automotive-grade by their respective data sheets and (2) require such customer of distributor/customer to in-
demnify and hold Micron harmless against all claims, costs, damages, and expenses and reasonable attorneys'
fees arising out of, directly or indirectly, any claim of product liability, personal injury, death, or property damage
resulting from any use of non-automotive-grade products in automotive applications.
Critical Applications. Products are not authorized for use in applications in which failure of the Micron compo-
nent could result, directly or indirectly in death, personal injury, or severe property or environmental damage
("Critical Applications"). Customer must protect against death, personal injury, and severe property and environ-
mental damage by incorporating safety design measures into customer's applications to ensure that failure of the
Micron component will not result in such harms. Should customer or distributor purchase, use, or sell any Micron
component for any critical application, customer and distributor shall indemnify and hold harmless Micron and
its subsidiaries, subcontractors, and affiliates and the directors, officers, and employees of each against all claims,
costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of
product liability, personal injury, or death arising in any way out of such critical application, whether or not Mi-
cron or its subsidiaries, subcontractors, or affiliates were negligent in the design, manufacture, or warning of the
Micron product.
Customer Responsibility. Customers are responsible for the design, manufacture, and operation of their systems,
applications, and products using Micron products. ALL SEMICONDUCTOR PRODUCTS HAVE INHERENT FAIL-
URE RATES AND LIMITED USEFUL LIVES. IT IS THE CUSTOMER'S SOLE RESPONSIBILITY TO DETERMINE
WHETHER THE MICRON PRODUCT IS SUITABLE AND FIT FOR THE CUSTOMER'S SYSTEM, APPLICATION, OR
PRODUCT. Customers must ensure that adequate design, manufacturing, and operating safeguards are included
in customer's applications and products to eliminate the risk that personal injury, death, or severe property or en-
vironmental damages will result from failure of any semiconductor component.
Limited Warranty. In no event shall Micron be liable for any indirect, incidental, punitive, special or consequential
damages (including without limitation lost profits, lost savings, business interruption, costs related to the removal
or replacement of any products or rework charges) whether or not such damages are based on tort, warranty,
breach of contract or other legal theory, unless explicitly stated in a written agreement executed by Micron's duly
authorized representative.
16Mb: 3V Embedded Parallel NOR Flash
Important Notes and Warnings
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General Description
The M29W160ET/B (2Mb x8 or 1Mb x16) is a nonvolatile device that can be read, erased
and reprogrammed. These operations can be performed using a single low voltage (2.7–
3.6V) supply. On power-up the memory defaults to read mode where it can be read in
the same way as a ROM or EPROM.
The device is divided into blocks that can be erased independently to preserve valid da-
ta while old data is erased. Each block can be protected independently to prevent acci-
dental PROGRAM or ERASE commands from modifying the memory. PROGRAM and
ERASE commands are written to the command interface of the memory. An on-chip
program/erase controller simplifies the process of programming or erasing the memory
by taking care of all of the special operations that are required to update the memory
contents.
The end of a PROGRAM or ERASE operation can be detected and any error conditions
identified. The command set required to control the memory is consistent with JEDEC
standards.
The blocks in the memory are asymmetrically arranged. The first or last 64KB have been
divided into four additional blocks. The 16KB boot block can be used for a small initiali-
zation code to start the microprocessor, the two 8 KB parameter blocks can be used for
parameter storage, and the remaining 32KB is a small main block where the application
may be stored.
CE#, OE#, and WE# signals control the bus operation. They enable simple connection to
most microprocessors, often without additional logic.
The device supplied with all the bits erased (set to 1).
16Mb: 3V Embedded Parallel NOR Flash
General Description
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Figure 1: Logic Diagram
VCC
A[19:0]
WE#
DQ[14:0]
DQ15/A-1
VSS
15
CE#
OE#
RST#
BYTE#
RY/BY#
20
Table 2: Signal Names
Name Description Type
A[19:0] Address inputs Input
CE# Chip enable Input
OE# Output enable Input
WE# Write enable Input
BYTE# Byte/word organization select Input
RST# Reset/block temporary unprotect Input
DQ[7:0] Data I/O I/O
DQ[14:8] Data I/O I/O
DQ15/A-1 Data I/O or address input I/O
RY/BY# Ready/busy output Output
VCC Core power supply Supply
VSS Ground Supply
NC Not connected internally
16Mb: 3V Embedded Parallel NOR Flash
General Description
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Signal Assignments
Figure 2: 48-Pin TSOP 160ET/B
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A15
A14
A13
A12
A11
A10
A9
A8
A19
RFU
WE#
RST#
RFU
RFU
RY/BY#
A18
A17
A7
A6
A5
A4
A3
A2
A1
A16
BYTE#
VSS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
VSS
CE#
A0
Note: 1. RFU = reserved for future use.
16Mb: 3V Embedded Parallel NOR Flash
Signal Assignments
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Figure 3: 48-Ball TFBGA 160ET/B
A
B
C
D
E
F
G
H
A
B
C
D
E
F
G
H
1
A3
A4
A2
A1
A0
CE#
OE#
VSS
1
A3
A4
A2
A1
A0
CE#
OE#
VSS
2
A7
A17
A6
A5
D0
D8
D9
D1
2
A7
A17
A6
A5
D0
D8
D9
D1
3
RY/BY#
RFU
A18
RFU
D2
D10
D11
D3
3
RY/BY#
RFU
A18
RFU
D2
D10
D11
D3
4
WE#
RST#
RFU
A19
D5
D12
VCC
D4
4
WE#
RST#
RFU
A19
D5
D12
VCC
D4
5
A9
A8
A10
A11
D7
D14
D13
D6
5
A9
A8
A10
A11
D7
D14
D13
D6
6
A13
A12
A14
A15
A16
BYTE#
D15/A-1
VSS
6
A13
A12
A14
A15
A16
BYTE#
D15/A-1
VSS
Top view – ball side down Bottom view – ball side up
Note: 1. RFU = reserved for future use.
16Mb: 3V Embedded Parallel NOR Flash
Signal Assignments
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Figure 4: 64-Ball FBGA 160ET/B
A
B
C
D
E
F
G
H
A
B
C
D
E
F
G
H
1
RFU
RFU
RFU
RFU
RFU
VCC
RFU
RFU
1
RFU
RFU
RFU
RFU
RFU
VCC
RFU
RFU
2
A3
A4
A2
A1
A0
CE#
OE#
VSS
2
A3
A4
A2
A1
A0
CE#
OE#
VSS
3
A7
A17
A6
A5
D0
D8
D9
D1
3
A7
A17
A6
A5
D0
D8
D9
D1
4
RY/BY#
VPP/WP#
A18
RFU
D2
D10
D11
D3
4
RY/BY#
VPP/WP#
A18
RFU
D2
D10
D11
D3
5
WE#
RST#
RFU
A19
D5
D12
VCC
D4
5
WE#
RST#
RFU
A19
D5
D12
VCC
D4
6
A9
A8
A10
A11
D7
D14
D13
D6
6
A9
A8
A10
A11
D7
D14
D13
D6
7
A13
A12
A14
A15
A16
BYTE#
D15/A-1
VSS
7
A13
A12
A14
A15
A16
BYTE#
D15/A-1
VSS
8
RFU
RFU
RFU
VCC
VSS
RFU
RFU
RFU
8
RFU
RFU
RFU
VCC
VSS
RFU
RFU
RFU
Top view – ball side down Bottom view – ball side up
Note: 1. RFU = reserved for future use.
16Mb: 3V Embedded Parallel NOR Flash
Signal Assignments
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Signal Descriptions
The table below is a comprehensive list of signals for this device family. All signals listed
may not be supported on this device. See Signal Assignments for information specific to
this device.
Table 3: Signal Descriptions
Name Type Description
A[MAX:0] Input Address: Selects the cells in the memory array to access during READ operations. During
WRITE operations, controls the commands sent to the command interface of the program/
erase controller.
CE# Input Chip enable: Activates the memory, enabling READ and WRITE operations. When CE# is
HIGH, all other pins are ignored.
OE# Input Output enable: Controls the bus READ operation of the memory.
WE# Input Write enable: Controls the bus WRITE operation of the command interface.
BYTE# Input Byte/word organization select: Switches between x8 and x16 bus modes. When BYTE# is
LOW, the device is in x8 mode; when HIGH, the device is in x16 mode.
RST# Input Reset/block temporary unprotect: Applies a hardware reset to the memory or temporarily
removes protection from all blocks that have been protected. A hardware reset is achieved
by holding RST# LOW for at least tPLPX. When RST# goes HIGH, the memory is ready for
READ and WRITE operations after tPHEL or tRHEL, whichever occurs last.
Holding RST# at VID temporarily unprotects the protected blocks so that PROGRAM and
ERASE operations are possible on all blocks. The transition from HIGH to VID must be slower
than tPHPHH.
DQ[7:0] I/O Data I/O: Outputs the data stored at the selected address during READ operations. During
WRITE operations, represents the commands sent to the command interface of the program/
erase controller.
DQ[14:8] I/O Data I/O: Outputs data stored at the selected address during a READ operation when BYTE#
is HIGH. When BYTE# is LOW, these pins are not used and are High-Z. During a WRITE opera-
tion, the command register does not use these bits. When reading the status register, these
bits should be ignored.
DQ15/A-1 I/O Data I/O or address input: When BYTE# is HIGH, this pin behaves as a data I/O pin,
DQ[14:8]. When BYTE# is LOW, this pin behaves as an address pin; DQ15/A-1 LOW selects the
LSB of the word on the other addresses, DQ15/A-1 HIGH selects the MSB. Throughout the
text, consider references to data I/O to include this pin when BYTE# is HIGH and consider ref-
erences to address inputs to include this pin when BYTE# is LOW, except when stated explicit-
ly otherwise.
RY/BY# Output Ready/busy: Open-drain output that can be used to identify when the device can be read.
RY/BY# is High-Z during read, auto select, and erase suspend modes. After a hardware reset,
a READ or WRITE operation cannot begin until RY/BY# becomes High-Z.
During a PROGRAM or ERASE operation, RY/BY# is LOW and remains LOW during READ/
RESET commands or hardware resets until the memory is ready to enter read mode.
The use of an open-drain output enables the RY/BY# pins from several memory devices to be
connected to a single pull-up resistor. A LOW indicates that one or more of the devices is
busy.
16Mb: 3V Embedded Parallel NOR Flash
Signal Descriptions
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Table 3: Signal Descriptions (Continued)
Name Type Description
VCC Supply Supply voltage: Provides the power supply for device operations. The command interface is
disabled when VCC <= VLKO. This prevents a WRITE operation from accidentally damaging the
data during power-up, power-down, and power surges. If the program/erase controller is
programming or erasing during this time, the operation aborts, and the contents being al-
tered will be invalid. See Note 1.
VSS Supply Ground: All VSS pins must be connected to the system ground.
RFU Reserved for future use: RFUs should be not connected.
Note: 1. A 0.1μF capacitor should be connected between VCC and VSS to decouple the current
surges from the power supply. The PCB track widths must be sufficient to carry the cur-
rents required during PROGRAM and ERASE operations.
16Mb: 3V Embedded Parallel NOR Flash
Signal Descriptions
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Memory Organization
Memory Configuration
The main memory array is divided into 64KB blocks.
The blocks in the memory are asymmetrically arranged. The first or last 64KB of memo-
ry has been divided into four additional blocks. The 16KB boot block can be used for
small initialization code to start the microprocessor, the two 8KB parameter blocks can
be used for parameter storage and the remaining 32KB small main block can be used
for application storage.
Memory Map, x8 – 16Mb Density
Table 4: x8 Top Boot, Blocks [34:0]
Block Block Size
Address Range
Start End
34 16KB 001F C000 001F FFFF
33 8KB 001F A000 001F BFFF
32 8KB 001F 8000 001F 9FFF
31 32KB 001F 0000 001F 7FFF
30 64KB 001E 0000 001E FFFF
2 64KB 0002 0000 0002 FFFF
1 64KB 0001 0000 0001 FFFF
0 64KB 0000 0000 0000 FFFF
Table 5: x8 Bottom Boot, Blocks [34:0]
Block Block Size
Address Range
Start End
34 64KB 001F 0000 001F FFFF
33 64KB 001E 0000 001E FFFF
32 64KB 001D 0000 001D FFFF
4 64KB 0001 0000 0001 FFFF
3 32KB 0000 8000 0000 FFFF
2 8KB 0000 6000 0000 7FFF
1 8KB 0000 4000 0000 5FFF
0 16KB 0000 0000 0000 3FFF
16Mb: 3V Embedded Parallel NOR Flash
Memory Organization
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Memory Map, x16 – 16Mb Density
Table 6: x16 Top Boot, Blocks [34:0]
Block Block Size
Address Range
Start End
34 8KW 000F E000 000F FFFF
33 4KW 000F D000 000F DFFF
32 4KW 000F C000 000F CFFF
31 16KW 000F 8000 000F BFFF
30 32KW 001E 0000 001E FFFF
2 32KW 0001 0000 0001 7FFF
1 32KW 0008 0000 0000 FFFF
0 32KW 0000 0000 0000 7FFF
Table 7: x16 Bottom Boot, Blocks [34:0]
Block Block Size
Address Range
Start End
34 32KW 000F 8000 000F FFFF
33 32KW 000F 0000 000F 7FFF
32 32KW 000E 8000 000E FFFF
4 32KW 0000 8000 0000 FFFF
3 16KW 0000 4000 0000 7FFF
2 4KW 0000 3000 0000 3FFF
1 4KW 0000 2000 0000 2FFF
0 8KW 0000 0000 0000 1FFF
16Mb: 3V Embedded Parallel NOR Flash
Memory Organization
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Bus Operations
Table 8: Bus Operations
Notes 1 and 2 apply to entire table
Operation CE# OE# WE#
8-Bit Mode 16-Bit Mode
A[MAX:0],
DQ15/A-1 DQ[14:8] DQ[7:0] A[MAX:0]
DQ15/A-1,
DQ[14:0]
READ L L H Cell address High-Z Data output Cell address Data output
WRITE L H L Command address High-Z Data input4Command address Data input4
STANDBY H X X X High-Z High-Z X High-Z
OUTPUT
DISABLE
X H H X High-Z High-Z X High-Z
Notes: 1. Typical glitches of less than 5ns on CE# and WE# are ignored by the device and do not
affect bus operations.
2. H = Logic level HIGH (VIH); L = Logic level LOW (VIL); X = HIGH or LOW.
3. If WP# = LOW, the highest/lowest block remains protected, depending on the line item.
4. Data input is required when issuing a command sequence or performing data polling or
block protection.
Read
Bus READ operations read from the memory cells, registers, or CFI space. A valid READ
operation requires setting the appropriate address on the address inputs, taking CE#
and OE# LOW and holding WE# HIGH. Data I/O signals output the value.
Write
Bus WRITE operations write to the command interface. A valid WRITE operation re-
quires setting the appropriate address on the address inputs. These are latched by the
command interface on the falling edge of CE# or WE#, whichever occurs last. Values on
data I/O signals are latched by the command interface on the rising edge of CE# or
WE#, whichever occurs first. OE# must remain HIGH during the entire operation.
Standby and Automatic Standby
When the device is in read mode, driving CE# HIGH places the device in standby mode
and drives data I/Os to High-Z. Supply current is reduced to standby (ICC2), by holding
CE# within VCC ±0.2V.
During PROGRAM or ERASE operations, the device continues to use the program/erase
supply current (ICC3) until the operation completes.
Automatic standby enables low power consumption during read mode. When CMOS
levels (VCC ± 0.2 V) drive the bus, and following a READ operation and a period of inac-
tivity specified in DC Characteristics, the memory enters automatic standby as internal
supply current is reduced to ICC2. Data I/O signals still output data if a READ operation
is in progress.
Output Disable
Data I/Os are High-Z when OE# is HIGH.
16Mb: 3V Embedded Parallel NOR Flash
Bus Operations
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Commands
All bus WRITE operations to the memory are interpreted by the command interface.
Commands consist of one or more sequential bus WRITE operations. Failure to observe
a valid sequence of bus WRITE operations will result in the memory returning to read
mode. The long command sequences are imposed to maximize data security.
The address used for the commands changes, depending on whether the memory is in
16-bit or 8-bit mode. See the x8 and x16 command tables, depending on the configura-
tion that is being used, for a summary of the commands.
Table 9: Commands – 16-Bit Mode (BYTE# = VIL)
Command Length
Bus WRITE Operations
1st 2nd 3rd 4th 5th 6th
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
READ/RESET 1 X F0
3 555 AA 2AA 55 X F0
AUTO SELECT 3 555 AA 2AA 55 555 90
PROGRAM 4 555 AA 2AA 55 555 A0 PA PD
UNLOCK BY-
PASS
3 555 AA 2AA 55 555 20
UNLOCK BY-
PASS PRO-
GRAM
2 X A0 PA PD
UNLOCK BY-
PASS RESET
2 X 90 X 00
CHIP ERASE 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10
BLOCK ERASE 6+ 555 AA 2AA 55 555 80 555 AA 2AA 55 BA 30
ERASE SUS-
PEND
1 X B0
ERASE RESUME 1 X 30
READ CFI
QUERY
1 55 98
Note: 1. X = " Don’t Care;" PA = Program address; PD = Program data; BA = Any address in the
block. All values in the table are in hexadecimal. The command interface only uses A-1,
A0–A10, and DQ0–DQ7 to verify the commands; A11–A20, DQ8–DQ14, and DQ15 are
"Don't Care." DQ15A-1 is A-1 when BYTE# is VIL or DQ15 when BYTE# is VIH.
Table 10: Commands – 8-Bit Mode (BYTE# = VIL)
Command Length
Bus WRITE Operations
1st 2nd 3rd 4th 5th 6th
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
READ/RESET 1 X F0
3 AAA AA 555 55 X F0
AUTO SELECT 3 AAA AA 555 55 AAA 90
16Mb: 3V Embedded Parallel NOR Flash
Commands
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Table 10: Commands – 8-Bit Mode (BYTE# = VIL) (Continued)
Command Length
Bus WRITE Operations
1st 2nd 3rd 4th 5th 6th
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
PROGRAM 4 AAA AA 555 55 AAA A0 PA PD
UNLOCK BY-
PASS
3 AAA AA 555 55 AAA 20
UNLOCK BY-
PASS PRO-
GRAM
2 X A0 PA PD
UNLOCK BY-
PASS RESET
2 X 90 X 00
CHIP ERASE 6 AAA AA 555 55 AAA 80 AAA AA 555 55 AAA 10
BLOCK ERASE 6+ AAA AA 555 55 AAA 80 AAA AA 555 55 BA 30
ERASE SUS-
PEND
1 X B0
ERASE RE-
SUME
1 X 30
READ CFI
QUERY
1 55 98
Note: 1. X = " Don’t Care;" PA = Program address; PD = Program data; BA = Any address in the
block. All values in the table are in hexadecimal. The command interface only uses A-1,
A0–A10, and DQ0–DQ7 to verify the commands; A11–A20, DQ8–DQ14, and DQ15 are
"Don't Care." DQ15A-1 is A-1 when BYTE# is VIL or DQ15 when BYTE# is VIH.
READ Operations
READ/RESET Command
The READ/RESET (F0h) command returns the device to read mode and resets the errors
in the status register. One or three bus WRITE operations can be used to issue the
READ/RESET command.
To return the device to read mode, this command can be issued between bus WRITE
cycles before the start of a PROGRAM or ERASE operation. If the READ/RESET com-
mand is issued during the timeout of a BLOCK ERASE operation, the device requires up
to 10μs to abort, during which time no valid data can be read.
READ CFI Command
The READ CFI (98h) command puts the device in read CFI mode and is valid only when
the device is in read array or auto select mode. One bus WRITE cycle is required to issue
the command.
Once in read CFI mode, bus READ operations will output data from the CFI memory
area. A READ/RESET command must be issued to return the device to the previous
mode (read array or auto select ). A second READ/RESET command is required to put
the device in read array mode from auto select mode.
16Mb: 3V Embedded Parallel NOR Flash
READ Operations
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AUTO SELECT Operations
AUTO SELECT Command
At power-up or after a hardware reset, the device is in read mode. It can then be put in
auto select mode by issuing an AUTO SELECT (90h) command or by applying VID to A9.
Auto select mode enables the following device information to be read:
Electronic signature, which includes manufacturer and device code information, as
shown in the Read Electronic Signature table.
Block protection, which includes the block protection status and extended memory
block protection indicator, as shown in the Block Protection table.
Electronic signature or block protection information is read by executing a READ opera-
tion with control signals and addresses set.
Auto select mode can be used by the programming equipment to automatically match a
device with the application code to be programmed.
Three consecutive bus WRITE operations are required to issue an AUTO SELECT com-
mand. The device remains in auto select mode until a READ/RESET or READ CFI com-
mand is issued.
The device cannot enter auto select mode when a PROGRAM or ERASE operation is in
progress (RY/BY# LOW). However, auto select mode can be entered if the PROGRAM or
ERASE operation has been suspended by issuing a PROGRAM SUSPEND or ERASE SUS-
PEND command.
Auto select mode is exited by performing a reset. The device returns to read mode un-
less it entered auto select mode after an ERASE SUSPEND or PROGRAM SUSPEND
command, in which case it returns to erase or program suspend mode.
Read Device ID
Table 11: Read Electronic Signature
Note 1 applies to entire table
READ Cycle CE# OE# WE#
Address Input Data I/O
8-Bit/16-Bit 8-Bit Only 16-Bit Only
A[MAX:10] A9 A[8:2] A1 A0 DQ[14:8] DQ[7:0]
DQ[15]/A-1,
DQ[14:0]
Manufacturer code L L H X VID X L L High-Z 20h 0020h
Device code L L H X VID X L H High-Z C4h2
49h3
22C4h2
2249h3
Notes: 1. H = Logic level HIGH (VIH); L = Logic level LOW (VIL); X = HIGH or LOW.
2. M29W160ET.
3. M29W160EB.
16Mb: 3V Embedded Parallel NOR Flash
AUTO SELECT Operations
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Block and Chip Protection
Block protection can be used to prevent any operation from modifying the data stored
in the Flash. Each block can be protected individually. Once protected, PROGRAM and
ERASE operations on the block fail to change the data.
Do not allow microprocessor service interrupts to interfere with timing, and do not
abort an operation before its completion. The CHIP UNPROTECT operation can take
several seconds, and a user message should be provided to show progression. (Refer to
the following flowcharts for details.)
Unlike the command interface of the program/erase controller, techniques for protect-
ing and unprotecting blocks change from one Flash memory supplier to another. Care
should be taken when changing drivers for one part to work on another.
BLOCK PROTECT Command
There are three techniques that can be used to control block protection. These are pro-
grammer technique, in-system technique, and temporary unprotect. Temporary unpro-
tect is controlled by RST#.
Unlike the command interface of the program/erase controller, the techniques for pro-
tecting and unprotecting blocks change between different Flash memory suppliers.
Table 12: Block and Chip Protection Signal Settings
Signals Block Protect Chip Unprotect
Verify Block Protec-
tion
Verify Block Unpro-
tect
CE# L VID L L
OE# VID VID L L
WE# L pulse L pulse H H
Address Input, 8-Bit and 16-Bit
A[MAX:16] Block base address X Block base address Block base address
A15 H
A14 X
A13 X
A12 H
A11 X X X X
A10 X X X X
A9 VID VID VID VID
A8 X X X X
A7 X X X X
A6 X X L H
A5 X X X X
A4 X X X X
A3 X X X X
A2 X X X X
A1 X X H H
16Mb: 3V Embedded Parallel NOR Flash
Block and Chip Protection
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Table 12: Block and Chip Protection Signal Settings (Continued)
Signals Block Protect Chip Unprotect
Verify Block Protec-
tion
Verify Block Unpro-
tect
A0 X X L L
Data I/O, 8-Bit and 16-Bit
DQ[15]/A-1, and
DQ[14:0]
X X Pass = XX01h Retry = XX01h
X X Retry = XX00h Pass = XX00h
Note: 1. H = Logic level HIGH (VIH); L = Logic level LOW (VIL); X = HIGH or LOW.
Block Protection Using Programmer Equipment
The programmer technique uses high voltage levels (VID) on some of the bus pins.
These cannot be achieved using a standard microprocessor bus; therefore, the techni-
que is recommended only for use in programming equipment.
To protect a block, follow the steps in the following figure. To unprotect the whole chip,
it is necessary to protect all of the blocks first, then all blocks can be unprotected at the
same time.
Figure 5: Block Protect Flowchart – Programmer Equipment
Verify
Protect
Setup End
ADDRESS = BLOCK ADDRESS
n = 0
START
WE# = VIH
OE#, A9 = VID ,
CE# = VIL
Wait 4µs
Wait 100µs
WE# = VIL
WE# = VIH
CE#, OE# = VIH
,
A0, A6 = VIL,
A1 = VIH
DATA
=
01h
Yes
Yes
No
CE# = VIL
Wait 4µs
OE# = VIL
Wait 60ns
Read DATA
A9 = VIH
CE#, OE# = VIH
++n
= 25
FAIL
PASS A9 = VIH
CE#, OE# = VIH
No
16Mb: 3V Embedded Parallel NOR Flash
Block and Chip Protection
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Figure 6: Chip Unprotect Flowchart – Programmer Equipment
PROTECT ALL BLOCKS
A6, A12, A15 = V IH
CE#, OE#, A9 = V ID
DATA
WE# = VIH
CE#, OE# = VIH
ADDRESS = CURRENT BLOCK ADDRESS
A0 = VIL , A1, A6 = VIH
Wait 10ms
=
00h
INCREMENT
CURRENT BLOCK
n = 0
CURRENT BLOCK = 0
Wait 4µs
WE# = VIL
++n
= 1000
START
YES
YESNO
NO LAST
BLOCK
YES
NO
CE# = VIL
Wait 4µs
OE# = VIL
Wait 60ns
Read DATA
FAIL PASS
Verify Unprotect Set-upEnd
A9 = VIH
CE#, OE# = VIH
A9 = VIH
CE#, OE# = VIH
16Mb: 3V Embedded Parallel NOR Flash
Block and Chip Protection
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