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EXTENDED COMMERCIAL TEMPERATURE RANGE
IDT74LVC02A
3.3V CMOS QUADRUPLE 2-INPUT POSITIVE-NOR GATE
APRIL 1999
1999 Integrated Device Technology, Inc. DSC-4579/-c
IDT74LVC02A
ADVANCE
INFORMATION
EXTENDED COMMERCIAL TEMPERATURE RANGE
DESCRIPTION
This quadruple 2-input positive-NOR gate is built using advanced dual
metal CMOS technology. The LCV02A device performs the Boolean
function Y = A + B or Y = A • B in positive logic.
The LVC02A has been designed with a ±24mA output driver. This driver
is capable of driving a moderate to heavy load while maintaining speed
performance.
Inputs can be driven from either 3.3V or 5V devices. This feature allows
the use of this device as a translator in a mixed 3.3V/5V system environ-
ment.
Functional Block Diagram PIN CONFIGURATION
SOIC/ SSOP/ TSSOP
TOP VIEW
3.3V CMOS
QUADRUPLE 2-INPUT
POSITIVE-NOR GATE
WITH 5 VOLT TOLERANT I/O
FEATURES:
– 0.5 MICRON CMOS Technology
– ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
– 1.27mm pitch SOIC, 0.65mm pitch SSOP and
0.65mm pitch TSSOP packages
– Extended commercial range of – 40°C to +85°C
–V
CC = 3.3V ±0.3V, Normal Range
–V
CC = 2.3V to 3.6V, Extended Range
– CMOS power levels (0.4µW typ. static)
– Rail-to-Rail output swing for increased noise margin
– All inputs, outputs and I/O are 5 Volt tolerant
– Supports hot insertion
Drive Features for LVC02A:
– High Output Drivers: ±24mA
– Reduced system switching noise
A
B
Y2
3
1
1A
VCC
1Y
5
6
4
GND 7
13
12
14
10
9
11
8
1B
2A
2Y
2B
4B
4Y
4A
3B
3Y
3A
(SO14-1)
(SO14-2)
(SO14-3)
APPLICATIONS:
• 5V and 3.3V mixed voltage systems
• Data communication and telecommunication systems
PIN DESCRIPTION
Pin Names Description
xA, xB Data Inputs
xY Data Outputs
FUNCTION TABLE (each gate) (1)
Inputs Outputs
xA xB xY
HX L
XH L
LLH
NOTE:
1. H
=
HIGH V ol t a
g
e Level
L
=
LOW Volta
g
e Level
X
=
Don’t Care
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EXTENDED COMMERCIAL TEMPERATURE RANGE
IDT74LVC02A
3.3V CMOS QUADRUPLE 2-INPUT POSITIVE-NOR GATE
1998 Integrated Device Technology, Inc. DSC-123456c
CAPACITANCE (TA = +25°C, f = 1.0MHZ)
Symbol Parameter(1) Conditions Typ. Max. Unit
CIN Input Capacitance VIN = 0V 4.5 6 pF
COUT Output
Capacitance VOUT = 0V 5.5 8 pF
CI/O I/O Port
Capacitance VIN = 0V 6.5 8 pF
LVC QUAD Link
NOTE:
1. As appl i cable t o the devic e t ype.
ABSOLUTE MAXIMUM RATINGS (1)
Symbol Description Max. Unit
V
TERM(2) Terminal Voltage with Respect to GND – 0.5 to +6.5 V
V
TERM(3) Terminal Voltage with Respect to GND – 0.5 to +6.5 V
TSTG Storage Temperature – 65 to +150 °C
IOUT DC Output Current – 50 to +50 mA
IIK
IOK Continuous Clamp Current,
VI < 0 or VO < 0 – 50 mA
ICC
ISS
Continuous Current through
each VCC or GND ±100 mA
LVC QUAD Link
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other c onditions abov e those indic ated in the operati onal s ections
of this specification is not implied. Exposure to absolute maximum
rating condit ions for extended periods may affec t reliability.
2. VCC terminals.
3. All termina l s except V CC.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: TA = – 40°c to +85°c
Symbol Parameter Test Conditions Min. Typ.(1) Max. Unit
VIH Input HIGH Voltage Level VCC = 2.3V to 2.7V 1.7 — — V
VCC = 2.7V to 3.6V 2 — —
VIL Input LOW Voltage Level VCC = 2.3V to 2.7V — — 0.7 V
VCC = 2.7V to 3.6V — — 0.8
IIH
IIL Input Leakage Current VCC = 3.6V VI = 0 to 5.5V — — ±5 µA
IOZH High Impedance Output Current VCC = 3.6V VO = 0 to 5.5V — — ±10 µA
IOZL (3-State Output pins)
IOFF Input/Output Power Off Leakage VCC = 0V, VIN or VO ≤5.5V — — ±50 µA
VIK Clamp Diode Voltage VCC = 2.3V, IIN = – 18mA — – 0.7 – 1.2 V
VHInput Hysteresis VCC = 3.3V — 100 — mV
ICCL
ICCH Quiescent Power Supply Current VCC = 3.6V VIN = GND or VCC ——10µA
ICCZ
∆ICC Quiescent Power Supply
Current Variation One input at VCC – 0.6V
other inputs at VCC or GND — — 500 µA
LVC QUAD Lin
k
NOTE:
1. Typic al v al ues are at VCC = 3.3V , +25°C ambient .
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EXTENDED COMMERCIAL TEMPERATURE RANGE
IDT74LVC02A
3.3V CMOS QUADRUPLE 2-INPUT POSITIVE-NOR GATE
OUTPUT DRIVE CHARACTERISTICS
Symbol Parameter Test Conditions(1) Min. Max. Unit
VOH Output HIGH Voltage VCC = 2.3V to 3.6V IOH = – 0.1mA VCC – 0.2 — V
VCC = 2.3V IOH = – 6mA 2 —
VCC = 2.3V IOH = – 12mA 1.7 —
VCC = 2.7V 2.2 —
VCC = 3.0V 2.4 —
VCC = 3.0V IOH = – 24mA 2.2 —
VOL Output LOW Voltage VCC = 2.3V to 3.6V IOL = 0.1mA — 0.2 V
VCC = 2.3V IOL = 6mA — 0.4
IOL = 12mA — 0.7
VCC = 2.7V IOL = 12mA — 0.4
VCC = 3.0V IOL = 24mA — 0.55 LVC QUAD Li nk
NOTE:
1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICA L CHARACTERISTICS OVER OPERA TING RANGE table for t he
appropriate VCC range. T A = – 40°C to +85°C.
OPERATING CHARACTERISTICS, TA = 25°C VCC = 2.5V±0.2V VCC = 3.3V±0.3V
Symbol Parameter Test Conditions Typical Typical Unit
CPD Power dissipation capacitance per gate CL = 0pF, f = 10Mhz — 9.5 pF
SWITCHING CHARACTERISTICS (1)
VCC = 2.5V±0.2V VCC = 2.7V VCC = 3.3V±0.3V
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
tPLH
tPHL Propagation Delay
xA or xB to xY ———5.414.4ns
tSK(0) Output Skew(2) —————1ns
NOTES:
1. See test circuits and waveforms . T A = – 40°C to + 85°C.
2. Skew between any two out puts of t he same package and switchi ng in the same di rection.
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EXTENDED COMMERCIAL TEMPERATURE RANGE
IDT74LVC02A
3.3V CMOS QUADRUPLE 2-INPUT POSITIVE-NOR GATE
Open
VLOAD
GND
VCC
Pulse
Generator D.U.T.
500Ω
500Ω
CL
RT
VIN VOUT
(1, 2)
LVC QU AD Link
INPUT
VIH
0V
VOH
VOL
tPLH1
tSK (x )
OUTPUT 1
OUTPUT 2
tPHL1
tSK (x )
tPLH2 tPHL2
VT
VT
VOH
VT
VOL
tSK(x ) = tPLH2 - tPLH1 or tPHL2 - tPHL1
LVC QUAD Link
DATA
INPUT 0V
0V
0V
0V
tREM
TIMING
INPUT
ASYNCHRONOUS
CONTROL
SYNCHRONOUS
CONTROL
tSU tH
tSU tH
VIH
VT
VIH
VT
VIH
VT
VIH
VT
LOW-HIGH-LOW
PULSE
HIGH-LOW-HIGH
PULSE
VT
tW
SAME PH ASE
IN PUT TR ANS ITION
OPPO SITE PHAS E
IN PUT TR ANS ITION
0V
0V
VOH
VOL
tPLH tPHL
tPHL
tPLH
OUTPUT
VT
VIH
VT
VT
VIH
VT
CONTROL
INPUT tPLZ 0V
OUTPUT
NORMALLY
LOW tPZH
0V
SWITCH
CLOSED
OUTPUT
NORMALLY
HIGH
ENABLE DISABLE
SWITCH
OPEN
tPHZ
0V
VLZ
VOH
VT
VT
tPZL
VLOAD/2 VLOAD/2
VIH
VT
VOL
VHZ
LVC QUAD Link
LVC QU AD Link
LVC QUAD Link
LVC QUAD Link
TEST CIRCUITS AND WAVEFORMS
TEST CONDITIONS PROPAGATION DELAY
TEST CIRCUITS FOR ALL OUTPUTS
ENABLE AND DISABLE TIMES
SET-UP, HOLD, AND RELEASE TIMES
SWITCH POSITION
OUTPUT SKEW - tsk (x)
PULSE WIDTH
Symbol VCC(1)= 2.5V ±0.2V VCC(2)= 3.3V ±0.3V & 2.7V Unit
VLOAD 2 x Vcc 6 V
VIH Vcc 2.7 V
VTVCC / 2 1.5 V
VLZ 150 300 mV
VHZ 150 300 mV
CL30 50 pF
LVC QUAD Link
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
NOTES:
1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs .
2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
Test Switch
Open Drain
Disable Low
Enable Low
VLOAD
Disable High
Enable High GND
All Other tests Open
LVC QUAD Link
CL= Load capacitance: includes ji g and probe capacitance.
RT = Termination resistance: shoul d be equal t o ZOUT of the P ul se
Generator.
NOTES:
1. Puls e Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2ns; t R ≤ 2ns .
2. Puls e Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2.5ns; t R ≤ 2.5ns.
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EXTENDED COMMERCIAL TEMPERATURE RANGE
IDT74LVC02A
3.3V CMOS QUADRUPLE 2-INPUT POSITIVE-NOR GATE
CORPORATE HEADQUARTERS for SALES:
2975 Stender Way 800-345-7015 or 408-727-6116
Santa Clara, CA 95054 fax: 408-492-8674
www.idt.com*
*To search for sales office near you, please click the sales button found on our home page or dial the 800# above and press 2.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
ORDERING INFORMATION
IDT XX LVC XXX XX
PackageDevice TypeTemp. Range
74
Quadruple 2-Input Positive-NO R Gate, ±24mA
– 40°C to +85°C
02A
S ma ll Outl ine IC (SO 14-1 )
Shrink Sm all O utline Package (SO 14-2)
Thin Shrink Sm all Outline Package (SO 14-3)
DC
PY
PG
