IDT74LVC02A 3.3V CMOS QUADRUPLE 2-INPUT POSITIVE-NOR GATE EXTENDED COMMERCIAL TEMPERATURE RANGE 3.3V CMOS QUADRUPLE 2-INPUT POSITIVE-NOR GATE WITH 5 VOLT TOLERANT I/O DESCRIPTION FEATURES: - - - - - - - - - - IDT74LVC02A ADVANCE INFORMATION 0.5 MICRON CMOS Technology ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) 1.27mm pitch SOIC, 0.65mm pitch SSOP and 0.65mm pitch TSSOP packages Extended commercial range of - 40C to +85C VCC = 3.3V 0.3V, Normal Range VCC = 2.3V to 3.6V, Extended Range CMOS power levels (0.4 W typ. static) Rail-to-Rail output swing for increased noise margin All inputs, outputs and I/O are 5 Volt tolerant Supports hot insertion This quadruple 2-input positive-NOR gate is built using advanced dual metal CMOS technology. The LCV02A device performs the Boolean function Y = A + B or Y = A * B in positive logic. The LVC02A has been designed with a 24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance. Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of this device as a translator in a mixed 3.3V/5V system environment. APPLICATIONS: Drive Features for LVC02A: - High Output Drivers: 24mA - Reduced system switching noise * 5V and 3.3V mixed voltage systems * Data communication and telecommunication systems Functional Block Diagram PIN CONFIGURATION 1 14 V CC 1A 2 13 4Y 1B 3 12 4B 2Y 4 (SO14-1) (SO14-2) 11 (SO14-3) 4A 2A 5 10 3Y 2B 6 9 3B GND 7 8 1Y A Y B SOIC/ SSOP/ TSSOP TOP VIEW FUNCTION TABLE (each gate) (1) Inputs 3A xA xB Outputs xY H X L X H L Pin Names xA, xB L L H xY PIN DESCRIPTION Description Data Inputs Data Outputs NOTE: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care EXTENDED COMMERCIAL TEMPERATURE RANGE APRIL 1999 1 c 1999 Integrated Device Technology, Inc. DSC-4579/- IDT74LVC02A 3.3V CMOS QUADRUPLE 2-INPUT POSITIVE-NOR GATE EXTENDED COMMERCIAL TEMPERATURE RANGE ABSOLUTE MAXIMUM RATINGS (1) CAPACITANCE (TA = +25C, f = 1.0MHZ) Symbol VTERM(2) Description Terminal Voltage with Respect to GND Max. - 0.5 to +6.5 Unit V VTERM(3) Terminal Voltage with Respect to GND - 0.5 to +6.5 V TSTG Storage Temperature - 65 to +150 C IOUT DC Output Current - 50 to +50 mA IIK IOK ICC Continuous Clamp Current, VI < 0 or VO < 0 Continuous Current through - 50 mA 100 mA ISS each VCC or GND Parameter(1) Conditions Typ. Max. Unit CIN Input Capacitance VIN = 0V 4.5 6 pF COUT Output VOUT = 0V 5.5 8 pF VIN = 0V 6.5 8 pF Symbol Capacitance CI/O I/O Port Capacitance LVC QUAD Link NOTE: 1. As applicable to the device type. LVC QUAD Link NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VCC terminals. 3. All terminals except VCC. DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = - 40c to +85c Symbol VIH Parameter Input HIGH Voltage Level VIL Input LOW Voltage Level Min. 1.7 Typ.(1) -- VCC = 2.7V to 3.6V 2 -- -- VCC = 2.3V to 2.7V -- -- 0.7 VCC = 2.7V to 3.6V -- -- 0.8 Test Conditions VCC = 2.3V to 2.7V Max. -- Unit V V IIH IIL IOZH Input Leakage Current VCC = 3.6V VI = 0 to 5.5V -- -- 5 A High Impedance Output Current VCC = 3.6V VO = 0 to 5.5V -- -- 10 A IOZL (3-State Output pins) IOFF Input/Output Power Off Leakage -- -- 50 A VIK Clamp Diode Voltage VCC = 2.3V, IIN = - 18mA -- - 0.7 - 1.2 V VH Input Hysteresis VCC = 3.3V -- 100 -- mV ICCL ICCH ICCZ Quiescent Power Supply Current VCC = 3.6V -- -- 10 A ICC Quiescent Power Supply Current Variation One input at VCC - 0.6V other inputs at VCC or GND -- -- 500 A VCC = 0V, VIN or VO 5.5V VIN = GND or VCC LVC QUAD Link NOTE: 1. Typical values are at VCC = 3.3V, +25C ambient. c 1998 Integrated Device Technology, Inc. 2 DSC-123456 IDT74LVC02A 3.3V CMOS QUADRUPLE 2-INPUT POSITIVE-NOR GATE EXTENDED COMMERCIAL TEMPERATURE RANGE OUTPUT DRIVE CHARACTERISTICS Symbol VOH VOL Parameter Output HIGH Voltage VCC = 2.3V to 3.6V Output LOW Voltage Test Conditions(1) IOH = - 0.1mA VCC = 2.3V IOH = - 6mA VCC = 2.3V IOH = - 12mA Min. VCC - 0.2 Max. -- 2 -- 1.7 -- VCC = 2.7V 2.2 -- VCC = 3.0V 2.4 -- 2.2 -- VCC = 3.0V IOH = - 24mA VCC = 2.3V to 3.6V IOL = 0.1mA -- 0.2 VCC = 2.3V IOL = 6mA -- 0.4 IOL = 12mA -- 0.7 VCC = 2.7V IOL = 12mA -- 0.4 VCC = 3.0V IOL = 24mA -- 0.55 Unit V V LVC QUAD Link NOTE: 1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range. TA = - 40C to +85C. OPERATING CHARACTERISTICS, TA = 25C Symbol CPD Parameter Power dissipation capacitance per gate Test Conditions CL = 0pF, f = 10Mhz VCC = 2.5V0.2V VCC = 3.3V0.3V Typical -- Typical 9.5 Unit pF SWITCHING CHARACTERISTICS (1) VCC = 2.5V0.2V Symbol tPLH tPHL tSK(0) Parameter Propagation Delay xA or xB to xY Output Skew(2) VCC = 2.7V VCC = 3.3V0.3V Min. -- Max. -- Min. -- Max. 5.4 Min. 1 Max. 4.4 Unit ns -- -- -- -- -- 1 ns NOTES: 1. See test circuits and waveforms. TA = - 40C to + 85C. 2. Skew between any two outputs of the same package and switching in the same direction. 3 IDT74LVC02A 3.3V CMOS QUADRUPLE 2-INPUT POSITIVE-NOR GATE TEST CIRCUITS AND WAVEFORMS PROPAGATION DELAY TEST CONDITIONS Symbol VLOAD EXTENDED COMMERCIAL TEMPERATURE RANGE VCC(1)= 2.5V 0.2V VCC(2)= 3.3V 0.3V & 2.7V 2 x Vcc 6 Unit V VIH Vcc 2.7 V VT VCC / 2 1.5 V VLZ 150 300 mV VHZ 150 300 mV CL 30 50 pF tPLH tPH L tPLH tPH L VOH VT VOL O U TPU T V IH VT 0V O PPO SITE P H AS E IN PU T TR AN S ITIO N LVC QUAD Link TEST CIRCUITS FOR ALL OUTPUTS LV C Q U A D L in k ENABLE AND DISABLE TIMES V LOAD V CC V IH VT 0V SA M E PH AS E IN PU T TR AN S ITIO N O pen 500 (1, 2) V IN C O N TR O L IN PU T V OUT Pulse G enerator D.U.T. tPZL 500 RT D ISAB LE EN ABLE GND O U TPU T SW ITCH N O R M ALLY CLO SED LO W t PZH O U TPU T SW ITCH N O R M ALLY OP EN H IGH CL L V C Q U A D L in k tPLZ V IH VT 0V V LOAD/2 V LOAD/2 VT V LZ V OL tPH Z VT V OH V HZ 0V 0V CL= Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. NOTES: 1. Pulse Generator for All Pulses: Rate 10MHz; tF 2ns; tR 2ns. 2. Pulse Generator for All Pulses: Rate 10MHz; tF 2.5ns; tR 2.5ns. NOTE: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. SWITCH POSITION SET-UP, HOLD, AND RELEASE TIMES Test Open Drain Disable Low Enable Low Disable High Enable High All Other tests LV C Q U A D L in k Switch VLOAD D A TA IN PU T tSU V IH VT 0V V IH VT 0V V IH VT 0V tH TIM IN G IN PU T GND t REM SY N C H RO N O U S C O N TR O L Open V IH VT 0V LVC QUAD Link OUTPUT SKEW - tsk (x) IN PU T tPLH1 AS YN C H RO N O U S C O N TR O L V IH tPH L1 tSK (x) L V C Q U A D L in k PULSE WIDTH tSK (x) VT V OL LO W -H IG H -LO W PU LSE V OH VT tW VT V OL O U TP U T 2 t PLH2 tH VT 0V V OH O U TP U T 1 t SU H IGH -LO W -H IG H PU LSE t PH L2 VT LV C Q U A D L in k tSK (x) = tPL H2 - tPLH1 or t PH L2 - tPHL1 LV C Q U A D L in k NOTES: 1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs. 2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank. 4 IDT74LVC02A 3.3V CMOS QUADRUPLE 2-INPUT POSITIVE-NOR GATE EXTENDED COMMERCIAL TEMPERATURE RANGE ORDERING INFORMATION XXX XX LVC IDT Tem p. Range Device Type XX Package DC PY PG Small Outline IC (SO14-1) Shrink S m all Outline Package (S O14-2) Thin Shrink Small Outline Package (SO14-3) 02A Quadruple 2-Input Positive-NOR Gate, 24mA 74 - 40C to +85C CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com* *To search for sales office near you, please click the sales button found on our home page or dial the 800# above and press 2. The IDT logo is a registered trademark of Integrated Device Technology, Inc. 5