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FEATURES DESCRIPTION
APPLICATIONS
FUNCTIONAL DIAGRAM
8
2
3
4
7
6
VCC
A
B
VBB
Y
Z
EYE PATTERN
1.5 Gbps
223-1 PRBS
750 MHz
VCC = 3.3 V, T A = 25°C, VID = 200 mV, VIC = 1.2 V, VTT = 3.3 V, RT = 50
Vertical Scale = 500 mV/div
Horizontal Scale = 200 ps/div
SN65CML100
SLLS547 NOVEMBER 2002
1.5-Gbps LVDS/LVPECL/CML-TO-CML TRANSLATOR/REPEATER
Provides Level Translation From LVDS or
This high-speed translator/repeater is designed forLVPECL to CML, Repeating From CML to CML
signaling rates up to 1.5 Gbps to support varioushigh-speed network routing applications. The driverSignaling Rates
(1)
up to 1.5 Gbps
output is compatible with current-mode logic (CML)CML Compatible Output Directly Drives
levels, and directly drives 50- or 25- loadsDevices With 3.3-V, 2.5-V, or 1.8-V Supplies
connected to 1.8-V, 2.5-V, or 3.3-V nominal supplies.Total Jitter < 70 ps
The capability for direct connection to the loads mayeliminate the need for coupling capacitors. TheLow 100 ps (Max) Part-To-Part Skew
receiver input is compatible with LVDS (TIA/EIA-644),Wide Common-Mode Receiver Capability
LVPECL, and CML signaling levels. The receiverAllows Direct Coupling of Input Signals
tolerates a wide common-mode voltage range, and25 mV of Receiver Input Threshold Hysteresis
may also be directly coupled to the signal source.Over 0-V to 4-V Common-Mode Range
The internal data path from input to output is fullydifferential for low noise generation and lowPropagation Delay Times, 800 ps Maximum
pulse-width distortion.3.3-V Supply Operation
The V
BB
pin is an internally generated voltage supplyAvailable in SOIC and MSOP Packages
to allow operation with a single-ended LVPECL input.For single-ended LVPECL input operation, theunused differential input is connected to V
BB
as aLevel Translation
switching reference voltage. When used, decouple622-MHz Central Office Clock Distribution
V
BB
with a 0.01- µF capacitor and limit the currentsourcing or sinking to 400 µA. When not used, V
BBHigh-Speed Network Routing
should be left open.Wireless Basestations
This device is characterized for operation from –40 °CLow Jitter Clock Repeater
(1)
to 85 °C.(1) The signaling rate of a line is the number of voltagetransitions that are made per second expressed in the unitsbps (bits per second).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2002–TBD, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS
PACKAGE DISSIPATION RATINGS
SN65CML100
SLLS547 NOVEMBER 2002
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
PART NUMBER PART MARKING PACKAGE STATUS
SN65CML100D CML100 SOIC ProductionSN65CML100DGK NWB MSOP Production
over operating free-air temperature range unless otherwise noted
(1)
UNIT
V
CC
Supply voltage range
(2)
–0.5 V to 4 VI
BB
Sink/source ±0.5 mAVoltage range, (A, B, Y, Z) 0 V to 4.3 VA, B, Y, Z, and GND ±5 kVHuman Body Model
(3)Electrostatic
All pins ±2 kVdischarge
Charged-Device Model
(4)
All pins ±1500 VContinuous power dissipation See Dissipation Rating TableT
stg
Storage temperature range –65 °C to 150 °CLead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under recommended operatingconditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.(3) Tested in accordance with JEDEC Standard 22, Test Method A114-A.7.(4) Tested in accordance with JEDEC Standard 22, Test Method C101.
MIN NOM MAX UNIT
V
CC
Supply voltage 3 3.3 3.6 V3.3-V nominal supply at terminator 3 3.3 3.6
VV
TT
Terminator supply voltage 2.5-V nominal supply at terminator 2.375 2.5 2.6251.8-V nominal supply at terminator 1.7 1.9 V|V
ID
| Magnitude of differential input voltage 0.1 1 VInput voltage (any combination of common-mode or input signals) 0 4 VV
BB
Output current 400 µAT
A
Operating free-air temperature –40 85 °C
T
A
25 °C DERATING FACTOR
(1)
T
A
= 85 °CPACKAGE
POWER RATING ABOVE T
A
= 25 °C POWER RATING
DGK 425 mW 3.4 mW/ °C 221 mWD 725 mW 5.8 mW/ °C 377 mW
(1) This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
2
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DEVICE CHARACTERISTICS
INPUT ELECTRICAL CHARACTERISTICS
OUTPUT ELECTRICAL CHARACTERISTICS
SN65CML100
SLLS547 NOVEMBER 2002
PARAMETER MIN NOM MAX UNIT
I
CC
Supply current, device only 9 12 mAV
BB
Switching reference voltage
(1)
1890 1950 2010 mV
(1) V
BB
parameter varies 1:1 with V
CC
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
Positive-going differential input voltageV
IT+
100threshold
See Figure 1 and Table 1 mVNegative-going differential input voltageV
IT-
–100thresholdV
ID(HYS)
Differential input voltage hysteresis,V
IT+
V
IT–
25 mVV
I
= 0 V or 2.4 V, Second input at 1.2 V –20 20I
I
Input current (A or B inputs) µAV
I
= 4 V, Second input at 1.2 V 33V
CC
= 1.5 V, V
I
= 0 V or 2.4 V,
–20 20Second input at 1.2 VI
I(OFF)
Power off input current (A or B inputs) µAV
CC
= 1.5 V, V
I
= 4 V, Second input at 1.2 V 33I
IO
Input offset current (|I
IA
- I
IB
|) V
IA
= V
IB,
0V
IA
4 V –6 6 µAV
I
= 0.4 sin (4E6 πt) + 0.5 V 3C
i
Differential input capacitance pFV
CC
= 0 V 3
(1) All typical values are at 25 °C and with a 3.3-V supply.
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
V
OH
Output high voltage
(2)
V
TT
–60 V
TT
–10 V
TT
mVR
T
= 50 , V
TT
= 3 V to 3.6 V or V
TT
= 2.5 V ±5%,V
OL
Output low voltage
(2)
V
TT
–1100 V
TT
–800 V
TT
–640 mVSee Figure 2|V
OD
| Differential output voltage magnitude 640 780 1000 mV
V
OH
Output high voltage
(3)
V
TT
–60 V
TT
–10 V
TT
mVR
T
= 25 , V
TT
= 3 V to 3.6 V or V
TT
= 2.5 V ±5%,V
OL
Output low voltage
(3)
V
TT
–550 V
TT
–400 V
TT
–320 mVSee Figure 2|V
OD
| Differential output voltage magnitude 320 390 500 mV
V
OH
Output high voltage
(2)
V
TT
–170 V
TT
–10 V
TT
mV
V
OL
Output low voltage
(2)
R
T
= 50 , V
TT
= 1.8 V ±5%, See Figure 2 V
TT
–1100 V
TT
–800 V
TT
–640 mV
|V
OD
| Differential output voltage magnitude 570 780 1000 mV
V
OH
Output high voltage
(3)
V
TT
–85 V
TT
–10 V
TT
mV
V
OL
Output low voltage
(3)
R
T
= 25 , V
TT
= 1.8 V ±5%, See Figure 2 V
TT
–500 V
TT
–400 V
TT
–320 mV
|V
OD
| Differential output voltage magnitude 285 390 500 mV
V
I
= 0.4 sin (4E6 πt) + 0.5 V 3C
o
Differential output capacitance pFV
CC
= 0 V 3
(1) All typical values are at 25 °C and with a 3.3-V supply.(2) Outputs are terminated through 50- resistors to V
TT
, CML level specifications are referenced to V
TT
and tracks 1:1 with variation ofV
TT
.(3) Outputs are terminated through 25- resistors to V
TT
; CML level specifications are referenced to V
TT
and tracks 1:1 with variation ofV
TT
.
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SWITCHING CHARACTERISTICS
SN65CML100
SLLS547 NOVEMBER 2002
over recommended operating conditions (unless otherwise noted)
NOM
(PARAMETER TEST CONDITIONS MIN MAX UNIT1)
t
PLH
Propagation delay time, low-to-high-level output 250 800 pst
PHL
Propagation delay time, high-to-low-level output 250 800 psR
T
= 50 or R
T
= 25 , SeeFigure 4t
r
Differential output signal rise time (20%–80%) 300 pst
f
Differential output signal fall time (20%–80%) 300 pst
sk(p)
Pulse skew (|t
PHL
t
PLH
|)
(2)
0 50 pst
sk(pp)
Part-to-part skew
(3)
V
ID
= 0.2 V 100 pst
jit(per)
Period jitter, rms (1 standard deviation)
(4)
750 MHz clock input
(5)
1 5 pst
jit(cc)
Cycle-to-cycle jitter (peak)
(4)
750 MHz clock input
(6)
8 27 pst
jit(pp)
Peak-to-peak jitter
(4)
1.5 Gbps 2
23
-1 PRBS input
(7)
30 70 pst
jit(det)
Deterministic jitter, peak-to-peak
(4)
1.5 Gbps 2
7
–1 PRBS input
(8)
25 65 ps
(1) All typical values are at 25°C and with a 3.3-V supply.(2) t
sk(p)
is the magnitude of the time difference between the t
PLH
and t
PHL
.(3) t
sk(pp)
is the magnitude of the difference in propagation delay times between any specified terminals of two devices when bothdevicesoperate with the same supply voltages, at the same temperature, and have identical packages and test circuits.(4) Jitter parameters are ensured by design and characterization. Measurements are made with a Tektronix TDS6604 oscilloscoperunningTektronix TDSJIT3 software. Agilent E4862B stimulus system jitter 2 ps t
jit(per)
, 16 ps t
jit(cc)
, 25 ps t
jit(pp)
, and 10 ps t
jit(det)
hasbeensubtracted from the values.(5) V
ID
= 200 mV, 50% duty cycle, V
IC
= 1.2 V, t
r
= t
f
25 ns (20% to 80%), measured over 1000 samples.(6) V
ID
= 200 mV, 50% duty cycle, V
IC
= 1.2 V, t
r
= t
f
25 ns (20% to 80%).(7) V
ID
= 200 mV, V
IC
= 1.2 V, t
r
= t
f
0.25 ns (20% to 80%), measured over 100k samples.(8) V
ID
= 200 mV, V
IC
= 1.2 V, t
r
= t
f
0.25 ns (20% to 80%). Deterministic jitter is sum of pattern dependent jitter and pulse width distortion.
4
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PARAMETER MEASUREMENT INFORMATION
Y
Z
A
B
VID VOD
VIB
VIA
VOZ
VOY
IIB
IIA
VIA+VIB VIC
2VOY+VOZ
2
Y
Z
RT
RTVTT
VOD
VOZ
VOY
_
+
VOD
VTT
RT2
RT1
Y
Z
Driver Device Receiver Device
RT1 = RT2 = RT
SN65CML100
SLLS547 NOVEMBER 2002
Figure 1. Voltage and Current Definitions
Table 1. Maximum Receiver Input Voltage Threshold
RESULTING DIFFERENTIAL RESULTING COMMON-APPLIED VOLTAGES
INPUT VOLTAGE MODE INPUT VOLTAGE
OUTPUT
(1)
V
IA
V
IB
V
ID
V
IC
1.25 V 1.15 V 100 mV 1.2 V H1.15 V 1.25 V –100 mV 1.2 V L4.0 V 3.9 V 100 mV 3.95 V H3.9 V 4. 0 V –100 mV 3.95 V L0.1 V 0.0 V 100 mV 0.5 V H0.0 V 0.1 V –100 mV 0.5 V L1.7 V 0.7 V 1000 mV 1.2 V H0.7 V 1.7 V –1000 mV 1.2 V L4.0 V 3.0 V 1000 mV 3.5 V H3.0 V 4.0 V –1000 mV 3.5 V L1.0 V 0.0 V 1000 mV 0.5 V H0.0 V 1.0 V –1000 mV 0.5 V L
(1) H = high level, L = low level
Figure 2. Output Voltage Test Circuit
Figure 3. Typical Termination for Output Driver
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1.4 V
1 V
tPLH
0.4 V
0 V
VIA
VIB
VID
80% 100%
0%
tPHL
20%
tftr
VOY - VOZ 0 V
Y
Z
A
B
VID 1 pF
VIB
VIA VOY
-0.4 V
VOZ
RT1
RT2 VTT
RT1 = RT2 = RT
PIN ASSIGNMENTS
VCC
Y
Z
GND
8
7
6
5
1
2
3
4
NC
A
B
VBB
D AND DGK PACKAGE
(TOP VIEW)
SN65CML100
SLLS547 NOVEMBER 2002
NOTE: All input pulses are supplied by a generator having the following characteristics: t
r
or t
f
0.25 ns, pulse repetition rate(PRR) = 50 Mpps, pulse width = 10 ±0.2 ns. C
L
includes instrumentation and fixture capacitance within 0,06 mm ofthe D.U.T.Measurement equipment provides a bandwidth of 5 GHz minimum.
Figure 4. Timing Test Circuit and Waveforms
Table 2. PIN DESCRIPTIONS
PIN FUNCTION
A, B Differential inputsY, Z Differential outputsV
BB
Reference voltage outputV
CC
Power supplyGND GroundNC No connect
Table 3. FUNCTION TABLE
DIFFERENTIAL INPUT OUTPUTS
(1)
V
ID
= V
A
V
B
Y ZV
ID
100 mV H L–100 mV < V
ID
< 100 mV ? ?V
ID
–100 mV L HOpen ? ?
(1) H = high level, L = low level, ? = intermediate
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EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
TYPICAL CHARACTERISTICS
0
2
4
6
8
10
12
0 250 500 750 1000
f − Frequency − MHz
− Supply Current − mAICC
VCC = 3.3 V,
TA = 25°C,
VIC = 1.2 V,
VID = 200 mV,
RT = 50 ,
VTT = 2.5 V
0
2
4
6
8
10
12
−40 −20 0 20 40 60 80 100
TA − Free-Air Temperature − °C
− Supply Current − mAICC
VCC = 3.3 V,
VIC = 1.2 V,
VID = 200 mV,
f = 750 MHz,
RT = 50 ,
VTT = 2.5 V
500
600
700
800
900
1000
− Differential Output Voltage − mVVOD
f − Frequency − MHz
VCC = 3.3 V,
TA = 25°C,
VIC = 1.2 V,
VID = 200 mV,
RT = 50
100 200 300 400 500 600 700 800
VTT = 3.3 V
VTT = 2.5 VVTT = 1.7 V
350
375
400
425
450
475
500
−40 −20 0 20 40 60 80 100
tPLH
tPHL
− Propagation Delay Time − ps
TA− Free-Air Temperature − °C
tpd
VCC = 3.3 V,
VIC = 1.2 V,
VID = 200 mV,
f = 25 MHz,
RT = 50 ,
VTT = 2.5 V
− Differential Output Voltage − mVVOD
f − Frequency − MHz
VCC = 3.3 V,
TA = 25°C,
VIC = 1.2 V,
VID = 200 mV,
RT = 25
100 200 300 400 500 600 700 800
250
300
350
400
450
500
VTT = 3.3 V
VTT = 2.5 V
VTT = 1.7 V
350
375
400
425
450
475
500
0 0.5 1 1.5 2 2.5 3 3.5 4
tPLH
tPHL
− Propagation Delay Time − ps
VIC − Common Mode Input Voltage − V
tpd
VCC = 3.3 V,
TA = 25°C,
VID = 200 mV
f = 25 MHz,
RT = 50 ,
VTT = 2.5 V
SN65CML100
SLLS547 NOVEMBER 2002
SUPPLY CURRENT SUPPLY CURRENT DIFFERENTIAL OUTPUT VOLTAGEvs vs vsFREQUENCY FREE-AIR TEMPERATURE FREQUENCY
Figure 5. Figure 6. Figure 7.
DIFFERENTIAL OUTPUT VOLTAGE PROPAGATION DELAY TIME PROPAGATION DELAY TIMEvs vs vsFREQUENCY COMMON-MODE INPUT VOLTAGE FREE-AIR TEMPERATURE
Figure 8. Figure 9. Figure 10.
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5
10
15
20
25
30
100 200 300 400 500 600 700 800
0
Peak-To-Peak Jitter − ps
f − Frequency − MHz
VCC = 3.3 V,
TA = 25°C,
VIC = 1.2 V,
RT = 50 ,
VTT = 2.5 V,
Input = Clock
VID = 0.5 V VID = 0.8 V
VID = 0.3 V
−40 −20 0 20 40 60 80 100
tPLH
tPHL
− Propagation Delay Time − ps
TA− Free-Air Temperature − °C
tpd
VCC = 3.3 V,
VIC = 1.2 V,
VID = 200 mV,
RT = 50 ,
VTT = 1.7 V,
f = 25 MHz
500
525
550
575
600
625
650
200 400 600 800 1000 1200 1400 1600
Peak-To-Peak Jitter − ps
Data Rate − Mbps
VCC = 3.3 V,
TA = 25°C,
VIC = 1.2 V,
RT = 50 ,
VTT = 2.5 V
Input = 223−1 PRBS
0
5
10
15
20
25
30
35
VID = 0.3 V
VID = 0.5 V
VID = 0.8 V
0 0.5 1 1.5 2 2.5 3 3.5 4
Peak-To-Peak Jitter − ps
VID = 0.5 V
0
10
20
30
40
50
60
VID = 0.3 V
VCC = 3.3 V,
TA = 25°C,
RT = 50 ,
VTT = 2.5 V
Input = 223−1 PRBS
VIC − Common Mode Input Voltage − V
VID = 0.8 V
200 400 600 800 1000 1200 1400 1600
Peak-To-Peak Jitter − ps
Data Rate − Mbps
VCC = 3.3 V, T A = 25°C,
VIC = 1.2 V, |VID| = 200 mV,
Input = 223−1 PRBS, RT = 50
5
10
15
20
25
30
VTT = 1.7 V
VTT = 2.5 V
VTT = 3.3 V
0 0.5 1 1.5 2 2.5 3 3.5 4
Peak-To-Peak Jitter − ps
VIC − Common Mode Input Voltage − V
VID = 0.3 V
VID = 0.5 V
0
5
10
15
20
25
30
VID = 0.8 V
VCC = 3.3 V,
TA = 25°C,
RT = 50 ,
VTT = 2.5 V
Input = Clock
200 400 600 800 1000 1200 1400 1600
Peak-To-Peak Jitter − ps
Data Rate − Mbps
VCC = 3.3 V, T A = 25°C,
VIC = 1.2 V,
VID = 200 mV,
Input = 223−1 PRBS,
RT = 25
VTT = 1.7 V
VTT = 2.5 V
VTT = 3.3 V
5
10
15
20
25
1.5 Gbps
223-1 PRBS
750 MHz
VCC = 3.3 V, T A = 25°C, VID = 200 mV, VIC = 1.2 V, VTT = 3.3 V, RT = 25
Horizontal Scale = 200 ps/div
Vertical Scale = 250 mV/div
SN65CML100
SLLS547 NOVEMBER 2002
TYPICAL CHARACTERISTICS (continued)
PROPAGATION DELAY TIME PEAK-TO-PEAK JITTER PEAK-TO-PEAK JITTERvs vs vsFREE-AIR TEMPERATURE FREQUENCY DATA RATE
Figure 11. Figure 12. Figure 13.
PEAK-TO-PEAK JITTER PEAK-TO-PEAK JITTER PEAK-TO-PEAK JITTERvs vs vsCOMMON MODE INPUT VOLTAGE COMMON MODE INPUT VOLTAGE DATA RATE
Figure 14. Figure 15. Figure 16.
PEAK-TO-PEAK JITTER
vsDATA RATE
Figure 17. Figure 18.
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1.5 Gbps
223-1 PRBS
750 MHz
VCC = 3.3 V, T A = 25°C, VID = 200 mV, VIC = 1.2 V, VTT = 2.5 V, RT = 50
Horizontal Scale = 200 ps/div
Vertical Scale = 500 mV/div
1.5 Gbps
223-1 PRBS
750 MHz
VCC = 3.3 V, T A = 25°C, VID = 200 mV, VIC = 1.2 V, VTT = 2.5 V, RT = 25
Horizontal Scale = 200 ps/div
Vertical Scale = 250 mV/div
1.5 Gbps
223-1 PRBS
750 MHz
VCC = 3.3 V, T A = 25°C, VIC = 1.2 V, VID = 200 mV, VTT = 1.7 V, RT = 25
Horizoontal Scale = 200 ps/div
Vertical Scale = 250 mV/div
1.5 Gbps
223-1 PRBS
750 MHz
VCC = 3.3 V, T A = 25°C, VIC = 1.2 V, VID = 200 mV, VTT = 1.7 V, RT = 50
Horizoontal Scale = 200 ps/div
Vertical Scale = 500 mV/div
SN65CML100
SLLS547 NOVEMBER 2002
TYPICAL CHARACTERISTICS (continued)
Figure 19. Figure 20.
Figure 21. Figure 22.
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Pattern
Generator
Oscilloscope
EVM
Power Supply 1 +
-
Power Supply 2 +
-
VCC
EVM
GND
DUT
GND
3.3 V
Matched
Cables
SMA to SMA
Matched
Cables
SMA to SMA
J2
J7
J6
J5
J4
J3 J1
100
50 50
DUT
VTT
SN65CML100
SLLS547 NOVEMBER 2002
TYPICAL CHARACTERISTICS (continued)
Figure 23. Jitter Setup Connections for SN65CML100
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APPLICATION INFORMATION
TYPICAL APPLICATION CIRCUITS (ECL, PECL, LVDS, etc.)
3.3 V or 5 V SN65CML100
3.3 V
50
50
A
B
50 50
VTT
VTT = VCC -2 V
ECL
3.3 V SN65CML100
3.3 V
50
50
A
B
CML
VTT
3.3 V SN65CML100
3.3 V
50 A
B
50
ECL VBB
VTT VTT = VCC -2 V
3.3 V or 5 V SN65CML100
3.3 V
50
50
A
B
100
LVDS
SN65CML100
SLLS547 NOVEMBER 2002
For single-ended input conditions, the unused differential input is connected to V
BB
as a switching referencevoltage. When V
BB
is used, decouple V
BB
via a 0.01- µF capacitor and limit the current sourcing or sinking to 0.4mA. When not used, V
BB
should be left open.
Figure 24. Low-Voltage Positive Emitter-Coupled Logic (LVPECL)
Figure 25. Current-Mode Logic (CML)
Figure 26. Single-Ended (LVPECL)
Figure 27. Low-Voltage Differential Signaling (LVDS)
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PACKAGE OPTION ADDENDUM
www.ti.com 16-Aug-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
SN65CML100D ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65CML100DG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65CML100DGK ACTIVE VSSOP DGK 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65CML100DGKG4 ACTIVE VSSOP DGK 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65CML100DGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65CML100DGKRG4 ACTIVE VSSOP DGK 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65CML100DR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65CML100DRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
PACKAGE OPTION ADDENDUM
www.ti.com 16-Aug-2012
Addendum-Page 2
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN65CML100DGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
SN65CML100DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Aug-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN65CML100DGKR VSSOP DGK 8 2500 358.0 335.0 35.0
SN65CML100DR SOIC D 8 2500 340.5 338.1 20.6
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Aug-2012
Pack Materials-Page 2
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