CY62167EV30LL-45BVXI - Cypress Semiconductor

Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600

Document #: 38-05446 Rev. *C Revised June 04, 2007

CY62167EV30 MoBL®

16-Mbit (1M x 16 / 2M x 8) Static RAM

Features

• TSOP I package configurable as 1M x 16 or as 2M x 8 SRAM

• Very high speed: 45 ns

• Wide voltage range: 2.20V–3.60V

• Ultra low standby power

— Typical standby current: 1.5 µA

— Maximum standby current: 12 µA

• Ultra low active power

— Typical active current: 2.2 mA @ f = 1 MHz

• Easy memory expansion with CE1, CE2, and OE features

• Automatic power down when deselected

• CMOS for optimum speed/power

• Offered in Pb-free 48-ball BGA and 48-pin TSOP I packages

Functional Description[1]

The CY62167EV30 is a high performance CMOS static RAM

organized as 1M words by 16 bits / 2M words by 8 bits. This

device features advanced circuit design to provide an ultra low

active current. This is ideal for providing More Battery Life™

(MoBL®) in portable applications such as cellular telephones.

The device also has an automatic power down feature that

significantly reduces power consumption by 99% when

addresses are not toggling. Place the device into standby

mode when deselected (CE1 HIGH or CE2 LOW or both BHE

and BLE are HIGH). The input and output pins (IO0 through

IO15) are placed in a high-impedance state when: the device

is deselected (CE1 HIGH or CE2 LOW), outputs are disabled

(OE HIGH), both Byte High Enable and Byte Low Enable are

disabled (BHE, BLE HIGH), or a write operation is in progress

(CE1 LOW, CE2 HIGH and WE LOW).

To write to the device, take Chip Enables (CE1 LOW and CE2

HIGH) and Write Enable (WE) input LOW. If Byte Low Enable

(BLE) is LOW, then data from IO pins (IO0 through IO7) is

written into the location specified on the address pins (A0

through A19). If Byte High Enable (BHE) is LOW, then data

from the IO pins (IO8 through IO15) is written into the location

specified on the address pins (A0 through A19).

To read from the device, take Chip Enables (CE1 LOW and

CE2 HIGH) and Output Enable (OE) LOW while forcing the

Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,

then data from the memory location specified by the address

pins will appear on IO0 to IO7. If Byte High Enable (BHE) is

LOW, then data from memory will appear on IO8 to IO15. See

the “Truth Table” on page 10 for a complete description of read

and write modes.

Logic Block Diagram

1M × 16 / 2M x 8

RAM Array IO0–IO7

ROW DECODER

A 8

A 7

A 6

A 5

A 2

COLUMN DECODER

A11

A12

A13

A14

A15

SENSE AMPS

DATA IN DRIVERS

A 4

A 3IO8–IO15

BLE

BHE

A16

A 0

A 1

A17

A 9

A18

A10

CE2

CE1

A19

BYTE

Power Down

Circuit BHE

BLE

CE2

CE1

Note

1. For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines.

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Document #: 38-05446 Rev. *C Page 2 of 13

CY62167EV30 MoBL®

Pin Configuration[2, 3, 4]

48-Ball FBGA Top View

48-Pin TSOP I Top View

Product Portfolio

Product VCC Range (V) Speed

(ns)

Power Dissipation

Operating ICC (mA)

Standby ISB2 (µA)

f = 1 MHz f = fmax

Min Typ[5] Max Typ[5] Max Typ[5] Max Typ[5] Max

CY62167EV30LL 2.20 3.0 3.60 45 2.2 4.0 25 30 1.5 12

A11

A10

CE1

IO10

IO8

IO9

IO13

IO12

IO14

IO15

Vss

IO0

BHE

CE2

A17

BLE

IO2

IO1

IO4

IO5IO6

IO7

A15

A14

A13

A19

A18 NC

A16

VCC

A1A2

A15

A14

A13

A12

A11

A10

A19

BHE

BLE

A18

A17

A16

BYTE

Vss

IO15/A20

IO7

IO14

IO6

IO13

IO5

IO12

IO4

Vcc

IO11

IO3

IO10

IO2

IO9

IO1

IO8

IO0

Vss

Notes

2. NC pins are not connected on the die.

3. The BYTE pin in the 48-TSOPI package has to be tied to VCC to use the device as a 1M X 16 SRAM. The 48-TSOPI package can also be used as a 2M X 8

SRAM by tying the BYTE signal to VSS. In the 2M x 8 configuration, Pin 45 is A20, while BHE, BLE and IO8 to IO14 pins are not used.

4. Ball H6 for the FBGA package can be used to upgrade to a 32M density.

5. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25°C.

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CY62167EV30 MoBL®

Maximum Ratings

Exceeding the maximum ratings may impair the useful life of

the device. These user guidelines are not tested.

Storage Temperature ................................–65°C to + 150°C

Ambient Temperature with

Power Applied............................................–55°C to + 125°C

Supply Voltage to Ground

Potential..............................–0.3V to 3.9V (VCC(max) + 0.3V

DC Voltage Applied to Outputs

in High Z State[6, 7] .............. –0.3V to 3.9V (VCC(max) + 0.3V

DC Input Voltage[6, 7] .......... –0.3V to 3.9V (VCC(max) + 0.3V

Output Current into Outputs (LOW) ............................ 20 mA

Static Discharge Voltage........................................... >2001V

(MIL-STD-883, Method 3015)

Latch up Current......................................................>200 mA

Operating Range

Device Range Ambient

Temperature VCC[8]

CY62167EV30LL Industrial –40°C to +85°C 2.2V to 3.6V

Electrical Characteristics

Over the Operating Range

Parameter Description Test Conditions 45 ns Unit

Min Typ[5] Max

VOH Output HIGH Voltage 2.2 < VCC < 2.7 IOH = –0.1 mA 2.0 V

2.7 < VCC < 3.6 IOH = –1.0 mA 2.4 V

VOL Output LOW Voltage 2.2 < VCC < 2.7 IOL = 0.1 mA 0.4 V

2.7 < VCC < 3.6 IOL = 2.1mA 0.4 V

VIH Input HIGH Voltage 2.2 < VCC < 2.7 1.8 VCC + 0.3V V

2.7 < VCC < 3.6 2.2 VCC + 0.3V V

VIL Input LOW Voltage 2.2 < VCC < 2.7 –0.3 0.6 V

2.7 < VCC < 3.6 For FBGA package –0.3 0.8 V

For TSOP I package –0.3 0.7[9] V

IIX Input Leakage Current GND < VI < VCC –1 +1 µA

IOZ Output Leakage Current GND < VO < VCC, Output Disabled –1 +1 µA

ICC VCC Operating Supply

Current

f = fMAX = 1/tRC VCC = VCC(max)

IOUT = 0 mA

CMOS levels

25 30 mA

f = 1 MHz 2.2 4.0 mA

ISB1 Automatic CE Power Down

Current—CMOS Inputs CE1 > VCC − 0.2V or CE2 < 0.2V

VIN > VCC − 0.2V, VIN < 0.2V,

f = fMAX (Address and Data Only),

f = 0 (OE, WE, BHE and BLE), VCC = 3.60V

1.5 12 µA

ISB2[10] Automatic CE Power Down

Current—CMOS Inputs CE1 > VCC − 0.2V or CE2 < 0.2V,

VIN > VCC − 0.2V or VIN < 0.2V,

f = 0, VCC = 3.60V

1.5 12 µA

Capacitance[11]

Parameter Description Test Conditions Max Unit

CIN Input Capacitance TA = 25°C, f = 1 MHz,

VCC = VCC(typ)

10 pF

COUT Output Capacitance 10 pF

Notes

6. VIL(min) = –2.0V for pulse durations less than 20 ns.

7. VIH(max) = VCC + 0.75V for pulse durations less than 20 ns.

8. Full Device AC operation assumes a 100 µs ramp time from 0 to VCC (min) and 200 µs wait time after VCC stabilization.

9. Under DC conditions the device meets a VIL of 0.8V. However, in dynamic conditions Input LOW Voltage applied to the device must not be higher than 0.7V. This

is applicable to TSOP I package only.

10. Only chip enables (CE1 and CE2), byte enables (BHE and BLE) and BYTE need to be tied to CMOS levels to meet the ISB2 / ICCDR spec. Other inputs can be

left floating.

11. Tested initially and after any design or process changes that may affect these parameters.

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CY62167EV30 MoBL®

Thermal Resistance[11]

Parameter Description Test Conditions BGA TSOP I Unit

ΘJA Thermal Resistance

(Junction to Ambient)

Still Air, soldered on a 3 × 4.5 inch, two-layer

printed circuit board

55 60 °C/W

ΘJC Thermal Resistance

(Junction to Case)

16 4.3 °C/W

AC Test Loads and Waveforms

Parameters 2.2V to 2.7V 2.7V to 3.6V Unit

R1 16667 1103 Ω

R2 15385 1554 Ω

RTH 8000 645 Ω

VTH 1.20 1.75 V

Data Retention Characteristics

Over the Operating Range

Parameter Description Conditions Min Typ[5] Max Unit

VDR VCC for Data Retention 1.5 V

ICCDR[10] Data Retention Current VCC = 1.5V,

CE1 > VCC − 0.2V, CE2 < 0.2V,

VIN > VCC − 0.2V or VIN < 0.2V

10 µA

tCDR[11] Chip Deselect to Data

Retention Time 0ns

tR[12] Operation Recovery Time tRC ns

Data Retention Waveform[13]

VCC

OUTPUT

30 pF

INCLUDING

JIG AND

SCOPE

GND

90%

10% 90%

10%

Rise Time = 1 V/ns Fall Time = 1 V/ns

OUTPUT V

Equivalent to: THÉVENIN EQUIVALENT

ALL INPUT PULSES

RTH

VCC(min)

tCDR

VDR >1.5 V

DATA RETENTION MODE

CE1 or

VCC

BHE.BLE

Notes

12. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 µs or stable at VCC(min) > 100 µs.

13. BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE.

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CY62167EV30 MoBL®

Switching Characteristics

Over the Operating Range[14, 15]

Parameter Description 45 ns Unit

Min Max

READ CYCLE

tRC Read Cycle Time 45 ns

tAA Address to Data Valid 45 ns

tOHA Data Hold from Address Change 10 ns

tACE CE1 LOW and CE2 HIGH to Data Valid 45 ns

tDOE OE LOW to Data Valid 22 ns

tLZOE OE LOW to LOW Z[16] 5ns

tHZOE OE HIGH to High Z[16, 17] 18 ns

tLZCE CE1 LOW and CE2 HIGH to Low Z[16] 10 ns

tHZCE CE1 HIGH and CE2 LOW to High Z[16, 17] 18 ns

tPU CE1 LOW and CE2 HIGH to Power Up 0 ns

tPD CE1 HIGH and CE2 LOW to Power Down 45 ns

tDBE BLE / BHE LOW to Data Valid 45 ns

tLZBE BLE / BHE LOW to Low Z[16] 10 ns

tHZBE BLE / BHE HIGH to HIGH Z[16, 17] 18 ns

WRITE CYCLE[18]

tWC Write Cycle Time 45 ns

tSCE CE1 LOW and CE2 HIGH to Write End 35 ns

tAW Address Setup to Write End 35 ns

tHA Address Hold from Write End 0 ns

tSA Address Setup to Write Start 0 ns

tPWE WE Pulse Width 35 ns

tBW BLE / BHE LOW to Write End 35 ns

tSD Data Setup to Write End 25 ns

tHD Data Hold from Write End 0 ns

tHZWE WE LOW to High-Z[16, 17] 18 ns

tLZWE WE HIGH to Low-Z[16] 10 ns

Notes

14. Test conditions for all parameters other than tri-state parameters assume signal transition time of 1 V/ns, timing reference levels of VCC(typ)/2, input pulse levels

of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in “AC Test Loads and Waveforms” on page 4.

15. AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. See application note AN13842 for further clarification.

16. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any

given device.

17. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedance state.

18. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, BHE or BLE or both = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate

a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal

that terminates the write.

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CY62167EV30 MoBL®

Switching Waveforms

Figure 1 shows address transition controlled read cycle waveforms.[19, 20]

Figure 1. Read Cycle No. 1

Figure 2 shows OE controlled read cycle waveforms.[20, 21]

Figure 2. Read Cycle No. 2

PREVIOUS DATA VALID DATA VALID

tAA

tOHA

tRC

ADDRESS

DATA OUT

50%

DATA VALID

tRC

tACE

tDOE

tLZOE

tLZCE

tPU

HIGH IMPEDANCE

tHZOE

tPD

tHZBE

tLZBE

HZCE

tDBE

CE1

ADDRESS

CE2

BHE/BLE

DATA OUT

VCC

SUPPLY

CURRENT

HIGH

ICC

ISB

IMPEDANCE

Notes

19. The device is continuously selected. OE, CE1 = VIL, BHE, BLE or both = VIL, and CE2 = VIH.

20. WE is HIGH for read cycle.

21. Address valid before or similar to CE1, BHE, BLE transition LOW and CE2 transition HIGH.

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CY62167EV30 MoBL®

Figure 3 shows WE controlled write cycle waveforms.[18, 22, 23]

Figure 3. Write Cycle No. 1

Switching Waveforms (continued)

tHD

tSD

tPWE

tSA

tHA

tAW

tSCE

tWC

tHZOE

VALID DATA

tBW

NOTE 24

CE1

ADDRESS

CE2

DATA IO

BHE/BLE

Notes

22. Data IO is high impedance if OE = VIH.

23. If CE1 goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high impedance state.

24. During this period the IOs are in output state. Do not apply input signals.

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CY62167EV30 MoBL®

Figure 4 shows CE1 or CE2 controlled write cycle waveforms.[18, 22, 23]

Figure 4. Write Cycle No. 2

Figure 5 shows WE controlled, OE LOW write cycle waveforms.[23]

Figure 5. Write Cycle No. 3

Switching Waveforms (continued)

tHD

tSD

tPWE

tHA

tAW

tSCE

tWC

tHZOE

VALID DATA

tBW

tSA

NOTE 24

CE1

ADDRESS

CE2

DATA IO

BHE/BLE

VALID DATA

tHD

tSD

tLZWE

tPWE

tSA

tHA

tAW

tSCE

tWC

tHZWE

tBW

NOTE 24

ADDRESS

DATA IO

BHE

/BLE

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CY62167EV30 MoBL®

Figure 6 shows BHE/BLE controlled, OE LOW write cycle waveforms.[23]

Figure 6. Write Cycle No. 4

Switching Waveforms (continued)

tHD

tSD

tSA

tHA

tAW

tWC

VALID DATA

tBW

tSCE

tPWE

NOTE 24

ADDRESS

DATA IO

BHE

/BLE

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CY62167EV30 MoBL®

Truth Table

CE1CE2WE OE BHE BLE Inputs/Outputs Mode Power

HXXXXXHigh Z Deselect/Power-Down Standby (I

SB)

XLXXXXHigh Z Deselect/Power Down Standby (I

SB)

XXXXHHHigh Z Deselect/Power Down Standby (I

SB)

LHHLLLData Out (IO

0–IO15) Read Active (ICC)

LHHLHLData Out (IO

0–IO7);

High Z (IO8–IO15)

Read Active (ICC)

LHHLLHHigh Z (IO

0–IO7);

Data Out (IO8–IO15)

Read Active (ICC)

L H H H L H High Z Output Disabled Active (ICC)

LHHHHLHigh Z Output Disabled Active (I

CC)

L H H H L L High Z Output Disabled Active (ICC)

L H L X L L Data In (IO0–IO15) Write Active (ICC)

L H L X H L Data In (IO0–IO7);

High Z (IO8–IO15)Write Active (ICC)

LHLXLHHigh Z (IO

0–IO7);

Data In (IO8–IO15)

Write Active (ICC)

Ordering Information

Speed

(ns) Ordering Code

Package

Diagram Package Type Operating

Range

45 CY62167EV30LL-45BVXI 51-85150 48-ball Fine Pitch Ball Grid Array (Pb-free) Industrial

CY62167EV30LL-45ZXI 51-85183 48-pin TSOP I (Pb-free)

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CY62167EV30 MoBL®

Package Diagrams

Figure 7. 48-Ball VFBGA (6 x 8 x 1 mm), 51-85150

A1 CORNER

0.75

Ø0.30±0.05(48X)

Ø0.25 M C A B

Ø0.05 M C

0.15(4X)

0.21±0.05

1.00 MAX

SEATING PLANE

0.55 MAX.

0.25 C

0.10 C

A1 CORNER

TOP VIEW BOTTOM VIEW

234

3.75

5.25

465231

6.00±0.10

8.00±0.10

6.00±0.10

1.875

2.625

0.26 MAX.

51-85150-*D

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CY62167EV30 MoBL®

Figure 8. 48-Pin TSOP I (12 mm x 18.4 mm x 1.0 mm), 51-85183

Package Diagrams (continued)

0.020[0.50]

0.007[0.17]

0.037[0.95]

0.002[0.05]

0°-5°

MAX.

0.028[0.70]

0.010[0.25]

0.004[0.10]

0.011[0.27]

0.041[1.05]

0.047[1.20]

0.472[12.00]

0.724 [18.40]

0.787[20.00]

0.006[0.15]

TYP.

0.020[0.50]

0.008[0.21] GAUGE PLANE

SEATING PLANE

0.004[0.10]

DIMENSIONS IN INCHES[MM] MIN.

MAX.

JEDEC # MO-142

51-85183-*A

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CY62167EV30 MoBL®

Document History Page

Document Title: CY62167EV30 MoBL® 16-Mbit (1M x 16 / 2M x 8) Static RAM

Document Number: 38-05446

REV. ECN NO. Issue Date Orig. of

Change Description of Change

** 202600 01/23/04 AJU New Data Sheet

*A 463674 See ECN NXR Converted from Advance Information to Preliminary

Removed ‘L’ bin and 35 ns speed bin from product offering

Modified Data sheet to include x8 configurability.

Changed ball E3 in FBGA pinout from DNU to NC

Changed the ISB2(Typ) value from 1.3 µA to 1.5 µA

Changed the ICC(Max) value from 40 mA to 25 mA

Changed Vcc stabilization time in footnote #9 from 100 µs to 200 µs

Changed the AC Test Load Capacitance value from 50 pF to 30 pF

Corrected typo in Data Retention Characteristics (tR) from 100 µs to tRC ns

Changed tOHA, tLZCE, tLZBE, and tLZWE from 6 ns to 10 ns

Changed tLZOE from 3 ns to 5 ns.

Changed tHZOE, tHZCE, tHZBE, and tHZWE from 15 ns to 18 ns

Changed tSCE, tAW, and tBW from 40 ns to 35 ns

Changed tPE from 30 ns to 35 ns

Changed tSD from 20 ns to 25 ns

Updated 48 ball FBGA Package Information.

Updated the Ordering Information table

*B 469169 See ECN NSI Minor Change: Moved to external web

*C 1130323 See ECN VKN Converted from preliminary to final

Changed ICC max spec from 2.8 mA to 4.0 mA for f=1MHz

Changed ICC typ spec from 22 mA to 25 mA for f=fmax

Changed ICC max spec from 25 mA to 30 mA for f=fmax

Added VIL spec for TSOP I package and footnote# 9

Added footnote# 10 related to ISB2 and ICCDR

Changed ISB1 and ISB2 spec from 8.5 µA to 12 µA

Changed ICCDR spec from 8 µA to 10 µA

Added footnote# 15 related to AC timing parameters

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