M74VHC1G125DTT1G - ON Semiconductor

May, 2011 − Rev. 16

1Publication Order Number:

MC74VHC1G125/D

MC74VHC1G125

Noninverting 3-State Buffer

The MC74VHC1G125 is an advanced high speed CMOS

noninverting 3−state buffer fabricated with silicon gate CMOS

technology. It achieves high speed operation similar to equivalent

Bipolar Schottky TTL while maintaining CMOS low power

dissipation.

The internal circuit is composed of three stages, including a buffered

3−state output which provides high noise immunity and stable output.

The MC74VHC1G125 input structure provides protection when

voltages up to 7 V are applied, regardless of the supply voltage. This

allows the MC74VHC1G125 to be used to interface 5 V circuits to 3 V

circuits.

Features

•High Speed: tPD = 3.5 ns (Typ) at VCC = 5 V

•Low Power Dissipation: ICC = 1 mA (Max) at TA = 25°C

•Power Down Protection Provided on Inputs

•Balanced Propagation Delays

•Pin and Function Compatible with Other Standard Logic Families

•Chip Complexity: FETs = 58; Equivalent Gates = 15

•These Devices are Pb−Free and are RoHS Compliant

Figure 1. Pinout (Top View)

VCC

OE

IN A

OUT Y

GND

IN A OUT Y

EN

OE

Figure 2. Logic Symbol

1

2

34

5

See detailed ordering and shipping information in the package

dimensions section on page 4 of this data sheet.

ORDERING INFORMATION

FUNCTION TABLE

L

H

X

A Input Y Output

L

H

Z

OE Input

L

H

MARKING

DIAGRAMS

PIN ASSIGNMENT

1

2

3 GND

OE

IN A

4

5V

CC

OUT Y

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SC−88A / SOT−353 / SC−70

DF SUFFIX

CASE 419A

TSOP−5 / SOT−23 / SC−59

DT SUFFIX

CASE 483

1

5

1

5

1

5

W0 M G

G

W0 = Device Code

M = Date Code*

G= Pb−Free Package

(Note: Microdot may be in either location)

*Date Code orientation and/or position may vary

depending upon manufacturing location.

1

5

W0 M G

G

M

MC74VHC1G125

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2

MAXIMUM RATINGS

Symbol Characteristics Value Unit

VCC DC Supply Voltage −0.5 to +7.0 V

VIN DC Input Voltage −0.5 to +7.0 V

VOUT DC Output Voltage VCC = 0

High or Low State

−0.5 to 7.0

−0.5 to VCC + 0.5

V

IIK Input Diode Current −20 mA

IOK Output Diode Current VOUT < GND; VOUT > VCC +20 mA

IOUT DC Output Current, per Pin +25 mA

ICC DC Supply Current, VCC and GND +50 mA

PDPower Dissipation in Still Air SC−88A, TSOP−5 200 mW

qJA Thermal Resistance SC−88A, TSOP−5 333 °C/W

TLLead Temperature, 1 mm from Case for 10 secs 260 °C

TJJunction Temperature Under Bias +150 °C

Tstg Storage Temperature −65 to +150 °C

VESD ESD Withstand Voltage Human Body Model (Note 1)

Machine Model (Note 2)

Charged Device Model (Note 3)

> 2000

> 200

N/A

V

ILatchup Latchup Performance Above VCC and Below GND at 125°C (Note 4) $500 mA

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

1. Tested to EIA/JESD22−A114−A.

2. Tested to EIA/JESD22−A115−A.

3. Tested to JESD22−C101−A.

4. Tested to EIA/JESD78.

RECOMMENDED OPERATING CONDITIONS

Symbol Characteristics Min Max Unit

VCC DC Supply Voltage 2.0 5.5 V

VIN DC Input Voltage 0.0 5.5 V

VOUT DC Output Voltage 0.0 VCC V

TAOperating Temperature Range −55 +125 °C

tr , tfInput Rise and Fall Time VCC = 3.3 V $ 0.3 V

VCC = 5.0 V $ 0.5 V

0

100

20

ns/V

Device Junction Temperature versus

Time to 0.1% Bond Failures

Junction

Temperature °CTime, Hours Time, Years

80 1,032,200 117.8

90 419,300 47.9

100 178,700 20.4

110 79,600 9.4

120 37,000 4.2

130 17,800 2.0

140 8,900 1.0

1

1 10 100 1000

TIME, YEARS

NORMALIZED FAILURE RATE

TJ= 80 C°

TJ= 90 C°

TJ= 100 C°

TJ= 110 C°

TJ= 130 C°

TJ= 120 C°

FAILURE RATE OF PLASTIC = CERAMIC

UNTIL INTERMETALLICS OCCUR

Figure 3. Failure Rate vs. Time Junction Temperature

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3

DC ELECTRICAL CHARACTERISTICS

Symbol Parameter Test Conditions

VCC

(V)

TA = 25°C TA ≤ 85°C−55 ≤ TA ≤ 125°C

Unit

Min Typ Max Min Max Min Max

VIH Minimum High−Level

Input Voltage

2.0

3.0

4.5

5.5

1.5

2.1

3.15

3.85

1.5

2.1

3.15

3.85

1.5

2.1

3.15

3.85

V

VIL Maximum Low−Level

Input Voltage

2.0

3.0

4.5

5.5

0.5

0.9

1.35

1.65

0.5

0.9

1.35

1.65

0.5

0.9

1.35

1.65

V

VOH Minimum High−Level

Output Voltage

VIN = VIH or VIL

IOH = −50 mA

2.0

3.0

4.5

1.9

2.9

4.4

2.0

3.0

4.5

1.9

2.9

4.4

1.9

2.9

4.4

V

VIN = VIH or VIL

IOH = −4 mA

IOH = −8 mA

3.0

4.5

2.58

3.94

2.48

3.80

2.34

3.66

V

VOL Maximum Low−Level

Output Voltage

VIN = VIH or VIL

IOL = 50 mA

2.0

3.0

4.5

0.0

0.1

V

VIN = VIH or VIL

IOL = 4 mA

IOL = 8 mA

3.0

4.5

0.36

0.44

0.52

V

IOZ Maximum 3−State

Leakage Current

VIN = VIH or VIL

VOUT = VCC or GND

5.5 ±0.2

5$2.5 $2.5 mA

IIN Maximum Input

Leakage Current

VIN = 5.5 V or GND 0 to

5.5

±0.1 ±1.0 $1.0 mA

ICC Maximum Quiescent

Supply Current

VIN = VCC or GND 5.5 1.0 20 40 mA

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

AC ELECTRICAL CHARACTERISTICS Cload = 50 pF, Input tr = tf = 3.0 ns

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎÎÎÎ

Test Conditions

ÎÎÎÎÎÎÎ

TA = 25°C

ÎÎÎÎ

TA ≤ 85°C

ÎÎÎÎÎÎ

−55 ≤ TA ≤ 125°C

ÎÎ

Unit

ÎÎÎ

Min

ÎÎÎ

Typ

ÎÎÎ

Max

ÎÎ

Min

ÎÎÎ

Max

ÎÎÎ

Min

ÎÎÎÎ

Max

ÎÎÎÎ

tPLH,

tPHL

ÎÎÎÎÎÎÎÎ

Maximum Propagation

Delay, Input A to Y

(Figures 3 and 4)

ÎÎÎÎÎÎÎÎ

VCC = 3.3 ± 0.3 V CL = 15 pF

CL = 50 pF

ÎÎÎ

4.5

6.4

ÎÎÎ

8.0

11.5

ÎÎ

ÎÎÎ

9.5

13.0

ÎÎÎ

ÎÎÎÎ

12.0

16.0

ÎÎ

ns

ÎÎÎÎÎÎÎÎ

VCC = 5.0 ± 0.5 V CL = 15 pF

CL = 50 pF

ÎÎÎ

3.5

4.5

ÎÎÎ

5.5

7.5

ÎÎ

ÎÎÎ

6.5

8.5

ÎÎÎ

ÎÎÎÎ

8.5

10.5

ÎÎÎÎ

tPZL,

tPZH

ÎÎÎÎÎÎÎÎ

Maximum Output

Enable Time,

Input OE to Y

(Figures 4 and 5)

ÎÎÎÎÎÎÎÎ

VCC = 3.3 ± 0.3 V CL = 15 pF

RL = 1000 WCL = 50 pF

ÎÎÎ

4.5

6.4

ÎÎÎ

8.0

11.5

ÎÎ

ÎÎÎ

9.5

13.0

ÎÎÎ

ÎÎÎÎ

11.5

15.0

ÎÎ

ns

ÎÎÎÎÎÎÎÎ

VCC = 5.0 ± 0.5 V CL = 15 pF

RL = 1000 WCL = 50 pF

ÎÎÎ

3.5

4.5

ÎÎÎ

5.1

7.1

ÎÎ

ÎÎÎ

6.0

8.0

ÎÎÎ

ÎÎÎÎ

8.5

10.5

ÎÎÎÎ

tPLZ,

tPHZ

ÎÎÎÎÎÎÎÎ

Maximum Output

Disable Time,

Input OE to Y

(Figures 4 and 5)

ÎÎÎÎÎÎÎÎ

VCC = 3.3 ± 0.3 V CL = 15 pF

RL 1000 WCL = 50 pF

ÎÎÎ

6.5

8.0

ÎÎÎ

9.7

13.2

ÎÎ

ÎÎÎ

11.5

15.0

ÎÎÎ

ÎÎÎÎ

14.5

18.0

ÎÎ

ns

ÎÎÎÎÎÎÎÎ

VCC = 5.0 ± 0.5 V CL = 15 pF

RL = 1000 WCL = 50 pF

ÎÎÎ

4.8

7.0

ÎÎÎ

6.8

8.8

ÎÎ

ÎÎÎ

8.0

10.0

ÎÎÎ

ÎÎÎÎ

10.0

12.0

ÎÎÎÎ

CIN

ÎÎÎÎÎÎÎÎ

Maximum Input

Capacitance

ÎÎÎÎÎÎÎÎ

ÎÎÎ

4.0

ÎÎÎ

10

ÎÎ

ÎÎÎ

10

ÎÎÎ

ÎÎÎÎ

10

ÎÎ

pF

ÎÎÎÎ

COUT

ÎÎÎÎÎÎÎÎ

Maximum 3−State Output

Capacitance (Output in

High Impedance State)

ÎÎÎÎÎÎÎÎ

ÎÎÎ

6.0

ÎÎÎ

ÎÎ

ÎÎÎ

ÎÎÎÎ

ÎÎ

pF

CPD Power Dissipation Capacitance (Note 5)

Typical @ 25°C, VCC = 5.0 V

pF

8.0

5. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.

Average operating current can be obtained by the equation: ICC(OPR) = CPD  VCC  fin + ICC. CPD is used to determine the no−load dynamic

power consumption; PD = CPD  VCC2  fin + ICC  VCC.

MC74VHC1G125

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4

SWITCHING WAVEFORMS

Figure 4. Switching Wave Forms Figure 5.

Y

50%

50% VCC

VCC

GND

HIGH

IMPEDANCE

VOL + 0.3V

VOH - 0.3V

Y

OE

tPZL tPLZ

tPZH tPHZ

*Includes all probe and jig capacitance

CL*

TEST POINT

DEVICE

UNDER

TEST

OUTPUT

Figure 6. Test Circuit

*Includes all probe and jig capacitance

Figure 7. Test Circuit

OUTPUT

TEST POINT

CL *

1 kWCONNECT TO VCC WHEN

TESTING tPLZ AND tPZL.

CONNECT TO GND WHEN

TESTING tPHZ AND tPZH.

DEVICE

UNDER

TEST

HIGH

IMPEDANCE

50%

50% VCC

VCC

GND

tPLH tPHL

A

Figure 8. Input Equivalent Circuit

INPUT

ORDERING INFORMATION

Device Package Shipping†

M74VHC1G125DFT1G SC−88A/SOT−353/SC−70

(Pb−Free)

3000 Units / Tape & Reel

M74VHC1G125DFT2G TSC−88A/SOT−353/SC−70

(Pb−Free)

M74VHC1G125DTT1G TSOP−5/SOT−23/SC−59

(Pb−Free)

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

MC74VHC1G125

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5

PACKAGE DIMENSIONS

NOTES:

1. DIMENSIONING AND TOLERANCING

PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. 419A−01 OBSOLETE. NEW STANDARD

419A−02.

4. DIMENSIONS A AND B DO NOT INCLUDE

MOLD FLASH, PROTRUSIONS, OR GATE

BURRS.

DIM

A

MIN MAX MIN MAX

MILLIMETERS

1.80 2.200.071 0.087

INCHES

B1.15 1.350.045 0.053

C0.80 1.100.031 0.043

D0.10 0.300.004 0.012

G0.65 BSC0.026 BSC

H--- 0.10---0.004

J0.10 0.250.004 0.010

K0.10 0.300.004 0.012

N0.20 REF0.008 REF

S2.00 2.200.079 0.087

B0.2 (0.008) MM

12 3

45

A

G

S

D 5 PL

H

C

N

J

K

−B−

SC−88A (SC−70−5/SOT−353)

CASE 419A−02

ISSUE K

MC74VHC1G125

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6

PACKAGE DIMENSIONS

TSOP−5

CASE 483−02

ISSUE H

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. MAXIMUM LEAD THICKNESS INCLUDES

LEAD FINISH THICKNESS. MINIMUM LEAD

THICKNESS IS THE MINIMUM THICKNESS

OF BASE MATERIAL.

4. DIMENSIONS A AND B DO NOT INCLUDE

MOLD FLASH, PROTRUSIONS, OR GATE

BURRS.

5. OPTIONAL CONSTRUCTION: AN

ADDITIONAL TRIMMED LEAD IS ALLOWED

IN THIS LOCATION. TRIMMED LEAD NOT TO

EXTEND MORE THAN 0.2 FROM BODY.

DIM MIN MAX

MILLIMETERS

A3.00 BSC

B1.50 BSC

C0.90 1.10

D0.25 0.50

G0.95 BSC

H0.01 0.10

J0.10 0.26

K0.20 0.60

L1.25 1.55

M0 10

S2.50 3.00

123

54 S

A

G

L

B

D

H

C

J

__

0.7

0.028

1.0

0.039

ǒmm

inchesǓ

SCALE 10:1

0.95

0.037

2.4

0.094

1.9

0.074

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

0.20

5X

CAB

T0.10

2X

2X T0.20

NOTE 5

T

SEATING

PLANE

0.05

K

M

DETAIL Z

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to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights

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PUBLICATION ORDERING INFORMATION

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Phone: 421 33 790 2910

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Phone: 81−3−5773−3850

MC74VHC1G125/D

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