Rev. 4235H–8051–10/06
1
Features
•80C52 Compatibl e
– 8051 Instruction Compatibl e
– Six 8-bit I/O Ports (64 Pins or 68 Pins Versions)
– Four 8-bit I/O P o rts (44 Pins Version )
– Three 16-bit Timer/ Counters
– 256 Bytes Scratch Pad RAM
– 9 Interrup t Sources wi th 4 Priority Levels
•Integrated Power Monitor (POR/PFD) to Super vise Internal Power Suppl y
•ISP (In-System Programming) Using Standard VCC Power Supply
•2048 Bytes Bo ot ROM Contains Low Level Flash Programming Routines a nd a Defaul t
Serial Loader
•High-speed Architecture
– In Standard Mode:
40 MHz (Vcc 2.7V to 5.5V, both Internal and external code execution)
60 MHz (Vcc 4.5V to 5.5V an d Inte rnal Code execution only)
– In X2 mode (6 Clocks/machine cycle)
20 MHz (Vcc 2.7V to 5.5V, both Internal and external code execution)
30 MHz (Vcc 4.5V to 5.5V an d Inte rnal Code execution only)
•64K Bytes On-chip Flash Program/Data Memory
– Byte and Page (128 By tes) Erase and W rite
– 100k Write Cyc les
•On-chip 1792 bytes Expanded RAM (XRAM)
– Software Selectable Size (0 , 256, 512, 768 , 1024, 1792 Bytes)
– 768 Bytes Sel ected at Reset for T89C51RD2 Compatibility
•On-chip 2048 Bytes EEPROM Block for Data Storage (AT89C51ED2 Only)
– 100K Write Cycles
•Dual Dat a Poi nter
•Variable Lengt h MOVX for Slow RAM/Per ipherals
•Improved X2 Mode with Independent Selection for CPU and Each Periphe ral
•Keyboard Interrupt Int erface on Port 1
•SPI Int erface (Master/Sl ave Mode)
•8-bit Clock Prescaler
•16-bit Programmable Counter Array
– High Speed Out put
–Compare/Capture
– Pulse W idth Modulator
– Watchdog Timer Capabilities
•Asynchronous Port Reset
•Full -duplex Enhanced UART with Dedi cated Internal Baud Rate Generator
•Low EMI (Inhibit ALE)
•Hardware Watchdog Timer (One-time Enabl ed wit h Reset- Out), Power-off Flag
•Power Contr ol Modes: Idle Mode, Power-down Mode
•Single Range Power Supply: 2.7V t o 5.5V
•Industrial Temper ature Range (-40 to +85°C)
•Packages: PLCC44, VQFP44, PLCC68, VQFP64, PDIL40
Description
AT89C51RD2/ED2 is high performance CMOS Flash version of th e 80C51 CMOS sin-
gle chip 8-bit microcont roller. It contains a 64-Kbyte Flash m em ory block for c ode and
for data.
The 64-Kby tes F lash memory can be programm ed either in parallel mod e or in serial
mode with t he ISP ca pability o r with softwa re. The prog rammi ng voltage is intern ally
generated from the standard VCC pin.
8-bit Flash
Microcontroller
AT89C51RD2
AT89C51ED2
2
AT89C51RD2/ED2
4235H–8051–10/06
The A T89C51RD2/E D2 retains all of the features of the A tmel 80C5 2 with 256 bytes of
intern al RAM, a 9-sour ce 4-level interrupt con troller and three timer/counters. The
AT 89C51ED2 prov ides 2048 byt es of EEPRO M fo r nonvolatile data storage.
In addition, the AT89C51RD2/E D2 has a Programmable Counter A rray, an X RAM of
1792 bytes, a Hardware Watchdog T imer, SPI interface, Keyboard, a more versat ile
serial chan nel that facilitates multiprocessor communication (EUART) and a speed
improvem ent mechanism (X2 Mode ).
The fully static design of the AT89C51RD2/ED2 allows to reduce sys tem power con-
sumpt ion by bring ing the clock fr equency d own t o any value , including DC, without loss
of data.
The A T89C5 1RD2/ED2 has 2 software-s electabl e mode s of reduced a ctivity and an 8-
bit clock prescaler for further reduction in power consumption. In the Idle mode the CPU
is frozen while the pe ripherals and the interrupt system are still operating. In the Power-
down mode the RAM is saved and all other func tions are inoperative.
The added features of the AT89C51RD2/ED2 make it more powerful for applic at ions
that need pulse width modulation, high sp eed I/O and counting capabilities such as
alarms, motor cont rol , corded phones, and smart card readers.
Table 1. M em ory Size and I/O Pins
Package Flash (Bytes) XRAM (Bytes) Total RA M (Bytes ) I/O
PLCC44/VQFP44/DIL40 64K 1792 2048 34
PLCC68/VQFP64 64K 1792 2048 50
3
AT89C51RD2/ED2
4235H–8051–10/06
Block Diagram
Figu re 1. Block Diagram
Timer 0 INT
RAM
256x8
T0
T1 RxD
TxD
WR
RD
EA
PSEN
ALE/
XTALA2
XTALA1 EUART
CPU
Timer 1
INT1
Ctrl
INT0
(2)
(2)
C51
CORE
(2) (2) (2) (2)
Port 0
P0
Port 1
Por t 2
Port 3
P1
P2
P3
XRAM
1792 x 8
IB-bus
PCA
RESET
PROG
Watch
-dog
PCA
ECI
VSS
VCC
(2)(2) (1)
(1): Alternate function of Port 1
(2): Alternate function of Port 3
(1)
Timer2
T2EX
T2
(1) (1)
Flash
64K x 8
Keyboard
(1)
Keyboard
MISO
MOSI
SCK
SS
Port4
P4
(1) (1)(1)(1)
BOOT
2K x 8
ROM
Regulator
POR / PFD
Port 5
P5
Parallel I/O Ports &
External Bus SPI
EEPROM*
2K x 8
(AT89C51ED2)
4
AT89C51RD2/ED2
4235H–8051–10/06
SFR Mapping The Specia l Function Registers (SFRs) o f the AT89C 51RD 2/ED2 fall into t he follo wing
categories:
• C 51 core registers: ACC, B , DPH, DPL, PSW, SP
• I/O port r e g isters: P0, P1, P2, P3 , PI2
• T i m er registers: T 2CON, T2MOD, TCON, TH0, TH1, TH2, TMOD, TL0, TL1, TL2,
RCAP2L, RCAP2H
• Serial I/O port registers: SADDR, SADEN, SBUF, SCON
• PCA (Programmable Counter Array) registers : CCON, CCAPMx , CL, CH, CCAPxH,
CCAPxL (x: 0 t o 4)
• Power and clock control registers: PCON
• Hardware Watchdog T i mer registers: WDTRST, WDTPRG
• Interrupt system registers: IE0, IPL0, IPH0, IE1, IPL1, IPH1
• Keyboard Interface registers: KBE, KBF, KBLS
• SPI regi sters: SPCON , SPST R , SPDAT
• BRG (Baud Rate Generator) registers: BRL, BDRCON
• Clock Prescaler register: CKRL
• Others: AUXR, AUXR1, CKCON0, CKCON1
5
AT89C51RD2/ED2
4235H–8051–10/06
Tab le 2. C51 Core SFRs
MnemonicAddName 76543210
ACC E0h Accumulator
B F0h B Register
PSW D0h Program Status Word CY AC F0 RS1 RS0 OV F1 P
SP 81h Stack Pointer
DPL 82h Data Pointer Low By te
DPH 83h Data Pointer High Byte
Tab le 3. System Management SFRs
MnemonicAddName 76543210
P CON 87h Po wer C on trol SM OD 1 SM OD 0 - P O F GF 1 GF 0 PD IDL
AUXR 8Eh Auxiliary Regis ter 0 DPU - M0 XRS2 XRS1 XRS0 EXTRAM AO
AUXR1 A2h Auxiliary Register 1 - - ENBOOT -GF30 -DPS
CKRL97hClock Reload Register --------
CK CKO N0 8F h Clo c k Contro l Register 0 - W DTX 2 PCA X2 SIX2 T2X2 T1X2 T0X2 X2
CKCKON1AFhClock Control Register 1 -------SPIX2
Tab le 4. Interrupt SFRs
MnemonicAddName 76543210
IEN0 A8h Interrupt Enable Control 0 EA EC ET2 ES ET1 EX1 ET0 EX0
IEN1 B1hInterrupt Enable Control 1 -----ESPI KBD
IPH0 B7h Interrupt Priority Control High 0 - PPCH PT2H PHS PT1H PX1H PT0H PX0H
IPL0 B8h Interru pt Priority Control Low 0 - PPCL PT2L PLS PT1L PX1L PT0L PX0L
IPH1 B3hInterrupt Priority Control High 1-----SPIH KBDH
IPL1 B2hInterrupt Priority Control Low 1-----SPIL KBDL
Tab le 5. Port SFRs
MnemonicAddName 76543210
P0 80h 8-bit Port 0
P1 90h 8-bit Port 1
P2 A0h 8-bit Port 2
P3 B0h 8-bit Port 3
P4 C0h 8-b it Port 4
6
AT89C51RD2/ED2
4235H–8051–10/06
P5 D8h 8-b it Port 5
P5 C7h 8-bit Port 5 (byte addressable)
Tab le 5. Port SFRs
MnemonicAddName 76543210
Tab le 6. Ti mer S FR s
MnemonicAddName 76543210
T CO N 88h Time r /C o un ter 0 and 1 Control TF 1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
T MOD 89h Time r/C o un ter 0 and 1 Mo de s G AT E 1 C/ T 1 # M11 M 0 1 GATE0 C/ T0 # M 1 0 M0 0
TL0 8Ah Timer/Counter 0 Low Byte
TH0 8Ch Ti mer/Counte r 0 Hig h Byte
TL1 8Bh Timer/Counter 1 Low Byte
TH1 8Dh Timer/Co unter 1 High Byt e
WD TRST A6 h Watc hDog Timer Reset
WDTPRGA7hWatchDog Timer Program -----WTO2WTO1WTO0
T2CON C8h Tim er/Counter 2 control TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2# CP/RL2#
T2MODC9hTimer/Counter 2 Mode ------T2OEDCEN
RCAP2H CBh T im er/C ounter 2 Re load /Cap ture
High Byte
RCAP2L CAh T imer /Cou nter 2 Re load/C aptur e
Low Byte
TH2 CDh Ti mer/Counte r 2 High Byte
TL2 CCh Timer/Counter 2 Low Byte
Tab le 7. PCA SFRs
Mnemo
-nicAddName 76543210
CCON D8h PCA Ti mer/Counter Control CF CR CCF4 CCF3 CCF2 CCF1 CCF0
CMOD D9h PCA T imer/Counter Mode CIDL WDTE CPS1 CPS0 ECF
CL E9h PCA Timer/Counter Low Byte
CH F9h PCA Timer/Counter High Byte
CCAPM0
CCAPM1
CCAPM2
CCAPM3
CCAPM4
DAh
DBh
DCh
DDh
DEh
PCA Timer/Counter Mode 0
PCA Timer/Counter Mode 1
PCA Timer/Counter Mode 2
PCA Timer/Counter Mode 3
PCA Timer/Counter Mode 4
ECOM0
ECOM1
ECOM2
ECOM3
ECOM4
CAPP0
CAPP1
CAPP2
CAPP3
CAPP4
CAPN0
CAPN1
CAPN2
CAPN3
CAPN4
MAT0
MAT1
MAT2
MAT3
MAT4
TOG0
TOG1
TOG2
TOG3
TOG4
PWM0
PWM1
PWM2
PWM3
PWM4
ECCF0
ECCF1
ECCF2
ECCF3
ECCF4
7
AT89C51RD2/ED2
4235H–8051–10/06
CCAP0H
CCAP1H
CCAP2H
CCAP3H
CCAP4H
FAh
FBh
FCh
FDh
FEh
PC A Compare Captu re Module 0 H
PC A Compare Captu re Module 1 H
PC A Compare Captu re Module 2 H
PC A Compare Captu re Module 3 H
PC A Compare Captu re Module 4 H
CCAP0H7
CCAP1H7
CCAP2H7
CCAP3H7
CCAP4H7
CCAP0H6
CCAP1H6
CCAP2H6
CCAP3H6
CCAP4H6
CCAP0H5
CCAP1H5
CCAP2H5
CCAP3H5
CCAP4H5
CCAP0H4
CCAP1H4
CCAP2H4
CCAP3H4
CCAP4H4
CCAP0H3
CCAP1H3
CCAP2H3
CCAP3H3
CCAP4H3
CCAP0H2
CCAP1H2
CCAP2H2
CCAP3H2
CCAP4H2
CCAP0H1
CCAP1H1
CCAP2H1
CCAP3H1
CCAP4H1
CCAP0H0
CCAP1H0
CCAP2H0
CCAP3H0
CCAP4H0
CCAP0L
CCAP1L
CCAP2L
CCAP3L
CCAP4L
EAh
EBh
ECh
EDh
EEh
PCA Compare Capture Module 0 L
PCA Compare Capture Module 1 L
PCA Compare Capture Module 2 L
PCA Compare Capture Module 3 L
PCA Compare Capture Module 4 L
CCAP0L7
CCAP1L7
CCAP2L7
CCAP3L7
CCAP4L7
CCAP0L6
CCAP1L6
CCAP2L6
CCAP3L6
CCAP4L6
CCAP0L5
CCAP1L5
CCAP2L5
CCAP3L5
CCAP4L5
CCAP0L4
CCAP1L4
CCAP2L4
CCAP3L4
CCAP4L4
CCAP0L3
CCAP1L3
CCAP2L3
CCAP3L3
CCAP4L3
CCAP0L2
CCAP1L2
CCAP2L2
CCAP3L2
CCAP4L2
CCAP0L1
CCAP1L1
CCAP2L1
CCAP3L1
CCAP4L1
CCAP0L0
CCAP1L0
CCAP2L0
CCAP3L0
CCAP4L0
Tab le 8. Serial I/O Port SFRs
MnemonicAddName 76543210
SCO N 98h Serial Control FE/SM0 SM1 SM2 REN TB8 RB8 TI RI
SBUF 99h Serial Data Buffer
SADEN B9h Sl ave Address Mask
SAD DR A9h Sl ave Addre ss
BDRCON 9Bh Baud Rate Control BRR TBCK RBCK SPD SRC
BRL 9Ah Baud Rate Reload
Tab le 7. PCA SFRs (Continued)
Mnemo
-nicAddName 76543210
Tab le 9. SPI Controller SFRs
MnemonicAddName 76543210
SPCON C3h SPI Control SPR2 SPEN SSDIS MSTR CPOL CPHA SPR1 SPR0
SPST A C4h SPI Status SPIF WCOL SSERR MODF
SPDAT C5h SPI Data SPD7 SPD6 SPD5 SPD4 SPD3 SPD2 SPD1 SPD0
Tab le 10. Keyboard I nterface SFRs
MnemonicAddName 76543210
KBLS 9Ch Keybo ard Level Selector KBLS7 KBLS6 KBLS5 KBLS4 KBLS3 KBLS2 KBLS1 KBLS0
KBE 9Dh Keyboard Input Enable KBE7 KBE6 KBE5 KBE4 KBE3 KBE2 KBE1 KBE0
KBF 9Eh Keyboard Flag Register KBF7 KBF6 KBF5 KBF4 KBF3 KBF2 KBF1 KBF0
Table 11. EEPROM data Memory SFR (A T8 9C51ED2 only)
MnemonicAddName 76543210
EECON D2h EEPROM Data Control EEE EEBUSY
8
AT89C51RD2/ED2
4235H–8051–10/06
Table 12 shows all SFRs with their address and their reset value.
Tab le 12. SFR Mappin g
Bit
Add ressa ble Non B it Addressable
0/8 1/9 2/A 3/B 4/C 5/D 6/E 7/F
F8h CH
0000 0000 CCAP0H
XXXX XXXX CCAP1H
XXXX XXXX CCAP2H
XXXX XXXX CCAP3H
XXXX XXXX CCAP4H
XXXX XXXX FFh
F0h B
0000 0000 F7h
E8h P5 bit
addressable
1111 1111
CL
0000 0000 CCAP0L
XXXX XXXX CCAP1L
XXXX XXXX CCAP2L
XXXX XXXX CCAP3L
XXXX XXXX CCAP4L
XXXX XXXX EFh
E0h ACC
0000 0000 E7h
D8h CCON
00X0 0000 CMOD
00XX X000 CCAPM0
X000 0000 CCAPM1
X000 0000 CCAPM2
X00 0 00 00 CCAPM3
X000 0000 CCAPM4
X000 0000 DFh
D0h PSW
0000 0000 FCON
XXXX 0000 EECON
xxxx xx00 D7h
C8h T2CON
0000 0000 T2MOD
XXXX XX00 RCAP2L
0000 0000 RCAP2H
0000 0000 TL2
0000 0000 TH2
0000 0000 CFh
C0h P4
1111 1111 SPCON
0001 0100 SPSTA
0000 0000 SPDAT
XXXX XXXX
P5 byte
Addressable
1111 1111 C7h
B8h IPL0
X000 000 SADEN
0000 0000 BFh
B0h P3
1111 1111 IEN1
XXXX X000 IPL1
XXXX X000 IPH1
XXXX X111 IPH0
X000 0000 B7h
A8h IEN0
0000 0000 SADDR
0000 0000 CKCON1
XXXX XXX0 AFh
A0h P2
1111 1111 AUXR1
0XXX X0X0 WDTRST
XXXX XXXX WDTPRG
XXXX X000 A7h
98h SCON
0000 0000 SBUF
XXXX XXXX BRL
0000 0000 BDRCON
XXX0 0000 KBLS
0000 0000 KBE
0000 0000 KBF
0000 0000 9Fh
90h P1
1111 1111 CKRL
1111 1111 97h
88h TCON
0000 0000 TMOD
0000 0000 TL0
0000 0000 TL1
0000 0000 TH0
0000 0000 TH1
0000 0000 AUXR
XX00 1000 CKCON0
0000 0000 8Fh
80h P0
1111 1111 SP
0000 0111 DPL
0000 0000 DPH
0000 0000 PCON
00X1 0000 87h
0/8 1/9 2/A 3/B 4/C 5/D 6/E 7/F
reserved
9
AT89C51RD2/ED2
4235H–8051–10/06
Pin Config urations
Figu re 2. Pin Confi gurations
43 42 41 40 3944 38 37 36 35 34
P1.4/CEX1
P1.0/T2
P1.1/T2EX/SS
P1.3/CEX0
P1.2/ECI
VCC
P0.0/AD0
P0.2/AD2
P0.3/AD3
P0.1/AD1
P0.4/AD4
P0.6/AD6
P0.5/AD5
P0.7/AD7
ALE/PROG
PSEN
EA
P2.7/A15
P2.5/A13
P2.6/A14
P1.5/CEX2/MISO
P1.6/CEX3/SCK
P1.7/CEX4/MOSI
RST
P3.0/RxD
P3.1/TxD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
P3.6/WR
P3.7/RD
XTAL2
XTAL1
VSS
P2.0/A8
P2.1/A9
P2.2/A10
P2.3/A11
P2.4/A12
NIC*
1213 17161514 201918 2122
33
32
31
30
29
28
27
26
25
24
23
AT89C51RD2/ED2
1
2
3
4
5
6
7
8
9
10
11
VQFP44 1.4
NIC*
NIC*
NIC*
PLCC44
AT89C51RD2/ED2
NIC*
NIC*
NIC*
PDIL40
P1.7CEX4/MOSI
P1.4/CEX1
RST
P3.0/RxD
P3.1/TxD
P1.3CEX0
1
P1.5/CEX2/MISO
P1.6/CEX3/SCK
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
P3.6/WR
P3.7/RD
XTAL2
XTAL1
VSS P2.0/A8
P2.1/A9
P2.2/A10
P2.3/A11
P2.4/A12
P0.4/AD4
P0.6/AD6
P0.5/AD5
P0.7/AD7
ALE/PROG
PSEN
EA
P2.7/A15
P2.5/A13
P2.6/A14
P1.0/T2
P1.2/ECI
P1.1/T2EX/SS VCC
P0.0/AD0
P0.1/AD1
P0.2/AD2
P0.3/AD3
AT89C51ED2
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
18 19 23222120 262524 2728
5 4 3 2 1 6 44 43 42 41 40
P1.4/CEX1
P1.0/T2
P1.1/T2EX/SS
P1.3/CEX0
P1.2/ECI
VCC
P0.0/AD0
P0.2/AD2
P0.1/AD1
P0.4/AD4
P0.6/AD6
P0.5/AD5
P0.7/AD7
ALE/PROG
PSEN
EA
P2.7/A15
P2.5/A13
P2.6/A14
P3.6/WR
P3.7/RD
XTAL2
XTAL1
VSS
P2.0/A8
P2.1/A9
P2.2/A10
P2.3/A11
P2.4/A12
P1.5/CEX2/MISO
P1.6/CEX3/SCK
P1.7/CEx4/MOSI
RST
P3.0/RxD
P3.1/TxD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
P0.3/AD3
NIC*
7
8
9
10
11
12
13
14
15
16
17
39
38
37
36
35
34
33
32
31
30
29
10
AT89C51RD2/ED2
4235H–8051–10/06
50
49
48
47
44
45
46
P4.5
P3.7/RD
XTAL2
XTAL1
P4.4
P3.6/WR
P4.3
NIC
NIC
P3.1/TxD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
37
38
39
40
41
42
43
AT89C51ED2
PLCC68
P0.4/AD4
P5.4
P5.3
P0.5/AD5
P0.6/AD6
NIC
P0.7/AD7
EA
NIC
ALE
P1.6/CEX3/SCK
P1.7/CEX4/MOSI
RST
NIC
NIC
NIC
P3.0/RxD
NIC
NIC
P1.5/CEX2/MISO
60
59
58
57
56
55
54
53
51
52
10
11
12
13
14
15
16
17
19
18
27
28
29
30
31
32
33
34
35
36
9
8
7
6
5
3
2
1
68
P5.0
P2.4/A12
P2.3/A11
P4.7
P2.2/A10
P4.6
P2.0/A8
P2.1/A9
NIC
VSS
P5.5
P0.3/AD3
P0.2/AD2
P5.6
P0.1/AD1
P0.0/AD0
P5.7
VCC
NIC
P1.0/T2
4
PSEN
NIC
P2.7/A15
P2.6/A14
P5.2
P5.1
P2.5/A13
67
65
64
63
62
61
66
20
21
22
23
26
25
24
P4.0
P1.1/T2EX/SS
P1.2/ECI
P1.3/CEX0
P4.1
P1.4/CEX1
P4.2
NIC: Not Internaly Co n nected
54
53
52
51
50
49
AT89C51ED2
VQFP64
P0.4/AD4
P5.4
P5.3
P0.5/AD5
P0.6/AD6
P0.7/AD7
EA
NIC
ALE
PSEN#
P1.5/CEX2/MISO
P1.6/CEX3/SCK
P1.7/A17/CEX4/MOSI
RST
NIC
NIC
NIC
P3.0/RxD
NIC
P4.2
48
47
46
45
44
43
42
41
39
40
1
2
3
4
5
6
7
8
10
9
17
18
19
20
21
22
23
24
25
26
64
63
62
61
60
59
58
57
56
55
P2.4/A12
P2.3/A11
P4.7
P2.2/A10
P2.1/A9
NIC
P4.6
P2.0/A8
VSS
P4.5
P5.5
P0.3/AD3
P0.2/AD2
P5.6
P0.1/AD1
P0.0/AD0
P5.7
VCC
NIC
P1.0/T2 11
12
13
16
15
14
P4.0
P1.1/T2EX/SS
P1.2/ECI
P1.3/CEX0
P4.1
P1.4/CEX1
38
37
36
33
34
35 P3.7/RD
XTAL2
XTAL1
P4.4
P3.6/WR
P4.3
NIC
P3.1/TxD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
27
28
29
30
31
32
P2.7/A15
P2.6/A14
P5.2
P5.1
P2.5/A13
P5.0
11
AT89C51RD2/ED2
4235H–8051–10/06
Tab le 13. Pin Description
Mnemonic
Pin Number Type Name and FunctionPLCC44 VQFP44 PLCC68 VQFP64 PDIL40
VSS 22 16 51 40 20 I Ground: 0V reference
VCC 44 38 17 8 40 I P ow er Supp ly : This is the power supply voltage for n ormal, id le and
power-down operation
P0.0 - P0.7 43 - 36 37 - 30 15, 14,
12, 11,
9,6, 5, 3
6, 5, 3,
2, 64,
61,60,59 I/O
Po rt 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that
have 1s written to them float and can be used as high impedance inputs.
Port 0 must be polarized to VCC or VSS in order to prevent any parasitic
curr ent consumption. Port 0 is also the multiplex ed low-order address
and da t a bus d ur ing acc ess to exte rn al pr o gra m and dat a me mo ry. In th i s
application, it uses stro ng internal pull-up when emit ting 1s. Port 0 also
inpu t s t he co de byt e s dur in g EP ROM pr o gra mmi ng. E xt er na l pul l- up s ar e
required during program verification during which P0 outputs the code
bytes.
32-39
P1.0 - P1.7 2 - 9 40 - 44
1 - 3
19, 21,
22, 23,
25, 27,
28, 29
10, 12 ,
13, 14 ,
16, 18 ,
19, 20
1-8 I/O Po r t 1 : Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1
pins that have 1s written to the m are pulled high by the int ernal pull-ups
and can be used as inputs . As inputs, Port 1 pins that are externall y
pulled low will source current because of the internal pull-ups. Port 1 also
receives the low-order address byte during memory programming and
verification.
Alternate functions for AT89C51RD2/ED2 Port 1 include:
24019 10 1I/OP1.0: Input/Output
I/O T2 (P1.0): Timer/Counter 2 external co unt inp ut/Clockout
34121 12 2I/OP1.1: Input/Output
IT2EX: Timer/Counter 2 Reload/Capture/Direction Control
ISS: SPI Slave Select
44222 13 3I/OP1.2: Input/Output
IECI: External Clock for the PCA
54323 14 4I/OP1.3: Input/Output
I/O CEX0: Capture/Compare External I/O for PCA module 0
64425 16 5I/OP1.4: Input/Output
I/O CEX1: Capture/Compare External I/O for PCA module 1
7 1 27 18 6 I/O P1.5: Input/Output
I/O CEX2: Capture/Compare External I/O for PCA module 2
I/O MISO: SPI Master Input Slave Output line
When SPI is in master mode, MISO receives data from the s lave per iph-
eral. When SPI is in slave mode, MISO outputs data to the master con-
troller.
8 2 28 19 7 I/O P1.6: Input/Output
I/O CEX3: Capture/Compare External I/O for PCA module 3
I/O SCK: SPI Serial Clock
12
AT89C51RD2/ED2
4235H–8051–10/06
9 3 29 20 8 I/O P1.7: Input/Output:
I/O CEX4: Capture/Compare External I/O for PCA module 4
I/O MOSI: SPI Master Output Slave Input line
When SPI is in master mode, MOSI outputs data t o the slave peripheral.
When SPI is in slave mo de, MOSI receives data from the mast er cont rol-
ler.
XTALA1 21 15 49 38 19 I XTALA 1: Input to the inverting oscillato r amplifier and input to the inter-
nal clock generator circuits.
XTALA2 20 14 48 37 18 O XTALA 2: Output from the inverting oscillator amplifier
P2.0 - P2.7 24 - 31 18 - 25
54, 55,
56, 58,
59, 61,
64, 65
43, 44 ,
45, 47 ,
48, 50 ,
53, 54
I/O
Po rt 2 : P ort 2 i s an 8 - bi t bid ir ect i ona l I/O po r t wit h int er nal pu ll -up s . P or t 2
pins that have 1s written to the m are pulled high by the int ernal pull-ups
and can be used as inputs . As inputs, Port 2 pins that are externally
pulled low w ill source current because of the int ernal pull-ups. Port 2
emits the high-order address byte during fet ches fr om external program
memory and during acce sses to external data memory that use 16-bit
addresses (MOVX @DP TR ).In this application, it uses strong internal
pull-ups emitting 1s. During accesses to external data memory that use
8-bit addresses (MOVX @Ri), port 2 emits the contents of the P2 SF R.
21-28
P3.0 - P3.7 11,
13 - 19 5,
7 - 13
34, 39,
40, 41,
42, 43,
45, 47
25, 28 ,
29, 30 ,
31, 32 ,
34, 36
10-17 I/O Po rt 3 : Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3
pins that have 1s written to the m are pulled high by the int ernal pull-ups
and can be used as inputs . As inputs, Port 3 pins that are externall y
pulled low will source current because of the internal pull-ups. Port 3 also
serves the special features of the 80C51 family, as listed below .
115342510IRXD (P3.0): Serial input port
137392811OTXD (P3.1): Serial ou tp ut po r t
148402912IINT0 (P3.2): External interrupt 0
159413013IINT1 (P3.3): External interrupt 1
16 10 42 31 14 I T0 (P3.4): Timer 0 exter nal input
17 11 43 32 15 I T1 (P3.5): Timer 1 external input
18 12 45 34 16 O WR (P3.6): Extern al data memory write strobe
19 13 47 36 17 O RD (P3. 7) : External data memory read strobe
P4.0 - P4.7 --
20, 24,
26, 44,
46, 50,
53, 57
11, 15,
17,33,
35,39,
42, 46
-I/O
Po rt 4 : Port 4 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3
pins that have 1s written to the m are pulled high by the int ernal pull-ups
and can be used as inputs . As inputs, Port 3 pins that are externall y
pulled low w ill source current because of the int ernal pull-ups.
P5.0 - P5.7 --
60, 62,
63, 7, 8,
10, 13,
16
49, 51 ,
52, 62 ,
63, 1, 4,
7
-I/O
Po rt 5 : Port 5 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3
pins that have 1s written to the m are pulled high by the int ernal pull-ups
and can be used as inputs . As inputs, Port 3 pins that are externall y
pulled low w ill source current because of the int ernal pull-ups.
RST 10 4 30 21 9 I
Reset: A high on this pin for two machine cycles while the oscillator is
running, resets the device. An internal diffused resistor to VSS permi ts a
power-on reset using only an ext ernal capacito r to VCC. This pin is an out-
put w hen the hardware watchdog force s a system r eset.
Tab le 13. Pin Description (Continued)
Mnemonic
Pin Number Type Name and FunctionPLCC44 VQFP44 PLCC68 VQFP64 PDIL40
13
AT89C51RD2/ED2
4235H–8051–10/06
ALE/PRO
G33 27 68 56 30 O (I) Add ress Latch Enable/Program Pu lse: Output pulse for latching th e
low by te of the addr ess during an access to external memory. In normal
operation, ALE is emitted at a constant rate of 1/6 (1/3 in X2 mode) the
os cill at or f r eque nc y, and ca n b e u sed for e xter n al timi ng or c lo ck in g. Not e
that one ALE puls e is skipped during each access to external data mem-
ory. This pin is also the program pulse i nput (PROG) during Flash pro-
gramming . ALE can be disabled by se tting SFR’s AUXR.0 bit. With this
bit set, ALE will be inactive during internal fetches.
PSEN 32 26 67 55 29 O Program Strobe ENable: The read strobe to external progra m memory.
When executing code from the external program mem ory, PSEN is acti-
vated twic e each machine cycle, except that two PSEN activ a tio ns ar e
skipped during each acce ss to external data memory. PS EN is not acti-
vated during fetches from internal program memory.
EA 35 29 2 58 31 I External Access Enable: EA must be externally held low to enable the
device to fetch code from external program memory locations 0000H to
FFFFH. If security level 1 is programmed, EA will be internally latched on
Reset.
Tab le 13. Pin Description (Continued)
Mnemonic
Pin Number Type Name and FunctionPLCC44 VQFP44 PLCC68 VQFP64 PDIL40
14
AT89C51RD2/ED2
4235H–8051–10/06
Port Types AT 89C51RD2 /ED2 I/O ports (P1, P2, P3, P4, P5) implement the quasi-bidirectional out-
put th at is comm on on the 80C5 1 an d mo st o f its de rivati ve s. T his o utp ut ty pe c an b e
used as both an input an d outp ut without the need t o reconfigure the port. This is possi-
ble because whe n t he port outputs a logic h igh, it i s weakly driven, al lowing an external
device to pull the pin low. When the pin is pul led low, i t is dri ven strongly and able to sink
a fairly large current. These features are somew hat similar to an open drain output
except tha t there are three pull-up transistors in the quasi-bidirectional outpu t that serve
different purpo ses. One o f these pull-ups, c alled the "weak" pull-up, is turned on when-
ever the port latch for the pin contains a logic 1. The weak pull-up sources a very small
current that will pull the pin high if it is left f l oating. A second pull-up, called the "medium"
pull-up, is turned on when the port latch for t he pin contains a logic 1 and the pin itself is
also at a logic 1 level. This pu ll-up provides t he primary source current for a quasi-bidi-
rectional pin that is outputting a 1. If a pin that has a logic 1 on it is pulled low by an
externa l device, the m edium pull-u p turns o ff, and only the we ak pull-up rem ains on. In
order to pull the pin low under these cond iti ons, the external device has to sink enou gh
cu rr ent to o verpow er the me dium pull -up and take the v oltage on the po rt pin bel ow its
input threshold.
The third pull-up is referred to as the "strong" pull-up. This pull-up is used to speed up
low-to-high transit i ons on a quasi-bidirectional port pin when the port latch changes f rom
a logic 0 to a lo gic 1. When this oc cu rs, the strong pu ll- up turns on for a brief time, t wo
CPU clocks, in order to pull t he port pin high quickly. Then it turns off again.
The DP U bit (bit 7 in AUX R register) allows to disable the perman ent we ak pull up of all
ports when latc h data is logical 0.
The quasi-bid irectional port configuration is shown in Figure 3.
Figu re 3. Quasi-B idire ctional Out put
2 CPU
Input
Pin
Strong Medium
N
Weak
P
Clock Delay
Port Latch
Data
Data
DPU
AUXR.7
PP
15
AT89C51RD2/ED2
4235H–8051–10/06
Oscillator T o op timi ze th e powe r co nsu mpti on an d exec utio n tim e nee de d for a s peci fic task, a n
internal prescaler feature has been implemented between the oscillator and the CPU
and peripherals.
Registers Table 14. CK RL Register
CKRL – Clock Reload Register (97h)
Rese t Value = 1111 1111b
Not bit addressable
Table 15. PCO N Regist er
PCO N – Power Control Register (87h)
Rese t Value = 00X1 0000b Not bit addressable
76543210
CKRL7 CKRL6 CKRL5 CKRL4 CKRL3 CKRL2 CKRL1 CKRL0
Bit Number Mnemonic Description
7:0 CKRL Clo ck Reload Register
Prescaler valu e
76543210
SMOD1 SMOD0 - POF GF1 GF0 PD IDL
Bit Number Bit Mnemoni c Description
7SMOD1
Serial Port M ode bit 1
Set to select double baud rate in mode 1, 2 or 3.
6SMOD0
Serial Port M ode bit 0
Cl ea red to selec t SM0 bit in SCON re gi ster.
Set to select FE bit in SCON register.
5-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4POF
Power-off Flag
Cl ea red by so ft war e t o re cog niz e th e n ext r es et ty pe .
Set by ha rdw ar e when VCC ris es from 0 to it s nomina l vo lt a ge. Can
also be set by software.
3GF1
Gen era l-pu r pos e Fla g
Cleared by software for general-purpose usage.
Set b y sof twa r e fo r ge ner al -pu rp os e usa ge .
2GF0
Gen era l-pu r pos e Fla g
Cleared by software for general-purpose usage.
Set b y sof twa r e fo r ge ner al -pu rp os e usa ge .
1PD
Power-down Mo de bit
Cleared by hardware when res et occurs.
Set to enter power-down mode.
0IDL
Idle Mode bit
Cleared by h ardware when interrupt o r re set occurs.
Set to enter idle mode.
16
AT89C51RD2/ED2
4235H–8051–10/06
Functional Block Diagram
Figu re 4. Functional Oscillator Block Diagram
Prescaler Divid er • A hardware RESET puts the prescaler divider in the following state:
•CKRL = FFh: F
CLK CPU = F CLK PERIPH = FOSC/2 (Standard C51 feature)
• Any value between FFh down to 00h can be written by software into CKR L register
in order to divide frequency of the sele cted os c illator:
• CK R L = 00h: minimum frequ enc y
FCLK CPU = F CLK PERIPH = FOSC/1020 (Standard Mode )
FCLK CPU = F CLK PERIPH = FOSC/510 (X2 Mode)
• C KR L = FF h: maximu m frequenc y
FCLK CPU = FCLK PERIPH = FOSC/2 (Standard Mode)
FCLK CPU = FCLK PERIPH = FOSC (X2 Mode)
FCLK CPU and FCLK PERIPH
In X 2 Mode, for CKRL<>0xFF:
In X1 Mode, for CKRL<>0xF F then:
Xtal2
Xtal1
Osc
CLK
Idle
CPU Clock
CKRL
Reload
8-bit
Prescaler-Divider
Reset
Peripheral Clock
:2
X2
0
1
FOSC
CKCON0
CLK
Periph
CPU
CKRL = 0xFF?
0
1
F
CPU F=CLKPERIPH
F
OSC
2 255 CKRL
–
()×
--------------------------------------------
---
=
F
CPU F=CLKPERIPH
F
OSC
4 255 CKRL
–
()×
--------------------------------------------
---
=
17
AT89C51RD2/ED2
4235H–8051–10/06
Enhanced Features In comparison to the original 80C52, the AT89C51RD2 /ED2 implement s some new f ea-
tures, which are:
• X2 option
• Dual Data Pointer
• Extended RAM
• Programmable Counter Array (PCA)
• Hardware Watchdog
• SPI inter face
• 4-level inter r upt priority system
• Power-of f flag
• ONCE mode
• ALE disablin g
• Some enhanc ed features are also located in the U ART and the Timer 2
X2 Feature The AT89C51RD2/ED2 core needs only 6 clock periods per machine cycle. Thi s feature
called ‘X2’ provides the following advantages :
• Divide frequency crystals by 2 (cheaper crystals) while keeping same CPU power.
• Save power consumption while keeping same CPU power (oscillator power saving).
• Save power consum ption by dividing dynam ical ly the operating frequency by 2 in
operating and idle modes.
• Increase CPU power by 2 while keeping same crystal frequency.
In order to keep the original C51 com patibility, a divider by 2 is inserted between the
XT AL1 signal and the m ain clo ck input of t he core (phase gene rator). This divi der may
be disabled by software.
Description The clo ck for the who le circuit and perip herals is first divided by t wo before be ing used
by t he CPU core and the peripherals.
This allows any cyclic ratio to be acc epted on XTAL1 input. In X2 mode, as this divider is
bypas sed, the signals on XTAL1 must have a cyclic ratio bet ween 40 to 60%.
Figure 5 shows t he clock generation block diagram. X2 bit is validated on the rising edge
of the XTAL1 ÷ 2 to avoid glitch es when switching from X2 to STD mode. Figure 6
shows the switching mode waveforms.
Fi gure 5 . Clock Generation Diagram
XTAL1 2
CKCON0
X2
8-bit Prescaler
FOSC
FXTAL 0
1
XTAL1:2 FCLK CPU
FCLK PERIPH
CKRL
18
AT89C51RD2/ED2
4235H–8051–10/06
Figu re 6. Mode Switching Waveforms
The X2 bit in the CKCON0 register (see Table 16) allows a switch from 12 clock periods
per instruc tion to 6 clock periods and v ice vers a. A t res et, t he speed is s et ac cording t o
X2 bit of Hardware Security B yte (HSB). By default, Standard mode is act ive. Setting the
X2 bit activates the X2 feature (X2 mode).
The T0X2, T1X2, T2X2 , UartX2, PcaX2, and WdX2 bits in th e CKCON0 register (Tabl e
16) and SPIX2 bit in the CKCON1 registe r (see Table 17) allows a switch from stan dard
peripheral speed (12 clock peri ods per peripheral clock cycl e) t o fast peripheral speed (6
clock periods per periphe ral clock cycle). These bits are active only i n X2 mode.
XTAL1:2
XTAL1
CPU Clock
X2 Bit
X2 ModeSTD Mode STD Mode
FOSC
19
AT89C51RD2/ED2
4235H–8051–10/06
Table 16. CKC ON0 Register
CKCON0 - Clock Contro l Register (8Fh)
Rese t Value = 0000 000’HSB. X2’b (See “Hardware Security Byte”)
Not bit addressable
76543210
- WDX2 PCAX2 SIX2 T2X2 T1X2 T0X2 X2
Bit
Number Bit
Mnemonic Description
7Reserved The values for this bit are indeterminite. Do not set this bit.
6WDX2
Watchdog Cloc k
(T h is con t rol bi t is vali da te d when the C PU clock X 2 i s s et; whe n X 2 is lo w, th is bit
has no effect).
Cleared to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock per iods per peri pheral clock cycle.
5PCAX2
Programmable Counter Array Clock
(T h is con t rol bi t is vali da te d when the C PU clock X 2 i s s et; whe n X 2 is lo w, th is bit
has no effect).
Cleared to select 6 clock periods per peripheral clock cycle. Set to select 12 clock
period s per pe ripheral clo c k cycle.
4SIX2
Enhanced UART Clock (Mode 0 and 2)
(T h is con t rol bi t is vali da te d when the C PU clock X 2 i s s et; whe n X 2 is lo w, th is bit
has no effect).
Cleared to select 6 clock periods per peripheral clock cycle. Set to select 12 clock
period s per pe ripheral clo c k cycle.
3T2X2
Timer2 Clock
(T h is con t rol bi t is vali da te d when the C PU clock X 2 i s s et; whe n X 2 is lo w, th is bit
has no effect).
Cleared to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock per iods per peri pheral clock cycle.
2T1X2
Timer1 Clock
(T h is con t rol bi t is vali da te d when the C PU clock X 2 i s s et; whe n X 2 is lo w, th is bit
has no effect).
Cleared to select 6 clock periods per peripheral clock cycle. Set to select 12 clock
period s per pe ripheral clo c k cycle.
1T0X2
Timer0 Clock
(T h is con t rol bi t is vali da te d when the C PU clock X 2 i s s et; whe n X 2 is lo w, th is bit
has no effect).
Cleared to select 6 clock periods per peripheral clock cycle. Set to select 12 clock
period s per pe ripheral clo c k cycle.
0X2
CPU Clock
Cleared to select 12 clock periods per machine cycle (STD mode) for CPU and
all the peripherals. Set to select 6 clock periods per machine cycle (X2 mode)
and to enable the individu al peri pherals’X2’ bit s. Programmed by ha rdware after
Power-up regarding Hardwa re Security By te (HSB), De fault setting, X2 is
cleared.