Rev. 4235H–8051–10/06
1
Features
•80C52 Compatibl e
– 8051 Instruction Compatibl e
– Six 8-bit I/O Ports (64 Pins or 68 Pins Versions)
– Four 8-bit I/O P o rts (44 Pins Version )
– Three 16-bit Timer/ Counters
– 256 Bytes Scratch Pad RAM
– 9 Interrup t Sources wi th 4 Priority Levels
•Integrated Power Monitor (POR/PFD) to Super vise Internal Power Suppl y
•ISP (In-System Programming) Using Standard VCC Power Supply
•2048 Bytes Bo ot ROM Contains Low Level Flash Programming Routines a nd a Defaul t
Serial Loader
•High-speed Architecture
– In Standard Mode:
40 MHz (Vcc 2.7V to 5.5V, both Internal and external code execution)
60 MHz (Vcc 4.5V to 5.5V an d Inte rnal Code execution only)
– In X2 mode (6 Clocks/machine cycle)
20 MHz (Vcc 2.7V to 5.5V, both Internal and external code execution)
30 MHz (Vcc 4.5V to 5.5V an d Inte rnal Code execution only)
•64K Bytes On-chip Flash Program/Data Memory
– Byte and Page (128 By tes) Erase and W rite
– 100k Write Cyc les
•On-chip 1792 bytes Expanded RAM (XRAM)
– Software Selectable Size (0 , 256, 512, 768 , 1024, 1792 Bytes)
– 768 Bytes Sel ected at Reset for T89C51RD2 Compatibility
•On-chip 2048 Bytes EEPROM Block for Data Storage (AT89C51ED2 Only)
– 100K Write Cycles
•Dual Dat a Poi nter
•Variable Lengt h MOVX for Slow RAM/Per ipherals
•Improved X2 Mode with Independent Selection for CPU and Each Periphe ral
•Keyboard Interrupt Int erface on Port 1
•SPI Int erface (Master/Sl ave Mode)
•8-bit Clock Prescaler
•16-bit Programmable Counter Array
– High Speed Out put
–Compare/Capture
– Pulse W idth Modulator
– Watchdog Timer Capabilities
•Asynchronous Port Reset
•Full -duplex Enhanced UART with Dedi cated Internal Baud Rate Generator
•Low EMI (Inhibit ALE)
•Hardware Watchdog Timer (One-time Enabl ed wit h Reset- Out), Power-off Flag
•Power Contr ol Modes: Idle Mode, Power-down Mode
•Single Range Power Supply: 2.7V t o 5.5V
•Industrial Temper ature Range (-40 to +85°C)
•Packages: PLCC44, VQFP44, PLCC68, VQFP64, PDIL40
Description
AT89C51RD2/ED2 is high performance CMOS Flash version of th e 80C51 CMOS sin-
gle chip 8-bit microcont roller. It contains a 64-Kbyte Flash m em ory block for c ode and
for data.
The 64-Kby tes F lash memory can be programm ed either in parallel mod e or in serial
mode with t he ISP ca pability o r with softwa re. The prog rammi ng voltage is intern ally
generated from the standard VCC pin.
8-bit Flash
Microcontroller
AT89C51RD2
AT89C51ED2
2
AT89C51RD2/ED2
4235H–8051–10/06
The A T89C51RD2/E D2 retains all of the features of the A tmel 80C5 2 with 256 bytes of
intern al RAM, a 9-sour ce 4-level interrupt con troller and three timer/counters. The
AT 89C51ED2 prov ides 2048 byt es of EEPRO M fo r nonvolatile data storage.
In addition, the AT89C51RD2/E D2 has a Programmable Counter A rray, an X RAM of
1792 bytes, a Hardware Watchdog T imer, SPI interface, Keyboard, a more versat ile
serial chan nel that facilitates multiprocessor communication (EUART) and a speed
improvem ent mechanism (X2 Mode ).
The fully static design of the AT89C51RD2/ED2 allows to reduce sys tem power con-
sumpt ion by bring ing the clock fr equency d own t o any value , including DC, without loss
of data.
The A T89C5 1RD2/ED2 has 2 software-s electabl e mode s of reduced a ctivity and an 8-
bit clock prescaler for further reduction in power consumption. In the Idle mode the CPU
is frozen while the pe ripherals and the interrupt system are still operating. In the Power-
down mode the RAM is saved and all other func tions are inoperative.
The added features of the AT89C51RD2/ED2 make it more powerful for applic at ions
that need pulse width modulation, high sp eed I/O and counting capabilities such as
alarms, motor cont rol , corded phones, and smart card readers.
Table 1. M em ory Size and I/O Pins
Package Flash (Bytes) XRAM (Bytes) Total RA M (Bytes ) I/O
PLCC44/VQFP44/DIL40 64K 1792 2048 34
PLCC68/VQFP64 64K 1792 2048 50
3
AT89C51RD2/ED2
4235H–8051–10/06
Block Diagram
Figu re 1. Block Diagram
Timer 0 INT
RAM
256x8
T0
T1 RxD
TxD
WR
RD
EA
PSEN
ALE/
XTALA2
XTALA1 EUART
CPU
Timer 1
INT1
Ctrl
INT0
(2)
(2)
C51
CORE
(2) (2) (2) (2)
Port 0
P0
Port 1
Por t 2
Port 3
P1
P2
P3
XRAM
1792 x 8
IB-bus
PCA
RESET
PROG
Watch
-dog
PCA
ECI
VSS
VCC
(2)(2) (1)
(1): Alternate function of Port 1
(2): Alternate function of Port 3
(1)
Timer2
T2EX
T2
(1) (1)
Flash
64K x 8
Keyboard
(1)
Keyboard
MISO
MOSI
SCK
SS
Port4
P4
(1) (1)(1)(1)
BOOT
2K x 8
ROM
Regulator
POR / PFD
Port 5
P5
Parallel I/O Ports &
External Bus SPI
EEPROM*
2K x 8
(AT89C51ED2)
4
AT89C51RD2/ED2
4235H–8051–10/06
SFR Mapping The Specia l Function Registers (SFRs) o f the AT89C 51RD 2/ED2 fall into t he follo wing
categories:
• C 51 core registers: ACC, B , DPH, DPL, PSW, SP
• I/O port r e g isters: P0, P1, P2, P3 , PI2
• T i m er registers: T 2CON, T2MOD, TCON, TH0, TH1, TH2, TMOD, TL0, TL1, TL2,
RCAP2L, RCAP2H
• Serial I/O port registers: SADDR, SADEN, SBUF, SCON
• PCA (Programmable Counter Array) registers : CCON, CCAPMx , CL, CH, CCAPxH,
CCAPxL (x: 0 t o 4)
• Power and clock control registers: PCON
• Hardware Watchdog T i mer registers: WDTRST, WDTPRG
• Interrupt system registers: IE0, IPL0, IPH0, IE1, IPL1, IPH1
• Keyboard Interface registers: KBE, KBF, KBLS
• SPI regi sters: SPCON , SPST R , SPDAT
• BRG (Baud Rate Generator) registers: BRL, BDRCON
• Clock Prescaler register: CKRL
• Others: AUXR, AUXR1, CKCON0, CKCON1
5
AT89C51RD2/ED2
4235H–8051–10/06
Tab le 2. C51 Core SFRs
MnemonicAddName 76543210
ACC E0h Accumulator
B F0h B Register
PSW D0h Program Status Word CY AC F0 RS1 RS0 OV F1 P
SP 81h Stack Pointer
DPL 82h Data Pointer Low By te
DPH 83h Data Pointer High Byte
Tab le 3. System Management SFRs
MnemonicAddName 76543210
P CON 87h Po wer C on trol SM OD 1 SM OD 0 - P O F GF 1 GF 0 PD IDL
AUXR 8Eh Auxiliary Regis ter 0 DPU - M0 XRS2 XRS1 XRS0 EXTRAM AO
AUXR1 A2h Auxiliary Register 1 - - ENBOOT -GF30 -DPS
CKRL97hClock Reload Register --------
CK CKO N0 8F h Clo c k Contro l Register 0 - W DTX 2 PCA X2 SIX2 T2X2 T1X2 T0X2 X2
CKCKON1AFhClock Control Register 1 -------SPIX2
Tab le 4. Interrupt SFRs
MnemonicAddName 76543210
IEN0 A8h Interrupt Enable Control 0 EA EC ET2 ES ET1 EX1 ET0 EX0
IEN1 B1hInterrupt Enable Control 1 -----ESPI KBD
IPH0 B7h Interrupt Priority Control High 0 - PPCH PT2H PHS PT1H PX1H PT0H PX0H
IPL0 B8h Interru pt Priority Control Low 0 - PPCL PT2L PLS PT1L PX1L PT0L PX0L
IPH1 B3hInterrupt Priority Control High 1-----SPIH KBDH
IPL1 B2hInterrupt Priority Control Low 1-----SPIL KBDL
Tab le 5. Port SFRs
MnemonicAddName 76543210
P0 80h 8-bit Port 0
P1 90h 8-bit Port 1
P2 A0h 8-bit Port 2
P3 B0h 8-bit Port 3
P4 C0h 8-b it Port 4
6
AT89C51RD2/ED2
4235H–8051–10/06
P5 D8h 8-b it Port 5
P5 C7h 8-bit Port 5 (byte addressable)
Tab le 5. Port SFRs
MnemonicAddName 76543210
Tab le 6. Ti mer S FR s
MnemonicAddName 76543210
T CO N 88h Time r /C o un ter 0 and 1 Control TF 1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
T MOD 89h Time r/C o un ter 0 and 1 Mo de s G AT E 1 C/ T 1 # M11 M 0 1 GATE0 C/ T0 # M 1 0 M0 0
TL0 8Ah Timer/Counter 0 Low Byte
TH0 8Ch Ti mer/Counte r 0 Hig h Byte
TL1 8Bh Timer/Counter 1 Low Byte
TH1 8Dh Timer/Co unter 1 High Byt e
WD TRST A6 h Watc hDog Timer Reset
WDTPRGA7hWatchDog Timer Program -----WTO2WTO1WTO0
T2CON C8h Tim er/Counter 2 control TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2# CP/RL2#
T2MODC9hTimer/Counter 2 Mode ------T2OEDCEN
RCAP2H CBh T im er/C ounter 2 Re load /Cap ture
High Byte
RCAP2L CAh T imer /Cou nter 2 Re load/C aptur e
Low Byte
TH2 CDh Ti mer/Counte r 2 High Byte
TL2 CCh Timer/Counter 2 Low Byte
Tab le 7. PCA SFRs
Mnemo
-nicAddName 76543210
CCON D8h PCA Ti mer/Counter Control CF CR CCF4 CCF3 CCF2 CCF1 CCF0
CMOD D9h PCA T imer/Counter Mode CIDL WDTE CPS1 CPS0 ECF
CL E9h PCA Timer/Counter Low Byte
CH F9h PCA Timer/Counter High Byte
CCAPM0
CCAPM1
CCAPM2
CCAPM3
CCAPM4
DAh
DBh
DCh
DDh
DEh
PCA Timer/Counter Mode 0
PCA Timer/Counter Mode 1
PCA Timer/Counter Mode 2
PCA Timer/Counter Mode 3
PCA Timer/Counter Mode 4
ECOM0
ECOM1
ECOM2
ECOM3
ECOM4
CAPP0
CAPP1
CAPP2
CAPP3
CAPP4
CAPN0
CAPN1
CAPN2
CAPN3
CAPN4
MAT0
MAT1
MAT2
MAT3
MAT4
TOG0
TOG1
TOG2
TOG3
TOG4
PWM0
PWM1
PWM2
PWM3
PWM4
ECCF0
ECCF1
ECCF2
ECCF3
ECCF4
7
AT89C51RD2/ED2
4235H–8051–10/06
CCAP0H
CCAP1H
CCAP2H
CCAP3H
CCAP4H
FAh
FBh
FCh
FDh
FEh
PC A Compare Captu re Module 0 H
PC A Compare Captu re Module 1 H
PC A Compare Captu re Module 2 H
PC A Compare Captu re Module 3 H
PC A Compare Captu re Module 4 H
CCAP0H7
CCAP1H7
CCAP2H7
CCAP3H7
CCAP4H7
CCAP0H6
CCAP1H6
CCAP2H6
CCAP3H6
CCAP4H6
CCAP0H5
CCAP1H5
CCAP2H5
CCAP3H5
CCAP4H5
CCAP0H4
CCAP1H4
CCAP2H4
CCAP3H4
CCAP4H4
CCAP0H3
CCAP1H3
CCAP2H3
CCAP3H3
CCAP4H3
CCAP0H2
CCAP1H2
CCAP2H2
CCAP3H2
CCAP4H2
CCAP0H1
CCAP1H1
CCAP2H1
CCAP3H1
CCAP4H1
CCAP0H0
CCAP1H0
CCAP2H0
CCAP3H0
CCAP4H0
CCAP0L
CCAP1L
CCAP2L
CCAP3L
CCAP4L
EAh
EBh
ECh
EDh
EEh
PCA Compare Capture Module 0 L
PCA Compare Capture Module 1 L
PCA Compare Capture Module 2 L
PCA Compare Capture Module 3 L
PCA Compare Capture Module 4 L
CCAP0L7
CCAP1L7
CCAP2L7
CCAP3L7
CCAP4L7
CCAP0L6
CCAP1L6
CCAP2L6
CCAP3L6
CCAP4L6
CCAP0L5
CCAP1L5
CCAP2L5
CCAP3L5
CCAP4L5
CCAP0L4
CCAP1L4
CCAP2L4
CCAP3L4
CCAP4L4
CCAP0L3
CCAP1L3
CCAP2L3
CCAP3L3
CCAP4L3
CCAP0L2
CCAP1L2
CCAP2L2
CCAP3L2
CCAP4L2
CCAP0L1
CCAP1L1
CCAP2L1
CCAP3L1
CCAP4L1
CCAP0L0
CCAP1L0
CCAP2L0
CCAP3L0
CCAP4L0
Tab le 8. Serial I/O Port SFRs
MnemonicAddName 76543210
SCO N 98h Serial Control FE/SM0 SM1 SM2 REN TB8 RB8 TI RI
SBUF 99h Serial Data Buffer
SADEN B9h Sl ave Address Mask
SAD DR A9h Sl ave Addre ss
BDRCON 9Bh Baud Rate Control BRR TBCK RBCK SPD SRC
BRL 9Ah Baud Rate Reload
Tab le 7. PCA SFRs (Continued)
Mnemo
-nicAddName 76543210
Tab le 9. SPI Controller SFRs
MnemonicAddName 76543210
SPCON C3h SPI Control SPR2 SPEN SSDIS MSTR CPOL CPHA SPR1 SPR0
SPST A C4h SPI Status SPIF WCOL SSERR MODF
SPDAT C5h SPI Data SPD7 SPD6 SPD5 SPD4 SPD3 SPD2 SPD1 SPD0
Tab le 10. Keyboard I nterface SFRs
MnemonicAddName 76543210
KBLS 9Ch Keybo ard Level Selector KBLS7 KBLS6 KBLS5 KBLS4 KBLS3 KBLS2 KBLS1 KBLS0
KBE 9Dh Keyboard Input Enable KBE7 KBE6 KBE5 KBE4 KBE3 KBE2 KBE1 KBE0
KBF 9Eh Keyboard Flag Register KBF7 KBF6 KBF5 KBF4 KBF3 KBF2 KBF1 KBF0
Table 11. EEPROM data Memory SFR (A T8 9C51ED2 only)
MnemonicAddName 76543210
EECON D2h EEPROM Data Control EEE EEBUSY
8
AT89C51RD2/ED2
4235H–8051–10/06
Table 12 shows all SFRs with their address and their reset value.
Tab le 12. SFR Mappin g
Bit
Add ressa ble Non B it Addressable
0/8 1/9 2/A 3/B 4/C 5/D 6/E 7/F
F8h CH
0000 0000 CCAP0H
XXXX XXXX CCAP1H
XXXX XXXX CCAP2H
XXXX XXXX CCAP3H
XXXX XXXX CCAP4H
XXXX XXXX FFh
F0h B
0000 0000 F7h
E8h P5 bit
addressable
1111 1111
CL
0000 0000 CCAP0L
XXXX XXXX CCAP1L
XXXX XXXX CCAP2L
XXXX XXXX CCAP3L
XXXX XXXX CCAP4L
XXXX XXXX EFh
E0h ACC
0000 0000 E7h
D8h CCON
00X0 0000 CMOD
00XX X000 CCAPM0
X000 0000 CCAPM1
X000 0000 CCAPM2
X00 0 00 00 CCAPM3
X000 0000 CCAPM4
X000 0000 DFh
D0h PSW
0000 0000 FCON
XXXX 0000 EECON
xxxx xx00 D7h
C8h T2CON
0000 0000 T2MOD
XXXX XX00 RCAP2L
0000 0000 RCAP2H
0000 0000 TL2
0000 0000 TH2
0000 0000 CFh
C0h P4
1111 1111 SPCON
0001 0100 SPSTA
0000 0000 SPDAT
XXXX XXXX
P5 byte
Addressable
1111 1111 C7h
B8h IPL0
X000 000 SADEN
0000 0000 BFh
B0h P3
1111 1111 IEN1
XXXX X000 IPL1
XXXX X000 IPH1
XXXX X111 IPH0
X000 0000 B7h
A8h IEN0
0000 0000 SADDR
0000 0000 CKCON1
XXXX XXX0 AFh
A0h P2
1111 1111 AUXR1
0XXX X0X0 WDTRST
XXXX XXXX WDTPRG
XXXX X000 A7h
98h SCON
0000 0000 SBUF
XXXX XXXX BRL
0000 0000 BDRCON
XXX0 0000 KBLS
0000 0000 KBE
0000 0000 KBF
0000 0000 9Fh
90h P1
1111 1111 CKRL
1111 1111 97h
88h TCON
0000 0000 TMOD
0000 0000 TL0
0000 0000 TL1
0000 0000 TH0
0000 0000 TH1
0000 0000 AUXR
XX00 1000 CKCON0
0000 0000 8Fh
80h P0
1111 1111 SP
0000 0111 DPL
0000 0000 DPH
0000 0000 PCON
00X1 0000 87h
0/8 1/9 2/A 3/B 4/C 5/D 6/E 7/F
reserved
9
AT89C51RD2/ED2
4235H–8051–10/06
Pin Config urations
Figu re 2. Pin Confi gurations
43 42 41 40 3944 38 37 36 35 34
P1.4/CEX1
P1.0/T2
P1.1/T2EX/SS
P1.3/CEX0
P1.2/ECI
VCC
P0.0/AD0
P0.2/AD2
P0.3/AD3
P0.1/AD1
P0.4/AD4
P0.6/AD6
P0.5/AD5
P0.7/AD7
ALE/PROG
PSEN
EA
P2.7/A15
P2.5/A13
P2.6/A14
P1.5/CEX2/MISO
P1.6/CEX3/SCK
P1.7/CEX4/MOSI
RST
P3.0/RxD
P3.1/TxD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
P3.6/WR
P3.7/RD
XTAL2
XTAL1
VSS
P2.0/A8
P2.1/A9
P2.2/A10
P2.3/A11
P2.4/A12
NIC*
1213 17161514 201918 2122
33
32
31
30
29
28
27
26
25
24
23
AT89C51RD2/ED2
1
2
3
4
5
6
7
8
9
10
11
VQFP44 1.4
NIC*
NIC*
NIC*
PLCC44
AT89C51RD2/ED2
NIC*
NIC*
NIC*
PDIL40
P1.7CEX4/MOSI
P1.4/CEX1
RST
P3.0/RxD
P3.1/TxD
P1.3CEX0
1
P1.5/CEX2/MISO
P1.6/CEX3/SCK
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
P3.6/WR
P3.7/RD
XTAL2
XTAL1
VSS P2.0/A8
P2.1/A9
P2.2/A10
P2.3/A11
P2.4/A12
P0.4/AD4
P0.6/AD6
P0.5/AD5
P0.7/AD7
ALE/PROG
PSEN
EA
P2.7/A15
P2.5/A13
P2.6/A14
P1.0/T2
P1.2/ECI
P1.1/T2EX/SS VCC
P0.0/AD0
P0.1/AD1
P0.2/AD2
P0.3/AD3
AT89C51ED2
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
18 19 23222120 262524 2728
5 4 3 2 1 6 44 43 42 41 40
P1.4/CEX1
P1.0/T2
P1.1/T2EX/SS
P1.3/CEX0
P1.2/ECI
VCC
P0.0/AD0
P0.2/AD2
P0.1/AD1
P0.4/AD4
P0.6/AD6
P0.5/AD5
P0.7/AD7
ALE/PROG
PSEN
EA
P2.7/A15
P2.5/A13
P2.6/A14
P3.6/WR
P3.7/RD
XTAL2
XTAL1
VSS
P2.0/A8
P2.1/A9
P2.2/A10
P2.3/A11
P2.4/A12
P1.5/CEX2/MISO
P1.6/CEX3/SCK
P1.7/CEx4/MOSI
RST
P3.0/RxD
P3.1/TxD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
P0.3/AD3
NIC*
7
8
9
10
11
12
13
14
15
16
17
39
38
37
36
35
34
33
32
31
30
29
10
AT89C51RD2/ED2
4235H–8051–10/06
50
49
48
47
44
45
46
P4.5
P3.7/RD
XTAL2
XTAL1
P4.4
P3.6/WR
P4.3
NIC
NIC
P3.1/TxD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
37
38
39
40
41
42
43
AT89C51ED2
PLCC68
P0.4/AD4
P5.4
P5.3
P0.5/AD5
P0.6/AD6
NIC
P0.7/AD7
EA
NIC
ALE
P1.6/CEX3/SCK
P1.7/CEX4/MOSI
RST
NIC
NIC
NIC
P3.0/RxD
NIC
NIC
P1.5/CEX2/MISO
60
59
58
57
56
55
54
53
51
52
10
11
12
13
14
15
16
17
19
18
27
28
29
30
31
32
33
34
35
36
9
8
7
6
5
3
2
1
68
P5.0
P2.4/A12
P2.3/A11
P4.7
P2.2/A10
P4.6
P2.0/A8
P2.1/A9
NIC
VSS
P5.5
P0.3/AD3
P0.2/AD2
P5.6
P0.1/AD1
P0.0/AD0
P5.7
VCC
NIC
P1.0/T2
4
PSEN
NIC
P2.7/A15
P2.6/A14
P5.2
P5.1
P2.5/A13
67
65
64
63
62
61
66
20
21
22
23
26
25
24
P4.0
P1.1/T2EX/SS
P1.2/ECI
P1.3/CEX0
P4.1
P1.4/CEX1
P4.2
NIC: Not Internaly Co n nected
54
53
52
51
50
49
AT89C51ED2
VQFP64
P0.4/AD4
P5.4
P5.3
P0.5/AD5
P0.6/AD6
P0.7/AD7
EA
NIC
ALE
PSEN#
P1.5/CEX2/MISO
P1.6/CEX3/SCK
P1.7/A17/CEX4/MOSI
RST
NIC
NIC
NIC
P3.0/RxD
NIC
P4.2
48
47
46
45
44
43
42
41
39
40
1
2
3
4
5
6
7
8
10
9
17
18
19
20
21
22
23
24
25
26
64
63
62
61
60
59
58
57
56
55
P2.4/A12
P2.3/A11
P4.7
P2.2/A10
P2.1/A9
NIC
P4.6
P2.0/A8
VSS
P4.5
P5.5
P0.3/AD3
P0.2/AD2
P5.6
P0.1/AD1
P0.0/AD0
P5.7
VCC
NIC
P1.0/T2 11
12
13
16
15
14
P4.0
P1.1/T2EX/SS
P1.2/ECI
P1.3/CEX0
P4.1
P1.4/CEX1
38
37
36
33
34
35 P3.7/RD
XTAL2
XTAL1
P4.4
P3.6/WR
P4.3
NIC
P3.1/TxD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
27
28
29
30
31
32
P2.7/A15
P2.6/A14
P5.2
P5.1
P2.5/A13
P5.0
11
AT89C51RD2/ED2
4235H–8051–10/06
Tab le 13. Pin Description
Mnemonic
Pin Number Type Name and FunctionPLCC44 VQFP44 PLCC68 VQFP64 PDIL40
VSS 22 16 51 40 20 I Ground: 0V reference
VCC 44 38 17 8 40 I P ow er Supp ly : This is the power supply voltage for n ormal, id le and
power-down operation
P0.0 - P0.7 43 - 36 37 - 30 15, 14,
12, 11,
9,6, 5, 3
6, 5, 3,
2, 64,
61,60,59 I/O
Po rt 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that
have 1s written to them float and can be used as high impedance inputs.
Port 0 must be polarized to VCC or VSS in order to prevent any parasitic
curr ent consumption. Port 0 is also the multiplex ed low-order address
and da t a bus d ur ing acc ess to exte rn al pr o gra m and dat a me mo ry. In th i s
application, it uses stro ng internal pull-up when emit ting 1s. Port 0 also
inpu t s t he co de byt e s dur in g EP ROM pr o gra mmi ng. E xt er na l pul l- up s ar e
required during program verification during which P0 outputs the code
bytes.
32-39
P1.0 - P1.7 2 - 9 40 - 44
1 - 3
19, 21,
22, 23,
25, 27,
28, 29
10, 12 ,
13, 14 ,
16, 18 ,
19, 20
1-8 I/O Po r t 1 : Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1
pins that have 1s written to the m are pulled high by the int ernal pull-ups
and can be used as inputs . As inputs, Port 1 pins that are externall y
pulled low will source current because of the internal pull-ups. Port 1 also
receives the low-order address byte during memory programming and
verification.
Alternate functions for AT89C51RD2/ED2 Port 1 include:
24019 10 1I/OP1.0: Input/Output
I/O T2 (P1.0): Timer/Counter 2 external co unt inp ut/Clockout
34121 12 2I/OP1.1: Input/Output
IT2EX: Timer/Counter 2 Reload/Capture/Direction Control
ISS: SPI Slave Select
44222 13 3I/OP1.2: Input/Output
IECI: External Clock for the PCA
54323 14 4I/OP1.3: Input/Output
I/O CEX0: Capture/Compare External I/O for PCA module 0
64425 16 5I/OP1.4: Input/Output
I/O CEX1: Capture/Compare External I/O for PCA module 1
7 1 27 18 6 I/O P1.5: Input/Output
I/O CEX2: Capture/Compare External I/O for PCA module 2
I/O MISO: SPI Master Input Slave Output line
When SPI is in master mode, MISO receives data from the s lave per iph-
eral. When SPI is in slave mode, MISO outputs data to the master con-
troller.
8 2 28 19 7 I/O P1.6: Input/Output
I/O CEX3: Capture/Compare External I/O for PCA module 3
I/O SCK: SPI Serial Clock
12
AT89C51RD2/ED2
4235H–8051–10/06
9 3 29 20 8 I/O P1.7: Input/Output:
I/O CEX4: Capture/Compare External I/O for PCA module 4
I/O MOSI: SPI Master Output Slave Input line
When SPI is in master mode, MOSI outputs data t o the slave peripheral.
When SPI is in slave mo de, MOSI receives data from the mast er cont rol-
ler.
XTALA1 21 15 49 38 19 I XTALA 1: Input to the inverting oscillato r amplifier and input to the inter-
nal clock generator circuits.
XTALA2 20 14 48 37 18 O XTALA 2: Output from the inverting oscillator amplifier
P2.0 - P2.7 24 - 31 18 - 25
54, 55,
56, 58,
59, 61,
64, 65
43, 44 ,
45, 47 ,
48, 50 ,
53, 54
I/O
Po rt 2 : P ort 2 i s an 8 - bi t bid ir ect i ona l I/O po r t wit h int er nal pu ll -up s . P or t 2
pins that have 1s written to the m are pulled high by the int ernal pull-ups
and can be used as inputs . As inputs, Port 2 pins that are externally
pulled low w ill source current because of the int ernal pull-ups. Port 2
emits the high-order address byte during fet ches fr om external program
memory and during acce sses to external data memory that use 16-bit
addresses (MOVX @DP TR ).In this application, it uses strong internal
pull-ups emitting 1s. During accesses to external data memory that use
8-bit addresses (MOVX @Ri), port 2 emits the contents of the P2 SF R.
21-28
P3.0 - P3.7 11,
13 - 19 5,
7 - 13
34, 39,
40, 41,
42, 43,
45, 47
25, 28 ,
29, 30 ,
31, 32 ,
34, 36
10-17 I/O Po rt 3 : Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3
pins that have 1s written to the m are pulled high by the int ernal pull-ups
and can be used as inputs . As inputs, Port 3 pins that are externall y
pulled low will source current because of the internal pull-ups. Port 3 also
serves the special features of the 80C51 family, as listed below .
115342510IRXD (P3.0): Serial input port
137392811OTXD (P3.1): Serial ou tp ut po r t
148402912IINT0 (P3.2): External interrupt 0
159413013IINT1 (P3.3): External interrupt 1
16 10 42 31 14 I T0 (P3.4): Timer 0 exter nal input
17 11 43 32 15 I T1 (P3.5): Timer 1 external input
18 12 45 34 16 O WR (P3.6): Extern al data memory write strobe
19 13 47 36 17 O RD (P3. 7) : External data memory read strobe
P4.0 - P4.7 --
20, 24,
26, 44,
46, 50,
53, 57
11, 15,
17,33,
35,39,
42, 46
-I/O
Po rt 4 : Port 4 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3
pins that have 1s written to the m are pulled high by the int ernal pull-ups
and can be used as inputs . As inputs, Port 3 pins that are externall y
pulled low w ill source current because of the int ernal pull-ups.
P5.0 - P5.7 --
60, 62,
63, 7, 8,
10, 13,
16
49, 51 ,
52, 62 ,
63, 1, 4,
7
-I/O
Po rt 5 : Port 5 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3
pins that have 1s written to the m are pulled high by the int ernal pull-ups
and can be used as inputs . As inputs, Port 3 pins that are externall y
pulled low w ill source current because of the int ernal pull-ups.
RST 10 4 30 21 9 I
Reset: A high on this pin for two machine cycles while the oscillator is
running, resets the device. An internal diffused resistor to VSS permi ts a
power-on reset using only an ext ernal capacito r to VCC. This pin is an out-
put w hen the hardware watchdog force s a system r eset.
Tab le 13. Pin Description (Continued)
Mnemonic
Pin Number Type Name and FunctionPLCC44 VQFP44 PLCC68 VQFP64 PDIL40
13
AT89C51RD2/ED2
4235H–8051–10/06
ALE/PRO
G33 27 68 56 30 O (I) Add ress Latch Enable/Program Pu lse: Output pulse for latching th e
low by te of the addr ess during an access to external memory. In normal
operation, ALE is emitted at a constant rate of 1/6 (1/3 in X2 mode) the
os cill at or f r eque nc y, and ca n b e u sed for e xter n al timi ng or c lo ck in g. Not e
that one ALE puls e is skipped during each access to external data mem-
ory. This pin is also the program pulse i nput (PROG) during Flash pro-
gramming . ALE can be disabled by se tting SFR’s AUXR.0 bit. With this
bit set, ALE will be inactive during internal fetches.
PSEN 32 26 67 55 29 O Program Strobe ENable: The read strobe to external progra m memory.
When executing code from the external program mem ory, PSEN is acti-
vated twic e each machine cycle, except that two PSEN activ a tio ns ar e
skipped during each acce ss to external data memory. PS EN is not acti-
vated during fetches from internal program memory.
EA 35 29 2 58 31 I External Access Enable: EA must be externally held low to enable the
device to fetch code from external program memory locations 0000H to
FFFFH. If security level 1 is programmed, EA will be internally latched on
Reset.
Tab le 13. Pin Description (Continued)
Mnemonic
Pin Number Type Name and FunctionPLCC44 VQFP44 PLCC68 VQFP64 PDIL40
14
AT89C51RD2/ED2
4235H–8051–10/06
Port Types AT 89C51RD2 /ED2 I/O ports (P1, P2, P3, P4, P5) implement the quasi-bidirectional out-
put th at is comm on on the 80C5 1 an d mo st o f its de rivati ve s. T his o utp ut ty pe c an b e
used as both an input an d outp ut without the need t o reconfigure the port. This is possi-
ble because whe n t he port outputs a logic h igh, it i s weakly driven, al lowing an external
device to pull the pin low. When the pin is pul led low, i t is dri ven strongly and able to sink
a fairly large current. These features are somew hat similar to an open drain output
except tha t there are three pull-up transistors in the quasi-bidirectional outpu t that serve
different purpo ses. One o f these pull-ups, c alled the "weak" pull-up, is turned on when-
ever the port latch for the pin contains a logic 1. The weak pull-up sources a very small
current that will pull the pin high if it is left f l oating. A second pull-up, called the "medium"
pull-up, is turned on when the port latch for t he pin contains a logic 1 and the pin itself is
also at a logic 1 level. This pu ll-up provides t he primary source current for a quasi-bidi-
rectional pin that is outputting a 1. If a pin that has a logic 1 on it is pulled low by an
externa l device, the m edium pull-u p turns o ff, and only the we ak pull-up rem ains on. In
order to pull the pin low under these cond iti ons, the external device has to sink enou gh
cu rr ent to o verpow er the me dium pull -up and take the v oltage on the po rt pin bel ow its
input threshold.
The third pull-up is referred to as the "strong" pull-up. This pull-up is used to speed up
low-to-high transit i ons on a quasi-bidirectional port pin when the port latch changes f rom
a logic 0 to a lo gic 1. When this oc cu rs, the strong pu ll- up turns on for a brief time, t wo
CPU clocks, in order to pull t he port pin high quickly. Then it turns off again.
The DP U bit (bit 7 in AUX R register) allows to disable the perman ent we ak pull up of all
ports when latc h data is logical 0.
The quasi-bid irectional port configuration is shown in Figure 3.
Figu re 3. Quasi-B idire ctional Out put
2 CPU
Input
Pin
Strong Medium
N
Weak
P
Clock Delay
Port Latch
Data
Data
DPU
AUXR.7
PP
15
AT89C51RD2/ED2
4235H–8051–10/06
Oscillator T o op timi ze th e powe r co nsu mpti on an d exec utio n tim e nee de d for a s peci fic task, a n
internal prescaler feature has been implemented between the oscillator and the CPU
and peripherals.
Registers Table 14. CK RL Register
CKRL – Clock Reload Register (97h)
Rese t Value = 1111 1111b
Not bit addressable
Table 15. PCO N Regist er
PCO N – Power Control Register (87h)
Rese t Value = 00X1 0000b Not bit addressable
76543210
CKRL7 CKRL6 CKRL5 CKRL4 CKRL3 CKRL2 CKRL1 CKRL0
Bit Number Mnemonic Description
7:0 CKRL Clo ck Reload Register
Prescaler valu e
76543210
SMOD1 SMOD0 - POF GF1 GF0 PD IDL
Bit Number Bit Mnemoni c Description
7SMOD1
Serial Port M ode bit 1
Set to select double baud rate in mode 1, 2 or 3.
6SMOD0
Serial Port M ode bit 0
Cl ea red to selec t SM0 bit in SCON re gi ster.
Set to select FE bit in SCON register.
5-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4POF
Power-off Flag
Cl ea red by so ft war e t o re cog niz e th e n ext r es et ty pe .
Set by ha rdw ar e when VCC ris es from 0 to it s nomina l vo lt a ge. Can
also be set by software.
3GF1
Gen era l-pu r pos e Fla g
Cleared by software for general-purpose usage.
Set b y sof twa r e fo r ge ner al -pu rp os e usa ge .
2GF0
Gen era l-pu r pos e Fla g
Cleared by software for general-purpose usage.
Set b y sof twa r e fo r ge ner al -pu rp os e usa ge .
1PD
Power-down Mo de bit
Cleared by hardware when res et occurs.
Set to enter power-down mode.
0IDL
Idle Mode bit
Cleared by h ardware when interrupt o r re set occurs.
Set to enter idle mode.
16
AT89C51RD2/ED2
4235H–8051–10/06
Functional Block Diagram
Figu re 4. Functional Oscillator Block Diagram
Prescaler Divid er • A hardware RESET puts the prescaler divider in the following state:
•CKRL = FFh: F
CLK CPU = F CLK PERIPH = FOSC/2 (Standard C51 feature)
• Any value between FFh down to 00h can be written by software into CKR L register
in order to divide frequency of the sele cted os c illator:
• CK R L = 00h: minimum frequ enc y
FCLK CPU = F CLK PERIPH = FOSC/1020 (Standard Mode )
FCLK CPU = F CLK PERIPH = FOSC/510 (X2 Mode)
• C KR L = FF h: maximu m frequenc y
FCLK CPU = FCLK PERIPH = FOSC/2 (Standard Mode)
FCLK CPU = FCLK PERIPH = FOSC (X2 Mode)
FCLK CPU and FCLK PERIPH
In X 2 Mode, for CKRL<>0xFF:
In X1 Mode, for CKRL<>0xF F then:
Xtal2
Xtal1
Osc
CLK
Idle
CPU Clock
CKRL
Reload
8-bit
Prescaler-Divider
Reset
Peripheral Clock
:2
X2
0
1
FOSC
CKCON0
CLK
Periph
CPU
CKRL = 0xFF?
0
1
F
CPU F=CLKPERIPH
F
OSC
2 255 CKRL
–
()×
--------------------------------------------
---
=
F
CPU F=CLKPERIPH
F
OSC
4 255 CKRL
–
()×
--------------------------------------------
---
=
17
AT89C51RD2/ED2
4235H–8051–10/06
Enhanced Features In comparison to the original 80C52, the AT89C51RD2 /ED2 implement s some new f ea-
tures, which are:
• X2 option
• Dual Data Pointer
• Extended RAM
• Programmable Counter Array (PCA)
• Hardware Watchdog
• SPI inter face
• 4-level inter r upt priority system
• Power-of f flag
• ONCE mode
• ALE disablin g
• Some enhanc ed features are also located in the U ART and the Timer 2
X2 Feature The AT89C51RD2/ED2 core needs only 6 clock periods per machine cycle. Thi s feature
called ‘X2’ provides the following advantages :
• Divide frequency crystals by 2 (cheaper crystals) while keeping same CPU power.
• Save power consumption while keeping same CPU power (oscillator power saving).
• Save power consum ption by dividing dynam ical ly the operating frequency by 2 in
operating and idle modes.
• Increase CPU power by 2 while keeping same crystal frequency.
In order to keep the original C51 com patibility, a divider by 2 is inserted between the
XT AL1 signal and the m ain clo ck input of t he core (phase gene rator). This divi der may
be disabled by software.
Description The clo ck for the who le circuit and perip herals is first divided by t wo before be ing used
by t he CPU core and the peripherals.
This allows any cyclic ratio to be acc epted on XTAL1 input. In X2 mode, as this divider is
bypas sed, the signals on XTAL1 must have a cyclic ratio bet ween 40 to 60%.
Figure 5 shows t he clock generation block diagram. X2 bit is validated on the rising edge
of the XTAL1 ÷ 2 to avoid glitch es when switching from X2 to STD mode. Figure 6
shows the switching mode waveforms.
Fi gure 5 . Clock Generation Diagram
XTAL1 2
CKCON0
X2
8-bit Prescaler
FOSC
FXTAL 0
1
XTAL1:2 FCLK CPU
FCLK PERIPH
CKRL
18
AT89C51RD2/ED2
4235H–8051–10/06
Figu re 6. Mode Switching Waveforms
The X2 bit in the CKCON0 register (see Table 16) allows a switch from 12 clock periods
per instruc tion to 6 clock periods and v ice vers a. A t res et, t he speed is s et ac cording t o
X2 bit of Hardware Security B yte (HSB). By default, Standard mode is act ive. Setting the
X2 bit activates the X2 feature (X2 mode).
The T0X2, T1X2, T2X2 , UartX2, PcaX2, and WdX2 bits in th e CKCON0 register (Tabl e
16) and SPIX2 bit in the CKCON1 registe r (see Table 17) allows a switch from stan dard
peripheral speed (12 clock peri ods per peripheral clock cycl e) t o fast peripheral speed (6
clock periods per periphe ral clock cycle). These bits are active only i n X2 mode.
XTAL1:2
XTAL1
CPU Clock
X2 Bit
X2 ModeSTD Mode STD Mode
FOSC
19
AT89C51RD2/ED2
4235H–8051–10/06
Table 16. CKC ON0 Register
CKCON0 - Clock Contro l Register (8Fh)
Rese t Value = 0000 000’HSB. X2’b (See “Hardware Security Byte”)
Not bit addressable
76543210
- WDX2 PCAX2 SIX2 T2X2 T1X2 T0X2 X2
Bit
Number Bit
Mnemonic Description
7Reserved The values for this bit are indeterminite. Do not set this bit.
6WDX2
Watchdog Cloc k
(T h is con t rol bi t is vali da te d when the C PU clock X 2 i s s et; whe n X 2 is lo w, th is bit
has no effect).
Cleared to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock per iods per peri pheral clock cycle.
5PCAX2
Programmable Counter Array Clock
(T h is con t rol bi t is vali da te d when the C PU clock X 2 i s s et; whe n X 2 is lo w, th is bit
has no effect).
Cleared to select 6 clock periods per peripheral clock cycle. Set to select 12 clock
period s per pe ripheral clo c k cycle.
4SIX2
Enhanced UART Clock (Mode 0 and 2)
(T h is con t rol bi t is vali da te d when the C PU clock X 2 i s s et; whe n X 2 is lo w, th is bit
has no effect).
Cleared to select 6 clock periods per peripheral clock cycle. Set to select 12 clock
period s per pe ripheral clo c k cycle.
3T2X2
Timer2 Clock
(T h is con t rol bi t is vali da te d when the C PU clock X 2 i s s et; whe n X 2 is lo w, th is bit
has no effect).
Cleared to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock per iods per peri pheral clock cycle.
2T1X2
Timer1 Clock
(T h is con t rol bi t is vali da te d when the C PU clock X 2 i s s et; whe n X 2 is lo w, th is bit
has no effect).
Cleared to select 6 clock periods per peripheral clock cycle. Set to select 12 clock
period s per pe ripheral clo c k cycle.
1T0X2
Timer0 Clock
(T h is con t rol bi t is vali da te d when the C PU clock X 2 i s s et; whe n X 2 is lo w, th is bit
has no effect).
Cleared to select 6 clock periods per peripheral clock cycle. Set to select 12 clock
period s per pe ripheral clo c k cycle.
0X2
CPU Clock
Cleared to select 12 clock periods per machine cycle (STD mode) for CPU and
all the peripherals. Set to select 6 clock periods per machine cycle (X2 mode)
and to enable the individu al peri pherals’X2’ bit s. Programmed by ha rdware after
Power-up regarding Hardwa re Security By te (HSB), De fault setting, X2 is
cleared.
20
AT89C51RD2/ED2
4235H–8051–10/06
Table 17. CKC ON1 Register
CKCON1 - Clock Contro l Register (AFh)
Reset Value = XXXX XXX0b
Not bit addressable
76543210
-------SPIX2
Bit
Number Bit
Mnemonic Description
7-Reserved
6-Reserved
5-Reserved
4-Reserved
3-Reserved
2-Reserved
1-Reserved
0SPIX2
SPI (This control bit is validated when the CPU clock X2 is set; when X2 is low,
this bit has no effect).
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock per iods per peri pheral clock cycle.
21
AT89C51RD2/ED2
4235H–8051–10/06
Dual Data Pointer
Register (DPTR) The ad dit ional da ta po int er can b e u sed to speed up c ode ex ecut ion and red uce cod e
size.
T he du al D PT R st ru c tur e is a way by w hic h the c hip will s p ec ify the address o f an e xte r-
nal data memory locati on. There are two 16-bit DPTR registers that address the external
memory, and a singl e bit called DPS = AUXR1.0 (see Table 18) that allows t he program
code to switch between them (Refer to Fi gure 7).
Figu re 7. Use of Dual Pointer
External Data Memory
AUXR1(A2H)
DPS
DPH(83H) DPL(82H)
07
DPTR0
DPTR1
22
AT89C51RD2/ED2
4235H–8051–10/06
Table 18. AUXR1 Register
AUXR 1- Auxiliary Register 1(0A2h)
Reset Value = XXXX XX0X0b
Not bit addressable
Note: 1. Bit 2 stu ck at 0; thi s al lows to use INC AUXR1 to toggl e DPS wit hout c hanging GF3.
ASSEM BLY LAN GUA GE
; Block move using dual data pointers
; Modifies DPTR0, DPTR1, A and PSW
; note: DPS exits opposite of entry state
; unless an extra INC AUXR1 is added
;
00A2 AUXR1 EQU 0A2H
;
0000 909000MOV DPTR,#SOURCE ; address of SOURCE
0003 05A2 INC AUXR1 ; switch data pointers
0005 90A000 MOV DPTR,#DEST ; address of DEST
0008 LOOP:
0008 05A2 INC AUXR1 ; switch data pointers
000A E0 MOVX A,@DPTR ; get a byte from SOURCE
000B A3 INC DPTR ; increment SOURCE address
000C 05A2 INC AUXR1 ; switch data pointers
000E F0 MOVX @DPTR,A ; write the byte to DEST
000F A3 INC DPTR ; increment DEST address
0010 70F6JNZ LOOP ; check for 0 terminator
0012 05A2 INC AUXR1 ; (optional) restore DPS
76543210
- - ENBOOT - GF3 0 - DPS
Bit
Number Bit
Mnemonic Description
7-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
6-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
5 ENBOOT Enab le Boot Fla sh
Cle ared t o disa ble boot ROM .
Set to map the boot ROM between F800h - 0FFFFh.
4-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
3GF3This bit is a general-purpose user flag.(1)
20Always cleared
1-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
0DPS
Data Pointer Sel ec tion
Cleared to select DPTR0.
Set to select DPTR1.
23
AT89C51RD2/ED2
4235H–8051–10/06
INC is a short (2 by tes) and fast (12 clock s) way to manipulate the DPS bit i n the AUXR1
SFR. However, note that t he INC instruction does not directly force the DPS bit to a par-
ticular s tate, but simply t oggles it. In simple rou tines, such a s the block move exam ple,
only the fact that DPS is togg led in the p roper sequenc e m at ters, not its actual value . In
oth er words, the blo ck move rout ine works the sam e whethe r D PS is '0 ' or '1' on entry.
Observ e that witho ut the last in struction (INC AU XR1), the rou tine will ex it with DPS in
the opposite s tate.
24
AT89C51RD2/ED2
4235H–8051–10/06
Expanded RAM
(XRAM) The AT89C51RD2/ED2 provides additional on-chip random access memory (RAM)
space for increas ed data parameter handling and high level language usage.
AT 89C51 RD2/ ED2 dev ice ha S expa nded R AM in externa l dat a space c onfig urabl e up
to 1792 bytes (see Table 19).
The AT89C51RD2/ED2 internal data memory is mapped into four separate segments.
The fou r segments are:
1. The Lower 128 bytes of RAM (addresses 00h to 7Fh) are directly and indirectly
addressable.
2. The Upper 128 bytes of RAM (addresses 80h to FFh) are indirect ly addressable
only.
3. The S pecial Function Registers, SFRs, (addresses 80h to FFh) are directly
addressable only.
4. The expanded RAM bytes are i ndirectly access ed by MOVX ins tructions, and
with the EX T R AM bit cleared in the AUX R register (see Table 19).
The lower 128 bytes can be accessed by either direct or indirect addressing. The Upper
128 bytes can be accessed by indirect addressing only. The Upper 128 bytes occupy
the sam e ad dres s sp ace as the S FR. Th at means they hav e the s am e address , but are
physi cally separate from SFR space.
Figu re 8. Internal and External Data Memory Address
W hen an instruction ac cesses an i nternal location ab ove addre ss 7Fh, the CPU kn ows
whether the access is to the upper 128 b ytes o f da ta RAM or to SFR space by the
address ing mode used in the i nst ruction.
• Instructions that use direct addressing access SFR space. For example: MOV
0A0H, # data, acc ess es the SFR at location 0A0h (which is P2).
• Instructions that use indirect addressing access the Upper 128 bytes of data RA M .
For example: MOV @R0, # data where R0 contains 0A0h, accesses the data byte
at address 0A0h, rather than P2 (whose address is 0A0h).
• The XRAM bytes can be accessed by i ndirect addressing, with E XTRAM bit cleared
and MOVX instructions. This part of memory which is physically located on-chip,
logically occupies the first bytes of external data memory. The bits XRS0 and XRS1
are used to hide a part of the available XRAM as explained in Table 19. This can be
XRAM
Upper
128 Bytes
Internal
RAM
Lower
128 Bytes
Internal
RAM
Special
Function
Register
80h 80h
00
0FFh or 6FFh 0FFh
00
0FFh
External
Data
Memory
0000
00FFh up to 06FFh
0FFFFh
Indirect Accesses Direct Accesses
Direct or Indire ct
Accesses
7Fh
25
AT89C51RD2/ED2
4235H–8051–10/06
useful if ex ternal peripherals are mapped at addresses already us ed by t he internal
XRAM.
• With EXT RAM = 0, the XRAM is indirectly addressed, using the MOVX instruction in
combination with any of the registers R0, R1 of the selected bank or DPT R. An
access t o XRAM will not affect ports P0, P2, P3.6 ( WR) and P3.7 (R D) . For
example, with EXTRA M = 0, MOVX @R 0, # data where R0 contains 0A0H,
accesses the XRAM at address 0A0H rather than external memory. An access to
external data memory l ocations higher than the accessible size of the XRAM will be
performed with the MOVX DPTR instructions in the same way as in the standard
80C51, with P0 and P2 as data/address busses, and P3.6 and P3.7 as write and
read timing signals. Acces ses to XRAM above 0FFH can only be done by the use of
DPTR.
• With EXTRAM = 1, MOVX @Ri and MOVX @DPTR will be si milar to the standard
80C51.MOV X @ Ri will provide an eight-bit address multiplexed with data on Port 0
and any output port pins can be used to output higher order address bits. This is to
pro v ide the exter na l pa g ing c apa b ili ty. M OV X @ D PTR will g ener ate a s ix teen-b it
address. Port2 outputs the high-order eight address bit s (the content s of DPH) whi le
Port0 multiplexes the low-order ei ght address bits (DPL) with data. MOVX @ Ri and
MOVX @DPTR will generate either rea d or write signals on P3.6 (WR ) and P3.7
(RD).
The stack pointer (SP) may be located anywhere in the 256 bytes R AM (lower and
upper RAM) internal data memory. The st ack may not be located in the XRAM.
The M0 bit allows to stretch th e XRAM timings; if M 0 is set, the r ead and write pu lses
are extended from 6 to 30 clock periods. This is useful to access external slow
peripherals.
26
AT89C51RD2/ED2
4235H–8051–10/06
Registers Table 19. AU XR Regi ster
AUXR - Auxiliary Register (8Eh)
Rese t Value = 0X00 10’HSB . XRAM’0 b
Not bit addressable
76543210
DPU - M0 XRS2 XRS1 XRS0 EXTRAM AO
Bit
Number Bit
Mnemonic Description
7DPU
Disable Weak Pull-up
Cleared by sof tware to activate the permanent weak pull-up ( default)
Set by software to di sable the weak pull-up (reduce power consumption)
6-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
5M0
Pulse len gth
Cleared to stretch MOVX control: the RD and the WR pu ls e le ng th is 6 clock
periods (default).
Se t to st r e tc h M O VX c on tr o l: t he RD and the WR pulse length is 30 clock periods.
4XRS2XRAM Size
XRS2 XRS1 XRS0 XR A M size
0 0 0 256 bytes
0 0 1 512 bytes
0 1 0 768 bytes(default)
0 1 1 1024 bytes
1 0 0 1792 bytes
3XRS1
2XRS0
1 EXTRAM
EXTRAM bit
Cleared to access internal XRAM using movx @ Ri/ @ DPTR.
Set to access external memory.
Programmed by hardware a f t er Power-up regarding Hardware Security Byte
(HSB), defa ult sett ing, XRAM selecte d.
0AO
ALE Output bit
Cl e ared , ALE is emi tte d at a con st ant r ate of 1/ 6 the osci ll a tor freq ue nc y (o r 1/ 3 if
X2 mode is used). (default) Set, ALE is active only during a MOVX or MOVC
instr u c tio n is use d.
27
AT89C51RD2/ED2
4235H–8051–10/06
Reset
Introduction The re set sourc es are: Power M anagemen t, Hardware W atchdog , PCA Wa tchdog an d
Rese t input.
Fi gure 9 . Reset schematic
Reset Input Th e Res et in put c an be use d to f orce a r ese t pu lse lo nger than the in tern al re set co n-
trolled by the Power Monitor. RST input has a pull-down resistor allowing power-on
reset by simply connec ting an exte rnal capacitor to VCC as shown in Figure 10. Resistor
value and i nput characteristics are di scu sse d in th e Section “DC Charact eristics” of the
AT 89C51RD2 /ED2 datas heet.
Fi gure 1 0 . Reset Circuitry and Power-On Reset
Power
Monitor
Hardware
Watchdog
PCA
Watchdog
RST
In ternal Reset
RST
RRST
VSS
To interna l reset
RST
VDD
+
b. Power -on Res e
t
a. RST input circuitry
28
AT89C51RD2/ED2
4235H–8051–10/06
Reset Output
Rese t output can be generated by two sources:
• Internal POR/PFD
• Hardware watchdog timer
As detailed in Section “Hardware Watchdo g T imer”, page 86, the WDT generates a 96-
clock period pulse on the RST pin.
In order to properly propagate this pulse to the rest of the application in case of external
capa citor or pow er-suppl y supervi sor circuit, a 1 kΩ res isto r m ust be ad ded a s sh ow n
Figure 11.
Fi gure 11. Recom me nded Reset Output Schema tic
RST
VDD
+
VSS
VDD
RST
1K
To other
on-board
circuitry
AT89C51XD2
29
AT89C51RD2/ED2
4235H–8051–10/06
Powe r Monitor Th e PO R/PFD f unct ion monitors the i nte rnal pow er- suppl y of the CPU core m emo ries
and the perip herals, and if needed, suspends their activity when the internal power sup-
ply fall s below a safety threshold. This is achieved by applying an internal reset to them.
By generating the Reset the Power Monitor insures a correct start up when
AT 89C51RD2 /ED2 is powered up.
Description In order to startup and main tain the microco ntroller in corre ct operating m ode, VCC has
to be st abilized in t he VCC operating ran ge and the oscillator has t o be stabilized with a
nomi nal amplitude comp atible with logic level VIH/VIL.
The se pa rame ters are cont rolled d uring t he three pha ses: po wer-up, norm al ope ration
and power going down. See Figure 12.
Fi gure 1 2 . Power Monitor Block Diagram
Note: 1. Once XTAL1 High and low levels reach above and below VIH/VIL. a 1024 clock
period delay will extend the reset coming from the Power Fail Detect. If the power
falls below the Power Fail Detect threshold level, the Reset will be applied
immediately.
The V oltage reg ulator generates a regu lated internal sup ply for the CPU core the mem -
ories and the peripherals. Spikes on the external Vcc are sm oothed by the voltage
regulator.
VCC
Power On Res et
Power Fail Detect
Voltag e Regulator
XTAL1 (1)
CPU core
Memories
Peripherals
Regulated
Supply
RST pin
Hardware
Watchdog
PCA
Watchdog
Internal Reset
30
AT89C51RD2/ED2
4235H–8051–10/06
The Powe r fa il dete ct m onitor the supply generated by the v oltage regulator and gener-
ate a reset if this supply f alls below a saf ety thresho ld as illu strated in the Fig ure 13
below.
Figu re 13. Power Fail Detect
When the power is applied, the Power Monitor immediately asserts a reset. Once the
inte rna l suppl y afte r the vo ltage regula tor reac h a sa fety level, the pow er mo nito r then
looks at the XTAL c lock in put. Th e internal reset will rema in ass erted unt il the Xtal1 lev-
els are above and below VIH and VIL. Further more. An internal counter will count 1024
clock periods before the reset is de-asserted.
If the internal power supply falls below a safety level, a reset is i mm edia tely asserted.
.
Vcc
t
Reset
Vcc
V
PFDP
V
PFDM
31
AT89C51RD2/ED2
4235H–8051–10/06
Timer 2 The Timer 2 in the AT89C51RD2/ED2 is the standard C52 Timer 2. It is a 16-bit
timer/cou nter: the c ount i s m aintaine d b y tw o ei ght-bit t imer regi sters, TH 2 and TL2 are
cascaded . It is controlled by T2CO N (Tabl e 20) and T2MO D (Table 21) regis ters. Timer
2 operation is sim ilar to Timer 0 and Tim er 1 . C/T2 selects FOSC/12 (time r operation) or
external pin T2 (counter operation) as the timer clock input. Setting TR2 allows TL2 to
incre men t by the selected input.
Time r 2 has 3 o perati ng mo des: captur e, aut oreloa d and Baud Rate Ge nera tor. Thes e
modes are se lected by the combination of RCLK, TCLK and CP/RL2 (T2CON).
Refer to th e At mel 8-bi t Microcon troller Hardwa re M anual f or the description of Capt ure
and Baud Rate Generator Modes.
Timer 2 includes the following enhancements:
• Auto-reload mode with up or down counter
• Programmable clock-output
Auto-reload Mode The auto-re load mod e con figu res Tim er 2 as a 16 -bit time r or eve nt counte r with auto-
ma tic reloa d. If DCEN bit in T 2MO D is cle ared, Tim er 2 beh aves as in 80 C52 (re fer to
the Atmel C51 Microcontroller H ardware Manual). If DCE N bit is set, Timer 2 acts as an
U p/dow n ti mer /cou nter a s sh ow n in Figu re 14. I n thi s mo de t he T 2E X pin con trols the
direction of count.
W hen T 2EX is hi gh, Timer 2 c ounts up. T im er overf low occurs at F FF Fh which set s t he
TF2 flag and gen erates an interrupt request. The overf low also causes the 16-bit value
in RCAP2H and RCAP 2L registers to be loaded into the timer registers TH2 and TL2.
When T2EX is low, Timer 2 counts down. Timer underflow occurs when the count in the
timer registers TH2 and TL2 equals the value stored in RCAP2H and RCAP2L registers.
The underf low sets TF2 flag and reloads FFFFh into the timer registers.
The EX F2 bit toggles when Timer 2 overflows or underflows accordi ng to the direction of
the count . EXF2 doe s not generate any interrupt. This bit can be used to provide 17-bit
resolution.
32
AT89C51RD2/ED2
4235H–8051–10/06
Fi gure 1 4 . Auto-reload Mode Up/ Down Count er (DCEN = 1)
Programmable
Clock-output In t he clock-out mode, Timer 2 operates as a 50% duty-cycle, progr ammable clock gen-
er ator (S ee Figure 15). T he input clock increme nts TL2 at fre quency FCLK PERIPH/2. The
timer repeatedly counts to over flow from a loaded value. At overflow, the contents of
RCAP2H and RC AP2L registers are loaded into TH2 and TL2. In this mode, Timer 2
overflows do not generate interrupts. The formula gives the clock-out frequency as a
function of the system oscillator frequency and the value in the RCAP2H and RCAP2L
registers:
For a 16 MHz system clock, Timer 2 has a programmable frequency range of 61 Hz
(FCLK PERIPH/216) to 4 M H z (F CLK PERIPH/4). The generated clock signal is brought out to
T2 pin (P1.0).
Timer 2 is programmed for the clock-out mode as follows:
• Set T2OE bit in T2MOD register.
• C lear C/T2 bit in T2CON register.
• Determine the 16- bit reload value from the formula and enter it in RCAP2H/RCAP2L
registers.
• Enter a 16-bit initial value in timer registers TH2/TL2. It can be the same as the
reload value or a different one depending on the application.
• To start the timer, set TR2 run control bit in T2CON register.
It is possible to use Timer 2 as a baud rate generator and a clock generator simulta-
neously. For this configuration, the baud rates and clock frequencies are not
independent since both functions use the values in the RCAP2H and RCAP2L r egister s.
(DOWN COUNTING RELOAD VALUE)
C/T2
TF2
TR2
T2
EXF2
TH2
(8-bit)
TL2
(8-bit)
RCAP2H
(8-bit)
RCAP2L
(
8-bit)
FFh
(8-bit) FFh
(8-bit)
TOGGLE
(UP COUNTING RELOAD VALUE)
TIMER 2
INTERRUP
T
FCLK PERIPH
0
1
T2CON T2CON
T2CON
T2CON
T2EX:
If DCEN = 1, 1 = UP
If DCEN = 1, 0 = DOWN
If DCEN = 0, up countin
g
:6
Clock O
–
utFrequency
F
CLKPERIPH
4 65536 RCAP2HRCAP2L⁄)
–
(×
---------------------------------------------------------------------------------------------
=
33
AT89C51RD2/ED2
4235H–8051–10/06
Fi gure 1 5 . Clock-out Mode C/T2 = 0
:6
EXF2
TR2
OVER-
FLOW
T2EX
TH2
(8-bit)
TL2
(8-bit)
TIMER 2
RCAP2H
(8-bit)
RCAP2L
(8-bit)
T2OE
T2
FCLK PERIPH
T2CON
T2CON
T2CON
T2MOD
INTERRUPT
QD
Toggle
EXEN2
34
AT89C51RD2/ED2
4235H–8051–10/06
Registers Table 20. T 2CON Register
T2CON - Timer 2 Control Register ( C8h)
Rese t Value = 0000 0000b
Bit addressable
76543210
TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2# CP/RL2#
Bit
Number Bit
Mnemonic Description
7 TF2 Tim er 2 ove rflow Fla g
Must be cleared by software.
Set by hardware on Timer 2 overflow, if RCLK = 0 and TCLK = 0.
6EXF2
Timer 2 External F lag
Set when a capture or a reload is cau s ed by a negative transition on T2EX pin i f
EXEN 2 = 1 .
When set, causes the CPU to vector to Timer 2 interrupt routine when Timer 2
interrupt is enabled.
Must be cleared by software. EXF2 doesn’t cause an interrupt in Up/do wn
counter m ode (DCEN = 1 ) .
5 RCLK Receive Clock bit
Cleared to use timer 1 overflow as receive clock for serial port in mode 1 or 3.
Set to use Timer 2 overflow as receive clock for serial port in mode 1 or 3.
4TCLK
Transmit Clock bit
Cleared to use timer 1 overflow as transmit clock for seria l port in mode 1 or 3.
Set to use Timer 2 overflow as transmit clock for serial port in mode 1 or 3.
3 EXEN2
Timer 2 External Enable bit
Cleared to ignore events on T2EX pin for Timer 2 operation.
Set to cause a capture or reload when a negative transition on T2EX pin is
detected, if Timer 2 is not used to clock the serial port.
2TR2
Timer 2 Run control bit
Cleared to turn off Timer 2.
Set to turn on Timer 2.
1C/T2#
Timer/Counter 2 select bit
Cleared for timer operation (input from internal clock system : FCLK PERIPH).
Set fo r coun t er op erat i on (inp ut fro m T2 inp ut pi n, fall i ng edg e tri gg er) . Mus t be 0
for clock out mode.
0CP/RL2#
Timer 2 Capture/Reload bit
If RCLK = 1 or TCLK = 1, CP/RL2# is ignored and timer is forced to auto-reload
on Timer 2 overflow.
Cleared to auto-reload on Timer 2 overflows or negative transitions on T2EX pin
if EXEN2=1.
Set to cap ture o n negative transitions on T2EX pin if E XEN2 = 1.
35
AT89C51RD2/ED2
4235H–8051–10/06
Table 21. T2MOD Regi ster
T2M OD - Timer 2 Mode Control Register (C9h)
Reset Value = XXXX XX00b
Not bit addressable
76543210
------T2OEDCEN
Bit
Number Bit
Mnemonic Description
7-
Reserved
T he valu e rea d fro m thi s bi t is indet erm in at e. D o no t set this bit.
6-
Reserved
T he valu e rea d fro m thi s bi t is indet erm in at e. D o no t set this bit.
5-
Reserved
T he valu e rea d fro m thi s bi t is indet erm in at e. D o no t set this bit.
4-
Reserved
T he valu e rea d fro m thi s bi t is indet erm in at e. D o no t set this bit.
3-
Reserved
T he valu e rea d fro m thi s bi t is indet erm in at e. D o no t set this bit.
2-
Reserved
T he valu e rea d fro m thi s bi t is indet erm in at e. D o no t set this bit.
1T2OE
Timer 2 Output Enable bit
Cleared to program P1.0/T2 as clock input or I/O port.
Set to program P1.0/T2 as cl ock output.
0 DCEN Down Counter Enable bit
Cleared to disa ble Timer 2 as up/down counter.
Set to enable Timer 2 as up/down counter.
36
AT89C51RD2/ED2
4235H–8051–10/06
Programmable
Counter Array (PCA) The PCA provides more timi ng capabilities with less CPU i ntervention than the standard
timer/c ounters. I ts adva ntages in clude reduced software ove rhead a nd impro ved accu-
racy. The PCA con si sts of a dedic ated timer/cou nter which serves as t he time base for
an array of five com pare/ca pture modu les. Its clock i nput can b e program med to co unt
any one of the following signals:
• Peripheral clock frequency (FCLK PERIPH) ÷ 6
• Peripheral clock frequency (FCLK PERIPH) ÷ 2
• Time r 0 overflow
• External input on ECI (P1 .2)
Each comp are/cap ture module can be program med in any one of the following modes:
• Rising and/or falling edge capture
• Software timer
• High-speed output
• Puls e width modulat or
Mo dule 4 ca n als o be pro grammed as a w atchd og time r (see Se ction "PCA Wa tchdo g
Timer" , page 47).
When the compare/captur e modules are programmed in the capture mode, soft ware
timer, or high speed output m ode, an interrupt can be generated when the module ex e-
cutes its function. All five modules plus the PCA timer overflow share one interrupt
vector.
The PCA timer/counter and compare/capture modul es share Port 1 for external I/O.
These pins a re listed belo w. If one or se veral bits in the po rt are not us ed for the PCA ,
they can still be us ed fo r standard I/O.
Th e PC A ti mer is a c om mon t im e bas e fo r all f ive m odu les ( see Fig ure 16 ). T he ti mer
count source is determined from the CPS1 and CPS0 bits in the CMOD register
(Table 22) and can be programmed t o run at:
• 1/6 the peripheral clock f reque nc y (F CLK PERIPH)
• 1/2 the peripheral clock f reque nc y (F CLK PERIPH)
• The Timer 0 overflow
• The input on the ECI pin (P 1. 2)
PCA Component External I/O Pin
16-bit Counter P1.2/ECI
16-bit Module 0 P1.3/CEX0
16-bit Module 1 P1.4/CEX1
16-bit Module 2 P1.5/CEX2
16-bit Module 3 P1.6/CEX3
37
AT89C51RD2/ED2
4235H–8051–10/06
The CMOD register includes three additional bits associated with the PCA (See
Figure 16 and Tab le 22).
• The CIDL bit whic h allows the PCA to stop during idle mode.
• The WDTE bit which enables or disables the watchdog function on mo dule 4.
• The ECF bit which when set causes an interrupt and the PCA overflow flag CF (in
the CCON SFR) to be set when the PCA timer overflows.
Figu re 16. PCA Timer/Counter
CIDL CPS1 CPS0 ECF
IT
CH CL
16 Bit Up Counter
To PCA
Modules
FCLK PERIPH/6
FCLK PERIPH/2
T0 OVF
P1.2
Idle
CMOD
0xD9
WDTE
CF CR CCON
0xD8
CCF4 CCF3 CCF2 CCF1 CCF0
Overflow
38
AT89C51RD2/ED2
4235H–8051–10/06
Table 22. CMOD Register
CMOD - PCA Counter Mode Register (D9h)
Rese t Value = 00XX X000b
Not bit addressable
The CCON register contains the run control bit for the PCA and the flags for the PCA
timer (CF) and eac h module (Refer to Table 23).
• Bit CR (CCON.6) must be set by softw are to run the PCA. The PCA is shu t off by
clearing this bit.
• Bi t CF: The CF bit (CCON.7) is set when the PCA counter overflows and an
interrupt will be generated if the ECF bit in the CMOD register is set. The CF bit can
only be cleared by software.
• Bits 0 through 4 are the flags for the modules (bit 0 for module 0, bit 1 for module 1,
etc.) and are set by hardware when either a match or a capture occurs. These flags
also can only be cleared by software.
76543210
CIDL WDTE - - - CPS1 CPS0 ECF
Bit
Number Bit
Mnemonic Description
7CIDL
Coun ter Idle Co ntrol
Cleared to program the PCA Counter to continue functioning during idle Mode.
Set to program PCA to be gated off during idle.
6WDTE
Wat c hd og Timer Enable
Cleared to di sable Watchdog Time r func tion on PC A Modul e 4.
Set to enable Watchdog Timer function on PCA Module 4.
5-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
3-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
2 CPS1 PCA Count Pulse Select
CPS1 CPS0 Sel ected PCA input
0 0 Internal clock FCLK PE RIPH/6
0 1 Internal clock FC LK PERIPH/2
1 0 Timer 0 Overflow
1 1 External clock at ECI/P1.2 pin (max rate = FCLK P ERIPH/4)
1 CPS0
0ECF
PCA Enab le Coun ter O ve rflow Inte rrupt
Cleared to disable CF bit in CCON to inhibit an interrupt.
Set to enable CF bit in CCON to generate an interrupt.
39
AT89C51RD2/ED2
4235H–8051–10/06
Table 23. CCON Register
CCON - PCA Counte r Control Register (D8h)
Rese t Value = 00X0 0000b
Bit addressable
The watchd og timer function is implemented in Mod ule 4 (See Figure 19).
The PCA interrup t system is sh ow n in Figur e 17.
76543210
CF CR - CCF4 CCF3 CCF2 CCF1 CCF0
Bit
Number Bit
Mnemonic Description
7CF
PCA Counter Overflow flag
Set by hardware when the counter rolls over. CF flags an interrupt if bit ECF in
CMOD is set. CF
may be set by either hardware or software but can only be cleared by software.
6CR
PCA Counter Run control bit
Must be cleared by software to turn the PCA counter off.
Set by software to turn the PCA counter on.
5-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4 CCF4 PCA Module 4 interrupt flag
M ust be cleared by softw are.
Set by ha rdware when a match or capture occurs.
3 CCF3 PCA Module 3 interrupt flag
M ust be cleared by softw are.
Set by ha rdware when a match or capture occurs.
2 CCF2 PCA Module 2 interrupt flag
M ust be cleared by softw are.
Set by ha rdware when a match or capture occurs.
1 CCF1 PCA Module 1 interrupt flag
M ust be cleared by softw are.
Set by ha rdware when a match or capture occurs.
0 CCF0 PCA Module 0 interrupt flag
M ust be cleared by softw are.
Set by ha rdware when a match or capture occurs.
40
AT89C51RD2/ED2
4235H–8051–10/06
Figu re 17. PCA In te r rupt Syste m
PCA Modules: each one of the five compare/capture modules has six possible func-
tions. It can perform :
• 16-bit Capture, positive-edge triggered
• 16-bit Capture, negative-edge triggered
• 16-bit Capture, both positive and negative-edge triggered
• 16-bit Software Timer
• 16-bit High Speed Output
• 8-bit Pulse Width Modulator
In addition, Mod ule 4 can be used as a Watchdog Timer.
Each mo dule in the PCA has a sp ecial fun ction register a ssociated with it. These regis-
ters are: CCAPM0 for Module 0, CCAPM1 for Module 1, etc. (See Table 24). The
registers contain the bits that control the mode that each module will operate in.
• The ECCF bit (CCAPM n.0 where n = 0, 1, 2, 3, or 4 dependi ng on the module)
enables the CCF flag in the CCON SFR t o generate an interrupt when a matc h or
compare occurs in the associated module.
• PWM (CCAPMn.1) enable s the pulse width modulation mode.
• The TOG bit (CCAPMn.2) when set causes the CEX output associated with the
module to toggle when there is a match between the PCA counter and the modules
capture/compare regis ter.
• The match bit MAT (CCAPMn.3) when set will cause the CCFn bit in the CCON
register to be set when there is a mat ch between t he PCA counter and the modules
capture/compare regis ter.
• The next two bits CAPN (CCAPMn.4) and CAPP (CCAPMn.5) determine the edge
that a capture input will be active on. The CAPN bit enables the negative edge, and
the CAPP bit enables the positive edge. If both bits are set both edges will be
enabled and a capture will occ ur for either transit ion.
• The last bit in the register ECOM (CCAPM n.6) when set enables the comparator
function.
CF CR CCON
0xD8
CCF4 CCF3 CCF2 CCF1 CCF0
Module 4
Module 3
Module 2
Module 1
Module 0
ECF
PCA Timer/Counter
ECCFn CCAPMn.0CMOD.0 IEN0.6 IEN0.7
To Interrupt
Priori ty Deco der
EC EA
41
AT89C51RD2/ED2
4235H–8051–10/06
Table 24 shows the CCAPMn settings for the various PCA func tions.
Table 24. CCA PMn Registers (n = 0-4)
CCAPM0 - PCA Module 0 Compare/Capture Control Register (0DAh)
CCAPM1 - PCA Module 1 Compare/Capture Control Register (0DBh)
CCAPM2 - PCA Module 2 Compare/Capture Control Register (0DCh)
CCAPM3 - PCA Module 3 Compare/Capture Control Register (0DDh)
CCAPM4 - PCA Module 4 Compare/Capture Control Register (0DEh)
Rese t Value = X000 0000b
Not bit addressable
76543210
- ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn
Bit
Number Bit
Mnemonic Description
7-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
6ECOMn
Enable Comparator
Cleared to disable the comparator function.
Set to enable the comparator function.
5 CAPPn Capt ure Pos itiv e
Cleared to disable positive edge capture.
Set to enable positive edge capture.
4 CAPNn Capture Neg ati ve
Cleared to disable negative edge capture.
Set to enable negative edge capture.
3MATn
Match
When MATn = 1, a matc h of the PCA counter with this module's
c ompare/capture register causes th e CCFn bit in CCON to be set, flag ging an
interrupt.
2 TOGn Toggle
When TOGn = 1, a match of the PCA counter with this module's
compare/capture register causes the CEXn pin to toggle.
1PWMn
Pulse Width M odulation Mode
Cleared to disable the CEXn pin to be used as a pul se wid th modulate d output.
Set to enable the CEXn pin to be used as a pulse width modulated output.
0 CCF0
Enable CCF interrupt
Cl ea red to di sa bl e comp ar e /cap t ure f la g CCFn in t he CCON regi st er t o ge ne rat e
an interrupt.
Set to enable compare/capture flag CCFn in the CCON register to generate an
interrupt.
42
AT89C51RD2/ED2
4235H–8051–10/06
Table 25. PCA M odule M odes (CC APM n Registers)
The re are two a dditiona l regist ers associ ated with each of the PC A mo dules. The y are
CCAPnH and CCAPnL and these are the registers that store the 16-bit count when a
ca pture oc curs or a com pare s hould occur. W hen a m odul e is used in the PWM m ode
these registers are used to control the duty cycle of the output (See Table 26 &
Table 27).
Table 26. CCA PnH Registers (n = 0 - 4)
CCAP0H - PCA Module 0 Compare/Capture Control Register High (0FAh)
CCAP1H - PCA Module 1 Compare/Capture Control Register High (0FBh)
CCAP2H - PCA Module 2 Compare/Capture Control Register High (0FCh)
CCAP3H - PCA Module 3 Compare/Capture Control Register High (0FDh)
CCAP4H - PCA Module 4 Compare/Capture Control Register High (0FEh)
Rese t Value = 0000 0000b
Not bit addressable
ECOMn CAPPn CAPNn MATn TOGn PWMm ECCFn Module Function
0000000 No Operation
X10000X
16-bit c aptur e by a posit ive-edge
trigger on CEXn
X01000X
16-bit capture by a negativ e trigger
on CEXn
X11000X
16-bit capture by a transition on
CEXn
100100X
16-bit Software T imer/Compare
mode.
100110X16-bit High Speed Output
10000108-bit PWM
1001X0XWatchdog Timer (module 4 only)
76543210
--------
Bit
Number Bit
Mnemonic Description
7 - 0 - PCA Module n Co mpare/Capture Control
CCAPnH Value
43
AT89C51RD2/ED2
4235H–8051–10/06
Table 27. CCAP nL Registers (n = 0 - 4)
CCAP0L - PCA Module 0 Compare/Capture Control Register Low (0EAh)
CCAP1L - PCA Module 1 Compare/Capture Control Register Low (0EBh)
CCAP2L - PCA Module 2 Compare/Cap ture Control Register Low (0ECh)
CCAP3L - PCA Module 3 Compare/Cap ture Control Register Low (0EDh)
CCAP4L - PCA Module 4 Compare/Capture Control Register Low (0EEh)
Rese t Value = 0000 0000b
Not bit addressable
Table 28. CH Register
CH - PCA Counter Register High (0F9h)
Rese t Value = 0000 0000b
Not bit addressable
Table 29. CL Regist er
CL - PCA Counter Register Low (0E9h)
Rese t Value = 0000 0000b
Not bit addressable
76543210
--------
Bit
Number Bit
Mnemonic Description
7 - 0 - PCA Module n Co mpare/Capture Control
CCAPnL Value
76543210
--------
Bit
Number Bit
Mnemonic Description
7 - 0 - PCA counter
CH Value
76543210
--------
Bit
Number Bit
Mnemonic Description
7 - 0 - PCA Counter
CL Value
44
AT89C51RD2/ED2
4235H–8051–10/06
PCA Capture Mode T o use on e of the P CA m odules in the c aptu re mode eith er one or both of the CCA PM
bits CAP N and CAPP for th at modu le m ust b e set. T he exte rnal CEX inpu t for the m od-
ule (on port 1) is sampled for a tran sition. When a valid transition occu rs the PCA
hard wa re lo ads the val ue of t he PC A cou nte r regi sters ( CH and CL) i nto th e mo dule 's
cap ture regist ers (CCAPnL and CCAPnH). If the CC Fn bit for the module in the CCO N
SF R and the ECCFn bit in the CCAPMn SFR are set then an interrupt will be generated
(Refer to Figure 1 8).
Figu re 18. PCA Capture Mode
16-bit Software Timer/
Compare Mode The P CA modules can be used a s software timers by setting both the ECOM and MAT
bits in the modules CCA PMn register. The PCA timer will be compared t o the module's
ca pture r egi ster s and w he n a m atch o ccurs an in terrup t wil l occu r if th e CC Fn (C CON
SF R) and the ECCFn (CCAPMn SFR) bits for t he modu le are both set (See Figure 19).
CF CR CCON
0xD8
CH CL
CCAPnH CCAPnL
CCF4 CCF3 CCF2 CCF1 CCF0
PCA IT
PCA Counter/Time r
ECOMn C CA PM n, n= 0 to 4
0xDA to 0xDE
CAPNn MATn TOGn PWMn ECCFnCAPPn
C
ex.n
Capture
45
AT89C51RD2/ED2
4235H–8051–10/06
Figu re 19. PCA Compare Mo de and PCA Watc hdog Timer
Before enabling ECOM b it, CCAPnL and CCAPnH sho uld be set with a non zero value,
otherwise an unwant ed match could happen. Writing to CCAPnH will set the ECOM bit.
Once ECOM is set, writing CCAPnL will clear ECOM so t hat an unwanted match doesn’t
occur while modifying the compare value. Writing to CCAPnH will set ECOM. For this
reason, user software should write CCAPnL first, and then CCAPnH. Of course, the
ECOM bit can still be controlled by accessing to CCAPMn r egister.
High Speed Output Mode In t his mode the CEX output (on port 1) associated with the PCA module will toggle
each time a match occurs between the PCA counter and the modules capture registers.
To activate this mode the TOG, MAT, and ECOM bits in the module's CCAPMn SFR
must be set (See Figure 20).
A prior write must be done to CCA PnL and CCA PnH before writing the ECOMn bit.
CH CL
CCAPnH CCAPnL
ECOMn C CAPMn, n = 0 to 4
0x DA to 0xDE
CAPNn MATn TOGn PWMn ECCFnCAPPn
16 bit comparator Match
CCON
0xD8
PCA IT
Enable
PC A cou nter/time r
RESET *
CIDL CPS1 CPS0 ECF CMOD
0xD9
WDTE
Reset
Write t o
CCAPnL
Write to
CCAPnH
CF CCF2 CCF1 CCF0
CR CCF3CCF4
10
46
AT89C51RD2/ED2
4235H–8051–10/06
Figu re 20. PCA High Speed Ou tput Mode
Before enabling ECOM b it, CCAPnL and CCAPnH sho uld be set with a non zero value,
otherwise an unwant ed matc h could happen.
Once ECOM is set, writing CCAPnL will clear ECOM so t hat an unwanted match doesn’t
occur while modifying the compare value. Writing to CCAPnH will set ECOM. For this
reason, user software should write CCAPnL first, and then CCAPnH. Of course, the
ECOM bit can still be controlled by accessing to CCAPMn r egister.
Pulse Width Modulato r
Mode All of the PCA mod ules c an be used as PWM outputs. Fi gure 21 shows the PW M func -
tion. The frequency of the output depends on the source for the PCA tim er. All of the
mod ules will have t he same freque ncy of ou tput because t hey all share the P CA timer.
The duty cycle of each module i s independent ly variable using the modules capture reg-
ister CCAPLn. When the val ue of the PCA CL SFR is less than the value in the modules
CCAPLn SFR the output will be low, when it is equal to or greater than the output will be
high. When CL overflows from FF to 00, CCAPLn is reloaded with the value in CCAPHn.
Thi s allo ws up dating th e PW M w ithout gl itch es. Th e PWM and E COM bits in t he mo d-
ule's CCAPM n register must be set to enable the PWM mode.
CH CL
CCAPnH CCAPnL
ECOMn CCAPMn, n = 0 to 4
0xDA to 0xDE
CAPNn MATn TOGn PWMn ECCFnCAPPn
16 bit comparator Match
CF CR
0xD8
CCF4 CCF3 CCF2 CCF1 CCF0
PCA IT
Enable
CEXn
PCA counter/timer
Write t o
CCAPnH
Reset
Wr i te to
CCAPnL
10
47
AT89C51RD2/ED2
4235H–8051–10/06
Fi gure 2 1 . PCA PWM Mode
PCA Watchdog Timer A n on-board watchdog timer is available with the PCA to improve the reliability of the
system without increasing chip count. Watchdog tim ers are useful for systems that are
susceptible to noise, power glitches, or electrostatic discharge. Module 4 is the only
PCA mod ule that can be program m ed as a watchdog. Howev er, this module can still be
used for other modes if th e watchd og is not needed. Figure 19 shows a d iagram of how
the watchdog works. The user pre-loads a 16-bit value in the compare regis ters. Just
like the other compa re modes, this 16-bit value is comp ared to the PCA timer value . If a
match is allowed to occur, an internal reset will be generated. This will not cause the
RST pin to be driven high.
In order to hold off the reset, the user has three options:
1. Periodically change the compare value so it will never match the PCA timer.
2. Periodically change the PCA timer val ue so it will never match the compare
values.
3. Disable the watchdog by clearing the WDTE bit before a match occurs and then
re-enable it.
CL
CCAPnH
CCAPnL
ECOMn CCA PMn, n= 0 to 4
0xD A t o 0x DE
CAPNn MATn TOGn PWMn ECCFnCAPPn
8-bit Comparator CEX
n
“0”
“1”
Enable
PCA Counter/T imer
Overflow
48
AT89C51RD2/ED2
4235H–8051–10/06
The f irst two options are mo re reliable bec ause th e watchdo g timer is never disabled as
in option #3. If the program count er ever goes ast ray, a ma tch will eventu ally occur a nd
cause a n internal reset . The second option is also not recom m ended if o ther PCA m od-
ules are being used. Remember, the PCA timer is the time base for all modules;
changing the time base for other modules would not be a good idea. Thus, in most appli-
cations the first solution is the best option.
This watchdog timer won’t generat e a reset out on the reset pin.
49
AT89C51RD2/ED2
4235H–8051–10/06
Serial I/O Port The serial I/O port in the AT89C51RD2/ED2 i s compatible with the serial I/O port in the
80C52.
It provides both synchronous and asynchronous communication modes. I t operates as a
Universal Asynchronous Receiver and Transmitter (UA RT) in three full-duplex modes
(Modes 1, 2 and 3). Asynchronous trans mission and reception can occur simultaneously
and at different baud rates
Serial I/O port includes the following enhancements:
• Fram ing error detection
• Automatic address recognit ion
Framing Error Detection F raming bit error de tectio n is pro vided fo r the th ree asyn chronou s mod es (mo des 1 , 2
and 3). T o enable the framing bit error de tection feat ure, set SMOD0 bit in PCON regis-
ter (See Figure 22).
Fi gure 2 2 . Framing Error Block Diagram
W hen this feature is enabl ed, the receiver chec ks each incom ing data frame for a valid
stop bit. An invalid stop bit may result f rom noise on the serial l ines or f rom simultaneous
tran smissio n by two C PUs . If a valid st op bit is n ot found, t he Fram ing Error bit (FE) i n
SCON register (See Table 33.) bit is set.
Softwa re may exa mine FE b it after each reception to ch eck for data erro rs. Once set,
only s oftware or a reset can clear FE bi t. Subsequ ently received fram es with valid stop
bits cannot clear FE bit. Whe n F E feature is enabled, RI rises on stop bit instead of the
last data bit (See Figure 23. and Figu re 24.).
Fi gure 2 3 . UART Timings in Mode 1
RITIRB8TB8RENSM2SM1SM0/FE
IDLPDGF0GF1POF-SMOD0SMOD1
To UART fram ing error c ontrol
SM0 to UART mode control (SMOD0 = 0)
Set FE bit if stop bit is 0 (framing error) (SMOD0 = 1)
SCON (98h)
PCON (87h)
Data byte
RI
SMOD0=X
Stop
bit
Start
bit
RXD D7D6D5D4D3D2D1D0
FE
SMOD0=1
50
AT89C51RD2/ED2
4235H–8051–10/06
Fi gure 2 4 . UART Timings in Modes 2 and 3
Automatic Address
Recognition T he automatic address rec og nition feat ure is enabled when the multiprocessor com m u-
nication feature is enabled (SM2 bit in SCO N register is set).
Impl ement ed in hard ware, auto matic add ress recog nition enh ances t he mult iprocessor
communication feature by allowing the serial port to examine the address of each
incoming command frame. Only when the serial port recognizes its own address, the
receiver sets RI bit i n SCON register to generate an interrupt. This ensures that the CPU
is not interrupted by command f rames address ed to other devices.
If desired , the user may ena ble the a utomatic addres s recog nition feature in m ode 1.In
this configuration, the stop bit takes the place of the ninth data bit. Bit RI is set only when
the re ceived comma nd frame ad dress m atches t he device’ s address an d is termina ted
by a valid stop bit.
To support aut om atic addres s rec ognition, a device is identified by a given ad dres s and
a broadca st address.
Note: The multiprocessor communication and automatic address recognition features cannot
be enabled in mod e 0 (i. e. sett ing SM2 bit in SCON reg ister in mode 0 has no effect).
Given Address Each de vice has an individual address that is specified in SADDR register; the SADEN
regi ster is a mask byte that contains don’t-ca re bits (defined by zeros) to form the
dev ice’s given address. The don’t-c are bits provide the flexibility to address one or more
sla ve s at a time. The follow ing ex am ple illu str at es how a given address is form ed.
To address a device by its individual address, the SADEN m ask byte must be 1111
1111b.
For example:
SADDR0101 0110b
SADEN1111 1100b
Given0101 01XXb
The following is an example of how to use given addresses to address different slaves:
Slave A:SADDR1111 0001b
SADEN1111 1010b
Given1111 0X0Xb
Slave B:SADDR1111 0011b
SADEN1111 1001b
Given1111 0XX1b
Slave C:SADDR1111 0010b
SADEN1111 1101b
Given1111 00X1b
RI
SMOD0=0
Data byte Ninth
bit Stop
bit
Start
bit
RXD D8D7D6D5D4D3D2D1D0
RI
SMOD0=1
FE
SMOD0=1
51
AT89C51RD2/ED2
4235H–8051–10/06
The SADEN by te is selected so that each slave may be addressed separately.
For slave A, bi t 0 (the LSB) is a don’t-care bit; for slaves B and C, bit 0 is a 1.To commu-
nicate with slave A only, the master must send an address where bit 0 is clear (e. g.
1111 0000b).
For slave A, bit 1 is a 1; for slaves B and C, bi t 1 is a don’t care bit. To co mmunicate with
slaves B and C, but not slave A, the mas ter must send an address wit h bits 0 and 1 both
set (e. g. 1111 0011b).
To communicate wit h slaves A, B and C, the master must send an address with bi t 0 set,
bit 1 clear, and bit 2 cle ar (e. g. 1111 0001b).
Broadcast Address A broadcast address is formed from the logical OR of the SADDR and SADEN registers
with zeros defined as don’t-care bits, e. g. :
SADDR 0101 0110b
SADEN 1111 1100b
Broadcast =SADDR OR SADEN1111 111Xb
The use of don’t-care bits prov ides flexibility in defining the broadcast address, however
in m ost applicat ions, a broa dcast addre ss is FFh. The f ollowing is an e xample of us ing
broadc ast addresses :
Slave A:SADDR1111 0001b
SADEN1111 1010b
Broadcast1111 1X11b,
Slave B:SADDR1111 0011b
SADEN1111 1001b
Broadcast1111 1X11B,
Slave C:SADDR=1111 0011b
SADEN1111 1101b
Broadcast1111 1111b
For slaves A and B, bit 2 is a don’ t care bit; f or slave C, bit 2 is set. To communicate with
all o f the s laves, the m as ter must send an addres s FF h. To com mu nicat e with slaves A
and B, but not slave C, the master can send and address FBh.
Reset Addresses On res et, the SADDR and SADEN registers are initialized to 00h, i. e. the given and
broadc ast addresses are XXXX XXXXb (all don’t-care bits). This ensures that the serial
port will reply to any addres s, and so, that it is backwards compatible with the 80C51
microcont rollers that do not support automatic address recog nition.
52
AT89C51RD2/ED2
4235H–8051–10/06
Registers Table 30. SA DEN Register
SADE N - Slave Address Mask Register (B9h)
Rese t Value = 0000 0000b
Not bit addressable
Table 31. SADDR Regi ster
SADDR - Slave Address Register (A9h)
Rese t Value = 0000 0000b
Not bit addressable
Baud Rate Selection for
UART for Mode 1 and 3 The Baud Rate Generator for t ransmit and receive clocks can be selected separatel y v ia
the T2CON and BDRC ON registers.
Fi gure 2 5 . Baud Rate Selec tion
76543210
76543210
RCLK
/ 16
RBCK
INT_BRG
0
1
TIMER1
0
1
0
1
TIMER2
INT_BRG
TIMER1
TIMER2
TIMER_BRG_RX
Rx Clo ck
/ 1 6
0
1
TIMER_BRG_TX
Tx Clock
TBCK
TCLK
53
AT89C51RD2/ED2
4235H–8051–10/06
Table 32. Ba ud Rate Selection Table UART
Internal Baud Rate Generato r
(BRG) When t he i nternal Baud Rate Genera tor i s used, the Baud Rat es are determined by t he
BRG overflow depen ding on t he BRL re load value , the value of S PD bit (Speed Mode)
in BDRCON register and the value of the SMOD1 bit in PCON regis ter.
Figu re 26. Internal Baud Rate
• The baud rate for UART is t oken by formula:
TCLK
(T2CON) RCLK
(T2CON) TBCK
(BDRCON) RBCK
(BDRCON) Clock Source
UART Tx Cloc k Source
UART Rx
0000Timer 1Timer 1
1000Timer 2Timer 1
0100Timer 1Timer 2
1100Timer 2Timer 2
X010INT_BRGTimer 1
X110INT_BRGTimer 2
0 X 0 1 Timer 1 INT_BRG
1 X 0 1 Timer 2 INT_BRG
X X 1 1 INT_BRG INT_BRG
0
1
Overflow
SPD
BDRCON.1
BRG
(8 bits)
BRL
(8 bits)
FClk Perip h ÷ 6
BRR
BDRCON.4
0
1
SMOD1
PCON.7
÷ 2 INT_BR
G
Baud_Rate = 6(1-SPD) ⋅ 32 ⋅ (256 -BRL)
2SMOD1 ⋅ FPER
BRL = 256 - 6(1-SPD) ⋅ 32 ⋅ Baud_Rate
2SMOD1 ⋅ FPER
54
AT89C51RD2/ED2
4235H–8051–10/06
Table 33. SCO N Regist er
SCON - Serial Control Regist er (98h)
Rese t Value = 0000 0000b
Bit addressable
76543210
FE/SM0 SM1 SM2 REN TB8 RB8 TI RI
Bit
Number Bit
Mnemonic Description
7
FE
Framing Error bit (SMOD0=1)
Cl ear to reset the error state, not cleared by a v alid stop bit.
Set by ha rdware when an invalid stop bit is dete cted.
SMOD0 must be set to enable access to the FE bit.
SM0 Seri al port Mo de bit 0
Refer to SM1 for serial po rt mode selection.
SMO D0 must be cleared to enable access to the SM0 bit.
6SM1
Seri al port Mode bit 1
SM0 SM1 Mode Baud Rate
0 0 Shift R egist er FXTAL/12 (or FXTAL /6 in mod e X2)
0 1 8-bit UART Variable
1 0 9-bit UARTF
XTAL/64 or FXTAL/32
1 1 9-bit UART Variable
5SM2
Seri al port Mo de 2 bit / M ul tiprocess or Co mmunicatio n Enab le bit
Clear to disable multiproc essor co m m unication feature.
Se t to en ab le mult ipr oces so r commu nica ti o n feat ure in mo de 2 and 3, and
ev entually mode 1.Th is bit s hould be cleare d in mode 0.
4REN
Reception En a ble bit
Clear to disable serial reception.
Set to enable serial reception.
3TB8
Transmitter Bit 8 / Ninth bit to transmit in modes 2 and 3
Clear to transmit a logic 0 in the 9th bit.
Set to tr ansmit a logic 1 in the 9th bit.
2RB8
Recei ver Bit 8 / Ninth bit rec eived in modes 2 and 3
Cleared by hardware if 9th bit received is a logic 0.
Set by ha rdware if 9th bit received is a logi c 1.
In mode 1, if SM2 = 0, RB8 is the received stop bit. In mode 0 RB8 is not
used.
1TI
Tra nsm it Inte r rup t flag
Clear to acknowledge interrupt.
Se t by har d ware at the en d o f th e 8 th bi t time i n mo de 0 o r at t he begi n ning
of the stop bit in the o ther mo des.
0RI
Recei ve Interrupt flag
Clear to acknowledge interrupt.
Set by hardware at th e end of t he 8th bi t time in m ode 0, s ee Figure 23.
and Figu re 24. in the other mod es.
55
AT89C51RD2/ED2
4235H–8051–10/06
Table 34. Example of Computed Val ue When X2=1, SMOD1=1, SPD=1
Table 35. Example of Computed Val ue When X2=0, SMOD1=0, SPD=0
The b aud rate g enerator can be u sed for m ode 1 or 3 (ref er to Figure 25 .), but also fo r
mode 0 for UART, thanks to the bit SRC located in BDRCON register (Table 42.)
UART Registers Table 36. SADEN Register
SADE N - Slave Address Mask Register for UA RT (B9h)
Rese t Value = 0000 0000b
Table 37. SADDR Regi ster
SADDR - Slave Address Register for UART (A9h)
Rese t Value = 0000 0000b
Baud Rates FOSC = 16. 384 MHz FOSC = 24MHz
BRL Error (%) BRL Error (%)
115200 247 1.23 243 0.16
57600 238 1.23 230 0.16
38400 229 1.23 217 0.16
28800 220 1.23 204 0.16
19200 203 0.63 178 0.16
9600 149 0.31 100 0.16
4800 43 1.23 - -
Baud Rates FOSC = 16. 384 MHz FOSC = 24MHz
BRL Error (%) BRL Error (%)
4800 247 1.23 243 0.16
2400 238 1.23 230 0.16
1200 220 1.23 202 3.55
600 185 0.16 152 0.16
76543210
76543210
56
AT89C51RD2/ED2
4235H–8051–10/06
Table 38. SBUF Regist er
SBUF - Serial B uff er Register for UART (99h)
Reset Value = XXXX XXXXb
Table 39. BRL Re gister
BRL - Baud Rate Reload Register for the i nte rnal baud rate generator, UART (9Ah)
Rese t Value = 0000 0000b
76543210
76543210
57
AT89C51RD2/ED2
4235H–8051–10/06
Table 40. T2CON Regist er
T2CON - Timer 2 Control Register ( C8h)
Rese t Value = 0000 0000b
Bit addressable
76543210
TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2# CP/RL2#
Bit
Number Bit
Mnemonic Description
7TF2
Timer 2 ove rf low Fla g
Must be cleared by software.
Set by hardware on timer 2 overflow, if RCLK = 0 and TCLK = 0.
6EXF2
Timer 2 External Flag
Set when a cap tu re or a r el oad is cau sed by a ne ga tive tra nsi tio n on T2EX pin if
EXEN2=1.
When set, causes the CPU to vector to timer 2 interrupt routine when tim er 2
interrupt is enabled.
Must be cleared by software. EXF2 doesn’t cause an interrupt in Up/down
counter m ode (DCEN = 1)
5RCLK
Receive Clock bit for UART
Cleared to use timer 1 overflow as receive clock for serial port in mode 1 or 3.
Set to use timer 2 overflow as receive clock for serial port in mode 1 or 3.
4TCLK
Transmit Clock bit for UART
Cle ared to use timer 1 overflow as transm it clock for serial por t i n mode 1 or 3.
Set to use timer 2 overflow as transmit clock for serial port in mode 1 or 3.
3EXEN2
Timer 2 External Enable bit
Cleared to ignore events on T2EX pin for timer 2 operation.
Set to cause a capture or reload when a negative transition on T2EX pin is
detected, if timer 2 is not used to clock the serial port.
2TR2
Timer 2 Run control bit
Cleared to turn off timer 2.
Set to turn on timer 2.
1C/T2#
Timer/Counter 2 select bit
Cle are d for time r op era tio n ( inpu t fr om i ntern al clo ck syst em : FCL K P ERI PH).
Set for counter op erat ion (input from T2 input pin, falli ng edge trigger). Mu st be
0 for clock out mode.
0CP/RL2#
Timer 2 Capture/Reload bit
If RCLK=1 or TCLK=1, CP/RL2# is ignored and timer is forced to auto-reload on
t im er 2 ov erf l ow.
Cle are d to a uto- re lo ad on time r 2 ov erf lo ws or negat i ve tr ansi ti ons on T2E X pin
if EXEN2=1.
Set to capture on negative transitions on T2EX pin if EXEN2=1.
58
AT89C51RD2/ED2
4235H–8051–10/06
Table 41. PCO N Regist er
PCO N - Power Control Register (87h)
Rese t Value = 00X1 0000b
Not bit addressable
Power-off flag reset value will be 1 only after a power on (cold reset). A warm reset
doesn’t affect the value of this bit.
76543210
SMOD1 SMOD0 - POF GF1 GF0 PD IDL
Bit
Number Bit
Mnemonic Description
7SMOD1
Serial port Mode bit 1 for UART
Set to select double baud rate in mode 1, 2 or 3.
6SMOD0
Serial port Mode bit 0 for UART
Cleared to select SM0 bit in SCON register .
Set to se lect FE bi t in SCON re gi ster.
5-
Reserved
The va lu e read fro m thi s bi t is in de ter mi nate . Do no t se t thi s bi t.
4POF
Power-Off Flag
Cleared to recognize next reset type.
Set by h ardwar e when VCC rises f rom 0 to its nominal voltage. Can also be set
by software.
3GF1
Ge ne ral purpose Flag
Cle are d b y u ser f o r gen era l p urp os e u sag e.
Set by us er f or g en eral p urpo se us age.
2GF0
Ge ne ral purpose Flag
Cle are d b y u ser f o r gen era l p urp os e u sag e.
Set by us er f or g en eral p urpo se us age.
1PD
Power-Down mode bit
Cleared by hardware when reset occurs.
Set to enter power-down mode.
0IDL
Idle mode bit
Cleared by hardware when interrupt or res et occurs.
Set to enter idle mode.
59
AT89C51RD2/ED2
4235H–8051–10/06
Table 42. BDR C ON Register
BDRCO N - Baud Rate Control Register (9Bh)
Rese t Value = XXX0 0000b
Not bit addressable
76543210
- - - BRR TBCK RBCK SPD SRC
Bit
Number Bit
Mnemonic Description
7-
Reserved
The value r ead from this bit is indeterminat e. Do not set this bit
6-
Reserved
The value r ead from this bit is indeterminat e. Do not set this bit
5-
Reserved
The va lu e read fro m thi s bi t is in de ter mi nate . Do no t se t thi s bi t.
4BRR
Baud Rate Run Control bit
Cleared to stop the internal Baud Rate Generator .
Set to start the internal Baud Rate Generator .
3TBCK
Transmission Baud rate Generator Selection bit for UART
Cleared to select Timer 1 or T imer 2 for the Baud Rate Generator.
Set to select internal Baud Rate Generator.
2RBCK
Reception Baud Rate Generator Selection bit fo r UART
Cleared to select Timer 1 or T imer 2 for the Baud Rate Generator.
Set to select internal Baud Rate Generator.
1 SPD Baud Rate Speed Control bit for UART
Cle ared to select the SLOW Baud Rate Generator.
Set to select the F AST Baud Rate Generator.
0SRC
Baud Rate Source select bit in Mode 0 fo r UART
Cleared to select FOSC/12 as the Baud Rate Generator (FCLK PERIP H/6 in X2
mode).
Set to select the internal Baud Rate Generator for UARTs in mode 0.
60
AT89C51RD2/ED2
4235H–8051–10/06
Keyboard Interface T he AT89C51RD2/ED2 implements a keyboard interface allowing the connect ion of a
8 x n matrix ke yboard. It is based on 8 i nputs with p rogrammable interrupt capability on
both high or low level. These inputs are avail able as alternate f unction of P1 and allow to
exit from idle and power-down mode s.
The keybo ard inte rfaces wi th the C 51 co re thro ugh 3 sp ecial fun ction regist ers: KBLS ,
the Keybo ard Level Selection register (Table 45), KBE, the Keyboard interrupt Enable
register (Table 44), and KBF, the Keyboard Flag register (Table 43).
Interrupt The keyboard inputs are considered as 8 independent interrupt sources sharing the
sa me int errupt v ector. An i nterru pt ena ble bit ( KBD in IE1 ) allow s g lobal enabl e or d is-
able of the ke yboa rd interru pt (see F igure 2 7). As det ailed i n Figu re 28 each ke yboa rd
inpu t has the capability to de tect a p rogramm able lev el accordin g to KBL S. x bit value.
Leve l detection is then reported in interru pt flags KBF.x that can be masked by softw are
using KBE. x bits.
This structure allow keyboard arrangement from 1 by n to 8 by n matrix and allows
usag e of P1 inputs for other purpose.
Fi gure 2 7 . Keyboard Interface Bloc k Diagram
Fi gure 2 8 . Keyboard Input Circuitry
Power Reduct ion Mode P1 inputs allow exit from idle and power-down modes as detailed in Section “Power
Management”, page 82.
P
1:x
KBE.x
KBF.x
KBLS.x
0
1
Vcc
Internal Pullup
P1.0
Keyboard Interfac
e
Interrupt Request
KBD
IE1
Inp ut Circuitry
P1.1 I np ut Circuitry
P1.2 I np ut Circuitry
P1.3 I np ut Circuitry
P1.4 I np ut Circuitry
P1.5 I np ut Circuitry
P1.6 I np ut Circuitry
P1.7 I np ut Circuitry
KBDIT
61
AT89C51RD2/ED2
4235H–8051–10/06
Registers Table 43. KBF Register
KBF-Keyboard Flag Register (9Eh)
Rese t Va lue = 0000 0000b
This register is read only access, all fl ags are automatically cleared by reading the
register.
76543210
KBF7 KBF6 KBF5 KBF4 KBF3 KBF2 KBF1 KBF0
Bit
Number Bit
Mnemonic Description
7KBF7
Keyboard line 7 flag
Set by h ardwa r e whe n the Port li ne 7 det e cts a pr og ramm ed l ev el. I t gene r ate s a
Keyboard interrupt req uest if the KBKBIE.7 bit in KBIE register is set.
Mu st be cle ared by softwar e.
6KBF6
Keyboard line 6 flag
Set by h ardwa r e whe n the Port li ne 6 det e cts a pr og ramm ed l ev el. I t gene r ate s a
Keyboard interrupt request if the KBIE.6 bit in KBIE register is s et.
Mu st be cle ared by softwar e.
5KBF5
Keyboard line 5 flag
Set by h ardwa r e whe n the Port li ne 5 det e cts a pr og ramm ed l ev el. I t gene r ate s a
Keyboard interrupt request if the KBIE.5 bit in KBIE register is s et.
Mu st be cle ared by softwar e.
4KBF4
Keyboard line 4 flag
Set by h ardwa r e whe n the Port li ne 4 det e cts a pr og ramm ed l ev el. I t gene r ate s a
Keyboard interrupt request if the KBIE.4 bit in KBIE register is s et.
Mu st be cle ared by softwar e.
3KBF3
Keyboard line 3 flag
Set by h ardwa r e whe n the Port li ne 3 det e cts a pr og ramm ed l ev el. I t gene r ate s a
Keyboard interrupt request if the KBIE.3 bit in KBIE register is s et.
Mu st be cle ared by softwar e.
2KBF2
Keyboard line 2 flag
Set by h ardwa r e whe n the Port li ne 2 det e cts a pr og ramm ed l ev el. I t gene r ate s a
Keyboard interrupt request if the KBIE.2 bit in KBIE register is s et.
Mu st be cle ared by softwar e.
1KBF1
Keyboard line 1 flag
Set by h ardwa r e whe n the Port li ne 1 det e cts a pr og ramm ed l ev el. I t gene r ate s a
Keyboard interrupt request if the KBIE.1 bit in KBIE register is s et.
Mu st be cle ared by softwar e.
0KBF0
Keyboard line 0 flag
Set by h ardwa r e whe n the Port li ne 0 det e cts a pr og ramm ed l ev el. I t gene r ate s a
Keyboard interrupt request if the KBIE.0 bit in KBIE register is s et.
Mu st be cle ared by softwar e.
62
AT89C51RD2/ED2
4235H–8051–10/06
Table 44. KBE Regist er
KBE- Keyboard Input Enable Register (9Dh)
Rese t Va lue = 0000 0000b
76543210
KBE7 KBE6 KBE5 KBE4 KBE3 KBE2 KBE1 KBE0
Bit
Number Bit
Mnemonic Description
7 KBE7 Keyboard line 7 Enable bit
Cleared to enable standard I/O pin.
Set to enable KBF.7 bit in KBF register to generate an interrupt request.
6 KBE6 Keyboard line 6 Enable bit
Cleared to enable standard I/O pin.
Set to enable KBF.6 bit in KBF register to generate an interrupt request.
5 KBE5 Keyboard line 5 Enable bit
Cleared to enable standard I/O pin.
Set to enable KBF.5 bit in KBF register to generate an interrupt request.
4 KBE4 Keyboard line 4 Enable bit
Cleared to enable standard I/O pin.
Set to enable KBF.4 bit in KBF register to generate an interrupt request.
3 KBE3 Keyboard line 3 Enable bit
Cleared to enable standard I/O pin.
Set to enable KBF.3 bit in KBF register to generate an interrupt request.
2 KBE2 Keyboard line 2 Enable bit
Cleared to enable standard I/O pin.
Set to enable KBF.2 bit in KBF register to generate an interrupt request.
1 KBE1 Keyboard line 1 Enable bit
Cleared to enable standard I/O pin.
Set to enable KBF.1 bit in KBF register to generate an interrupt request.
0 KBE0 Keyboard line 0 Enable bit
Cleared to enable standard I/O pin.
Set to enable KBF.0 bit in KBF register to generate an interrupt request.
63
AT89C51RD2/ED2
4235H–8051–10/06
Table 45. KBLS Register
KBLS -Keyboard Level Selector Register (9Ch)
Rese t Va lue = 0000 0000b
76543210
KBLS7 KBLS6 KBLS5 KBLS4 KBLS3 KBLS2 KBLS1 KBLS0
Bit
Number Bit
Mnemonic Description
7KBLS7
Keyboard line 7 Level Selection bit
Cleared to enable a lo w leve l detection on P ort line 7.
Set to enable a high le vel detection on Port line 7.
6KBLS6
Keyboard line 6 Level Selection bit
Cleared to enable a lo w leve l detection on P ort line 6.
Set to enable a high le vel detection on Port line 6.
5KBLS5
Keyboard line 5 Level Selection bit
Cleared to enable a lo w leve l detection on P ort line 5.
Set to enable a high le vel detection on Port line 5.
4KBLS4
Keyboard line 4 Level Selection bit
Cleared to enable a lo w leve l detection on P ort line 4.
Set to enable a high le vel detection on Port line 4.
3KBLS3
Keyboard line 3 Level Selection bit
Cleared to enable a lo w leve l detection on P ort line 3.
Set to enable a high le vel detection on Port line 3.
2KBLS2
Keyboard line 2 Level Selection bit
Cleared to enable a lo w leve l detection on P ort line 2.
Set to enable a high le vel detection on Port line 2.
1KBLS1
Keyboard line 1 Level Selection bit
Cleared to enable a lo w leve l detection on P ort line 1.
Set to enable a high le vel detection on Port line 1.
0KBLS0
Keyboard line 0 Level Selection bit
Cleared to enable a lo w leve l detection on P ort line 0.
Set to enable a high le vel detection on Port line 0.
64
AT89C51RD2/ED2
4235H–8051–10/06
Serial Port Interface
(SPI) The Serial Peripheral Interface Module (SPI) allows full-duplex, synchronous, serial
comm unication bet ween the MCU and peripheral devices, including other MCUs.
Features Features of the SPI Module include the following:
• Full-duplex, three-wir e synchronous transfers
• Master or Slave operation
• Eight programmable Mast er clock rates
• Serial clock with program mable polarity and phase
• Master Mode fault error flag with MCU i nterrupt capability
• Write co llis ion flag p r ot e c ti o n
Signal Description Fig ure 29 shows a typic al SPI bus con figura tion using o ne Mast er contro ller and m any
Slave peripherals. The bus is made of three wires connecting all the devices.
Fi gure 2 9 . SPI Master/S laves Interconnection
The Mast er de vi ce se lects the ind ivid ual S lave dev ices by usin g fo ur pin s of a paral lel
port to control the four SS pins of the Slave devices.
Master Output Slave Inp ut
(MOSI) Thi s 1-bit s igna l is direct ly conne cted b etwe en the Mast er Devi ce an d a Slave Devi ce.
The MOSI line is us ed to transfer data in series from the Mast er to the Slave. Therefore,
it is an output signal from the Ma ster, and an input s ignal to a Slave. A Byte (8-bit word)
is transmitted most significant bit (MSB) first, least significant bit (LS B ) last.
Master Inpu t Slave Output
(MISO) Thi s 1-bit sig nal i s direct ly conne cted b etwe en the Slave De vice and a M aste r Device.
The MISO line is us ed to transfer data in series from the Slave to the Master. Therefore,
it is an out put signal from the Slave, and an input signal to the Master. A Byte (8-bit
word) is transmitted most significant bit (M S B) first, least significant bit (LSB) last.
SPI Serial Clock (SCK) This signal is used to synchronize the data movem ent both in and out of the devices
through their MOSI and MISO lines. It is driven by the Master for eight clock cycles
which allows to exchange one Byte on the serial lines.
Slave Select (SS)Each Slave peripheral is selected by one Slave Select pin (SS). T his si gnal mus t st ay
low for any message f or a Slave. It is obvious t hat only one M aster (SS high level) can
Slave 1
MISO
MOSI
SCK
SS
MISO
MOSI
SCK
SS
PORT
0
1
2
3
Slave 3
MISO
MOSI
SCK
SS
Slave 4
MISO
MOSI
SCK
SS
Slave 2
MISO
MOSI
SCK
SS
VDD
Master
65
AT89C51RD2/ED2
4235H–8051–10/06
drive the network. The Master may select each Slave device by softw are through port
pins (Figure 30). To prevent bus conflicts on the MISO line, only one s lave should be
select ed at a time by the Master for a transmission.
In a M aster confi guration, t he S S l ine can be us ed i n conj unc tion wi th the M ODF f lag in
the SPI Status register (SPSTA) to prev ent multiple masters from driving MOSI and
SCK (see Error conditions).
A high level on the SS pin puts the MISO line of a Slave SPI in a hi gh-impedanc e state.
The SS pin could be used as a general-purpose if the following cond itions are met:
• The device is configured as a Master and the SSDIS control bit in SPCON is set.
This kind of configuration can be found when only one Master is driving the net work
and there is no way that the SS pin could be pull ed l ow . Therefore, the MODF flag in
the SPSTA will never be set(1).
• The Device is conf i gured as a Slave with CPHA and SSDIS control bit s set(2). This
kind of configuration can happen when the system comprises one Master and one
Slave only. Therefore, the device should always be selected and there is no reason
that the Master uses the S S pin to select the communicat ing Slave device.
Note: 1. Clear ing SSDIS cont rol bit does not clear M OD F.
2. Special care should be taken not to set SSDIS cont rol bit when CPHA = ’0’ because
in this mode, the SS is used to st ar t t he transm ission.
Baud Rate In Mast er mode, the baud rate can be selected from a baud rate generator which is con-
trolled by three bits in the SPCON registe r: SPR2, SPR1 and SPR0.The Master clock is
select ed from one of seven clock rates resulting from the division of the internal clock by
2, 4, 8, 16, 32, 64 or 128.
Table 46 gives the different clock rates selected by SPR2:SPR1: S PR0.
Table 46. SPI Master Baud Rate S election
SPR2 SPR1 SPR0 Clock Rate Baud Rate Divisor (BD)
000 F
CLK PERIPH /2 2
001 F
CLK PERIPH /4 4
010 F
CLK PERIPH/8 8
011 F
CLK PERIPH /16 16
100 F
CLK PERIPH /32 32
101 F
CLK PERIPH /64 64
110 F
CL K PERIP H /128 128
1 1 1 Don’t Use No BR G
66
AT89C51RD2/ED2
4235H–8051–10/06
Functional Description Figure 30 shows a detailed structure of the SPI Module.
Fi gure 3 0 . SPI Module B lock Diagram
Operati ng Mod es The Serial Peripheral I nterface can be configured in one of the two modes: Master mode
or Slave m ode . Th e co nfigur atio n and initia liza tion of the S PI M odul e is m ade thro ug h
one register:
• The Serial Peripheral Control register (SPCON )
Onc e the SPI is configured, the data exchange is made using:
•SPCON
• The S erial Peripheral STAtus register (SPSTA)
• The S erial Peripheral DATa register (SPDAT )
During an S PI trans mis sion, data is simul taneous ly transmitte d (shifted ou t serially) and
received (shifted in serially). A serial clock line (SCK) synchronizes shifting and sam-
pling on the two serial data lines (MOSI and MISO). A Slave Select line (SS) allows
individual selection of a Slave SPI dev ice; Slav e devices that are not selected do not
interfere with SPI bus activ i ties.
W hen the Mast er device transm its data to the Slave device via the MOS I line, the Slave
device responds by sending data to the Master device via the MISO line. This implies
full-duplex transmission wi th both data out and data in synchronized with the same clock
(Figure 31).
Shift Re gi s te r01
234567
Internal Bus
Pin
Control
Logic MISO
MOSI
SCK
M
S
Clock
Logic
Clock
Divider
Clock
Select
/4
/64
/128
SPI Interrupt Requ est
8-bit bus
1-bit signa
l
SS
FCLK PERIP H
/32
/8
/16 Receive Data Register
SPDAT
SPI
Control
SPSTA
CPHA SPR0SPR1CPOLMSTRSSDISSPEN
SPR2 SPCON
WCOL MODFSPIF -----
67
AT89C51RD2/ED2
4235H–8051–10/06
Fi gure 3 1 . Full-Dupl ex Master-Slave Interconnection
Ma st er Mo de The SPI operates in Master mode when the Master bit, MSTR (1), in the SPCO N register
is set. Only one Master SPI device can initiate transmissions. Software begins the trans-
mission from a Master SPI M odule by writing to the Serial Peripheral Data Register
(SPD AT). If the shift re gister is e mpty, th e Byte is imme diately transferred to the sh ift
regist er. The Byte begi ns shifting out on M OSI pin u nder the con trol of the seri al clock,
SC K. S imultan eou sly, a noth er Byte shifts i n fro m the S lave on th e Mas ter’s MISO pin.
The transm iss ion end s when t he Serial Perip heral transfe r data fla g, SPIF, in SPSTA
becomes set. At the same time that S PIF becomes set, the received Byte from the Slave
is t ran sfe rred t o th e recei ve data re giste r in S P DAT. Soft war e c lear s SP IF by r eadi ng
the Serial P eripheral Status register (SPSTA) with the SPIF bit set, and then reading the
SPDAT.
Slave Mod e The SPI operates in Slave mode when the Master bit, MSTR (2 ) , in th e S PCON register is
cleare d. Before a data transmission occurs, the Slave Select p in, SS, of the Slave
device must be set to ’0’ . SS must remain low until the t rans m ission is complete.
In a Sl ave SPI Mod ule, da ta enters t he shift regis ter under the c ontrol of the SCK from
the Master SPI Module. After a Byte enters the shift register, it is immediately trans-
ferred to the receive data register in SPDAT, and the SPIF bit is set. To prevent an
overflow condition, Slave software must then read the SPDAT before another Byte
enters the shift register (3). A Slave SPI must complete the wri te to the SPDAT (shift reg-
ister) at least one bus cycle before the Master SPI starts a transmission. If the write to
the da ta register is late, the SPI t ransmits the dat a already in the shif t regist er f rom the
previous transmission. The maximum SCK f requency allowed in slave mode is FCLK PERIPH
/4.
Transm issio n Form ats So ftwa re c an sel ec t a ny of f our c omb inat ion s of se rial clock ( SCK ) ph ase and p olar ity
using two bits in the SPCON: the Clock Polarity (CPOL (4)) and the Clock Phase
(CPHA4). CPOL defines the de fault SCK line level in idle state. It has no significant
effect on the tran smissio n format. CPHA defines the edges on which the input data are
sample d an d t he edges on which the output data are shifted (Figure 32 and Figure 33).
The clock phase and polarity should be identical for the Master SPI device and the com-
munic ating Slave device.
8- bit Shi ft register
SPI
Clock Ge nerator
Master MCU
8- bit Shi ft register
MISOMISO
MOSI MOSI
SCK SCK
VSS
VDD SSSS Slave MCU
1. The SPI Module should be config ured as a Master befor e it is enabled (SPEN set). Also ,
the Maste r SPI should be configured before the Slave SPI.
2. The SPI Module should be con figured as a Slave b efo re it is enabl ed (SPEN set ).
3. The maximum frequency of the SCK for an SPI configured as a Slave is the bus clock
speed.
4. Before writing to the CPOL and CPHA bits, the SPI should be disabled ( SPEN = ’0’).
68
AT89C51RD2/ED2
4235H–8051–10/06
Figu re 32. Data Transmission Form at (CPHA = 0)
Figu re 33. Data Transmission Form at (CPHA = 1)
Figu re 34. CPHA/SS Timing
As shown in Figure 32, the first SC K edge is the MSB capture strobe. Therefore, the
Slave must begin driving its data before the first SCK edge, and a falling edge on the SS
pin is used to start the transmission. The SS pin must be toggled high and then low
between each Byte transmit ted (Figure 34).
Figure 33 shows an SPI transmission in which CPHA is ’1’. In this case, the Master
begins driving its M OSI pin on the first SC K edge. Therefore, the Slav e uses the first
SCK edge as a start transmis sion signal. The SS pin can remain low bet ween transmis-
sions (Figure 34). Thi s format m ay be pref erred i n system s hav ing only on e M as ter and
only one Slave driving the MISO data line.
MSB bit6 bit5 bit4 bit3 bit2 bit1 LSB
bit6 bit5 bit4 bit3 bit2 bit1MSB LSB
132 45678
Capture Point
SS (to Slave)
MISO (from Slave)
MOS I (from Master)
SCK (CPOL = 1)
SCK (CPOL = 0)
SPEN (Internal)
SCK Cycle Nu mber
MSB bit6 bit5 bit4 bit3 bit2 bit1 LSB
bit6 bit5 bit4 bit3 bit2 bit1
MSB LSB
132 45678
Capture Point
SS (to Slave)
MISO (from Sl ave)
MOSI (from Master)
SCK (CPOL = 1)
SCK (CPOL = 0)
SPEN (Internal)
SCK Cycle Nu mber
Byte 1 Byte 2 Byte 3
MISO/MOSI
Master SS
Slave SS
(CPHA = 1)
Slave SS
(CPHA = 0)
69
AT89C51RD2/ED2
4235H–8051–10/06
Error Conditions The following flags in the SPSTA signal SPI error conditions:
Mode Fault (MODF) Mo de Fa ult e rror in Ma ster m ode SP I indi cate s that t he le vel on the Sl ave S elect (S S)
pin is i nconsistent wi th the a ctual mode of the device. MO DF is set to warn th at there
may be a multi-master conflict for system control. In this case, the SPI system is
affected in the following ways:
• An SPI receiver/error CPU i nterrupt request is generated
• The SPEN bit in SPCON is cleared. This disables the SPI
• The MSTR bit in SPCON is cleared
When SS Disable (SSDIS ) bit in the SPCON register is cleared, the MODF flag is set
when the SS signal become s ’0’.
However, as stated before, for a s ystem with one Master, if t he S S pin of the Master
dev ice is pulle d low, there is no way that another M aster attempts to drive the netwo rk.
In this case, to prevent the MO DF flag from bei ng set, software can set the S SD IS bit in
the SPCON register and therefore making the SS pin as a general-purpose I/O pin.
Clearing the M ODF bit is accom plished b y a read of SPSTA regi s ter with MODF bit s et,
followed by a write to the SPCON register. SPEN Control bit may be restored to i ts orig-
inal set state after the MODF bit has been cleared.
Writ e C ollis ion (W C OL ) A Write Collision (WCOL) flag in t he SPSTA is set when a write to the SPDAT register is
done during a transm it sequenc e.
W COL does not cause an interruption, and the transfer continues uninterrupte d.
Clearing the WCOL bit is done through a softwar e sequence of an access to SPSTA
and an access to SPDAT.
Overrun Condition A n ove rrun conditio n occu rs wh en the M ast er device tries to send severa l data Bytes
and the Slave devise has not cleared the SPIF bit issuing from the previous data Byte
transmit ted. In this case, t he receiver buffer c ontains the Byte sent after the SPIF bit was
last cleared. A read of the S P DA T returns this Byte. All others Bytes are lost.
This condition is not detecte d by the SPI peripheral.
SS Error Flag (SSERR) A Synchronous Serial Slave Error occurs when SS goes high before the end of a
rec eived data in slave mode . SSERR d oes n ot cau se in i nterrupt ion, thi s bit is cleare d
by writing 0 to SPEN bit (reset of the SPI state mach ine).
Interrupts Two S PI status flags can generate a CPU interrupt requests:
Table 47. SPI Inter ru p ts
Serial Peripheral data transfer f lag, SPIF: This bit is set by hardware when a transfer
has been completed. SPIF bit generates transmitter CPU interrupt requests .
Mode Fault flag, MODF: This bit becomes set to indicate that the level on the SS is
inconsi st ent with the mode of the SPI. MODF with SSDIS reset, generates receiver/error
CPU interrupt requests. When SSDIS is set, no MODF interrupt request is generated.
Figure 35 gives a logical view of the above statements.
Flag Request
SPIF (SP data transfer) SPI Transmitter Interrupt request
MODF (Mode Fault) SPI Receiver/Error Interrupt Request (if SSDIS = ’0’)
70
AT89C51RD2/ED2
4235H–8051–10/06
Fi gure 3 5 . SPI Interrupt Requests Ge neration
Registers There are three registers in the Module that provide control, status and data storage functions. These registers
ar e de scri bes in th e followi ng parag r a phs.
Serial Peripheral Control
Register (SPCON) • The Serial Peripheral Control Register does the following:
• Selects one of the Master clock rates
• Configure the SPI Module as Master or Slave
• Selects serial clock polarity and phase
• Enables the SPI Module
• Frees the SS pin for a general-purpose
Table 48 describes this register and explains the use of each bit
Table 48. SPCON Register
SPCON - Serial Peripheral Control Register (0C3H )
SSDIS
MODF
CPU Interrupt Request
SPI Receiver/error
CPU Interrupt Request
SPI Transmitter SPI
CPU Interrupt Request
SPIF
76543210
SPR2 SPEN SSDIS MSTR CPOL CPHA SPR1 SPR0
Bit Number Bit Mnemonic Description
7 SPR2 Serial Peripheral Rate 2
Bit with SPR1 and SPR0 define the c lock rate.
6 SPEN Serial Peripheral Enable
Cleared to disable the SPI interface.
Set to en able the SPI interface.
5SSDIS
SS Disable
Cleared to enab le SS in bot h Master and Slav e modes.
Set to disa ble SS in both Master and Slave modes. In Slave m ode,
this bit has no effect if CPHA =’0’. When SSDIS is set, no MODF
interrupt request is gener ated.
4MSTR
Ser ial Per iphe ral Master
Cleared to configure the SPI as a Slave.
Set to conf igure the SPI as a Maste r.
3CPOL
Clock Polarity
Cleared to have the SCK set to ’0’ in idle state.
Set to have the SCK set to ’1’ in idle low.
2CPHA
Clock Phase
Cleared to have the dat a sampled when the SCK leaves the idle
state (see CPOL).
Set to h ave the data sa mple d w hen th e SC K r etur ns t o i dle s t ate ( s ee
CPOL).
71
AT89C51RD2/ED2
4235H–8051–10/06
Rese t Value = 0001 0100b
Not bit addressable
Serial Peripheral Status Register
(SPSTA) T he Se rial Peripheral Status Register contains flags to signal the following condi tions:
• Data transfer comple te
• Write co llis ion
• Inconsistent logic level on SS pin (mode fault error)
Table 49 describes the SPSTA regi ster and explains the use of every bit in the register.
Table 49. SPSTA Register
SPSTA - Serial Peripheral Status and Control register (0C4H)
1SPR1 SPR2 SPR1 SPR0 Serial Peripheral Rate
00 0F
CLK PERIPH /2
00 1 F
CLK PERIPH /4
01 0 F
CLK PERIPH /8
01 1F
CLK PERIPH /16
10 0F
CLK PERIPH /32
10 1F
CLK PERIPH /64
11 0F
CLK PERIPH /128
1 1 1 Invalid
0 SPR0
Bit Number Bit Mnemonic Description
76543210
SPIF WCOL SSERR MODF - - - -
Bit
Number Bit
Mnemonic Description
7 SPIF
Ser ial Peripheral Data Tran sfer Flag
Cleared by hardware to indicate data transfer is in progress or has been
approved by a clearing sequence.
Set by hardware to indicate that the data transfer has been comp leted.
6WCOL
Write Collision Flag
Cleared by hardware to indicat e t hat no collision has occurred or ha s been
approved by a clearing sequence.
Set by hardware to indicate that a collision has been detected.
5 SSERR Synchronous Serial Slave Error Flag
Set by hardware when SS is de-asserted before the end of a recei ved data.
Cleare d by disabling the SPI (clearing SPEN bit in SPCON).
4MODF
Mode Fault
Cleared by hardware to indicate that the SS pin is at appropriate logic level, or
has been approved by a clearing s equence.
Set by hardware to indicate that the SS pin i s at inappropr iate l ogic level.
3-
Reserved
The value r ea d fr om this bit is ind et er m in ate. Do no t set this bi t
2-
Reserved
The value r ea d fr om this bit is ind et er m in ate. Do no t set this bi t.
72
AT89C51RD2/ED2
4235H–8051–10/06
Reset Value = 00X0 XXXXb
Not Bit addressable
Serial Peripheral DATa Register
(SPDAT) The Se rial Peripheral Data Regis ter (Table 50) is a read/wri te buffer for the receive data
register. A write to SPDAT places data di rectly into the s hift register. No transmit buffer i s
available in this model.
A Read of the SPDAT returns the value located in t he rec eive buffer and not t he content
of the shift regist e r.
Table 50. SPDAT Regi ster
SPDAT - Serial Peripheral Data Regist er (0C5H)
Reset Valu e = In de te r min ate
R7:R0: Receive data bits
SPCON, SPSTA and SPD AT registe rs may be read and written at any time while there
is no on -going ex chang e. Howeve r, spec ial care sh ould be tak en whe n writing to t hem
while a transmission is on-going:
• Do not change SPR2, SP R1 and SPR0
• Do not change CPHA and CPOL
• Do not change MSTR
• Clear ing SPEN w o uld imme dia tely disabl e the peripheral
• Writing to the SPDAT will cause an overflow.
1-
Reserved
The value r ea d fr om this bit is ind et er m in ate. Do no t set this bi t.
0-
Reserved
The value r ea d fr om this bit is ind et er m in ate. Do no t set this bi t.
Bit
Number Bit
Mnemonic Description
76543210
R7 R6 R5 R4 R3 R2 R1 R0
73
AT89C51RD2/ED2
4235H–8051–10/06
Inter r upt S yst em The AT89C 51R D2/ED2 ha s a total of 9 inter rupt ve ctors: two e xtern al interrupt s (IN T0
and I NT1), t hree timer i nterrupt s ( timers 0, 1 a nd 2) , the serial po rt interrupt, SPI inter-
rupt, K eyboard interrupt and the PCA global interrupt. These int errupts are shown in
Figure 36.
Figu re 36. Interrupt Control System
Each of the interrupt sources can be individually enabled or disabled by setting or clear-
ing a bit in t he Interrupt Enabl e register (Table 54 and Table 56). This register also
contain s a global disable bit, which must be cleared to disable all int errupt s at once.
Each interrupt source can also be individually programmed to one out of f our pri ority lev-
els by setting or clearing a bit in the Interrupt Priority register (Table 57) and in the
Interrupt Prio rity High regi ster (Table 5 5 and Tabl e 56 ) s hows t he bit v alues an d priority
levels associa ted with each combination.
IE1
0
3
High Priority
Interrupt
Interrupt
Polling
Sequence, Decreasing from
High to Low Priority
Low Priority
Interrupt
Gl obal Disable
Individu al Enable
EXF2
TF2
TI
RI
TF0
INT0
INT1
TF1
IPH, IPL
IE0
0
3
0
3
0
3
0
3
0
3
0
3
PCA IT
KBD IT
SPI IT
0
3
0
3
74
AT89C51RD2/ED2
4235H–8051–10/06
Registers The PCA interrupt vector is located at address 0033H, the SPI interrupt vector is located
at a ddress 004B H and Keyboard in terrupt vect or is located at address 003BH. All other
vectors addresses are the same as standard C52 devices .
Table 51. Priority Level Bit Values
A low -p riority interrupt can be interrupt ed by a high priority interrupt, but not by a nother
low-p riority inte rrupt. A high-pr iority interru pt can’t be i nterrup ted by any othe r inte rrupt
source.
If two interrupt requests of diffe rent priority levels are received simultaneously, the
reques t of higher priority level is s erviced. If i nterrupt re quests of the same priority level
ar e received simul taneous ly, an in terna l polling sequenc e determ ines wh ich requ est is
se rviced. Thu s within ea ch priori ty level there is a second p riority stru cture de termined
by the polling sequence.
IPH.x IPL.x Interrupt Level Priority
0 0 0 (Lowest)
011
102
1 1 3 (Highe st )
75
AT89C51RD2/ED2
4235H–8051–10/06
Interrupt Sources and
Vector Addr ess es Table 52. Interrupt Sources and Vector Addres ses
Number Polling Priority Interrupt Source Interrupt
Request Vector
Address
0 0 Reset 0000h
1 1 INT0 IE0 0003h
2 2 Timer 0 TF0 000Bh
3 3 INT1 IE1 0013h
4 4 Timer 1 IF1 001Bh
5 6 UART RI+TI 0023h
6 7 Timer 2 TF2+EXF2 002 Bh
7 5 PCA CF + CCFn (n = 0 - 4) 0033h
8 8 Keyboard KBDIT 003Bh
9 9 - - 0043h
10 10 SPI SPIIT 004Bh
76
AT89C51RD2/ED2
4235H–8051–10/06
Table 53. IENO Regi ster
IEN0 - Interrupt Enable Register (A8h)
Rese t Value = 0000 0000b
Bit addressable
76543210
EA EC ET2 ES ET1 EX1 ET0 EX0
Bit
Number Bit
Mnemonic Description
7EA
Enable All interr upt bit
Cleared to disable all interrupts.
Set to enable all interrupts.
6EC
PCA interrupt enable bit
Cleared to disable.
Set to enable.
5ET2
Timer 2 overflow interrupt Enable bit
Cleared to disable timer 2 overflow interrupt.
Set to enable timer 2 overflow interrupt.
4ES
Serial port Enable bit
Cleared to disable serial port interrupt.
Set to enable serial port interrupt.
3ET1
Timer 1 overflow interrupt Enable bit
Cleared to disable timer 1 overflow interrupt.
Set to enable timer 1 overflow interrupt.
2 EX1 Extern al inte rrup t 1 Enable bit
Cleared to disable external interrupt 1.
Set to enable external interrupt 1.
1ET0
Timer 0 overflow interrupt Enable bit
Cleared to disable timer 0 overflow interrupt.
Set to enable timer 0 overflow interrupt.
0 EX0 Extern al inte rrup t 0 Enable bit
Cleared to disable external interrupt 0.
Set to enable external interrupt 0.
77
AT89C51RD2/ED2
4235H–8051–10/06
Table 54. IPL0 Register
IPL0 - Interrupt Priority Register (B8h)
Rese t Value = X000 0000b
Bit addressable
76543210
- PPCL PT2L PSL PT1L PX1L PT0L PX0L
Bit
Number Bit
Mnemonic Description
7-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
6 PPCL PCA inte rr upt Prio ri ty bit
Refer to PPCH for priority level.
5PT2L
Timer 2 overflow interrupt Priority bit
Refer to PT2H for priority level.
4 PSL Serial port Priority bit
Refer to PSH for priori ty level.
3PT1L
Timer 1 overflow interrupt Priority bit
Refer to PT1H for priority level.
2PX1L
External interrupt 1 Priori ty bit
Refer to PX1H for priority level.
1PT0L
Timer 0 overflow interrupt Priority bit
Refer to PT0H for priority level.
0PX0L
External interrupt 0 Priori ty bit
Refer to PX0H for priority level.
78
AT89C51RD2/ED2
4235H–8051–10/06
Table 55. IPH0 Register
IPH0 - Interrupt Priority High Register (B7h)
Rese t Value = X000 0000b
Not bit addressable
76543210
- PPCH PT2H PSH PT1H PX1H PT0H PX0H
Bit
Number Bit
Mnemonic Description
7-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
6 PPCH
PCA interrupt Priority high b it.
PPCH PPCL Priority Level
00Lowest
01
10
1 1 Highest
5PT2H
Timer 2 overflow interrupt Priority High bit
PT2H PT2L Priority Level
00Lowest
01
10
1 1 Highest
4 PSH
Serial port Priority High bit
PSH PSL Priority Level
0 0 Lowest
0 1
1 0
1 1 Highest
3PT1H
Timer 1 overflow interrupt Priority High bit
PT1H PT1L Priority Level
00 Lowest
01
10
1 1 Highest
2 PX1H
External interrupt 1 Priority High bit
PX1H PX1L Priority Level
00Lowest
01
10
1 1 Highest
1PT0H
Timer 0 overflow interrupt Priority High bit
PT0H PT0L Priority Level
00Lowest
0 1
10
1 1 Highest
0 PX0H
External interrupt 0 Priority High bit
PX0H PX0L Priority Level
0 0 Lowest
01
10
1 1 Highest
79
AT89C51RD2/ED2
4235H–8051–10/06
Table 56. IEN1 Register
IEN1 - Interrupt Enable Register (B1h)
Reset Value = XXXX X000 b
Bit addressable
76543210
-----ESPI-KBD
Bit
Number Bit
Mnemonic Description
7-Reserved
6-Reserved
5-Reserved
4-Reserved
3-Reserved
2ESPI
SPI interrupt Enable bit
Cleared to disable SPI interrupt.
Set to enable SPI interrupt.
1Reserved
0 KBD Keyboard interrupt Enable bit
Cleared to dis able keyboard interrupt.
Set to enable keyboard inte rrupt.
80
AT89C51RD2/ED2
4235H–8051–10/06
Table 57. IPL1 Register
IPL1 - Interrupt Priority Register (B2h)
Reset Value = XXXX X000 b
Bit addressable
76543210
- - - - - SPIL TWIL KBDL
Bit
Number Bit
Mnemonic Description
7-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
6-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
5-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
3-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
2 SPIL SPI interrupt Priority bit
Refer to SPIH for priority level .
1-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
0 KBDL Keyboard interrupt Priority bit
Refer to KBDH for priority level.
81
AT89C51RD2/ED2
4235H–8051–10/06
Table 58. IPH1 Register
IPH1 - Interrupt Priority High Register (B3h)
Reset Value = XXXX X000 b
Not bit addressable
76543210
- - - - - SPIH - KBDH
Bit
Number Bit
Mnemonic Description
7-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
6-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
5-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
3-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
2SPIH
SPI interrupt Priority High bit
SPIH SPIL Priority Level
0 0 Lowest
0 1
1 0
1 1 Highest
1-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
0 KBDH
Keyboard interrupt Priority High bit
KB DH KBDL Priority Level
00 Lowest
0 1
10
1 1 Highest
82
AT89C51RD2/ED2
4235H–8051–10/06
Power Management
Introduction Two power reduc t ion modes are imp lement ed in the AT89C51RD2/ED2. The Idle mode
and the Power-Down mode. These m odes are detailed in the following sections. In addi-
tion to these power reduction modes, the clocks of the core and peripherals can be
dy nam ically divi ded by 2 us ing the X2 m ode deta iled in Sect ion “En ha nce d Fea tures ”,
page 17.
Idle Mode Idle mode is a power reduction mode that reduces the power consumption. In this mode,
program exec ution halts. Idle mode freezes the clock to the CPU at known states while
the peripherals continue t o be clock ed. The CPU status before entering Idle mode is
pr eserved, i .e., the p rogra m counter a nd pro gram stat us word regi ster retai n their data
for the duration of I dle m ode. The con tents of the SFRs and RAM are also retained. The
status of the Port pins during Idle mode is detailed in T able 59 .
Ente ring Idle Mode To enter Idle mode, set the IDL bit in PCON register (see Table 60). The
AT 89C51RD2/ED2 enters Idle mo de upon execution of the instruction that sets IDL bi t.
The instruction that sets IDL bit is the las t instruction execute d.
Note: If IDL bit and PD bit are set simultaneously, the AT89C51RD2/ED2 enters Power-Down
mode. Then it does not go in Idle mode when exiti ng Power -Down m ode.
Exi t ing Idle Mode There are two ways to exit Idle mode:
1. Generate an enabl ed interrupt.
– Hardware clears IDL bit in PCON regis ter which restores the clock to the
CPU. Executi on resumes with the int err upt serv ice routi ne. Upon completion
of the int errupt service routine, program execution resumes with the
instruction immediately following the instruction that activated Idle mode.
The general purpos e flags (GF1 and GF0 in P CON register) may be used to
indicate whether an interrupt occurred duri ng normal operation or during Idle
mode. When Idle m ode is exited by an interrupt, the interrupt service routine
may examine GF 1 and GF0.
2. Generate a reset.
– A logic high on the RST pin clears IDL bi t in PCON regist er directly and
asynchronousl y. This restores the clock to the CPU. Program execution
momentarily resumes with the instruction imm ediately following the
instruction that activated the Idle mode and may cont i nue for a number of
clock cycles be fore the i nternal reset algorithm takes control. Reset
initiali z es the AT89C51RD2/ED2 and vectors the CPU to addres s C:0000h.
Note: During the t ime that execution r esum es, the int ernal RAM cannot be accessed; howev er,
it is possible for the Port pins to be accessed. To avoid unexpected outputs at the Port
pins, the instruction immediately following the instr uction that activated Idle mode should
not write to a Port pin or to the extern al RAM .
Power-Down Mode The Power-Down mode places the AT89C51RD2/ED2 in a very low power state.
Power-Down mo de stop s the o scillator, freezes all clock at kno wn s tates. The CPU sta-
tus prior to ent eri ng Power-Down mode is preserved, i.e., the program counter, program
status wo rd register retain their data for the duration of Power-Down m ode. In addition,
83
AT89C51RD2/ED2
4235H–8051–10/06
the SFR and RAM contents are preserved. The status of the Port pins during Power-
Down mode is detailed in Table 59.
Note: VCC may be reduced to as low as VRET during Power-Down mode to further reduce
power dissipation. Take care, however, that VDD is not reduced until Power-Down mode
is invoked.
Ent e ring Power - D ow n Mode To enter Powe r-Down mo de, set PD bit in PCON reg ister. The AT89C51RD2/ED2
enters the Power-Down mode upon execution of the instruction t hat sets P D bit. The
instruction that sets PD bit is the last instruction executed.
Exiting Power-Down Mode Note: If VCC was reduced during the Power-Down m ode, do not exit Power- Down m ode until
VCC is restored to the nor m al ope rati ng lev el.
There are three ways to exit the Power-Down mode:
1. Generate an enabled ex ternal interrupt.
– The AT89C51RD2/ED2 provides capability to exit from Power-Down using
INT0#, INT1#.
Hardware clears PD bit in PCON register which star t s the osci llator and
restores the clocks to the CPU and peripherals. Using INTx# i nput,
execution resumes when th e input is released (see Figure 37). Execution
resumes with the interrupt service routine. Upon completion of the interrupt
service routine, program execution resumes wi th t he instructi on i mmediat ely
following the instruc tion t hat activated Power-Down mode.
Note: The exter nal interr upt used to e xi t Power -Down m ode m ust be configured as lev el sen si -
tive (INT0# and INT1#) and must be assigned the highest priority. In addition, the
duration of the inter rupt must be lo ng enough t o allow the oscillat o r to stab iliz e . Th e ex e-
cutio n will only resume when the interr upt is deasserted.
Note: Exit from power-down by ext ernal interr upt does not affect the SFRs nor the i nternal RA M
content.
Figu re 37. Power-Down Exit Waveform Using INT1:0#
2. Generate a reset.
– A logic high on the RST pin clears PD bit in PCON register di rectly and
asynchronously. This starts the oscillator and restores the clock to the CPU
and peripherals. Program execution m ome ntarily resumes with the
instruction immediately following the instruction that activated Power-Down
mode and may continue for a number of cl ock cycles before the i nternal
reset algorithm takes c ontrol. Reset initializes the AT89C51RD2/ED2 and
vectors the CPU to address 0000h.
INT1:0#
OSC
Power- down ph ase Os cill at or res t art phase Acti ve phaseAc tiv e phase
84
AT89C51RD2/ED2
4235H–8051–10/06
3. Generate an enabled ex ternal Keyboa rd interrupt (same behavio r as external
interrupt).
Note: During the t ime that execution r esum es, the int ernal RAM cannot be accessed; howev er,
it is possible for the Port pins to be accessed. To avoid unexpected outputs at the Port
pins, the instruction immediately following the instr uction that activated the Power-Down
mode should not wri te t o a Port pin or to the exter nal RAM.
Note: Exit from power-down by reset redefines all the SFRs, but does not affect the internal
RAM content.
Table 59. Pin Conditions in Spec ial Opera ting Modes
Mode Port 0 Port 1 Port 2 Port 3 Port 4 ALE PSEN#
Reset Floating High High High High High High
Idle
(internal
code) Data Data Data Data Data High High
Idle
(external
code) Floating Data Data Data Data High High
Power-
Down
(internal
code)
Data Data Data Data Data Low Low
Power-
Down
(external
code)
Floating Data Data Data Data Low Low
85
AT89C51RD2/ED2
4235H–8051–10/06
Registers Table 60. PC O N Regist er
PCON (S87:h) Power configuration Register
Rese t Value= XXXX 0000b
76543210
----GF1GF0PD IDL
Bit
Number Bit
Mnemonic Description
7-4 - Reserved
The value read from these bits i s indet erminate. D o not set these bits.
3GF1
General Purpose flag 1
One use is to i ndicate whether an i nterrupt oc curred durin g normal ope ration or
during Idle mode.
2GF0
General Purpose flag 0
One use is to i ndicate whether an i nterrupt oc curred durin g normal ope ration or
during Idle mode.
1PD
Power-Down Mode bit
Cleared by har dware w hen an int errupt or reset oc curs.
Set to activate the Power-Dow n m ode.
If IDL and PD are both set, PD takes prece den ce .
0IDL
Idle Mo de bit
Cleared by har dware w hen an int errupt or reset oc curs.
Set to activate the Idle mode.
If IDL and PD are both set, PD takes prece den ce .
86
AT89C51RD2/ED2
4235H–8051–10/06
Hardware Watchdog
Timer The WDT is intended as a recovery method in situations where the CPU may be sub-
jected t o software upset. The WDT consist s of a 14-bit counter and the Watchdog Timer
R eSeT (WD TRST) S FR. The WDT is b y defau lt disabl ed from e xiting rese t. To en able
the WDT, user m ust write 01 EH and 0 E1H in seque nce to t he WDTR ST, SFR l ocation
0A6 H. When WDT is enab led, it will increment every machine cycle wh ile t he oscillator
is running and there is no way to disable t he WDT except through reset (ei t her hardware
reset or WDT overflow reset). When WDT overflows, it will dri ve an output RESET H IGH
pulse at t he RST-pin.
Using the WDT To enable the WDT, user must write 01EH and 0E1H in sequence to the WDTRST, SFR
location 0A6H. When WDT is enabled, the user needs to service it by writing to 01EH
and 0E1H to WDTRST to avoid WDT overflow. The 14-bit counter overflows when it
reaches 16383 (3FFFH) and this will reset the device. When WDT i s enabled, it will
increm ent every machi ne cycle while the oscillator is running. This means the user must
reset the WDT at least every 16383 machine cycle. To reset the WDT the user must
write 01E H and 0E1H to WDT RST. WDT RST is a write only reg ister. Th e WDT count er
cannot be read or written. When WDT overf lows, it wil l generate an output RESET pulse
at the RST-pin. The RESET pulse duration i s 96 x T C L K PE RI PH , where TCLK PERIPH= 1/F CLK
PERIPH. To make the best use of the WDT, it should be serviced in those sections of c ode
that will periodically be executed within the tim e required to prevent a WDT reset.
To have a more powerful WDT, a 27 counter has been added to extend the Time-out
capability, ranking from 16 ms to 2s @ FOSCA = 12 MHz. To manage this f eature, refer to
WDTPRG register description, Table 61. The WD TPRG register should be configured
before the WDT activation sequence, and can not be modified until next reset.
Table 61. WDTRS T Register
WD TRST - Watchdog Res et Register (0A6h )
Reset Value = XXXX XXXXb
Write only, this SFR is used to reset/enable the WDT by writing 01EH then 0E1H in
sequence.
76543210
--------
87
AT89C51RD2/ED2
4235H–8051–10/06
Table 62. WDTPRG Register
WDTPRG - Wat chdog Timer Out Regist er (0A7h)
Reset Value = XXXX X000
WDT during Power-down
and Idle In Powe r- down mo de t he osc illato r s top s, w hich me ans the WDT al so s tops . Wh ile in
Power-do wn mo de th e user does not need to service the WDT. There are 2 m et hods of
exiting Power-down mode: by a hardware reset or via a level activated ext ernal interrupt
which is enab led prior to entering Power-down mode. When P ower-down is exited with
hardware reset, servicing the WDT should occur as it normally s hould whenever the
AT89 C51 RD2/ED 2 is reset. Exiting Pow er-down with a n interrupt is signif icantly dif fer-
ent. The interrupt is held low long enough for the oscillator to stabilize. When the
interrupt is brought high, the interrupt is serviced. To prevent the WDT from resetting the
device while the interrupt pin is held low, the WDT is not started until the interrupt is
pulled high. It is suggested that the WDT be reset during the interrupt service routine.
To ensure that the WDT does not overflow wi thin a f ew states of exiting of powerdown, it
is bett er to reset the WDT just before entering powerdown.
In the Idle m ode, the osc illator co ntinues t o run. To prevent the WD T from resetting the
AT89C51RD2/ED2 while in Idle mode, the us er should always set up a timer that will
periodical ly exit Idle, servi c e the WDT, and re-enter Idle mode.
76543210
- - - - - S2 S1 S0
Bit
Number Bit
Mnemonic Description
7-
Reserved
The value read from this bit is undetermined. Do not try to set this bit.
6-
5-
4-
3-
2S2
WDT Time-out select bit 2
1S1WDT Time-out select bit 1
0S0WDT Time-out select bit 0
S2 S1 S0 Selected Time-out
000 (2
14 - 1) machin e cycles, 16. 3 ms @ FOSCA =12 MHz
001 (2
15 - 1) machin e cycles, 32.7 ms @ FOSCA=12 MHz
010 (2
16 - 1) machin e cycles, 65. 5 ms @ FOSCA=12 MHz
011 (2
17 - 1) machine cycles, 131 ms @ FOSCA=12 MHz
100 (2
18 - 1) machine cycles, 262 ms @ FOSCA=12 MHz
101 (2
19 - 1) machine cycles, 542 ms @ FOSCA=12 MHz
110 (2
20 - 1) machine cycles, 1.05 ms @ FOSCA=12 MHz
111 (2
21 - 1) machine cycles, 2.09 ms @ FOSCA=12 MHz
88
AT89C51RD2/ED2
4235H–8051–10/06
ONCE® Mode (ON -
Chip Emula tion) The ONCE m ode facilitates testing and debugg ing of systems using AT89C51RD2/ E D2
without remo ving the circuit fr om the board. The ONCE mode is invok ed b y driving c er-
tain pins of the AT89C51RD2/ED2 ; the following sequenc e m ust be exercised:
• Pull ALE low while the device is in reset (RST high) and PSEN is high.
• Hold ALE low as RST is de ac tivated.
While the AT89C51RD2/ED2 is i n ONCE mode, an emulator or test CPU can be used to
drive the circuit. Table 63 shows the status of the port pins during ONCE mode.
Normal operation is restored when normal reset is applied.
Table 63. External Pin Status During ONCE Mode
ALE PSEN Po rt 0 Port 1 Port 2 Port 3 Port I2 XTAL A1/ 2 XTAL B1/2
Weak
pull-up Weak
pull-up Float Weak
pull-up Weak
pull-up Weak
pull-up Float Active Active
89
AT89C51RD2/ED2
4235H–8051–10/06
Powe r-off Fla g The power-off flag allows the user to distinguish between a “cold start” reset and a
“warm start” reset.
A cold s tart reset is the on e induced by VCC switch-on. A wa rm start reset occurs whil e
VCC is still applied to the device and could be generated for example by an exit from
power-down.
The power-off flag (POF) is located in PCON register (Table 64). POF is s et by hard-
ware when VCC rises fro m 0 to its nom ina l vol tag e. Th e P OF ca n be set or cl eare d by
software allowing the user to determine the t ype of reset.
Table 64. PCO N Regist er
PCO N - Power Control Register (87h)
Rese t Value = 00X1 0000b
Not bit addressable
76543210
SMOD1 SMOD0 - POF GF1 GF0 PD IDL
Bit
Number Bit
Mnemonic Description
7SMOD1
Serial port Mode bit 1
Set to select double baud rate in mode 1, 2 or 3.
6SMOD0
Serial port Mode bit 0
Cleared to select SM0 bit in SCON register .
Set to select FE bit in SCON register .
5-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4POF
Power-Off Flag
Cle are d by sof twa re t o rec og nize t he next rese t typ e.
Set by hardware when VCC rises f rom 0 t o i ts n omi na l vol t age. Can al so be set by
software.
3GF1
General-purpose Flag
Cleared by user for general-purpose usage.
Set by user for general-purpose usage.
2GF0
General-purpose Flag
Cleared by user for general-purpose usage.
Set by user for general-purpose usage.
1PD
Power-down mode bit
Cle ared by ha rdware wh en reset occur s.
Set to e nt er po wer- d own mo de .
0IDL
Idle mode bit
Cleared b y hardware when interrupt or reset occurs.
Set to enter idle mode.
90
AT89C51RD2/ED2
4235H–8051–10/06
Reduced EMI Mode The ALE signal is used to demultiplex address and data buses on port 0 when used with
external program or data memory. Nevertheless, during internal code execution, ALE
sign al is s till g enerate d. In o rder to red uce EM I, ALE sign al can be d isabl ed by s etting
AO bit.
The A O bit is located in AUXR register at bit location 0. As soon as AO is set, A LE is no
longer output but remains active during MOVX and MOVC instructions and external
fetches . During ALE disabling, ALE pin is weakly pulled high.
Table 65. AUXR Regi ster
AUXR - Auxiliary Register (8Eh)
Rese t Value = XX00 10’HSB. XRAM ’0b
Not bit addressable
76543210
DPU - M0 XRS2 XRS1 XRS0 EXTRAM AO
Bit
Number Bit
Mnemonic Description
7DPU
Disable Weak Pull-up
Cleared by software to activate the permanent weak pull-up (default)
Set by so ftware to disable the wea k pull-up ( redu ce powe r consumptio n)
6-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
5M0
Pulse len gth
Cleared to stretch MOVX control: the RD and the WR pu ls e leng th is 6 cloc k
periods (de fault).
Se t to st r e tc h M O VX c on tro l: t he RD and the WR pulse length is 30 clock periods.
4XRS2XRAM Size
XRS2 XRS1 XRS0 XRA M siz e
0 0 0 256 bytes
0 0 1 512 bytes
0 1 0 768 bytes(default)
0 1 1 1024 bytes
1 0 0 1792 bytes
3XRS1
2XRS0
1 EXTRAM
EXTRAM bit
Cleared to access internal XRAM using MOVX @ Ri/ @ DPTR.
Set t o access e xternal m emory.
Programmed by hardware after Power-up regarding Hardware Security Byte
(HSB), default settin g, XRAM selecte d.
0AO
ALE Output bit
Cl e ared , ALE is e mi tte d at a con sta nt rat e of 1/ 6 t he osci ll ato r f req ue nc y (or 1 / 3 if
X2 mode is used) (def ault) . Set, ALE i s active only during a MOVX or MOVC
instr u c tio n is use d.
91
AT89C51RD2/ED2
4235H–8051–10/06
EEPROM Data
Memory This feature is available only for the AT89C51ED2 device.
The 2K bytes on-chip EEPROM memory block is located at add re sses 0000h t o 07FFh
of the XRAM/ERAM memory space and is selected by setting control bits in t he EECON
register.
A read or write access to the EEPROM me mory is done with a MOVX instruction.
Write Data Data is written by byte to the EEPROM memory b lock as for an external R AM memory.
The following procedure is used to write to the EEPROM memory:
• Check EEBUS Y flag
• If the user application interrupts routines use XRAM m emo ry space: Save and
disable int errupts.
• Load DPTR with the address to write
• St ore A register with the data to be written
• Set bit EEE o f EEC ON re g ister
• Execute a M OVX @DPTR, A
• Clea r bit EEE o f EEC O N reg ister
• Restore interrupts.
• EEBUSY flag in EECON is t hen set by hardware to indicate that programming is in
progress and that the EEPROM segment is not available for reading or writ i ng.
• The end of programming is indicated by a hardware clear of the EEBUSY flag.
Figure 38 represents the optimal write sequence to the on-chip EEPROM da ta memor y.
92
AT89C51RD2/ED2
4235H–8051–10/06
Fi gure 3 8 . Recommended EEPROM Data Write Sequence
EEPROM Data Write
Sequence
Data Write
DPTR= Addres s
ACC= Data
Exec: MOVX @DPTR, A
Last B yte
to L oad?
EEPROM Mapping
EECON = 00h (EEE=0)
Save & Disable IT
EA= 0
Rest ore IT
EEPROM Data Mapping
EECON = 02h (EEE=1)
EEBusy
Cleared?
93
AT89C51RD2/ED2
4235H–8051–10/06
Read Data The following procedure is used to read the data stored in the EEPROM memory:
• Check EEBUS Y flag
• If the user application interrupts routines use XRAM m emo ry space: Save and
disable int errupts.
• Load DPTR with the address to read
• Set bit EEE o f EEC ON re g ister
• Execute a M OVX A, @DPTR
• Clea r bit EEE o f EEC O N reg ister
• Restore interrupts.
Fi gure 3 9 . Recommended EEPROM Data Read Sequence
EEPROM Data Read
Sequence
Data Read
DPTR= Address
ACC= Data
Exec: MOVX A, @DPTR
La s t Byte
to Read?
EEPROM Data Mapping
EECON = 02h (EEE=1)
EEPROM Data Mapping
EECON = 00h (EEE = 0
Save & Disable IT
EA= 0
Restore IT
EEBusy
Cleared?
94
AT89C51RD2/ED2
4235H–8051–10/06
Registers Table 66. E ECON Register
EECON (0D2h)
EEPROM Control Regist e r
Reset Value = XXXX XX00b
Not bit addressable
76543210
------EEEEEBUSY
Bit Number Bit
Mnemonic Description
7 - 2 - Reserved
The value r ead from this bit is indeterminat e. Do not set this bit.
1 EEE
Enable EEPROM Space bit
Set to map the EEPROM space during MOVX instructions (Write or Read to
the EEPROM.
Clear to map the XR AM space during MOVX.
0 EEBUSY
Progra mmi ng Busy flag
Set by hardware when programming is in progress.
Cleared by hardware when programming is done.
Can not be set or cleared by software.
95
AT89C51RD2/ED2
4235H–8051–10/06
Flash/EEPROM
Memory T he Flash memory increases EEPROM and RO M functionality with in-circuit electrical
erasure a nd program m ing. It conta ins 64K by tes of program m emo ry organized res pec-
tively in 512 pages of 128 bytes. T his memory is both p ara llel and serial In-System
Programmable (ISP). ISP allows d evices to alter their own program memory in the
actual end product un der software control. A defaul t serial loader (bootload er) p rogram
allows ISP of the Flash.
The program m ing doe s not require e xternal dedicat ed program m ing vol tage. The nec -
essary high programming voltage is generated on-chip using the standard VCC pins of
the microco ntroller.
Features • Flas h E EPRO M Inte rnal Pr ogra m Memor y
• Boot vector allows user provided Fl ash loader code to reside anywhere in the Flash
mem or y spa c e. Th is config ur ation pr ovides flex i b ilit y to the user.
• Default loader in Boot ROM allows programming via the serial port wit hout the need
of a user prov id ed loader.
• Up to 64K bytes external program memo ry if the internal program m em ory is
disabled (EA = 0).
• Programming and erasing voltage with standard power supply
• Read/Programming/Erase:
– Byte-wise read without wait state
– Byte or page erase and programming (10 ms)
• Typical programming time (64K bytes) is 22s with on chip serial bootloader
• Parallel programming with 87C51 compatible hardware interface to programmer
• Programmable security for the code in the Flash
• 100K write cycles
• 10 years data retention
Flash Programming and
Erasure The 64-K by te Flash is pro grammed by bytes or by pages of 128 by tes. It i s not neces-
sary to erase a by te or a page before programming. The programming of a byte or a
page includes a se lf erase before programming.
There are three methods of programming the Flash memory :
1. The on-chip ISP bootloader may be invoked whic h will us e low lev el r out ines to
program the pages. The interface used for serial downloading of Flash is the
UART.
2. The Flash may be programme d or erased in the end-user application by calling
low-level routines thro ugh a common ent ry point in the Boot ROM .
3. The Flash may be programme d using the parallel method by using a conven-
tional EPROM programm er. The parallel programming method us ed by these
devices is similar to that used by EPROM 87C51 but it is not identical and the
commercially available programm ers need to have support for the
AT89C51RD2/ED2. The bootloader and the Application Programming Interf ace
(API) routines are located in t he B OOT ROM .
96
AT89C51RD2/ED2
4235H–8051–10/06
Flash Registers and
Memory Map The AT89C51RD2/ED2 Fl ash memory uses several registers for its manag em ent:
• Hardware register can only be accessed through the parallel programming modes
which are handled by the parallel pr ogrammer.
• Software registers are in a spec ial page o f the Flash memory which can be
accessed through the API or with the parallel programming modes. This page,
called "Extra Flash Memory", is not in the internal Flas h program mem ory
addressing space.
Hardware Register T he only ha rdware regi ster of the AT89 C51R D2/ED2 is ca lled Hardware B yte or Hard-
ware Secur ity Byte (HSB) .
Table 67. H a rdw a r e Securi ty Byt e (HSB )
Boot Loader Jump Bit (BLJB)
One bit of the HSB, t he BLJB bit, is used to force the boot address:
• When this bit is programmed (‘0’ value) the boot address is F800h.
• When this bit is unprogrammed (‘1’ value) the boot address is 0000h.
By defa ult, this bit is programmed and the ISP is enabled.
Flash Memory Lock Bits Th e th ree l ock bits pro vide diff eren t lev el s of protec tio n fo r the on -chip co de an d da ta
when programm ed as sh own in Table 68.
76543210
X2 BLJB - - XRAM LB2 LB1 LB0
Bit
Number Bit
Mnemonic Description
7X2
X2 Mode
Programmed (‘0’ value) to force X2 mode (6 clocks per instruction) after reset.
Unprogrammed (‘1’ Value) to force X1 mode, Standard Mode, after reset
(Default).
6BLJB
Boot Loader Jump Bit
Unprogrammed (‘1’ value) to start the us er’s app licati on on next reset at address
0000h.
Pr ogr am med ( ‘0’ val ue) to sta rt th e boot loa der at addr ess F8 00 h on ne xt rese t
(Default).
5-
Reserved
4-Reserved
3XRAM
XRAM config bit (only programmable by programmer tools)
Programmed to inhi bit XRAM.
Unprogrammed, this bit to valid XRAM (Default).
2-0 LB2-0 User Memory Lock Bits (only programmable by programmer tools)
See Table 68
97
AT89C51RD2/ED2
4235H–8051–10/06
Table 68. Prog ram Lock Bits
Note: U: Unprogr am med or "o ne" level.
P: Programmed or "zero" lev el .
X: Do not care
WARNING: Security level 2 and 3 should only be programmed after Flash and code
verification.
These s ecurity bits prote ct the code access through the parallel progra mming interface.
They are set by default t o l ev el 4 . The code access t hrough the I SP is still po ssi ble a nd
is co ntrolled by the " software sec urity bits" whic h are stored i n the extr a Flash mem ory
accessed by the ISP firmware.
To load a new application with t he parallel program mer, a c hip erase must first be done.
Th is will s et th e H S B i n it s inactive s ta te and will er ase the F lash m e m ory . Th e par t r ef -
erence can always be read using Flash parallel programming mo des.
Default Val ues The default value of the HSB provides parts ready to be pr ogrammed with ISP:
• BLJB: Programm ed force ISP operation.
• X2: Unprogrammed to force X1 mode (Standard Mode).
• XRAM: Unprogrammed to valid XRAM
• LB2-0: Security level four to protect the code from a parallel access with maximum
security.
Software Registers S ev eral registers are used in factory and by parallel programmers . These values are
used by Atmel ISP.
These re gisters are in the "Extra Flash Mem ory" part of the Flash memory. This block is
also called "XAF" or eXtra Array Flash. They are accessed in the following ways:
• Comman ds issued by the parallel mem ory programm er.
• Comman ds issued by the ISP software.
• Calls of API issued by the application soft ware.
Several software registers are described in Table 69.
Program Lock Bits
Prote cti on Des crip tion
Security
Level LB0 LB1 LB2
1 U U U No program lock features enabled.
2PUU
M OVC ins tr uction executed fr om external program memory is di sabled
from fetching code bytes from internal memory, EA is sample d and
latched on reset, and further parall el p rogram ming of the on chip code
m em ory i s disabled.
ISP and software programming with API are still allowed.
3XPU
Same as 2, also v erify c ode mem ory th rough p aral lel pro gramming
int erfac e is disa bled .
4 X X P Same as 3, also external execution is disabled (Default).
98
AT89C51RD2/ED2
4235H–8051–10/06
Table 69. Default Values
After programming the part by ISP, the BSB must be cl eared (00h) in order to allo w the
applicat ion to boot at 0000h.
The co ntent of the Software Security Byte (SSB) is described in Table 70 and Table 71.
To ass ure code protection from a parallel access, the HS B m ust also be at t he requi red
level.
Table 70. Soft war e Se c u r ity By te
The two lock bits provide different levels of protection for the on-chip code and data,
when programm ed as sh own in Table 71.
Mnemonic Definition Default value Descripti on
SBV Soft ware Boot Vector FCh
BSB Boot Status Byte 0FFh
SSB Software Security Byte FFh
Copy of the Manufacturer Code 58h Atmel
Copy of the Device ID #1: Fami ly Code D7h C51 X2, Electric ally E rasable
Copy of the Device ID #2: Memories Size
and Type ECh AT89C51RD2/ED2 64KB
Copy of the Device ID #3: Name and
Revision EFh AT89C51RD2/ED2 64KB,
Revision 0
76543210
------LB1LB0
Bit
Number Bit
Mnemonic Description
7-
Reserved
Do not clear this bit.
6-
Reserved
Do not clear this bit.
5-
Reserved
Do not clear this bit.
4-
Reserved
Do not clear this bit.
3-
Reserved
Do not clear this bit.
2-
Reserved
Do not clear this bit.
1-0 LB1-0 User Me mory L ock Bi ts
See Table 71
99
AT89C51RD2/ED2
4235H–8051–10/06
Table 71. User Memory Lock Bits of the SSB
Note: X: Do n o t care
WARNING: Securit y lev el 2 and 3 should only be programmed after Flas h verificati on.
Flash Memory Status AT 89C51RD2 /ED2 parts are delivered in standard with the ISP ROM bootloader.
After ISP or parallel programming, the possible contents o f the Flash memory are sum -
marized in Figure 40:
Figu re 40. Flash Memory Possible Contents
Memory Organization When the EA pin is high, the processor fetches instructions from i nternal program Flash.
If the EA pin is t ied low, all program memory fetches are from external memory.
Program Lock Bits
Prote cti on Des cri ptio n
Security
Level LB0 LB1
1 1 1 No program lock features enabled.
2 0 1 ISP programming of the Flash is disabled.
3 X 0 Same as 2, also verify through ISP programming interface is disabled.
0000h
Virgin
Default A f te r ISP After Parallel
Programming Afte r Parallel
Programming Af ter Paral le l
Programming
ApplicationApplication Virgin
After ISP
or
Dedicated
ISP Dedicated
ISP
Application
Virgin
or
Application
Virgin
or
Application
FFFFh
100
AT89C51RD2/ED2
4235H–8051–10/06
Bo otl oad er Architec tur e
Introduction The bo otloader man ages com munica tion acc ording to a spec ifically defined protocol to
provide th e whole acces s and serv ice on F lash m emo ry. Furthermore, a ll access es and
routines can be called from the user application.
Figu re 41. Diagram Context Description
Acronyms ISP: In-System Progra mming
SBV: Software Bo ot Vector
BSB: Boot Sta tus Byte
SSB: Software Se curity Byte
HW: Hardware Byte
Bootloader Flash Memor
y
Access Via
Specific
Protocol
Access From
User
Application
101
AT89C51RD2/ED2
4235H–8051–10/06
Functional Descr iption F igure 42. Bootloader Functional Description
On the above diag ram, the on-chip bootloader proce sses are:
• ISP Com munication Management
The p urpose o f this p rocess is to manag e the com munic ation and its prot ocol bet ween
the on-chip bootloader and a external device. The on-chip ROM implements a serial
pr otocol (se e se ction “B ootloa der Pro tocol ”). This p roce ss transl ate s erial co mm unica-
tion frame (UART) into Flash memory access (read, write, erase , etc.).
• User Call Management
Several Applica tion Program Interface (API) calls are available for use b y an application
program to permit selective erasing and programming of Flash pages. All calls are m ade
through a com m on in terface (A P I ca lls), included in the ROM bootloader. The program -
ming f unctions are selected by sett ing up the microcont roller’s registers before making a
cal l to a co mmon en try point (0xF FF0). Resul ts are return ed in the re gisters. The pur-
pose on this process is to translate the registers values into internal Flash Memory
Management.
• Flash Memory Managem ent
This process manages low level access to Flash memory (performs read and write
access).
I SP Com munication
Management
User
Application
Specific Pro tocol
Communication
Management
Flash
Memory
External Host with
Flash Memory
User Call
Managem ent (API)
102
AT89C51RD2/ED2
4235H–8051–10/06
Bootl oade r Functionality The bootloader can be activated by two means: Hardware conditions or regular boot
process.
The Hardwa re co nditi ons ( EA = 1 , PS EN = 0) during t he Re set# fa llin g edge force th e
on-chip bootloader execution. This allows an application to be built that will normally
execute the end user’s code but can be manually forced into default ISP operation.
As PSEN is a an o utpu t port in n ormal operating mode a fter reset, user application
should take care t o release PSEN after falling edge of reset signal. The hardware condi-
tions are sampled at rese t signal falling edge, thus they can be released at any time
when reset input is low.
To ensure correct microcontroller startup, the PSEN pin should not be tied to ground
during power-on (Se e Figure 43).
Figu re 43. Hardware conditions typical sequence during power-on.
The on-chip bootload er boot process is shown Figure 44.
VCC
PSEN
RST
Table 72. Bo otloader Process Des cription
Purpose
Hardware Co nditions The Hard ware Conditions force the boot loader execution whatever
BLJB, BSB and SBV values.
BLJB
T he Boot Lo ad er Ju m p Bi t for c e s the applic atio n ex ec utio n.
BLJB = 0 => Bootloader execution
BLJB = 1 => Application exec ution
The BLJB is a fus e bit in the Hardware Byte.
It can be modified by hardware (programmer) or by software (API).
Note: The BLJB test is performed by hardware to prevent any
pr og r a m ex ec utio n.
SBV
The Software Boot Vecto r c ontai ns t he high address of cu stomer
bootloader stored in t he appli cation.
SBV = FCh (default value) if no customer bootloader in user Flash.
Not e: The c ustomer bootl oader is called by JMP [S BV]00h
instruction.
103
AT89C51RD2/ED2
4235H–8051–10/06
Boot Process
Figu re 44. Bootloader Process
RESET
Hardware
Condition?
BLJB!= 0
?
User App lic ati on
Hardware
Software
Atmel BOOT LOADERUSER BOOT LOADER
BLJB = 1
BSB = 00h
?
SBV = FCh
?
PC = 0000h
PC= [SBV]0 0h
BLJB = 0
If BLJB = 0 th en ENBOOT Bit (AUXR1) is Set
else EN BOOT Bit (AUXR1) is Cleared
ENBOOT = 1
ENBOOT = 0
Yes (PSEN = 0, EA = 1, and ALE =1 or Not Connected)
104
AT89C51RD2/ED2
4235H–8051–10/06
ISP Protocol Description
Physical Layer The UAR T used to transmit information has the following configuration:
• Character: 8-bit data
• Parity: none
• Stop: 2 bits
• Flow control: none
• Baudrate: autobaud is performed by the bootloa der to comp ute the baudrate
chosen by the host.
Frame Description The Serial Protocol is based on the Intel Hex-type records.
Intel Hex records consist of ASCII characters used to represent hexadecimal values and
are summa rized below.
Fi gure 4 5 . Intel Hex Ty pe Frame
• Record Mark:
Reco rd Mark is the start of frame. This field must contain ’:’.
• Reclen:
R ecle n s pec ifie s th e n um ber of b yte s of inf orm ati on o r da ta w h ich fo l low s th e Re cor d
Type field of t he record.
• Load Offset:
Load Offset spec ifies the 16-bi t starting load of fset of t he data b ytes, t heref ore this field
is used only for Data P rogram Rec ord (see Section “ISP Commands Su mmary ”).
• Record Type:
R ecord T yp e speci fies the co mman d type . Th is fiel d is us ed to interp ret the rema inin g
inform ation withi n the fram e. The enco ding fo r all the curren t record types is descr ibed
in Section “ISP Commands Summary”.
• Data/Info:
Data/Info i s a variabl e length f ield. It co nsists of zero or m ore by tes encoded as pairs of
hexa decim al digits. The meaning of data depends on the Record Type.
• Checksum:
The two’ s compl emen t of the 8-b it bytes that result fr om con vertin g each pa ir of AS CII
hexa decim al digits to one by te of binary, and in cluding the Reclen field to and includi ng
the last byte of the Data/Info field. Therefore, the sum of all the ASCII pairs in a record
after conv erting to binary, from the Reclen f iel d to and including the Checksum field, is
zero.
Record Record
Load Data
Mark
’:’ Reclen Offset Type or
Info Checksum
1-byte 1-byte 2-bytes 1-byte n-bytes 1-byte
105
AT89C51RD2/ED2
4235H–8051–10/06
Functional Description
Software Security Bi ts (SSB) The SSB protect s any Flash access from ISP comma nd.
The comm and "P rogram Software Security Bit" can only write a higher priority level.
There are three levels of security:
• level 0: NO_SECURITY (FFh)
This is the default level.
From level 0, one can write level 1 or l evel 2.
• level 1: WRITE_SECURITY (FEh )
For this level it is impossible to write in the Flash memory, BSB and SBV.
The Bo otloader returns ’P’ on write access.
From level 1, one can write only level 2.
• level 2: RD_WR_SECURITY (F Ch
T he lev e l 2 forbids all read and write accesses to/from the Flash/EEPROM memory.
The Bo otloader returns ’L’ on read or wri te access .
Only a full chip erase in parallel mode (using a programmer) or ISP command can reset
the software security bits.
From level 2, one cannot read and write anyt hing.
Table 73. Soft war e Se c u r ity By te Be havior
Level 0 Level 1 Level 2
Flash/EE PROM Any access allowed Read- only access allowed Any access n ot allow ed
Fuse Bit Any access al lowed Read- only access allowed Any access not allow ed
BSB & SB V Any access allowe d Read-only access allowe d Any access not allowed
SS B Any acce ss allowed Write level 2 allowed Re ad-only access a llowed
Manufacturer
Info Read-onl y access allowed Read-only access allowed Read-only access allowed
Bootloade r Info Read- only access al lowed Read-only acce ss allowed Re ad-only access allowed
Erase Block Allowed Not allowed Not allowed
Full Chip Erase Allowed Allowed Allowed
Blank Check Allowed Allowed Allowed
106
AT89C51RD2/ED2
4235H–8051–10/06
Full Chip Erase The ISP co mmand " Full Ch ip Eras e" eras es all user Fla sh memor y (fills with FF h) and
sets some by tes used by the bootloade r at their default values:
• BSB = FFh
• SBV = FCh
• SSB = FFh
The Full Chip Erase does not affect the bootloader.
Checksum E rro r When a chec ksum error is detected, send ‘X’ fol l owed with CR&LF.
Flow Description
Overview An initialization step mus t be performed after each Reset. After microcontroller res et,
the bootload er waits for an autobaud sequence (see section ‘Autobaud Performan ces’).
When the communication is initial ized, the protocol depends on the record type
request ed by the host.
FLIP , a so ftware u tility to im plemen t ISP p rogra mming with a P C, is av ailable f rom the
Atmel web si te .
Communication Initialization The host initializes th e communicat ion by sending a ’U’ character to help the boo tloader
to compu te the baudrate (autobaud).
Fi gure 4 6 . Initialization
Host
Bootloader
"U" Perf orms Autobaud
Init Communication
If (Not Received "U") "U"
Communication Opene d
Else Sends Back “U” Charac
ter
107
AT89C51RD2/ED2
4235H–8051–10/06
Autobaud Performances The ISP feature allows a wide range of baud rates in the user application. It is also
adapt able to a wide range of oscillator frequencies. This is accompl ished by measuri ng
the b it-tim e of a single bi t in a recei ved cha racter. Thi s inf ormation is th en used to pro-
gra m the baud rate in terms of timer counts based on the oscillator frequ ency. The ISP
feature requires that an initial character (an uppercase U) be sent to the
AT 89C51RD2 /ED2 to establish the baud rate. Table show the autobaud capabil ity.
Command Data Stream
Protocol A ll command s are sent using the s ame flow. Eac h frame sent by th e host is echoed by
the bootload er.
Tab le 74. Autobaud P erformanc es
Frequency (MHz)
Baudrate ( kHz) 1.84 32 2 2.4576 3 3.6864 4 5 6 7 .3728
2400 OK OK OK OK OK OK OK OK OK
4800 OK - OK OK OK OK OK OK OK
9600 OK - OK OK OK OK OK OK OK
19200 OK - OK OK OK - - OK OK
38400 - - OK OK - OK OK OK
57600 ----OK---OK
115200 --------OK
Frequency (MHz)
Baudrate ( kHz) 8 10 11.059 2 12 14.746 16 20 24 26.6
2400 OK OK OK OK OK OK OK OK OK
4800 OK OK OK OK OK OK OK OK OK
9600 OK OK OK OK OK OK OK OK OK
19200 OK OK OK OK OK OK OK OK OK
38400 - - OK OK OK OK OK OK OK
57600 - - OK - OK OK OK OK OK
115200 - - OK - OK - - - -
108
AT89C51RD2/ED2
4235H–8051–10/06
Figu re 47. Command Flow
Bootloader
":"
Sends First Character of the
Frame If (not received ":")
Sends Frame (made of 2 AS CII Get s F rame, and Sends Back Echo
for Each Received Byte
Host
Else
":" Sends Echo an d Star t
Reception
Characters Per By te)
Echo Anal ysis
109
AT89C51RD2/ED2
4235H–8051–10/06
Wr ite/Prog ram Commands
Description This flow is common to the following frames:
• Flash/EEPROM Programmi ng Data Frame
• EOF or Atmel Frame (only Programming Atmel Frame)
• Config Byte Programming Data Frame
• Baud Rate Frame
Figu re 48. Write/Program Flow
Example
Host Bootloader
Write Command
’X’ & CR & LF
NO_SECURITY
Wait Wr ite Comm an d
Checksum Error
Wait Programming
Send Security Error
Send COMMAND_OK
Send Write Command
Wait Checksum Error
Wait COMMAND_OK
Wait Security Error
OR
COMMAND ABORTED
COMMAND FINISHED
Send Checksum Error
COMMAND ABORTED
’P’ & CR & LF
OR
’.’ & CR & LF
HOST : 01 0010 00 55 9A
BOOTLOADER : 01 0010 00 55 9A . CR LF
Programming Data (write 55h at address 0010h in the Flash)
HOST : 02 0000 03 05 01 F5
BOOTLOADER : 02 0000 03 05 01 F5. CR LF
Progr amm ing Atmel func ti on (write SSB to level 2)
HOST : 03 0000 03 06 00 55 9F
BOOTLOADER : 03 0000 03 06 00 55 9F . CR LF
Writing Frame (write BSB to 55h)
110
AT89C51RD2/ED2
4235H–8051–10/06
Blank Check Command
Description
Figu re 49. Blank Check Flow
Example
Host Bootloader
Blank Check Comman d
’X’ & CR & LF
Flash Blank
Wait Blan k Check Comma nd
Send Fi rst Address
Send COMMAND_OK
Send Blank Check Command
Wait Checksum Error
Wait Address not
Erased
Wait COMMAND_OK
OR
COMMAND ABORTED
COMMAND FINISHED
Send Checksum Error
COMMAND FINISHED
’.’ & CR & LF
OR
address & CR & LF not Erased
Checksum Error
HOST : 05 0000 04 0000 7FFF 01 78
BOOTLOADER : 05 0000 04 0000 7FFF 01 78 . CR LF
Blank Check ok
BOOTLOADER : 05 0000 04 0000 7FFF 01 70 X CR LF CR LF
Blank Check with checksum error
HOST : 05 0000 04 0000 7FFF 01 70
BOOTLOADER : 05 0000 04 0000 7FFF 01 78 xxxx CR LF
Blank Check ok at address xxxx
HOST : 05 0000 04 0000 7FFF 01 78
111
AT89C51RD2/ED2
4235H–8051–10/06
Display Dat a Description
Figu re 50. Display Flow
Example
Host
Bootloader
Display Command
’X’ & CR & LF
RD_WR_SECURITY
Wait Display Comm and
Read Data
Send Security Error
Send Display Data
Send Display Command
Wait Checksum Error
Wait D is pla y Data
Wait Security Error
OR
COMMAND ABORTED
COMMAND FINISHED
Send Checksum Error
COMMAND ABORTED
’L’ & CR & LF
OR
"Address = "
All Data Read
Complet Frame
"Read ing Valu e"
CR & LF
All Data ReadAll Data Read
COMMAND FINISHED
Checksum error
HOST : 05 0000 04 0000 0020 00 D7
BOOTLOADER : 05 0000 04 0000 0020 00 D7
BOOTLOADER 0000=-- --- dat a-- -- -- CR LF (16 data)
BOOTLOADER 0010=-- --- dat a-- -- -- CR LF (16 data)
BOOTLOADER 0020=data CR LF ( 1 dat a)
Display data from address 0000h to 0020h
112
AT89C51RD2/ED2
4235H–8051–10/06
Read Function Description T his flow is similar for the following frames:
• Reading Frame
• EOF Frame/ Atmel Frame (only reading Atmel Frame)
Figu re 51. Read Flow
Example
Host Bootloader
Read Command
’X’ & CR & LF
RD_WR_SECURITY
Wait Read Command
Read Value
Send Security error
Send Data Read
Send Read Command
Wait Checksum Error
Wait Value of Data
Wait Security Error
OR
COMMAND ABORTED
COMMAND FINISHED
Send Checksum error
COMMAND ABORTED
’L’ & CR & LF
OR
’v alue’ & ’.’ & CR & LF
Checksum error
HOST : 02 0000 05 07 02 F0
BOOTLOADER : 02 0000 05 07 02 F0 Value . CR LF
HOST : 02 0000 01 02 00 FB
BOOTLOADER : 02 0000 01 02 00 FB Value . CR LF
Read function (read SBV)
Atmel Read function (read Bootloader version)
113
AT89C51RD2/ED2
4235H–8051–10/06
ISP Comma nd s Summar y
Tab le 75. ISP Commands Summary
Command Comm and Name Data[0] Data[1] Command Effect
00h Program Code Pr ogram N b Code Byte.
Bootloader will accept up to 128 (80h) dat a bytes. The data
by tes shou ld be 128 byte page flash boundary.
03h Write Func tio n
01h
00h Er ase block0 (0 000h-1 FFFh)
20h Er ase block1 (2 000h-3 FFFh)
40h Er ase block2 (4 000h-7 FFFh)
80h Erase block3 (8000h- BFFFh)
C0h Erase block4 (C000h- FFFFh)
03h 00h Hardware Reset
04h 00h Erase SBV & BSB
05h 00h Program SSB level 1
01h Program SSB level 2
06h 00h Program BSB (value to write in data[2])
01h Program SBV (value to write in data[2])
07h - Full Chip Erase (This command need s about 6 sec to be
executed)
0Ah 04h Program BLJB fuse (value to write in data[2])
08h Program X2 fuse (value to write in da ta[2])
04h Display Function
Data[0:1] = start address
Data [2:3] = end address
Data[4] = 00h:Display Co de
Data[4] = 01h: Blank che ck
Data[4] = 02h: Display EEPR OM
Di splay Cod e
Bl a nk C h eck
Di splay EEPR O M data
05h Read Function
00h
00h Man ufacturer Id
01h Devi ce Id #1
02h Devi ce Id #2
03h Devi ce Id #3
07h
00h Read SSB
01h Read BSB
02h Read SBV
06h Read Ext r a Byte
0Bh 00h Read Hardware Byte
0Eh 00h Read Device Boot ID1
01h Read Device Boot ID2
0Fh 00h Read Bootloader Version
07h Program EEPROM data Program Nn EEprom Data Byte.
Bootloader will accept up to 128 (80h) data bytes.
114
AT89C51RD2/ED2
4235H–8051–10/06
API Call Description T he IAP allows to reprogram a microcontrol ler on-chip F lash memory w ithout removing
it from the system and while the embedded application is running.
The user application can call some Application Programming Interface (API) routines
allowing IAP. These API are executed by the bootloa der.
To call the corresponding API , the user must use a set of Flash_api routines which c an
be linked with the application.
Example of Flash_api routines are available on the Atmel web site on the software appli-
cation note:
C Flash Drivers for the A T 89C51RD2 /ED2
The API calls description and arguments are shown i n Table 76.
Process The application selec ts an API by s etting R1, ACC, DPTR0 and DPTR1 regi st ers.
All calls are made through a common interface “USER_CALL” at the address FFF0h.
Th e jum p at the US ER _CA LL m ust b e done by LCAL L ins truct ion to be ab le to c om e-
back in the application.
Before jump at t he USER_CALL, the bit ENBOOT in AUX R1 register must be set.
Constraints T he interrupts are not disabled by the bootloader.
In terrupts must be disa bled b y user prior to j ump to th e USE R_CA LL, t hen re-e nable d
when returning.
Interrupts must also be disabled before accessing EEP ROM Data then re-enabled after.
The user must take care of hardware watchdog before launchi ng a Flash operation.
Tab le 76. API Call Summary
Command R1 A DPTR0 DPTR1 Returned Value Command Effect
READ MANUF ID 00h XXh 0000h XXh ACC = Manufacturer
Id Read Manufacturer identifier
READ DEVICE ID1 00h XXh 0001h XXh ACC = Device Id 1 Read Device identifier 1
READ DEVICE ID2 00h XXh 0002h XXh ACC = Device Id 2 Read Device identifier 2
READ DEVICE ID3 00h XXh 0003h XXh ACC = Device Id 3 Read Device identifier 3
ER ASE BLOCK 01h XXh
DPH = 00h
00h A CC = DPH
Er ase block 0
DPH = 20h Erase block 1
DPH = 40h Erase block 2
DPH = 80h Erase block 3
DPH = C0h Erase block 4
PR OGRAM DATA
BYTE 0 2h Vau e to write Address of
by te to
program XXh ACC = 0: DONE Program up one da ta byt e in the on-chip
flash memory.
115
AT89C51RD2/ED2
4235H–8051–10/06
PROGRAM SSB 05h XXh
DPH = 00h
DPL = 00h
00h ACC = SSB value
Set SSB leve l 1
DPH = 00h
DPL = 01h Set SSB leve l 2
DPH = 00h
DPL = 10h Set SSB leve l 0
DPH = 00h
DPL = 11h S et SSB leve l 1
PROGRAM BSB 06h New BSB
value 0000h XXh none Program boot status byte
PROGRAM SBV 06h New SBV
value 000 1h XXh none P rogram sof tw a r e bo ot ve ctor
READ SSB 07h XXh 0000h XXh ACC = SSB Read Software Security Byte
READ BSB 07h XXh 0001h XXh ACC = BSB Read Boot Sta tus Byte
READ SBV 07h XXh 0002h XXh ACC = SBV Read Software Boot Vector
PR OGRAM DATA
PAGE 09h Num ber of
byte to
program
Address of
the firs t byte
to program in
the Flash
memory
Addres s in
XRAM of the
first data to
program
ACC = 0: DONE
Pr ogram up to 128 bytes in user Flash.
Re m ar k : num ber of by t e s to pr o gr a m is
li mit e d such as the Flas h w rit e rema i ns in a
single 128 bytes page. Hence, when ACC
is 128, valid values of DPL are 00h, or , 80h.
PROGRAM X2 FUSE 0Ah Fuse value
00h or 01h 0008 h XXh none Program X2 fuse bit with ACC
PROGRAM BLJB
FUSE 0Ah Fuse value
00h or 01h 0004h XXh none Program BLJB fuse bit with ACC
READ HSB 0Bh XXh XXXXh XXh ACC = HSB Read Hardware Byte
READ BOOT ID1 0Eh XXh DPL = 00h XXh ACC = ID1 Read boot ID1
READ BOOT ID2 0Eh XXh DPL = 01h XXh ACC = ID2 Read boot ID2
READ BOOT VERSION 0Fh XXh XXXXh XXh ACC = Boot_Version Read bootloader version
Tab le 76. API Call Summary (Continued)
Command R1 A DPTR0 DPTR1 Returned Value Command Effect
116
AT89C51RD2/ED2
4235H–8051–10/06
Electrical Characteristics
Ab solu te Maximum Rati ngs
DC Param eters for Standard Voltage
I = industrial ............................. ............ ...............-40°C to 8 5°C
Sto r ag e Temp e rature.......... .. ..... .. ..... ... ..... .. .. -6 5°C to + 150°C
Voltage on VCC to VSS ......................................-0.5V to + 6.5V
VVoltage on Any Pin to VSS .......................-0.5V to VCC + 0.5V
Power Dissipation........................................................... 1 W(2)
Note: Stresses at or above those listed under “Absolute
Maximum Ratings” may cause permanent damage t o
the device. This is a st ress rating only and functional
operation of the device at these or any other condi-
tions above those indicated in the operational
sections of this specification is not impli ed. Exposure
to absolute maximum rating conditions may affect
device r eliabi l ity.
Power dissipation is based on the maximum allow-
able die temperature and the thermal resistance of
the package.
TA = -40°C to +85°C; VSS = 0V;
VCC =2.7V to 5.5V and F = 0 to 40 MHz (both internal and external code execution)
VCC =4.5V to 5.5V and F = 0 to 60 MHz (internal code execution only)
Symbol Parameter Min Typ Max Unit Test Conditions
VIL Input Low Voltage -0.5 0.2 VCC - 0.1 V
VIH Input High Voltage except RST, XTAL1 0.2 VCC + 0.9 VCC + 0.5 V
VIH1 Input High Voltage RST, XT AL 1 0.7 VCC VCC + 0.5 V
VOL Output Low Voltage, ports 1, 2, 3, 4 (6)
0.3
0.45
1.0
V
V
V
VCC = 4.5V to 5.5V
IOL = 100 μA(4)
IOL = 1.6 m A(4)
IOL = 3.5 m A(4)
0.45 V VCC = 2.7V to 5.5V
IOL = 0.8 m A(4)
VOL1 Output Low Voltage, port 0, ALE, PSEN (6)
0.3
0.45
1.0
V
V
V
VCC = 4.5V to 5.5V
IOL = 200 μA(4)
IOL = 3.2 m A(4)
IOL = 7.0 m A(4)
0.45 V VCC = 2.7V to 5.5V
IOL = 1.6 m A(4)
VOH Output High Volt age, ports 1, 2, 3, 4
VCC - 0. 3
VCC - 0. 7
VCC - 1. 5
V
V
V
VCC = 5 V ± 10%
IOH = -10 μA
IOH = -30 μA
IOH = -60 μA
0.9 VCC VVCC = 2.7V to 5.5V
IOH = -10 μA
117
AT89C51RD2/ED2
4235H–8051–10/06
Notes: 1. Operating ICC is measured with all output pins di sconnected; XTAL1 driven with TCLCH, TCHCL = 5 ns (see Figure 55), VIL =
VSS + 0.5V, VIH = VCC - 0.5V; XTAL2 N.C.; EA = RST = Port 0 = VCC. ICC woul d be slightly higher if a crystal oscillator used
(see Figure 52).
2. Idle ICC is measured wi th all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5 ns, VIL = VSS + 0.5V, VIH = VCC -
0.5V; XTAL2 N.C; Port 0 = VCC; EA = RST = VSS (s ee Figure 53).
3. Power-down ICC is measured with al l output pins disconnect ed; EA = VSS, PORT 0 = VCC; XTAL2 NC.; RST = VSS (see Fi g-
ure 54) .
4. Capacitance loa ding on Ports 0 and 2 may cause spurious n o i se pul ses to be su perim posed on the V OLS of ALE and Ports 1
and 3. The noi se is d ue t o external bus capacita nce di scharging in to the Port 0 and Port 2 p ins when these pins m ake 1 t o 0
transit ion s during bus operation. I n the worst cases (capacit i ve l oadi ng 100 pF), the noise pulse on the ALE l ine may exc eed
0.45V with maxi VOL peak 0.6V. A Schm itt Tri gger use is not necessary.
5. Typical values are based on a limit ed number of samples and are not guaranteed. The values listed ar e at room t em peratur e
and 5V.
6. Under steady state (non-transi ent) conditions, IOL must be ext e rn ally l imi ted a s foll ow s:
Maximum IOL per port pin: 10 mA
Maximum IOL per 8-bit port:
Port 0: 26 mA
Ports 1, 2 and 3: 15 mA
VOH1 Output High Volt age, port 0, ALE, PSE N
VCC - 0. 3
VCC - 0. 7
VCC - 1. 5
V
V
V
VCC = 5 V ± 10%
IOH = -200 μA
IOH = -3.2 mA
IOH = -7.0 mA
0.9 VCC VVCC = 2.7V to 5.5V
IOH = -10 μA
RRST RST Pull-down Resistor 50 200(5) 250 kΩ
IIL Lo gical 0 Input Current ports 1, 2, 3, 4 and 5 -50 μAV
IN = 0.45V
ILI Input Leakage Current ±10 μA 0.45V < VIN < VCC
ITL Lo gical 1 to 0 Transition Cu rrent, ports 1, 2, 3, 4 -650 μAV
IN = 2.0V
CIO Capacitance of I/O Buffer 10 pF FC = 3 MHz
TA = 25°C
IPD Pow er-down Cur rent 75 150 μA2.7 < V
CC < 5.5 V (3)
ICCOP Power Supply Current on normal mode 0.4 x Frequency (MHz) + 5 mA VCC = 5.5V(1)
ICCIDLE Power Supply Current on idle mode 0.3 x Frequency (MHz) + 5 mA VCC = 5.5V(2)
ICCWRITE Power Supp ly Curre nt on fl ash or EEdat a write 0.8 x Frequency (MHz) + 15 mA VCC = 5.5V
tWRITE Flas h or EEdata pro gr a m mi ng tim e 7 17 m s 2 . 7 < VCC < 5.5 V
VPFDM Inte rnal POR/PFD VPF DM thres hold 2.25 2.5 2.69 V
VPFDP Internal POR/PFD VPFDP threshold 2.15 2.35 2.62 V
Vhyst Internal POR/PFD Hystere sys 70 140 250 mV
Vcc
dV/dt Maximum Vcc Power supply slew rate(7) 0.1 V/µs
TA = -40°C to +85°C; VSS = 0V;
VCC =2.7V to 5.5V and F = 0 to 40 MHz (both internal and external code execution)
VCC =4.5V to 5.5V and F = 0 to 60 MHz (internal code execution only) (Continued)
Symbol Parameter Min Typ Max Unit Test Conditions
118
AT89C51RD2/ED2
4235H–8051–10/06
Maximum to tal IOL for all output pins: 71 mA
If IOL exceeds the test condition, VOL may exceed t he r elated specificat ion. Pins are not guar ant eed t o sink cur rent great er
than the listed test conditions.
7. The maximum dV/ dt value specifi es the maxim um Vcc drop to issur e no int ern al POR/PFD reset.
Fi gure 5 2 . ICC Test Condition, Active Mode
Fi gure 5 3 . ICC Test Condition, Idle Mode
Fi gure 5 4 . ICC Test Condition, Power-down Mode
EA
VCC
V
CC
ICC
(NC)
CLOCK
SIGNAL
VCC
All other pins are disc onnected.
RST
XTAL2
XTAL1
VSS
VCC
P0
RST EA
XTAL2
XTAL1
VSS
VCC
V
CC
ICC
(NC)
P0
VCC
All other pins are disconnected.
CLOCK
SIGNAL
RST EA
XTAL2
XTAL1
VSS
VCC
V
CC
ICC
(NC)
P0
VCC
All other pins are disconnected.
119
AT89C51RD2/ED2
4235H–8051–10/06
Fi gure 5 5 . Clock Signal Waveform for ICC Tests in Active and Idle Modes
AC Parameters
Explanation of the AC
Symbols Each timing symbol has 5 characters . The first character is always a “T” (s tands for
time). The other characters, depending on their positions, stand for t he name of a signal
or the logical status of that signal. The following is a list of all the characters and what
they stand for.
Example:TAVLL = Time for Address Valid to ALE Low.
TLLPL = Time for ALE Low to PSEN Low.
(Load Capaci ta nce for port 0, ALE and PSEN = 100 pF; L oad Capac ita nce for all other
outputs = 80 pF.)
Table 77 Table 80, and Table 83 give the des cription of each AC symbols.
Table 78, Table 79, Table 81 and Table 84 gives the range for each AC parameter.
Table 78, Table 79 and Table 85 give the frequency derat ing formula of the AC parame-
ter for each spee d range desc ription. To calcul ate ea ch AC symb ols. take the x value in
the corr eponding column (-M) and use this value in the formula.
Example: TLLIU for -M and 20 MHz, Standard clock.
x = 35 ns
T 50 ns
TCCIV = 4T - x = 165 ns
Ext ernal Program Mem ory
Characteristics Tabl e 77. Symbol Description
VCC-0.5V
0.45V 0.7VCC
0.2VCC-0.1
TCLCH
TCHCL
TCLCH = TCHCL = 5ns.
Symbol Parameter
T Oscillator clock period
TLHLL ALE pulse width
TAVLL A ddress Valid to ALE
TLLAX Address Hold After ALE
TLLIV AL E to V a lid Ins truction In
TLLPL ALE to PSEN
TPLPH PSEN Pulse Width
TPLIV PSEN to Vali d Ins tru c tio n In
TPXIX In put Instruction Hold After PSEN
TPXIZ Input Instruction Float After PSEN
TAVIV Address to Valid Instruction In
TPLAZ PSEN Low to Address Float
120
AT89C51RD2/ED2
4235H–8051–10/06
Table 78. AC Par a meters for a Fi x Clock
Table 79. AC Param eters for a Variable Clock
Symbol -M Units
Min Max
T25 ns
TLHLL 35 ns
TAVLL 5ns
TLLAX 5ns
TLLIV n 65 ns
TLLPL 5ns
TPLPH 50 ns
TPLIV 30 ns
TPXIX 0ns
TPXIZ 10 ns
TAVIV 80 ns
TPLAZ 10 ns
Symbol Type Standard Clock X2 Clock X parameter for
-M range Units
TLHLL Min 2 T - x T - x 15 ns
TAVLL Min T - x 0.5 T - x 20 ns
TLLAX M in T - x 0.5 T - x 20 ns
TLLIV Max 4 T - x 2 T - x 35 ns
TLLPL Min T - x 0.5 T - x 15 ns
TPLPH Min 3 T - x 1.5 T - x 25 ns
TPLIV Max 3 T - x 1.5 T - x 45 ns
TPXIX Min x x 0 ns
TPXIZ Max T - x 0.5 T - x 15 ns
TAVIV Max 5 T - x 2.5 T - x 45 ns
TPLAZ Max x x 10 ns
121
AT89C51RD2/ED2
4235H–8051–10/06
Ext ernal Program Mem ory
Read Cycle
Exte rnal Data M em o ry
Characteristic s Table 80. Symbol Description
TPLIV
TPLAZ
ALE
PSEN
PORT 0
PORT 2
A0-A7A0-A7 INSTR ININSTR IN INSTR IN
ADDRESS
OR SFR-P2 ADDRESS A8-A15ADDRESS A8-A15
12 TCLCL
TAVIV
TLHLL
TAVLL
TLLIV
TLLPL
TPLPH
TPXAV
TPXIX
TPXIZ
TLLAX
Symbol Parameter
TRLRH RD Pulse Width
TWLWH WR Pulse Width
TRLDV RD to Valid Data In
TRHDX D ata Hold After RD
TRHDZ Data Float After RD
TLLDV ALE to V a lid Data In
TAVDV Address to V alid Dat a In
TLLWL ALE to WR or RD
TAVWL Ad dress to WR or R D
TQVWX Data Valid to WR Tran s i tion
TQVWH Data Set-up to WR Hig h
TWHQX Data Hold After WR
TRLAZ RD Low to Address Float
TWHLH RD or WR H ig h t o ALE high
122
AT89C51RD2/ED2
4235H–8051–10/06
Table 81. AC Par a meters for a Fi x Clock
Symbol
-M
UnitsMin Max
TRLRH 125 ns
TWLWH 125 ns
TRLDV 95 ns
TRHDX 0ns
TRHDZ 25 ns
TLLDV 155 ns
TAVDV 160 ns
TLLWL 45 105 ns
TAVWL 70 ns
TQVWX 5ns
TQVWH 155 ns
TWHQX 10 ns
TRLAZ 0ns
TWHLH 545ns
Table 82. AC Param eters for a Variable Clock
Symbol Type Standard
Clock X2 Clock X parameter for
-M range Units
TRLRH Min 6 T - x 3 T - x 25 ns
TWLWH Min 6 T - x 3 T - x 25 ns
TRLDV Max 5 T - x 2.5 T - x 30 ns
TRHDX Min x x 0 ns
TRHDZ Max 2 T - x T - x 25 ns
TLLDV Max 8 T - x 4T -x 45 ns
TAVDV Max 9 T - x 4.5 T - x 65 ns
TLLWL Min 3 T - x 1.5 T - x 30 ns
TLLWL Max 3 T + x 1.5 T + x 30 ns
TAVWL Min 4 T - x 2 T - x 30 ns
TQVWX Min T - x 0.5 T - x 20 ns
TQVWH Min 7 T - x 3.5 T - x 20 ns
TWHQX Min T - x 0.5 T - x 15 ns
TRLAZ Max x x 0 ns
TWHLH Min T - x 0.5 T - x 20 ns
TWHLH Max T + x 0.5 T + x 20 ns
123
AT89C51RD2/ED2
4235H–8051–10/06
External Data M em o ry Write
Cycle
Externa l Data Mem o ry Read Cycle
Serial Port Timing - Shift
Register Mod e Table 83. Sym bol Description
TQVWH
TLLAX
ALE
PSEN
WR
PORT 0
PORT 2
A0-A7 DATA OUT
ADDRESS
OR SFR-P2
TAVWL
TLLWL
TQVWX
ADDRESS A8-A15 OR SFR P2
TWHQX
TWHLH
TWLWH
ALE
PSEN
RD
PORT 0
PORT 2
A0-A7 DATA IN
ADDRESS
OR SFR-P2
TAVWL
TLLWL
TRLAZ
ADDRESS A8-A15 OR SFR P2
TRHDZ
TWHLH
TRLRH
TLLDV
TRHDX
TLLAX
TAVDV
Symbol Parameter
TXLXL Se ri al port clock cycl e time
TQVHX Output data set-u p to clock risin g edge
TXHQX Output data hold after clock rising edge
TXHDX Input data hol d after clock rising edge
TXHDV Clock rising edge to input data valid
124
AT89C51RD2/ED2
4235H–8051–10/06
Table 84. AC Par a meters for a Fi x Clock
Table 85. AC Param eters for a Variable Clock
Shi ft Regis te r Timi ng
Waveforms
Externa l Clock Drive
Waveforms
Symbol
-M
UnitsMin Max
TXLXL 300 ns
TQVHX 200 ns
TXHQX 30 ns
TXHDX 0ns
TXHDV 117 ns
Symbol Type Standard
Clock X2 Clock X Parameter For
-M Range Units
TXLXL Min 12 T 6 T ns
TQVHX M in 10 T - x 5 T - x 50 ns
TXHQX Min 2 T - x T - x 20 ns
TXHDX Min x x 0 ns
TXHDV Max 10 T - x 5 T - x 133 ns
INPUT DATA VALIDVALID VALID VALID
0123456 87
ALE
CLOCK
OUTPUT DATA
WRITE to SBUF
CLEAR RI
TXLXL
TQVXH TXHQX
TXHDV TXHDX SET TI
SET RI
INSTRUCTION
01234567
VALID VALID VALID VALID
VCC-0.5V
0.45V
0.7VCC
0.2VCC-0.1
TCHCL TCLCX TCLCL
TCLCH
TCHCX
125
AT89C51RD2/ED2
4235H–8051–10/06
AC Testing Input/Output
Waveforms
AC in puts during testin g are driven at VCC - 0.5 fo r a logic “1” and 0.45V for a logic “0”.
Timing m easurem ent are made at VIH min for a logi c “1” and VIL max for a logic “0”.
Float Wavefor ms
For t iming pu rposes a s port pi n is no lon ger float ing whe n a 100 m V chang e from loa d
voltage occurs and begins to float when a 100 mV change from the loaded VOH/VOL lev el
occurs. IOL/IOH ≥ ± 20 mA.
Clock Waveforms Valid in normal clock mode. In X2 mode XTAL2 must be changed t o XTAL2/2.
INPUT/OUTPUT 0.2 VCC + 0.9
0.2 VCC - 0.1
VCC -0.5V
0.45V
FLOAT
VOH - 0.1V
VOL + 0.1V
VLOAD VLOAD + 0.1V
VLOAD - 0.1V
126
AT89C51RD2/ED2
4235H–8051–10/06
Figu re 56. Internal Clock Signals
This diagram indicates when signa ls are clocked intern ally. The time it takes the signals to propagate to the pins, ho wever,
ranges f rom 25 to 125 ns. Thi s propagation delay is dependent on variables such as temperat ur e and pin loading. Propaga-
tion al so va ries f rom ou tput to o utpu t and comp onent . Typ ically though (TA = 25°C full y load ed) RD and W R pr opagat ion
delays are approxim ately 50 ns. The other signals are typically 85 ns. Propagation delay s are incorporated in the AC
specifications.
DATA PCL OUT DATA PCL OUT DATA PCL OUT
SAMPLED SAM PLED SAMPLED
STATE4 STATE5 STATE6 STATE1 STATE2 STATE3 STATE4 STATE5
P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2
FLOAT FLOAT FLOAT
THESE SIGNALS ARE NOT ACTIVA T ED DURING THE
EXECUTION OF A MO V X INSTRUCTION
INDICATES ADDRESS TRANSITIONS
EXTERNAL PROGRAM MEMORY FETCH
FLOAT
DATA
SAMPLED
DP L OR Rt OUT
INDICATES DPH OR P2 SFR TO PCH TRANSITION
PCL OUT (IF PROGRAM
MEMORY IS E XTERNAL)
PCL OUT (EVEN IF PROGRAM
MEMOR Y IS INTERNAL)
PCL OUT (IF PROGRA
M
MEMORY I S EXT ERNA
L)
OLD DATA NEW DATA P0 PINS SAMPLED
P1, P2, P3 PINS SAMPLED P1, P2, P3 PINS SAMPLED
P0 PINS SAMPLED
RXD SAMPLE D
INTERNAL
CLOCK
XTAL2
ALE
PSEN
P0
P2 (EXT)
READ CYCLE
WRITE CYCLE
RD
P0
P2
WR
PORT OPERATION
MOV PORT SRC
MOV DEST P0
MOV DEST POR T (P1. P2. P3)
(INCLUDES INTO. INT1. TO T1)
SERIAL PORT SHIFT CLOCK
TXD (MODE 0)
DATA OUT
DP L OR Rt OUT
INDICATES DPH OR P2 SFR TO PCH TRANSITION
P0
P2
RXD SAMPL ED
127
AT89C51RD2/ED2
4235H–8051–10/06
Ordering Information
Note: 1. For PLCC68 and VQFP64 packages, please contact Atmel sal es office for avai lability.
Tab le 86. Poss ible Order Entries
P art Num ber Da ta EEPROM Sup ply Voltage Temperature
Range Package Packing Product Marking
AT89C51RD2-SLSIM
No
2.7V - 5.5V Industrial
PLCC44 Stick AT89C51RD2-IM
AT89C51RD2-RLTIM VQFP44 Tray AT89C51RD2-IM
AT89C51RD2-RDTIM(1) VQFP64 Tray AT89C51RD2-IM
AT89C51RD2-SMSIM(1) PLCC68 Stick AT89C51RD2-IM
AT89C51ED2-SLSIM
Yes
PLCC44 Stick AT89C51ED2-IM
AT89C51ED2-RLTIM VQFP44 Tray AT89C51ED2-IM
AT89C51ED2-3CSIM PDIL40 Stick AT89C51ED2-IM
AT89C5 1ED2- SMSIM PLCC68 Stick AT89C51ED2-IM
AT89C51ED2-RDTIM VQFP64 Tray AT89C51ED2-IM
AT89C51RD2-SLSUM
No
2.7V - 5.5V Industrial &
Green
PLCC44 Stick AT89C51RD2-UM
AT89C51RD2-RLTUM VQFP44 Tray AT89C51RD2-UM
AT89C51RD2-RDTUM(1) VQFP64 Tray AT89C51RD2-UM
AT89C51RD2-SMSUM(1) PLCC68 Stick AT89C51RD2-UM
AT89C51ED2-SLSUM
Yes
PLCC44 Stick AT89C51ED2-UM
AT89C51ED2-RLTUM VQFP44 Tray AT89C51ED2-UM
AT89C51ED2-3CSUM PDUL40 Stick AT89C51ED2-UM
AT89C5 1ED2- SMSUM PLCC68 Stick AT89C51ED2-UM
AT89C51ED2-RDTUM VQFP64 Tray AT89C51ED2-UM
128
AT89C51RD2/ED2
4235H–8051–10/06
Pac kag in g Info rmat io n
PLCC44
129
AT89C51RD2/ED2
4235H–8051–10/06
VQFP44
130
AT89C51RD2/ED2
4235H–8051–10/06
PLCC68
131
AT89C51RD2/ED2
4235H–8051–10/06
VQFP64
132
AT89C51RD2/ED2
4235H–8051–10/06
PDIL40
133
AT89C51RD2/ED2
4235H–8051–10/06
Datasheet Change
Log for
AT89C51RD2/ED2
Changes fr om 4235A -
04/03 to 4135B - 06/03 1. VIH mi n changed from 0.2 V CC + 1.1 to 0.2 VCC + 0.9.
2. Added POR/PFD and reset specific sections.
3. Added DIL40 package.
4. Added Flash write programming time spec ification.
Changes fr om 4235B -
06/03 to 4235C - 08/03 1. Changed maximum frequency to 60 MHz in X1 mode and 30 MHz in X2 mode
for Vcc = 4.5V to 5.5V and internal code execu tion.
2. Added PDIL40 Packaging for AT89C51ED2.
Changes fr om 4235C -
08/03 to 4235D - 12/03 1. Improved explan ations throughout the doc ume nt.
Changes fr om 4235D -
12/03 to 4235E - 04/04 1. Improved explan ations throughout the doc ume nt.
Changes from 4235E -
04/04 to 4235F - 09/04 1. Improved explan ations in Flash and EEPRO M sections .
Changes from 4235F -
09/04 to 4235G 08/05 1. Added ‘I ndustrial & Green” produ ct versions.
Changes fr om 4235G
08/05 to 4235H - 10/06 1. Correction to PDIL figure on page 9.
iA–8051–10/06
AT89C51RD2/ED2
Table of Contents
Features ................................................................................................. 1
Description ............................................................................................ 1
Block Diagram ...................................................................................... 3
SFR Mapping ......................................................................................... 4
Pin Configurations ............................................................................... 9
Port Types ........................................................................................... 14
Oscillator ............................................................................................. 15
Registers............................................................................................................. 15
Functional Block Diagram ...................................................................................16
Enhanced Features ............................................................................ 17
X2 Featu r e. ............ ............ ................ ............ ............ ................ ............ ............ . 17
Dual Data Poin ter Register (DPTR) ................................................... 21
Expanded RAM (XRAM) ..................................................................... 24
Registers............................................................................................................. 26
Reset .................................................................................................... 27
Introduction......................................................................................................... 27
Reset Input......................................................................................................... 27
Reset Output .... ............ ............ ............ ........... ................. ............ ............ ...........28
Power Monitor ..................................................................................... 29
Description .......................................................................................................... 29
Timer 2 ................................................................................................. 31
Auto-reload Mode... ............................................................................................ 31
Programmable
Clock-output................................................................................................................. 32
Registers............................................................................................................. 34
Programmable Counte r Array (PCA) ................................................ 36
PCA Capture Mo de............................................................................................. 44
16-bit Software Timer/ Compare Mode............................................................... 44
High Speed Ou tput Mode................................................................................... 45
Pulse Width Modulator Mode.............................................................................. 46
PCA Watchdog Time r......................................................................................... 47
ii
A–8051–10/06
AT89C51RD2/ED2
Serial I/O Port ...................................................................................... 49
Fra mi n g Erro r De te cti o n. ............ ............ ............ ................ ............ ............ ........ 49
Automatic Add ress Recogni tion......................................................... . ................ 50
Registers............................................................................................................. 52
Baud Rate Selection for UART for M ode 1 and 3..................... .......................... 52
UART Registers .................................................................................................. 55
Keyboard Interface ............................................................................. 60
Registers............................................................................................................. 61
Serial Port Interface (SPI) .................................................................. 64
Features.............................................................................................................. 64
Signal Description......................... ............ ....... ....... ............ ....... ....... ............ ...... 64
Functional Description........................................................................................ 66
Interrupt System ................................................................................. 73
Registers............................................................................................................. 74
Interrupt Sources and Vector Addresses............................................................ 75
Power Management ............................................................................ 82
Introduction......................................................................................................... 82
Idle Mode............................................................................................................ 82
Power-Down Mode............................................................................................. 82
Registers............................................................................................................. 85
Hardware Watchdog Timer ................................................................ 86
Using th e WDT................................................................................................... 86
WDT during Power-down and Idle. . ................ .................................................... 87
ONCE® Mode (ON- Chip Emulation) .................................................. 88
Power-off Flag ..................................................................................... 89
Reduced EMI Mode ............................................................................. 90
EEPROM Data Memory ...................................................................... 91
Write Data........................................................................................................... 91
Read Data........................................................................................................... 93
Registers............................................................................................................. 94
Flash/EEPROM Memory ..................................................................... 95
Features.............................................................................................................. 95
Flash Programm ing and E rasure............................. . .......................................... 95
Flash Registers and Memory Map. . ................................................. ................... 96
Flash Memo ry Sta tus. ........ ................ ............ ............ ................ ............ ............ . 99
Memory Organizati on ......................................................................................... 99
iii A–8051–10/06
AT89C51RD2/ED2
Bootloader Architecture.................................................................................... 100
ISP Protocol Description ...................................................................................1 04
Functional Description...................................................................................... 105
Flow Des c ription............. ............ ............ ............ ................ ............ ............ ...... 106
API Call Description.......................................................................................... 1 14
Ele ctrical Char act eristics ................ ............................ ......... ............ 1 16
Absolute Maximum Rat ing s ....... ............ ............ ................ ............ ............ .......11 6
DC Parameters for Standard Voltage ............................... .......................... ......1 16
AC Para mete r s........ ............ ................. ........... ............ ................. ............ ........ 119
Ordering Information ........................................................................ 127
Packaging Information ..................................................................... 128
PLCC44..................... ............ ............ ............ ............ ................ ............ ........... 12 8
VQF P4 4..... ............ ............ ................ ............ ............ ................ ............ ........... 12 9
PLCC68..................... ............ ............ ............ ............ ................ ............ ........... 13 0
VQF P6 4..... ............ ............ ................ ............ ............ ................ ............ ........... 13 1
PDIL 40....... ................ ............ ............ ................. ............ ........... ............ ........... 132
Datasheet Change Log for AT89C51RD2/ED2 ............................... 133
Changes from 4235 A -04/03 to 4135B - 06/03................................................. 133
Changes from 4235 B -06/03 to 4235C - 08/03................................................. 133
Changes from 4235 C - 08/03 to 4235D - 1 2/03 ................................................ 133
Changes from 4235 D - 12/03 to 4235E - 04/04................................................ 133
Changes from 4235 E - 04/04 to 4235F - 09/04. .................. . ............................ 133
Changes from 4235 F - 09/04 to 4235G - 08/05. ............................................... 133
Changes from 4235 G - 08/05 to 4235H - 10/06 ............................................ . .. 133
Table of Contents .................................................................................. i
Pr inted o n recycled pape r.
A–8051–10/06
© Atm el Corporation 2006. All rights reserved. Atmel®, lo go and com bin ati ons th e reof, a r e regist e r e d tr a de m ar k s , and Ev ery w h er e You Ar eSM
are the trade ma rk s of Atm el Co r po r ation or i ts s u bs idiar ie s. Ot he r term s and product n am es m a y be t rade m ark s of ot hers.
Disclaimer: The information in this document is provided in connection with Atmel products. No l icense, express or implied, by estoppel o r otherwise,to anyintellectu-
alproperty right is granted by this document or in connec tion with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS O F
SALE LOCAT ED ON ATMEL’S WEB SITE, ATMEL AS SUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STAT UTORYWAR-
RANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICU-
LARPURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL
OR INCIDEN-TAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, O R LOSS OF INFORMA-
TION) ARISING OUTOF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAM-
AGES. Atmel makes nor epres enta tionsor warranties with respect to the ac curacy or completeness of the c ontents of this document and re ser ves the right to make
changes to specificationsand product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein.
Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended,
authorized, or warranted for usea s components in applications intended to support or sustainlife.
Atmel Corporation Atmel Operations
2325 O rchard Park way
San Jos e, CA 951 31, USA
Tel: 1( 408) 441-03 11
Fax : 1(408 ) 487 -2600
Regional Headquarters
Europe
Atm el Sa rl
Rout e des Ars enau x 41
Case P ostale 8 0
CH-170 5 Fri bour g
Switzerland
Tel: ( 41) 26-426- 5555
Fax : (41) 26 -426 -550 0
Asia
Room 1219
Chin achem Golden P laza
77 Mod y Road T sims hatsu i
Ea st Kowl oon
Hong K ong
Tel: ( 852) 2721-97 78
Fax : (852) 2 722 -1369
Japan
9F, T onet su Shi nkawa B ldg.
1-24 -8 Sh inkaw a
Chuo- ku, Tok yo 10 4-00 33
Japan
Tel: ( 81) 3-3523- 3551
Fax : (81) 3- 3523 -758 1
Memory
2325 O rch ard Par kway
San Jo se, C A 95131 , USA
Tel : 1(408 ) 441 -031 1
Fax: 1(4 08) 436- 4314
Microcontrollers
2325 O rch ard Par kway
San Jo se, C A 95131 , USA
Tel : 1(408 ) 441 -031 1
Fax: 1(4 08) 436- 4314
La Ch antrer ie
BP 70 602
44306 Na ntes Cede x 3, Fra nce
Tel : (33) 2- 40- 18-18- 18
Fax: (33) 2-40-18-19-60
ASIC/ASSP/Smart Cards
Zone In dustrie lle
13106 Ro usset Ced ex, Fra nce
Tel : (33) 4- 42- 53-60- 00
Fax: (33) 4-42-53-60-01
1150 E ast C heyenn e Mtn . Blvd.
Col orad o Spr ings, C O 8090 6, USA
Tel : 1(719 ) 576 -330 0
Fax: 1(7 19) 540- 1759
Scottish Enterp rise Technology Park
Maxwell Building
East Kilbr ide G7 5 0QR, S cotl and
Tel : (44) 13 55-8 03-0 00
Fax: (44) 1355 -242 -743
RF/Automotive
Theresienstrasse 2
Postfach 3535
74025 H eil bronn, Germa ny
Tel: (49) 71-31-67-0
Fax : (4 9) 71 -31-67 -234 0
1150 Ea st Ch eyen ne Mtn. B lvd.
Colo rado Spring s, CO 80 906, U SA
Tel: 1( 719) 576-33 00
Fax : 1 (719) 540-1 759
Biometrics/Imaging/Hi-Rel MPU/
High Speed Converters/RF Datacom
Avenue de R ochepl eine
BP 123
38521 S aint -Egr eve Ced ex, Fra nce
Tel: (33) 4-76-58-30-00
Fax : (3 3) 4-7 6-58-3 4-80
Literature Requests
www.atmel.com/literature