5962-8771002GA /NOPB - NATIONAL SEMICONDUCTOR

www.latticesemi.com 1DS1020_23.5

ispMACH

4000V/B/C/Z Family

3.3 V/2.5 V/1.8 V In-System Programmable

SuperFAST

High Density PLDs

April 2016 Data Sheet DS1020

or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

Features

High Performance

•f

MAX = 400 MHz maximum operating frequency

•t

PD = 2.5 ns propagation delay

• Up to four global clock pins with programmable

clock polarity control

• Up to 80 PTs per output

Ease of Design

• Enhanced macrocells with individual clock,

reset, preset and clock enable controls

• Up to four global OE controls

• Individual local OE control per I/O pin

• Excellent First-Time-FitTM and refit

• Fast path, SpeedLockingTM Path, and wide-PT

path

• Wide input gating (36 input logic blocks) for fast

counters, state machines and address decoders

Zero Power (ispMACH 4000Z) and Low

Power (ispMACH 4000V/B/C)

• Typical static current 10 µA (4032Z)

• Typical static current 1.3 mA (4000C)

• 1.8 V core low dynamic power

• ispMACH 4000Z operational down to 1.6 V VCC

Broad Device Offering

• Multiple temperature range support

– Commercial: 0 to 90 °C junction (Tj)

– Industrial: –40 to 105 °C junction (Tj)

– Extended: –40 to 130 °C junction (Tj)

• For AEC-Q100 compliant devices, refer to

LA-ispMACH 4000V/Z Automotive Data Sheet

Easy System Integration

• Superior solution for power sensitive consumer

applications

• Operation with 3.3 V, 2.5 V or 1.8 V LVCMOS I/O

• Operation with 3.3 V (4000V), 2.5 V (4000B) or

1.8 V (4000C/Z) supplies

• 5 V tolerant I/O for LVCMOS 3.3, LVTTL, and

PCI interfaces

• Hot-socketing

• Open-drain capability

• Input pull-up, pull-down or bus-keeper

• Programmable output slew rate

• 3.3 V PCI compatible

• IEEE 1149.1 boundary scan testable

• 3.3 V/2.5 V/1.8 V In-System Programmable

(ISP™) using IEEE 1532 compliant interface

• I/O pins with fast setup path

• Lead-free package options

Table 1. ispMACH 4000V/B/C Family Selection Guide

ispMACH

4032V/B/C

ispMACH

4064V/B/C

ispMACH

4128V/B/C

ispMACH

4256V/B/C

ispMACH

4384V/B/C

ispMACH

4512V/B/C

Macrocells 32 64 128 256 384 512

I/O + Dedicated Inputs 30+2/32+4 30+2/32+4/

64+10

64+10/92+4/

96+4

64+10/96+14/

128+4/160+4

128+4/192+4 128+4/208+4

tPD (ns) 2.5 2.5 2.7 3.0 3.5 3.5

tS (ns) 1.8 1.8 1.8 2.0 2.0 2.0

tCO (ns) 2.2 2.2 2.7 2.7 2.7 2.7

fMAX (MHz) 400 400 333 322 322 322

Supply Voltages (V) 3.3/2.5/1.8V 3.3/2.5/1.8V 3.3/2.5/1.8V 3.3/2.5/1.8V 3.3/2.5/1.8V 3.3/2.5/1.8V

Pins/Package 44 TQFP4

48 TQFP444 TQFP4

48 TQFP4

100 TQFP 100 TQFP

128 TQFP

144 TQFP1

100 TQFP

144 TQFP1

176 TQFP

256 ftBGA2/

fpBGA2, 3

176 TQFP

256 ftBGA/

fpBGA3

176 TQFP

256 ftBGA/

fpBGA3

1. 3.3 V (4000V) only.

2. 128-I/O and 160-I/O configurations.

3. Use 256 ftBGA package for all new designs. Refer to PCN#14A-07 for 256 fpBGA package discontinuance.

4. 1.0 mm thickness.

ispMACH 4000V/B/C/Z Family Data Sheet

Table 2. ispMACH 4000Z Family Selection Guide

ispMACH 4000 Introduction

The high performance ispMACH 4000 family from Lattice offers a SuperFAST CPLD solution. The family is a blend

of Lattice’s two most popular architectures: the ispLSI® 2000 and ispMACH 4A. Retaining the best of both families,

the ispMACH 4000 architecture focuses on significant innovations to combine the highest performance with low

power in a flexible CPLD family.

The ispMACH 4000 combines high speed and low power with the flexibility needed for ease of design. With its

robust Global Routing Pool and Output Routing Pool, this family delivers excellent First-Time-Fit, timing predictabil-

ity, routing, pin-out retention and density migration.

The ispMACH 4000 family offers densities ranging from 32 to 512 macrocells. There are multiple density-I/O com-

binations in Thin Quad Flat Pack (TQFP), Chip Scale BGA (csBGA) and Fine Pitch Thin BGA (ftBGA) packages

ranging from 44 to 256 pins/balls. Table 1 shows the macrocell, package and I/O options, along with other key

parameters.

The ispMACH 4000 family has enhanced system integration capabilities. It supports 3.3 V (4000V), 2.5 V (4000B)

and 1.8 V (4000C/Z) supply voltages and 3.3 V, 2.5 V and 1.8 V interface voltages. Additionally, inputs can be

safely driven up to 5.5 V when an I/O bank is configured for 3.3 V operation, making this family 5 V tolerant. The

ispMACH 4000 also offers enhanced I/O features such as slew rate control, PCI compatibility, bus-keeper latches,

pull-up resistors, pull-down resistors, open drain outputs and hot socketing. The ispMACH 4000 family members

are 3.3 V/2.5 V/1.8 V in-system programmable through the IEEE Standard 1532 interface. IEEE Standard 1149.1

boundary scan testing capability also allows product testing on automated test equipment. The 1532 interface sig-

nals TCK, TMS, TDI and TDO are referenced to VCC (logic core).

Overview

The ispMACH 4000 devices consist of multiple 36-input, 16-macrocell Generic Logic Blocks (GLBs) interconnected

by a Global Routing Pool (GRP). Output Routing Pools (ORPs) connect the GLBs to the I/O Blocks (IOBs), which

contain multiple I/O cells. This architecture is shown in Figure 1.

ispMACH 4032ZC ispMACH 4064ZC ispMACH 4128ZC ispMACH 4256ZC

Macrocells 32 64 128 256

I/O + Dedicated Inputs 32+4/32+4 32+4/32+12/

64+10/64+10

64+10/96+4 64+10/96+6/

128+4

tPD (ns) 3.5 3.7 4.2 4.5

tS (ns) 2.2 2.5 2.7 2.9

tCO (ns) 3.0 3.2 3.5 3.8

fMAX (MHz) 267 250 220 200

Supply Voltage (V) 1.8 1.8 1.8 1.8

Max. Standby Icc (µA) 20 25 35 55

Pins/Package 48 TQFP

56 csBGA

48 TQFP

56 csBGA

100 TQFP

132 csBGA

100 TQFP

132csBGA

100 TQFP

132 csBGA

176 TQFP

ispMACH 4000V/B/C/Z Family Data Sheet

Figure 1. Functional Block Diagram

The I/Os in the ispMACH 4000 are split into two banks. Each bank has a separate I/O power supply. Inputs can

support a variety of standards independent of the chip or bank power supply. Outputs support the standards com-

patible with the power supply provided to the bank. Support for a variety of standards helps designers implement

designs in mixed voltage environments. In addition, 5 V tolerant inputs are specified within an I/O bank that is con-

nected to VCCO of 3.0 V to 3.6 V for LVCMOS 3.3, LVTTL and PCI interfaces.

ispMACH 4000 Architecture

There are a total of two GLBs in the ispMACH 4032, increasing to 32 GLBs in the ispMACH 4512. Each GLB has

36 inputs. All GLB inputs come from the GRP and all outputs from the GLB are brought back into the GRP to be

connected to the inputs of any other GLB on the device. Even if feedback signals return to the same GLB, they still

must go through the GRP. This mechanism ensures that GLBs communicate with each other with consistent and

predictable delays. The outputs from the GLB are also sent to the ORP. The ORP then sends them to the associ-

ated I/O cells in the I/O block.

Generic Logic Block

The ispMACH 4000 GLB consists of a programmable AND array, logic allocator, 16 macrocells and a GLB clock

generator. Macrocells are decoupled from the product terms through the logic allocator and the I/O pins are decou-

pled from macrocells through the ORP. Figure 2 illustrates the GLB.

I/O

Block

ORP ORP

GOE0

GOE1

VCC

GND

TCK

TMS

TDI

TDO

Generic

Logic

Block

Generic

Logic

Block

I/O

Block

ORP ORP

Generic

Logic

Block

Generic

Logic

Block

I/O

Block

I/O Bank 0

I/O Bank 1

I/O

Block

CLK0/I

CLK1/I

CLK2/I

CLK3/I

Global Routing Pool

VCCO0

GND

VCCO1

GND

16 16

ispMACH 4000V/B/C/Z Family Data Sheet

Figure 2. Generic Logic Block

AND Array

The programmable AND Array consists of 36 inputs and 83 output product terms. The 36 inputs from the GRP are

used to form 72 lines in the AND Array (true and complement of the inputs). Each line in the array can be con-

nected to any of the 83 output product terms via a wired-AND. Each of the 80 logic product terms feed the logic

allocator with the remaining three control product terms feeding the Shared PT Clock, Shared PT Initialization and

Shared PT OE. The Shared PT Clock and Shared PT Initialization signals can optionally be inverted before being

fed to the macrocells.

Every set of five product terms from the 80 logic product terms forms a product term cluster starting with PT0.

There is one product term cluster for every macrocell in the GLB. Figure 3 is a graphical representation of the AND

Array.

Logic Allocator

36 Inputs

from GRP

16 Macrocells

To ORP

To GRP

Product Term

Output Enable

Sharing

1+OE

16 MC Feedback Signals

Clock

Generator

1+OE

CLK0

CLK1

CLK2

CLK3

1+OE

AND Array

36 Inputs,

83 Product Terms

ispMACH 4000V/B/C/Z Family Data Sheet

Figure 3. AND Array

Enhanced Logic Allocator

Within the logic allocator, product terms are allocated to macrocells in product term clusters. Each product term

cluster is associated with a macrocell. The cluster size for the ispMACH 4000 family is 4+1 (total 5) product terms.

The software automatically considers the availability and distribution of product term clusters as it fits the functions

within a GLB. The logic allocator is designed to provide three speed paths: 5-PT fast bypass path, 20-PT Speed

Locking path and an up to 80-PT path. The availability of these three paths lets designers trade timing variability for

increased performance.

The enhanced Logic Allocator of the ispMACH 4000 family consists of the following blocks:

• Product Term Allocator

• Cluster Allocator

• Wide Steering Logic

Figure 4 shows a macrocell slice of the Logic Allocator. There are 16 such slices in the GLB.

PT0

PT1 Cluster 0

PT2

PT3

PT4

In[0]

In[34]

In[35]

Note:

Indicates programmable fuse.

PT80

PT81

PT82

Shared PT Clock

Shared PT Initialization

Shared PTOE

PT76

PT77

PT78

PT79

PT75

Cluster 15

ispMACH 4000V/B/C/Z Family Data Sheet

Figure 4. Macrocell Slice

Product Term Allocator

The product term allocator assigns product terms from a cluster to either logic or control applications as required

by the design being implemented. Product terms that are used as logic are steered into a 5-input OR gate associ-

ated with the cluster. Product terms that used for control are steered either to the macrocell or I/O cell associated

with the cluster. Table 3 shows the available functions for each of the five product terms in the cluster. The OR gate

output connects to the associated I/O cell, providing a fast path for narrow combinatorial functions, and to the logic

allocator.

Table 3. Individual PT Steering

Cluster Allocator

The cluster allocator allows clusters to be steered to neighboring macrocells, thus allowing the creation of functions

with more product terms. Table 4 shows which clusters can be steered to which macrocells. Used in this manner,

the cluster allocator can be used to form functions of up to 20 product terms. Additionally, the cluster allocator

accepts inputs from the wide steering logic. Using these inputs, functions up to 80 product terms can be created.

Table 4. Available Clusters for Each Macrocell

Product Term Logic Control

PTnLogic PT Single PT for XOR/OR

PTn+1 Logic PT Individual Clock (PT Clock)

PTn+2 Logic PT Individual Initialization or Individual Clock Enable (PT Initialization/CE)

PTn+3 Logic PT Individual Initialization (PT Initialization)

PTn+4 Logic PT Individual OE (PTOE)

Macrocell Available Clusters

M0 — C0 C1 C2

M1 C0 C1 C2 C3

M2 C1 C2 C3 C4

M3 C2 C3 C4 C5

M4 C3 C4 C5 C6

M5 C4 C5 C6 C7

M6 C5 C6 C7 C8

n+1

n-1

n-2

from

n-1

from

n-4

from

n+2

from

n+1

5-PT

From

n-4 1-80

PTs

To n+4

Fast 5-PT

Path

To XOR (MC)

Cluster

Individual Product

Term Allocator

Cluster

Allocator

SuperWIDE™

Steering Logic

ispMACH 4000V/B/C/Z Family Data Sheet

Wide Steering Logic

The wide steering logic allows the output of the cluster allocator n to be connected to the input of the cluster alloca-

tor n+4. Thus, cluster chains can be formed with up to 80 product terms, supporting wide product term functions

and allowing performance to be increased through a single GLB implementation. Table 5 shows the product term

chains.

Table 5. Product Term Expansion Capability

Every time the super cluster allocator is used, there is an incremental delay of tEXP. When the super cluster alloca-

tor is used, all destinations other than the one being steered to, are given the value of ground (i.e., if the super clus-

ter is steered to M (n+4), then M (n) is ground).

Macrocell

The 16 macrocells in the GLB are driven by the 16 outputs from the logic allocator. Each macrocell contains a pro-

grammable XOR gate, a programmable register/latch, along with routing for the logic and control functions.

Figure 5 shows a graphical representation of the macrocell. The macrocells feed the ORP and GRP. A direct input

from the I/O cell allows designers to use the macrocell to construct high-speed input registers. A programmable

delay in this path allows designers to choose between the fastest possible set-up time and zero hold time.

M7 C6 C7 C8 C9

M8 C7 C8 C9 C10

M9 C8 C9 C10 C11

M10 C9 C10 C11 C12

M11 C10 C11 C12 C13

M12 C11 C12 C13 C14

M13 C12 C13 C14 C15

M14 C13 C14 C15 —

M15 C14 C15 — —

Expansion

Chains

Macrocells Associated with Expansion Chain

(with Wrap Around)

Max PT/

Macrocell

Chain-0 M0 ?

M4 ?

M8 ?

M12 ?

M0 75

Chain-1 M1 ?

M5 ?

M9 ?

M13 ?

M1 80

Chain-2 M2 ?

M6 ?

M10 ?

M14 ?

M2 75

Chain-3 M3 ?

M7 ?

M11 ?

M15 ?

M3 70

Macrocell Available Clusters

ispMACH 4000V/B/C/Z Family Data Sheet

Figure 5. Macrocell

Enhanced Clock Multiplexer

The clock input to the flip-flop can select any of the four block clocks along with the shared PT clock, and true and

complement forms of the optional individual term clock. An 8:1 multiplexer structure is used to select the clock. The

eight sources for the clock multiplexer are as follows:

• Block CLK0

• Block CLK1

• Block CLK2

• Block CLK3

• PT Clock

• PT Clock Inverted

• Shared PT Clock

•Ground

Clock Enable Multiplexer

Each macrocell has a 4:1 clock enable multiplexer. This allows the clock enable signal to be selected from the fol-

lowing four sources:

• PT Initialization/CE

• PT Initialization/CE Inverted

• Shared PT Clock

• Logic High

Initialization Control

The ispMACH 4000 family architecture accommodates both block-level and macrocell-level set and reset capability.

There is one block-level initialization term that is distributed to all macrocell registers in a GLB. At the macrocell

level, two product terms can be “stolen” from the cluster associated with a macrocell to be used for set/reset func-

Single PT Block CLK0

Block CLK1

Block CLK2

Block CLK3

PT Clock (optional)

Shared PT Clock

D/T/L Q

Shared PT Initialization

PT Initialization/CE (optional)

PT Initialization (optional)

From Logic Allocator

Power-up

Initialization

To ORP

To GRP

From I/O Cell

Delay

ispMACH 4000V/B/C/Z Family Data Sheet

tionality. A reset/preset swapping feature in each macrocell allows for reset and preset to be exchanged, providing

flexibility.

Note that the reset/preset swapping selection feature affects power-up reset as well. All flip-flops power up to a

known state for predictable system initialization. If a macrocell is configured to SET on a signal from the block-level

initialization, then that macrocell will be SET during device power-up. If a macrocell is configured to RESET on a

signal from the block-level initialization or is not configured for set/reset, then that macrocell will RESET on power-

up. To guarantee initialization values, the VCC rise must be monotonic, and the clock must be inactive until the reset

delay time has elapsed.

GLB Clock Generator

Each ispMACH 4000 device has up to four clock pins that are also routed to the GRP to be used as inputs. These

pins drive a clock generator in each GLB, as shown in Figure 6. The clock generator provides four clock signals that

can be used anywhere in the GLB. These four GLB clock signals can consist of a number of combinations of the

true and complement edges of the global clock signals.

Figure 6. GLB Clock Generator

Output Routing Pool (ORP)

The Output Routing Pool allows macrocell outputs to be connected to any of several I/O cells within an I/O block.

This provides greater flexibility in determining the pinout and allows design changes to occur without affecting the

pinout. The output routing pool also provides a parallel capability for routing macrocell-level OE product terms. This

allows the OE product term to follow the macrocell output as it is switched between I/O cells. Additionally, the out-

put routing pool allows the macrocell output or true and complement forms of the 5-PT bypass signal to bypass the

output routing multiplexers and feed the I/O cell directly. The enhanced ORP of the ispMACH 4000 family consists

of the following elements:

• Output Routing Multiplexers

• OE Routing Multiplexers

• Output Routing Pool Bypass Multiplexers

Figure 7 shows the structure of the ORP from the I/O cell perspective. This is referred to as an ORP slice. Each

ORP has as many ORP slices as there are I/O cells in the corresponding I/O block.

CLK0

CLK1

CLK2

CLK3

Block CLK0

Block CLK1

Block CLK2

Block CLK3

ispMACH 4000V/B/C/Z Family Data Sheet

Figure 7. ORP Slice

Output Routing Multiplexers

The details of connections between the macrocells and the I/O cells vary across devices and within a device

dependent on the maximum number of I/Os available. Tables 5-9 provide the connection details.

Table 6. ORP Combinations for I/O Blocks with 8 I/Os

I/O Cell Available Macrocells

I/O 0 M0, M1, M2, M3, M4, M5, M6, M7

I/O 1 M2, M3, M4, M5, M6, M7, M8, M9

I/O 2 M4, M5, M6, M7, M8, M9, M10, M11

I/O 3 M6, M7, M8, M9, M10, M11, M12, M13

I/O 4 M8, M9, M10, M11, M12, M13, M14, M15

I/O 5 M10, M11, M12, M13, M14, M15, M0, M1

I/O 6 M12, M13, M14, M15, M0, M1, M2, M3

I/O 7 M14, M15, M0, M1, M2, M3, M4, M5

Output Routing Multiplexer

OE Routing Multiplexer

ORP

Bypass

Multiplexer

From Macrocell

From PTOE

To I/O

Cell

To I/O

Cell

Output

5-PT Fast Path

ispMACH 4000V/B/C/Z Family Data Sheet

Table 7. ORP Combinations for I/O Blocks with 16 I/Os

Table 8. ORP Combinations for I/O Blocks with 4 I/Os

Table 9. ORP Combinations for I/O Blocks with 10 I/Os

I/O Cell Available Macrocells

I/O 0 M0, M1, M2, M3, M4, M5, M6, M7

I/O 1 M1, M2, M3, M4, M5, M6, M7, M8

I/O 2 M2, M3, M4, M5, M6, M7, M8, M9

I/O 3 M3, M4, M5, M6, M7, M8, M9, M10

I/O 4 M4, M5, M6, M7, M8, M9, M10, M11

I/O 5 M5, M6, M7, M8, M9, M10, M11, M12

I/O 6 M6, M7, M8, M9, M10, M11, M12, M13

I/O 7 M7, M8, M9, M10, M11, M12, M13, M14

I/O 8 M8, M9, M10, M11, M12, M13, M14, M15

I/O 9 M9, M10, M11, M12, M13, M14, M15, M0

I/O 10 M10, M11, M12, M13, M14, M15, M0, M1

I/O 11 M11, M12, M13, M14, M15, M0, M1, M2

I/O 12 M12, M13, M14, M15, M0, M1, M2, M3

I/O 13 M13, M14, M15, M0, M1, M2, M3, M4

I/O 14 M14, M15, M0, M1, M2, M3, M4, M5

I/O 15 M15, M0, M1, M2, M3, M4, M5, M6

I/O Cell Available Macrocells

I/O 0 M0, M1, M2, M3, M4, M5, M6, M7

I/O 1 M4, M5, M6, M7, M8, M9, M10, M11

I/O 2 M8, M9, M10, M11, M12, M13, M14, M15

I/O 3 M12, M13, M14, M15, M0, M1, M2, M3

I/O Cell Available Macrocells

I/O 0 M0, M1, M2, M3, M4, M5, M6, M7

I/O 1 M2, M3, M4, M5, M6, M7, M8, M9

I/O 2 M4, M5, M6, M7, M8, M9, M10, M11

I/O 3 M6, M7, M8, M9, M10, M11, M12, M13

I/O 4 M8, M9, M10, M11, M12, M13, M14, M15

I/O 5 M10, M11, M12, M13, M14, M15, M0, M1

I/O 6 M12, M13, M14, M15, M0, M1, M2, M3

I/O 7 M14, M15, M0, M1, M2, M3, M4, M5

I/O 8 M2, M3, M4, M5, M6, M7, M8, M9

I/O 9 M10, M11, M12, M13, M14, M15, M0, M1

ispMACH 4000V/B/C/Z Family Data Sheet

Table 10. ORP Combinations for I/O Blocks with 12 I/Os

ORP Bypass and Fast Output Multiplexers

The ORP bypass and fast-path output multiplexer is a 4:1 multiplexer and allows the 5-PT fast path to bypass the

ORP and be connected directly to the pin with either the regular output or the inverted output. This multiplexer also

allows the register output to bypass the ORP to achieve faster tCO.

Output Enable Routing Multiplexers

The OE Routing Pool provides the corresponding local output enable (OE) product term to the I/O cell.

I/O Cell

The I/O cell contains the following programmable elements: output buffer, input buffer, OE multiplexer and bus

maintenance circuitry. Figure 8 details the I/O cell.

Figure 8. I/O Cell

Each output supports a variety of output standards dependent on the VCCO supplied to its I/O bank. Outputs can

also be configured for open drain operation. Each input can be programmed to support a variety of standards, inde-

pendent of the VCCO supplied to its I/O bank. The I/O standards supported are:

I/O Cell Available Macrocells

I/O 0 M0, M1, M2, M3, M4, M5, M6, M7

I/O 1 M1, M2, M3, M4, M5, M6, M7, M8

I/O 2 M2, M3, M4, M5, M6, M7, M8, M9

I/O 3 M4, M5, M6, M7, M8, M9, M10, M11

I/O 4 M5, M6, M7, M8, M9, M10, M11, M12

I/O 5 M6, M7, M8, M9, M10, M11, M12, M13

I/O 6 M8, M9, M10, M11, M12, M13, M14, M15

I/O 7 M9, M10, M11, M12, M13, M14, M15, M0

I/O 8 M10, M11, M12, M13, M14, M15, M0, M1

I/O 9 M12, M13, M14, M15, M0, M1, M2, M3

I/O 10 M13, M14, M15, M0, M1, M2, M3, M4

I/O 11 M14, M15, M0, M1, M2, M3, M4, M5

GOE 0

From ORP

*Global fuses

From ORP

To Macrocell

To GRP

GOE 1

GOE 2

GOE 3

VCC

VCCO

ispMACH 4000V/B/C/Z Family Data Sheet

• LVTTL • LVCMOS 1.8

• LVCMOS 3.3 • 3.3V PCI Compatible

• LVCMOS 2.5

All of the I/Os and dedicated inputs have the capability to provide a bus-keeper latch, Pull-up Resistor or Pull-down

Resistor. A fourth option is to provide none of these. The selection is done on a global basis. The default in both

hardware and software is such that when the device is erased or if the user does not specify, the input structure is

configured to be a Pull-up Resistor.

Each ispMACH 4000 device I/O has an individually programmable output slew rate control bit. Each output can be

individually configured for fast slew or slow slew. The typical edge rate difference between fast and slow slew set-

ting is 20%. For high-speed designs with long, unterminated traces, the slow-slew rate will introduce fewer reflec-

tions, less noise and keep ground bounce to a minimum. For designs with short traces or well terminated lines, the

fast slew rate can be used to achieve the highest speed.

Global OE Generation

Most ispMACH 4000 family devices have a 4-bit wide Global OE Bus, except the ispMACH 4032 device that has a

2-bit wide Global OE Bus. This bus is derived from a 4-bit internal global OE PT bus and two dual purpose I/O or

GOE pins. Each signal that drives the bus can optionally be inverted.

Each GLB has a block-level OE PT that connects to all bits of the Global OE PT bus with four fuses. Hence, for a

256-macrocell device (with 16 blocks), each line of the bus is driven from 16 OE product terms. Figures 9 and 10

show a graphical representation of the global OE generation.

Figure 9. Global OE Generation for All Devices Except ispMACH 4032

Shared PTOE

(Block 0)

Shared PTOE

(Block n)

Global

Fuses GOE (0:3)

to I/O cells

Internal Global OE

PT Bus

(4 lines)

4-Bit

Global OE Bus

Global OE

Fuse connection

Hard wired

ispMACH 4000V/B/C/Z Family Data Sheet

Figure 10. Global OE Generation for ispMACH 4032

Zero Power/Low Power and Power Management

The ispMACH 4000 family is designed with high speed low power design techniques to offer both high speed and

low power. With an advanced E2 low power cell and non sense-amplifier design approach (full CMOS logic

approach), the ispMACH 4000 family offers SuperFAST pin-to-pin speeds, while simultaneously delivering low

standby power without needing any “turbo bits” or other power management schemes associated with a traditional

sense-amplifier approach.

The zero power ispMACH 4000Z is based on the 1.8 V ispMACH 4000C family. With innovative circuit design

changes, the ispMACH 4000Z family is able to achieve the industry’s “lowest static power”.

IEEE 1149.1-Compliant Boundary Scan Testability

All ispMACH 4000 devices have boundary scan cells and are compliant to the IEEE 1149.1 standard. This allows

functional testing of the circuit board on which the device is mounted through a serial scan path that can access all

critical logic notes. Internal registers are linked internally, allowing test data to be shifted in and loaded directly onto

test nodes, or test node data to be captured and shifted out for verification. In addition, these devices can be linked

into a board-level serial scan path for more board-level testing. The test access port operates with an LVCMOS

interface that corresponds to the power supply voltage.

IEEE 1532-Compliant In-System Programming

Programming devices in-system provides a number of significant benefits including: rapid prototyping, lower inven-

tory levels, higher quality and the ability to make in-field modifications. All ispMACH 4000 devices provide In-Sys-

tem Programming (ISP™) capability through the Boundary Scan Test Access Port. This capability has been

implemented in a manner that ensures that the port remains complaint to the IEEE 1149.1 standard. By using IEEE

1149.1 as the communication interface through which ISP is achieved, users get the benefit of a standard, well-

defined interface. All ispMACH 4000 devices are also compliant with the IEEE 1532 standard.

The ispMACH 4000 devices can be programmed across the commercial temperature and voltage range. The PC-

based Lattice software facilitates in-system programming of ispMACH 4000 devices. The software takes the

JEDEC file output produced by the design implementation software, along with information about the scan chain,

and creates a set of vectors used to drive the scan chain. The software can use these vectors to drive a scan chain

Shared PTOE

(Block 0)

Shared PTOE

(Block 1)

Global

Fuses GOE (3:0)

to I/O cells

Internal Global OE

PT Bus

(2 lines)

4-Bit

Global OE Bus

Global OE

Fuse connection

Hard wired

ispMACH 4000V/B/C/Z Family Data Sheet

via the parallel port of a PC. Alternatively, the software can output files in formats understood by common auto-

mated test equipment. This equipment can then be used to program ispMACH 4000 devices during the testing of a

circuit board.

User Electronic Signature

The User Electronic Signature (UES) allows the designer to include identification bits or serial numbers inside the

device, stored in E2CMOS memory. The ispMACH 4000 device contains 32 UES bits that can be configured by the

user to store unique data such as ID codes, revision numbers or inventory control codes.

Security Bit

A programmable security bit is provided on the ispMACH 4000 devices as a deterrent to unauthorized copying of

the array configuration patterns. Once programmed, this bit defeats readback of the programmed pattern by a

device programmer, securing proprietary designs from competitors. Programming and verification are also

defeated by the security bit. The bit can only be reset by erasing the entire device.

Hot Socketing

The ispMACH 4000 devices are well-suited for applications that require hot socketing capability. Hot socketing a

device requires that the device, during power-up and down, can tolerate active signals on the I/Os and inputs with-

out being damaged. Additionally, it requires that the effects of I/O pin loading be minimal on active signals. The isp-

MACH 4000 devices provide this capability for input voltages in the range 0 V to 3.0 V.

Density Migration

The ispMACH 4000 family has been designed to ensure that different density devices in the same package have

the same pin-out. Furthermore, the architecture ensures a high success rate when performing design migration

from lower density parts to higher density parts. In many cases, it is possible to shift a lower utilization design tar-

geted for a high density device to a lower density device. However, the exact details of the final resource utilization

will impact the likely success in each case.

ispMACH 4000V/B/C/Z Family Data Sheet

Absolute Maximum Ratings1, 2, 3

ispMACH 4000C/Z ispMACH 4000B ispMACH 4000V

(1.8 V) (2.5 V) (3.3 V)

Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . .–0.5 to 2.5 V. . . . . . . . . –0.5 to 5.5 V . . . . . . . . . .–0.5 to 5.5 V

Output Supply Voltage (VCCO) . . . . . . . . . . . . . . .–0.5 to 4.5 V. . . . . . . . . –0.5 to 4.5 V . . . . . . . . . .–0.5 to 4.5 V

Input or I/O Tristate Voltage Applied4, 5 . . . . . . . . .–0.5 to 5.5 V. . . . . . . . . –0.5 to 5.5 V . . . . . . . . . .–0.5 to 5.5 V

Storage Temperature . . . . . . . . . . . . . . . . . . . . . –65 to 150 C . . . . . . . . –65 to 150 C. . . . . . . . . –65 to 150 C

Junction Temperature (Tj) with Power Applied . . –55 to 150 C . . . . . . . . –55 to 150 C. . . . . . . . . –55 to 150 C

1. Stress above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional

operation of the device at these or any other conditions above those indicated in the operational sections of this specification

is not implied.

2. Compliance with Lattice Thermal Management document is required.

3. All voltages referenced to GND.

4. Undershoot of –2 V and overshoot of (VIH (MAX) + 2 V), up to a total pin voltage of 6.0V, is permitted for a duration of < 20 ns.

5. Maximum of 64 I/Os per device with VIN > 3.6 V is allowed.

Recommended Operating Conditions

Erase Reprogram Specifications

Hot Socketing Characteristics1,2,3

Symbol Parameter Min. Max. Units

VCC

Supply Voltage for 1.8 V Devices

ispMACH 4000C 1.65 1.95 V

ispMACH 4000Z 1.7 1.9 V

ispMACH 4000Z, Extended Functional Voltage

Operation

1.61, 2

1.9 V

Supply Voltage for 2.5 V Devices 2.3 2.7 V

Supply Voltage for 3.3 V Devices 3.0 3.6 V

Junction Temperature (Commercial) 0 90 C

Junction Temperature (Industrial) -40 105 C

Junction Temperature (Extended) -40 130 C

1. Devices operating at 1.6 V can expect performance degradation up to 35%.

2. Applicable for devices with 2004 date codes and later. Contact factory for ordering instructions.

Parameter Min. Max. Units

Erase/Reprogram Cycle 1,000 — Cycles

Note: Valid over commercial temperature range.

Symbol Parameter Condition Min. Typ. Max. Units

IDK Input or I/O Leakage Current 0  VIN  3.0V, Tj = 105 °C — ±30 ±150 µA

0  VIN  3.0V, Tj = 130 °C — ±30 ±200 µA

1. Insensitive to sequence of VCC or VCCO. However, assumes monotonic rise/fall rates for VCC and VCCO, provided (VIN - VCCO)  3.6 V.

2. 0 < VCC < VCC (MAX), 0 < VCCO < VCCO (MAX).

3. IDK is additive to IPU, IPD or IBH. Device defaults to pull-up until fuse circuitry is active.

ispMACH 4000V/B/C/Z Family Data Sheet

I/O Recommended Operating Conditions

DC Electrical Characteristics

Over Recommended Operating Conditions

Standard

VCCO (V)1

Min. Max.

LVTT L 3.0 3 . 6

LVCMOS 3.3 3.0 3.6

Extended LVCMOS 3.322.7 3.6

LVCMOS 2.5 2.3 2.7

LVCMOS 1.8 1.65 1.95

PCI 3.3 3.0 3.6

1. Typical values for VCCO are the average of the min. and max. values.

2. ispMACH 4000Z only.

Symbol Parameter Condition Min. Typ. Max. Units

IIL, IIH1, 4 Input Leakage Current

(ispMACH 4000Z) 0  VIN < VCCO —0.51µA

IIH1Input High Leakage Current

(ispMACH 4000Z) VCCO < VIN  5.5 V — — 10 µA

IIL, IIH1Input Leakage Current

(ispMACH 4000V/B/C)

0  VIN  3.6 V, Tj = 105 °C — — 10 µA

0  VIN  3.6 V, Tj = 130 °C — — 15 µA

IIH1,2 Input High Leakage Current

(ispMACH 4000V/B/C)

3.6 V < VIN  5.5 V, Tj = 105 °C

3.0 V  VCCO  3.6 V ——20µA

3.6 V < VIN  5.5 V, Tj = 130 °C

3.0 V  VCCO  3.6 V ——50µA

IPU

I/O Weak Pull-up Resistor Current

(ispMACH 4000Z) 0  VIN  0.7 VCCO –30 — –150 µA

I/O Weak Pull-up Resistor Current

(ispMACH 4000V/B/C) 0  VIN  0.7 VCCO –30 — –200 µA

IPD I/O Weak Pull-down Resistor Current VIL (MAX)  VIN  VIH (MAX) 30 — 150 µA

IBHLS Bus Hold Low Sustaining Current VIN = VIL (MAX) 30 — — µA

IBHHS Bus Hold High Sustaining Current VIN = 0.7 VCCO –30 — — µA

IBHLO Bus Hold Low Overdrive Current 0 V  VIN  VBHT — — 150 µA

IBHHO Bus Hold High Overdrive Current VBHT  VIN  VCCO ——–150 µA

VBHT Bus Hold Trip Points — VCCO * 0.35 — VCCO * 0.65 V

C1I/O Capacitance3VCCO = 3.3 V, 2.5 V, 1.8 V — 8—pf

VCC = 1.8 V, VIO = 0 to VIH (MAX) — —

C2Clock Capacitance3VCCO = 3.3 V, 2.5 V, 1.8 V — 6—pf

VCC = 1.8 V, VIO = 0 to VIH (MAX) — —

C3Global Input Capacitance3VCCO = 3.3 V, 2.5 V, 1.8 V — 6—pf

VCC = 1.8 V, VIO = 0 to VIH (MAX) — —

1. Input or I/O leakage current is measured with the pin configured as an input or as an I/O with the output driver tristated. It is not

measured with the output driver active. Bus maintenance circuits are disabled.

2. 5 V tolerant inputs and I/O should only be placed in banks where 3.0 V  VCCO  3.6 V.

3. TA = 25 °C, f = 1.0 MHz

4. IIH excursions of up to 1.5 µA maximum per pin above the spec limit may be observed for certain voltage conditions on no more than 10%

of the device’s I/O pins.

ispMACH 4000V/B/C/Z Family Data Sheet

Supply Current, ispMACH 4000V/B/C

Over Recommended Operating Conditions

Symbol Parameter Condition Min. Typ. Max. Units

ispMACH 4032V/B/C

ICC1,2,3 Operating Power Supply Current

Vcc = 3.3 V — 11.8 — mA

Vcc = 2.5 V — 11.8 — mA

Vcc = 1.8 V — 1.8 — mA

ICC4Standby Power Supply Current

Vcc = 3.3 V — 11.3 — mA

Vcc = 2.5 V — 11.3 — mA

Vcc = 1.8 V — 1.3 — mA

ispMACH 4064V/B/C

ICC1,2,3 Operating Power Supply Current

Vcc = 3.3 V — 12 — mA

Vcc = 2.5 V — 12 — mA

Vcc = 1.8 V — 2 — mA

ICC5Standby Power Supply Current

Vcc = 3.3 V — 11.5 — mA

Vcc = 2.5 V — 11.5 — mA

Vcc = 1.8 V — 1.5 — mA

ispMACH 4128V/B/C

ICC1,2,3 Operating Power Supply Current

Vcc = 3.3 V — 12 — mA

Vcc = 2.5 V — 12 — mA

Vcc = 1.8 V — 2 — mA

ICC4Standby Power Supply Current

Vcc = 3.3 V — 11.5 — mA

Vcc = 2.5 V — 11.5 — mA

Vcc = 1.8 V — 1.5 — mA

ispMACH 4256V/B/C

ICC1,2,3 Operating Power Supply Current

Vcc = 3.3 V — 12.5 — mA

Vcc = 2.5 V — 12.5 — mA

Vcc = 1.8 V — 2.5 — mA

ICC4Standby Power Supply Current

Vcc = 3.3 V — 12 — mA

Vcc = 2.5 V — 12 — mA

Vcc = 1.8 V — 2 — mA

ispMACH 4384V/B/C

ICC1,2,3 Operating Power Supply Current

Vcc = 3.3 V — 13.5 — mA

Vcc = 2.5 V — 13.5 — mA

Vcc = 1.8 V — 3.5 — mA

ICC4Standby Power Supply Current

Vcc = 3.3 V — 12.5 — mA

Vcc = 2.5 V — 12.5 — mA

Vcc = 1.8 V — 2.5 — mA

ispMACH 4512V/B/C

ICC1,2,3 Operating Power Supply Current

Vcc = 3.3 V — 14 — mA

Vcc = 2.5 V — 14 — mA

Vcc = 1.8 V — 4 — mA

ispMACH 4000V/B/C/Z Family Data Sheet

ICC4Standby Power Supply Current

Vcc = 3.3 V — 13 — mA

Vcc = 2.5 V — 13 — mA

Vcc = 1.8 V — 3 — mA

1. TA = 25 °C, frequency = 1.0 MHz.

2. Device configured with 16-bit counters.

3. ICC varies with specific device configuration and operating frequency.

4. TA = 25 °C

Supply Current, ispMACH 4000Z

Over Recommended Operating Conditions

Symbol Parameter Condition Min. Typ. Max. Units

ispMACH 4032ZC

ICC1, 2, 3, 5 Operating Power Supply Current

Vcc = 1.8 V, TA = 25 °C — 50 — µA

Vcc = 1.9 V, TA = 70 °C — 58 — µA

Vcc = 1.9 V, TA = 85 °C — 60 — µA

Vcc = 1.9 V, TA = 125 °C — 70 — µA

ICC4, 5 Standby Power Supply Current

Vcc = 1.8 V, TA = 25 °C — 10 — µA

Vcc = 1.9 V, TA = 70 °C — 13 20 µA

Vcc = 1.9 V, TA = 85 °C — 15 25 µA

Vcc = 1.9 V, TA = 125 °C — 22 — µA

ispMACH 4064ZC

ICC1, 2, 3, 5 Operating Power Supply Current

Vcc = 1.8 V, TA = 25 °C — 80 — µA

Vcc = 1.9 V, TA = 70 °C — 89 — µA

Vcc = 1.9 V, TA = 85 °C — 92 — µA

Vcc = 1.9 V, TA = 125 °C — 109 — µA

ICC4, 5 Standby Power Supply Current

Vcc = 1.8 V, TA = 25 °C — 11 — µA

Vcc = 1.9 V, TA = 70 °C — 15 25 µA

Vcc = 1.9 V, TA = 85 °C — 18 35 µA

Vcc = 1.9 V, TA = 125 °C — 37 — µA

ispMACH 4128ZC

ICC1, 2, 3, 5 Operating Power Supply Current

Vcc = 1.8 V, TA = 25 °C — 168 — µA

Vcc = 1.9 V, TA = 70 °C — 190 — µA

Vcc = 1.9 V, TA = 85 °C — 195 — µA

Vcc = 1.9 V, TA = 125 °C — 212 — µA

ICC4, 5 Standby Power Supply Current

Vcc = 1.8 V, TA = 25 °C — 12 — µA

Vcc = 1.9 V, TA = 70 °C — 16 35 µA

Vcc = 1.9 V, TA = 85 °C — 19 50 µA

Vcc = 1.9 V, TA = 125 °C — 42 — µA

Supply Current, ispMACH 4000V/B/C (Cont.)

Over Recommended Operating Conditions

Symbol Parameter Condition Min. Typ. Max. Units

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4256ZC

ICC1, 2, 3, 5 Operating Power Supply Current

Vcc = 1.8 V, TA = 25 °C — 341 — µA

Vcc = 1.9 V, TA = 70 °C — 361 — µA

Vcc = 1.9 V, TA = 85 °C — 372 — µA

Vcc = 1.9 V, TA = 125 °C — 468 — µA

ICC4, 5 Standby Power Supply Current

Vcc = 1.8 V, TA = 25 °C — 13 — µA

Vcc = 1.9 V, TA = 70 °C — 32 55 µA

Vcc = 1.9 V, TA = 85 °C — 43 90 µA

Vcc = 1.9 V, TA = 125 °C — 135 — µA

1. TA = 25 °C, frequency = 1.0 MHz.

2. Device configured with 16-bit counters.

3. ICC varies with specific device configuration and operating frequency.

4. VCCO = 3.6 V, VIN = 0 V or VCCO, bus maintenance turned off. VIN above VCCO will add transient current above the specified standby ICC.

5. Includes VCCO current without output loading.

Supply Current, ispMACH 4000Z (Cont.)

Over Recommended Operating Conditions

Symbol Parameter Condition Min. Typ. Max. Units

ispMACH 4000V/B/C/Z Family Data Sheet

I/O DC Electrical Characteristics

Over Recommended Operating Conditions

Standard

VIL VIH VOL

Max (V)

VOH

Min (V)

IOL1

(mA)

IOH1

(mA)Min (V) Max (V) Min (V) Max (V)

LVTT L –0.3 0.80 2.0 5.5 0.40 VCCO - 0.40 8.0 –4.0

0.20 VCCO - 0.20 0.1 –0.1

LVCM O S 3.3 –0.3 0.80 2.0 5.5 0.40 VCCO - 0.40 8.0 –4.0

0.20 VCCO - 0.20 0.1 –0.1

LVCM O S 2.5 –0.3 0.70 1.70 3.6 0.40 VCCO - 0.40 8.0 –4.0

0.20 VCCO - 0.20 0.1 –0.1

LVCM O S 1.8

(4000V/B) –0.3 0.63 1.17 3.6 0.40 VCCO - 0.45 2.0 –2.0

0.20 VCCO - 0.20 0.1 –0.1

LVCM O S 1.8

(4000C/Z) –0.3 0.35 * VCC 0.65 * VCC 3.6 0.40 VCCO - 0.45 2.0 –2.0

0.20 VCCO - 0.20 0.1 –0.1

PCI 3.3 (4000V/B) –0.3 1.08 1.5 5.5 0.1 VCCO 0.9 VCCO 1.5 –0.5

PCI 3.3 (4000C/Z) –0.3 0.3 * 3.3 * (VCC / 1.8) 0.5 * 3.3 * (VCC / 1.8) 5.5 0.1 VCCO 0.9 VCCO 1.5 –0.5

1. The average DC current drawn by I/Os between adjacent bank GND connections, or between the last GND in an I/O bank and the end of

the I/O bank, as shown in the logic signals connection table, shall not exceed n*8mA. Where n is the number of I/Os between bank GND

connections or between the last GND in a bank and the end of a bank.

ispMACH 4000V/B/C/Z Family Data Sheet

VO Output Voltage (V)

Typical I/O Output Current (mA)

3.3 V VCCO

VO Output Voltage (V)

100

2.01.51.00.5

0 2.0 2.5 3.0 3.51.51.00.5 0 2.0 2.51.51.00.5

Typical I/O Output Current (mA)

1.8 V VCCO

VO Output Voltage (V)

IOH

Typical I/O Output Current (mA)

2.5 V VCCO

IOL

IOH

IOL

IOH

IOL