24LC01BT-I/P - Microchip Technology, Inc.

24AA01/24LC01B

Device Selection Table

Features:

• Single supply with operation down to 1.7V for

24AAXX devices, 2.5V for 24LCXX devices

• Low-power CMOS technology:

- Read current 1 mA, typical

- Standby current 1 μA, typical (I-temp)

• 2-wire serial interface, I2C™ compatible

• Schmitt Trigger in puts for noise sup pression

• Output slope control to eliminate ground bounce

• 100 kHz and 400 kHz compatibility

• Page write time 3 ms, typical

• Hardware write-protect

• ESD protection >4,000V

• More than 1 million erase/write cycles

• Data retention >200 years

• Factory programmable available

• Packages include 8-lead PDIP, SOIC, TSSOP,

DFN, MSOP and 5-lead SOT-23

• Pb-free and RoHS compliant

• Temperature ranges:

- Industrial (I): -40°C to +85°C

- Automotive (E): -40°C to +125°C

Description:

The Microchip Technology Inc. 24AA01/24LC01B

(24XX01* ) is a 1 Kb it El ect ric all y Era sable PROM. Th e

devi ce is orga nized as o ne block o f 128 x 8 -bit memor y

with a 2-wire serial interface. Low-voltage design

permit s operation down to 1.7V with st andby and ac tive

currents of only 1 μA and 1 mA, respectively. The

24XX01 also has a page write capability for up to 8

bytes of data. The 24XX01 is available in the standard

8-pin PDIP, surface mount SOIC, TSSOP, 2x3 DFN and

MSOP packages, and is also available in the 5-lead

SOT-23 package.

Package Types

Block Diagram

Part

Number VCC

Range Max. Clock

Frequency Temp.

Ranges

24AA01 1.7-5.5 400 kHz(1) I

24LC01B 2.5-5.5 400 kHz I, E

Note 1: 100 kHz for VCC <2.5V

VSS

VCC

SCL

SDA

PDIP, MSOP SOIC, TSSOP

VSS

VCC

SCL

SDA

DFN

VSS

SCL

SDA

VCC

SOT-23-5

SCL

Vss

SDA

Vcc

Note: Pins A0, A1 and A2 are not used by the 24XX01 (no

intern al connect ions).

HV Generator

EEPROM

Array

Page Latches

YDEC

XDEC

Sense Amp.

Memory

Control

Logic

I/O

Control

Logic

I/O

SDA

SCL

VCC

VSS R/W Control

1K I2C™ Serial EEPROM

24AA01/24LC01B

1.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings (†)

VCC.............................................................................................................................................................................6.5V

All inputs and outputs w.r.t. VSS ......................................................................................................... -0.3V to VCC +1.0V

Storage temperature ...............................................................................................................................-65°C to +150°C

Ambient temperature with power applied................................................................................................-40°C to +125°C

ESD protection on all pins......................................................................................................................................................≥ 4kV

TABLE 1-1: DC CHARACTERISTICS

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to

the device. This is a stress rating only and functional operation of the device at those or any other conditions

above th ose indi cated in the opera tional li stings of this sp ecificati on is no t implie d. Exposu re to maxim um rating

conditions for extended periods may affect device reliability.

DC CHARACTERISTICS Industrial (I): TA = -40°C to +85°C, VCC = +1.7V to +5.5V

Automotive (E): TA = -40°C to +125°C, VCC = +2.5V to +5.5V

Param.

No. Sym. Characteristic Min. Typ. Max. Units Conditions

D1 VIH WP, SCL and SDA pins —————

D2 — High-level input voltage 0.7 VCC ——V—

D3 VIL Low-level input voltage — — 0.3 VCC V—

D4 VHYS Hysteresis of Schmitt

Trigger inputs 0.05 VCC ——V(Note)

D5 VOL Low-level output voltage — — 0.40 V IOL = 3.0 mA, VCC = 2.5V

D6 ILI Input leakage current ——±1μAVIN = VSS or VCC

D7 ILO Output leakage cur rent ——±1μAVOUT = VSS or VCC

D8 CIN,

COUT Pin capacitance

(all inputs/ou tpu t s) ——10pFVCC = 5.0V (Note)

TA = 25°C, FCLK = 1 MHz

D9 ICC write Operating current —0.13mAVCC = 5.5V, SCL = 400 kHz

D10 ICC read — 0.05 1 mA —

D11 ICCS Standby current —

—0.01

—1

5μΑ

μΑ

Industrial

Automotive

SDA = SCL = VCC

WP = VSS

Note: This parameter is periodically sampled and not 100% tested.

24AA01/24LC01B

TABLE 1-2: AC CHARACTERISTICS

AC CHARACTERISTICS Industrial (I): TA = -40°C to +85°C, VCC = +1.7V to +5.5V

Automotive (E): TA = -40°C to +125°C, VCC = +2.5V to +5.5V

Param.

No. Sym. Characteristic Min. Typ. Max. Units Conditions

CLK Clock frequency —

——

—400

100 kHz 2.5V ≤ VCC ≤ 5.5V

1.7V ≤ VCC < 2.5V (24AA01)

HIGH Clock high time 600

4000 —

——

—ns 2.5V ≤ VCC ≤ 5.5V

1.7V ≤ VCC <2.5V (24AA01)

3TLOW Clock low time 1300

4700 —

——

—ns 2.5V ≤ VCC ≤ 5.5V

1.7V ≤ VCC < 2.5V (24AA01)

4TRSDA and SCL rise time

(Note 1) —

——

—300

1000 ns 2.5V ≤ VCC ≤ 5.5V

1.7V ≤ VCC < 2.5V (24AA01)

FSDA and SCL fall time — —

—300 ns (Note 1)

HD:STA Start condition hold time 600

4000 —

——

—ns 2.5V ≤ VCC ≤ 5.5V

1.7V ≤ VCC < 2.5V (24AA01)

7TSU:STA Start condition setup

time 600

4700 —

——

—ns 2.5V ≤ VCC ≤ 5.5V

1.7V ≤ VCC < 2.5V (24AA01)

HD:DAT Data input hold time 0 —

——ns(Note 2)

SU:DAT Data input setup time 100

250 —

——

—ns 2.5V ≤ VCC ≤ 5.5V

1.7V ≤ VCC < 2.5V (24AA01)

10 TSU:STO Stop condition setup

time 600

4000 —

——

—ns 2.5V ≤ VCC ≤ 5.5V

1.7V ≤ VCC < 2.5V (24AA01)

11 TAA Output valid from clock

(Note 2) —

——

—900

3500 ns 2.5V ≤ VCC ≤ 5.5V

1.7V ≤ VCC < 2.5V (24AA01)

12 TBUF Bus free-time: Time the

bus mu st be free befo r e

a new transmission can

start

1300

4700 —

——

—ns 2.5V ≤ VCC ≤ 5.5V

1.7V ≤ VCC < 2.5V (24AA01)

13 TOF Output fall time from VIH

minimum to VIL

maximum

20+0.1CB

——

—250

250 ns 2.5V ≤ VCC ≤ 5.5V

1.7V ≤ VCC < 2.5V (24AA01)

14 TSP Input filter spike

suppression

(SDA and SCL pins)

— — 50 ns (No tes 1 and 3)

15 TWC Write cycl e time

(byte or page) ——5ms—

16 — Endurance 1M — — cycles 25°C, (Note 4)

Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.

2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region

(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.

3: The co mbine d TSP and VHYS specifica tio ns are d ue to n ew Sc hm it t Trigger inp ut s w h ic h p rov id e i mp r oved

noise spike suppression. This eliminates the need for a TI specification for standard operation.

4: This parameter is not tested but ensured by character ization. For endurance estimates in a spe c ific

applic ation, pl ease co nsult the Total Enduran ce™ Mode l which ca n be obt ain ed from Mi crochi p’ s web site

at www.microchip.com.

24AA01/24LC01B

FIGURE 1-1: BUS TIMING DATA

FIGURE 1-2: BUS TIMING START/STOP

524

8910

14 6

SCL

SDA

OUT

Start Stop

SCL

SDA

24AA01/24LC01B

2.0 FUNCTIONAL DESCRIPTION

The 24XX01 supports a bidirectional, 2-wire bus and

data transmission protocol. A device that sends data

onto the bus is defined as transmitter, while defining a

device receiving data as a receiver. The bus has to be

controlled by a master device which generates the

Serial Clock (SCL), controls the bus access and

generates the Start and Stop conditions, while the

24XX01 works as slave. Both master and slave can

operate as transmitter or receiver, but the master

device determines which mode is activated.

3.0 BUS CHARACTERISTICS

The following bus protocol has been defined:

• Data transfer may be initiated only when the bus

is not busy.

• During data transfer, the data line must remain

stab le when ever th e clock lin e is high . Change s in

the data line while the clock line is high will be

interpreted as a Start or Stop condition.

Accordingly, the following bus conditions have been

defined (Figure 3-1).

3.1 Bus Not Busy (A)

Both data and clock lines remain high.

3.2 Start Data Transfer (B)

A high-to-low transition of the SDA line while the clock

(SCL) is high determines a Start condition. All

commands must be preceded by a Start condition.

3.3 S top Data Transfer (C)

A low-to-high transition of the SDA line while the clock

(SCL) is high determines a Stop condition. All

operations must be ended with a Stop condition.

3.4 Data Valid (D)

The state of the data line represents valid data when,

after a Start condition, the data line is stable for the

duration of the high period of the clock signal.

The data on the line must be changed during the low

period of the clock signal. There is one clock pulse per

bit of data.

Each dat a transf er is initiated w ith a S tart condition an d

terminated with a Stop condition. The number of data

bytes transferred between the Start and Stop

conditions is determined by the master device and is,

theoretically, unlimited (although only the last sixteen

will be st ored when doi ng a w rit e op erat ion ). Whe n an

overwrite does occur, it will replace data in a first-in

first-out (FIFO ) fash ion.

3.5 Acknowledge

Each receiving device, when addressed, is obliged to

generate an acknowledge after the reception of each

byte. The mast er device mus t ge nera te a n ext ra c lock

pulse which is associated with this Acknowledge bit.

The device that acknowledges has to pull down the

SDA line d uring th e ackn owledge clock pulse in such a

way that the SDA line is stable low during the high

period of the acknowledge-related clock pulse. Of

course, setup and hold times must be taken into

account. During reads, a master must signal an end of

data to t he sla ve by no t gene rating a n Ack nowledg e bit

on the las t by te that has be en c loc ke d ou t of th e sl av e.

In this c as e, the sl ave (24 XX01) will le av e th e d at a line

high to enable the master to generate the Stop

condition.

FIGURE 3-1: DAT A TRANSFER SEQUENCE ON THE SERIAL BUS

Note: The 24XX01 does not generate any

Acknowledge bits if an internal

programming cycle is in progress.

SCL

SDA

(A) (B) (D) (D) (A)(C)

Start

Condition Address or

Acknowledge

Valid

Data

Allowed

to Change

Stop

Condition

24AA01/24LC01B

3.6 Device Addressing

A control byte is the first byte received following the

S tar t condition from the mas ter device . The contro l byte

consis ts of a four -bit control c ode. For the 24XX01, thi s

is set as ‘1010’ binary for read and write operations.

The next three bits of the control byte are “don’t cares”

for the 24XX01.

The last bit of the control byte defines the operation to

be performed. When set to ‘1’, a read operation is

select ed. W hen set to ‘0’ , a write operati on is se lecte d.

Follow in g the Start condi tio n, the 24XX01 moni tors the

SDA bus, checking the device type identifier being

transmitted. Upon receiving a ‘1010’ code, the slave

device output s an Acknow ledge signal on the SDA lin e.

Depen din g on th e state of the R/W bit, the 24XX01 wil l

select a read or write operation.

FIGU RE 3-2 : CONTROL BYT E

ALLOCATION

Operation Control

Code Block Select R/W

Read 1010 Block Addre ss 1

Write 1010 Block Address 0

10 10xxx

R/W ACK

Start Bit

Read/Write Bit

x = “don’t care”

Slave Address

Acknowled ge Bit

Control Code

Block

Select

Bits

24AA01/24LC01B

4.0 WRITE OPERATION

4.1 Byte Write

Following the Start condition from the master, the

device code (4 bits), the block address (3 bits, “don’t

cares”) and the R/W bit , whic h is a lo gic low, is pla ced

onto the bus by the master transmitter . This indicates to

the addressed slave receiver that a byte with a word

address will follow after it has generated an Acknowl-

edge bit during the ninth clock cycle. Therefore, the

next byte transmitted by the master is the word address

and will be written into the Address Pointer of the

24XX01. After receiving another Acknowledge signal

from the 24XX01, the master device will transmit the

data word to be written into the addressed memory

location. The 24XX01 acknowledges again and the

master generates a Stop condition. This initiates the

internal write cycle, and, during this time, the 24XX01

will not generate Acknowledge signals (Figure 4-1).

4.2 Page Write

The write control byte, wo rd address and firs t data by te

are transmitted to the 24XX01 in the same way as in a

byte write. However, instead of generating a Stop

conditi on, the mas ter transmit s up to 8 data bytes to the

24XX01, which are temporarily stored in the on-chip

page buffer and will be written into the memory once

the master has transmitted a Stop condition. Upon

receipt of each word, the four lower-order Address

Pointer bits are internally incremented by ‘1’. The

higher-order 7 bits of the word address remain

constant. If the master should transmit more than 8

words prior to generating the Stop condition, the

address counter will roll over and the previously

receive d dat a will be overwri tten. As w ith the byte w rite

operation, once the Stop condition is received, an

internal write cycle will begin (Figure 4-2).

FIGURE 4-1: BYTE WRITE

FIGURE 4-2: PAGE WRITE

Note: Page write opera tions are l imited to wri ting

bytes within a single physical page

regardless of the number of bytes

actually being written. Physical page

boundaries start at addresses that are

integer multiples o f the page buf fer size (or

‘page siz e’ ) an d end at ad dres s es tha t a re

integer multiples of [page size – 1]. If a

Page Write command attempts to write

across a physical page boundary, the

result is that the data wraps around to the

beginning of the current page (overwriting

data previously stored there), instead of

being w ritten to the next page, as migh t be

expected. It is therefore necessary for the

application software to prevent page write

operations that would attempt to cross a

page boundary.

S P

Bus Acti vity

Master

SDA Line

Bus Activity

Control

Byte Word

Address Data

1010xxx0

x = “don’t care”

Block

Select

Bits

S P

Bus Acti vity

Master

SDA Line

Bus Acti vity

Control

Byte Word

Address (n) Data (n) Data (n + 7)

Data (n + 1)

x = “don’t care”

10 10 xxx0

Block

Select

Bits

24AA01/24LC01B

5.0 ACKNOWLEDGE POLLING

Since the device will not acknowledge during a write

cycle, this can be used to determine when the cycle is

complete (this feature can be used to maximize bus

throughput). Once the Stop condition for a Write

comma nd has been is sued from the master , the device

initiates the internally-timed write cycle. ACK polling

can then be initiated immediately. This involves the

master sending a S tart c ondition fo llowed by t he contro l

byte for a W rite command (R/W = 0). If the device is still

busy wi th the write cycle, no ACK will be returned. If the

cycle is complete, the device will return the ACK and

the master can then proceed with the next Read or

Write command. See Figure 5-1 for a flow diagram of

this operation.

FIGURE 5-1: ACKNOWLEDGE POLLING

FLOW

6.0 WRITE PROTECTION

The W P pin a llows th e user t o writ e-prote ct the entire

array (00-7F ) when the pin is tied to VCC. If tied to VSS,

the write protection is disabled.

Send

Write Command

Send Stop

Condition to

Initiate Write Cycle

Send Start

Send Control Byte

with R/W = 0

Did Device

Acknowledge

(ACK = 0)?

Operation

Yes

24AA01/24LC01B

7.0 READ OPERATION

Read operations are initiated in the same way as write

operations, with the exception that the R/W bit of the

slave address is set to ‘1’. There are three basic types

of read operat ions: current address read , rand om rea d

and sequential read.

7.1 Current Address Read

The 24XX01 contains an address counter that

maintains the address of the last word accessed,

inter nal ly i nc rem ente d by ‘ 1’. Th erefore, if the p reviou s

access (either a read or write operation) was to

address n, the next current address read operation

would access data f rom add ress n + 1 . Upon re ceipt of

the slave address with R/W bit set to ‘1’, the 24XX01

issues an acknowledge and transmits the 8-bit data

word. Th e master will not acknowle dge the transfe r , but

does generate a Stop condition and the 24XX01

discontinues transmission (Figure 7-1).

7.2 Random Read

Random read operations allow the master to access

any memory location in a random manner. To perform

this typ e of re ad ope ratio n, th e w ord add res s mus t firs t

be set. This is accomplished by sending the word

address to the 24XX01 as part of a write operation.

Once th e word address is s ent, the master ge nerates a

Start condition following the acknowledge. This

terminates the write operation, but not before the inter-

nal Address Pointer is set. The master then issues the

control byt e agai n, but wi th the R/ W bit se t to a ‘ 1’. The

24XX01 will then issue an acknowledge and transmits

the 8-bit data word. The master will not acknowledge

the transfer , but do es generate a S top condition and the

24XX01 discontinues transmission (Figure 7-2).

7.3 Sequentia l Read

Sequential reads are initiated in the same way as a

random read, except that once the 24XX01 transmits

the first data byte, the master issues an acknowledge

(as opposed to a S top condition in a random read). This

directs the 24XX01 to transmit the next sequentially

addressed 8-bit word (Figure 7-3).

To provide sequential reads the 24XX01 contains an

internal Address Pointer which is incremented by one

at the completion of each operation. This Address

Pointer allows the entire memory contents to be serially

read during one operation.

7.4 Noise Protection

The 24XX01 employs a VCC threshold detector circuit

which disables the internal erase/write logic if the VCC

is below 1.5V at nominal conditions.

The SCL and SDA inputs have Schmitt Trigger and

filter circuits which suppress noise spikes to assure

proper device operation even on a noisy bus.

FIGURE 7-1: CURRENT ADDRESS READ

Bus Activity

Master

SDA Line

Bus Activity

Control

Byte Data (n)

Block

Select

Bits

x = “don’t care”

1010

xxx1

24AA01/24LC01B

FIGURE 7-2: RANDOM READ

FIGU RE 7-3 : SEQUE NT I AL RE A D

S P

Bus Activity

Master

SDA Line

Bus Activity

Control

Byte

Word

Address (n) Control

Byte

TData (n)

x = “don’t care”

10 10 xxx01010xxx 1

Block

Select

Bits

Block

Select

Bits

Bus Activity

Master

SDA Line

Bus Activity

Control

Byte

Data (n) Data (n + 1) Data (n + 2) Data (n + x)

24AA01/24LC01B

8.0 PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 8-1.

TABLE 8-1: PIN FUNCTION TABLE

8.1 A0, A1, A2

The A0, A1 and A2 pins are not used by the 24XX01.

They may be left floating or tied to either VSS or VCC.

8.2 Serial Address/Data Input/Output

(SDA)

The SDA input is a bidirectional pin used to transfer

addresse s and data into an d out of the device . Since

it is an open-drain terminal, the SDA bus requires a

pull-up resistor to VCC (typical 10 kΩ for 100 kHz,

2kΩ fo r 40 0 kHz ).

For normal data transfer, SDA is allowed to change

only during SCL low. Changes during SCL high are

reserved for indicating Start and Stop conditions.

8.3 Serial Clock (SCL)

The SCL in put is u sed to sy nc hro niz e th e da t a tra nsfer

to and from the device.

8.4 Wr it e-Protect (WP)

This pin must be connected to either VSS or VCC.

If tied to VSS, normal memory operation is enabled

(read/wri te the ent ire memory 00-7F).

If tied to VCC, write operations are inhibited. The entire

memory will be write-protected. Read operations are

not affected.

This feature allows the user to use the 24XX01 as a

serial ROM when WP is enabled (tied to VCC).

Name PDIP SOIC TSSOP DFN MSOP SOT23 Description

A0 1 1 1 1 1 — Not Connected

A1 2 2 2 2 2 — Not Connected

A2 3 3 3 3 3 — Not Connected

VSS 4 4 4 4 4 2 Ground

SDA 5 5 5 5 5 3 Serial Address/Data I/O

SCL 6 6 6 6 6 1 Serial Clock

WP 7 7 7 7 7 5 Write-Protect Input

VCC 8 8 8 8 8 4 +1.7V to 5.5V Power Supply

24AA01/24LC01B

9.0 PACKAGING INFORMATION

9.1 Package Marking Information

XXXXXXXX

T/XXXNNN

YYWW

8-Lead PDIP (300 mil) Example:

8-Lead SOIC (3.90 mm) Example:

XXXXXXXT

XXXXYYWW

NNN

8-Lead TSSOP Example:

24LC01B

I/P 13F

0527

24LC01BI

SN 0527

13F

8-Lead MSOP Example:

XXXX

TYWW

NNN

XXXXT

YWWNNN

4L1B

I527

13F

4L1BI

52713F

5-Lead SOT-23 Example:

XXNN M13F

8-Lead 2x3 DFN

XXX

YWW

214

527

Example:

24AA01/24LC01B

Part Number

1st Line Marking Codes

TSSOP MSOP SOT-23 DFN

I Temp. E Temp. I Temp. E Temp.

24AA01 4A01 4A01T B1NN — 211 —

24LC01B 4L1B 4L1BT M1NN N1NN 214 215

Note: T = Temperature grade (I, E)

NN = Alphanumeric traceability code

Legend: XX...X Part number or part number code

T Temperature (I, E)

Y Year code (last digit of calendar year)

YY Year code (last 2 digits of calendar year)

WW Week code (week of January 1 is week ‘01’)

NNN Alphanumeric traceability code (2 characters for small packages)

Pb-free JEDEC designator for Matte Tin (Sn)

Note: For very small packages with no room for the Pb-free JEDEC designator

, the marking will only appear on the outer carton or reel label.

Note: In the event the full Mi croch ip pa rt numbe r canno t be ma rked on one line , it wil

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

Note: Please visit www.microchip.com/Pbfree for the latest information on Pb-free conversion.

*Standard OTP marking consists of Microchip part number, year code, week code, and traceability code.

24AA01/24LC01B

8-Lead Plastic Dual In-Line (P or PA) – 300 mil Body [PDIP]

otes:

. Pin 1 visual index feature may vary, but must be located with the hatched area.

. § Significant Characteristic.

. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side.

. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units INCHES

Dimension Limits MIN NOM MAX

Number of Pins N 8

Pitch e .100 BSC

Top to Seating Plane A – – .210

Molded Package Thickness A2 .115 .130 .195

Base to Seating Plane A1 .015 – –

Shoulder to Shoulder Width E .290 .310 .325

Molded Package Width E1 .240 .250 .280

Overall Length D .348 . 365 .400

Tip to Seating Plane L .115 .130 .150

Lead Thickness c .008 .010 . 015

Upper Lead Width b1 .040 .060 .070

Lower Lead Width b . 014 .018 .022

Overall Row Spacing § eB – – .430

NOTE 1

Microchip Technology Drawing C04-018

24AA01/24LC01B

8-Lead Plastic Small Outl ine (SN or OA) – Narrow, 3.90 mm Body [SOIC]

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. § Signi ficant Characteristic.

3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.

4. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units MILLIMETERS

Dimension Limits MIN NOM MAX

Number of Pins N 8

Pitch e 1.27 BSC

Overall Height A – – 1.75

Molded Package Thickness A2 1.25 – –

Standoff §A1 0.10 – 0.25

Overall Width E 6.00 BSC

Molded Package Width E 1 3.90 BSC

Overall Length D 4.90 BSC

Chamfer (optional) h 0.25 – 0.50

Foot Length L 0.40 – 1.27

Footprint L1 1.04 REF

Foot Angle φ0° – 8°

Lead Thickness c 0.17 – 0.25

Lead Width b 0.31 – 0.51

Mold Draft Angle Top α5° – 15°

Mold Draft Angle Bottom β5° – 15°

NOTE 1

12 3

Microchip Technology Drawing C04-057

24AA01/24LC01B

8-Lead Plastic Thin Shri nk Small Outline (ST) – 4.4 mm Body [TSSOP]

otes:

. Pin 1 visual index feature may vary, but must be located within the hatched area.

. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.

. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units MILLIMETERS

Dimension Limits MIN NOM MAX

Number of Pins N 8

Pitch e 0.65 BSC

Overall Height A – – 1.20

Molded Package Thickness A2 0.80 1.00 1.05

Standoff A1 0.05 – 0.15

Overall Width E 6.40 BSC

Molded Package Width E1 4.30 4.40 4.50

Molded Package Length D 2.90 3.00 3.10

Foot Length L 0.45 0.60 0.75

Footprint L1 1.00 REF

Foot Angle φ0° – 8°

Lead Thickness c 0.09 – 0.20

Lead Width b 0.19 – 0.30

NOTE 1

L1 L

Microchip Technology Drawing C04-086

24AA01/24LC01B

8-Lead Plastic Micro Small Outline Package (MS or UA) [MSOP]

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.

3. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units MILLIMETERS

Dimension Limits MIN NOM MAX

Number of Pins N 8

Pitch e 0.65 BSC

Overall Height A – – 1.10

Molded Package Thickness A2 0. 75 0.85 0.95

Standoff A1 0.00 – 0.15

Overall Width E 4.90 BSC

Molded Package Width E 1 3.00 BSC

Overall Length D 3.00 BSC

Foot Length L 0.40 0.60 0.80

Footprint L1 0.95 REF

Foot Angle φ0° – 8°

Lead Thickness c 0.08 – 0.23

Lead Width b 0.22 – 0.40

NOTE 1

L1 L

Microchip Technology Drawing C04-111

24AA01/24LC01B

5-Lead Plastic Small Outl ine Transistor (OT or CT) [SOT-23]

otes:

. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.127 mm per side.

. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units MILLIMETERS

Dimension Limits MIN NOM MAX

Number of Pins N 5

Lead Pitch e 0.95 BSC

Outside Lead Pitch e1 1.90 BSC

Overall Height A 0.90 – 1.45

Molded Package Thickness A2 0.89 – 1 .30

Standoff A1 0.00 – 0.15

Overall Width E 2.20 – 3.20

Molded Package Width E1 1.30 – 1 .80

Overall Length D 2.70 – 3.10

Foot Length L 0.10 – 0.60

Footprint L1 0.35 – 0.80

Foot Angle φ0° – 30°

Lead Thickness c 0.08 – 0.26

Lead Width b 0.20 – 0.51

123

A2 c

Microchip Technology Drawing C04-091

24AA01/24LC01B

8-Lead Plastic Dual Fla t, No Lead Package (MC) – 2x3x0.9 mm Body [DFN]

otes:

. Pin 1 visual index feature may vary, but must be located within the hatched area.

. Package may have one or more exposed tie bars at ends.

. Package is saw singulated.

. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units MILLIMETERS

Dimension Limits MIN NOM MAX

Number of Pins N 8

Pitch e 0.50 BSC

Overall Height A 0.80 0.90 1. 00

Standoff A1 0.00 0.02 0.05

Contact Thickness A3 0.20 REF

Overall Length D 2.00 BSC

Overall Width E 3.00 BSC

Exposed Pad Length D2 1.30 – 1.75

Exposed Pad Width E2 1.50 – 1.90

Contact Width b 0.18 0.25 0.30

Contact Length L 0.30 0.40 0.50

Contact-to-Exposed Pad K 0.20 – –

NOTE 1

EXPOSED PAD

NOTE 1

A3A1

NOTE 2

BOTTOM VIEW

TOP VIEW

Microchip Technology Drawing C04-123

24AA01/24LC01B

APPENDIX A: REVISIO N HIST ORY

Revision C

Corrections to Section 1.0, Electrical Characteristics.

Section 9.1, 24LC01B standard marking code.

Revision D

Added DFN package.

Revision E

Revi se d F ig ur e 3 -2 C o nt ro l B yte Al l oc at io n; Fi g ure 4- 1

Byte Write; Figure 4-2 Page Write; Section 6.0 Write

Protectio n; Figure 7-1 Curre nt Address Read ; Figure 7-

2 Random Read; Figure 7-3 Sequential Read.

Revision F (01/2007)

Revised Device Selection Table; Revised Features

Section; Changed 1.8V to 1.7V; Revised Table 1-1,

1-2, 8-1; Replaced Package Drawings; Revised

Product ID System.

Revision G (03/2007)

Replaced Package Drawings (Rev. AM).

24AA01/24LC01B

THE MICROCHIP WEB SITE

Microc hip pro vides onl ine s upport v ia our W WW site at

www.microchi p.c om . Thi s web si te i s us ed as a m ean s

to make files and information easily available to

customers. Accessible by using your favorite Internet

browser, the web site contains the following

information:

•Product Support – Data sheets and errata,

application notes and sample programs, design

resources, user’s guides and hardware support

docume nts , latest softw are releas es and archived

software

•General Technical Support – Frequently Asked

Questions (FAQ), technical support requests,

online dis cu ss io n gr oups, Micro chi p con sul tant

program member listing

•Business of Microchip – Product selector and

ordering guides, latest Microchip press releases,

listing of seminars and events, listings of

Microchip sales offices, distributors and factory

representatives

CUSTOMER CHANGE NOTIFICATION

SERVICE

Microchip’s customer notification service helps keep

customers current on Microchip products. Subscribers

will receive e-mail notification whenever there are

changes, updates, revisions or errata related to a

specif ied produ ct family or develo pment tool of interes t.

To register, access the Microchip web site at

www.microchip.com, click on Customer Change

Notification and follow the registration instructions.

CUSTOMER SUPPORT

Users of Microchip products can receive assistance

through several channels:

• Distributor or Representative

• Local Sales Office

• Field Application Engineer (FAE)

• Technical Support

• Development Systems Information Line

Customers should contact their distributor,

representative or field application engineer (FAE) for

support. Local sales offices are also available to help

customers. A listing of sales offices and locations is

included in the back of this document.

Technical s upport is a vailable through the web site

at: http://support.microchip.com

24AA01/24LC01B

READER RESPONSE

It is ou r intentio n to provide you with the b es t do cument a t ion po ss ib le to e ns ure suc c es sfu l u se of y ou r M icr oc hip pro d-

uct. If you wi sh to prov ide you r comment s on org anizatio n, clar ity, subj ect matte r , and ways i n which o ur docum entatio n

can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.

Please list the following information, and use this outline to provide us with your comments about this document.

To: Technical Publications Manager

RE: Reader Response Total Pages Sent ________

From: Name

Company

Address

City / State / ZIP / Country

Telephone: (_______) _________ - _________

Application (optional):

Would you like a reply? Y N

Device: Literature Number:

Questions:

FAX: (______) _________ - _________

DS21711G24AA01/24LC01B

1. What are the best features of this document ?

2. How does this document meet your hardware and software development needs?

3. Do you find the organization of this document easy to follow? If not, why?

4. What additions to the document do you think would enhance the structure and subject?

5. What deletions from the document could be made without affecting the overall usefulness?

6. Is there any incorrect or misleading information (what and where)?

7. How would you improve this document?

24AA01/24LC01B

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

PART NO. X/XX

PackageTemperature

Range

Device

Device: 24AA01: = 1.7V, 1 Kbit I2C™ Serial EEPROM

24AA01T: = 1.7V, 1 Kbit I2C Seria l EEPROM

(Tape and Reel)

24LC01B: = 2.5V, 1 Kbit I2C Seria l EEPROM

24LC01BT: = 2.5V, 1 Kbit I2C Seri al EEPR OM

(Tape and Reel)

Temperature

Range: I = -40°C to +85°C

E = -40°C to +125°C

Package: MC = 2x3 DFN, 8-lead

P = Plastic DIP (300 mil body), 8-lead

SN = Plastic SOIC (3.90 mm body), 8-lead

ST = Plastic TS SO P (4. 4 mm), 8-lead

MS = Plastic Micro Small Outline (MSOP), 8-lead

OT = SOT-23, 5-lead (Tape and Reel only)

Examples:

a) 24AA01-I/P: Industrial Temperature,1.7V

PDIP package

b) 24AA01-I/SN: Industrial Temperature,

1.7V, SOIC package

c) 24AA01T-I/OT: Industrial Temperature,

1.7V, SOT-23 package, tape and reel

d) 24LC01B-I/P: Industrial Temperature,

2.5V, PDIP package

e) 24LC01B-E/SN: Extended Temperature,

2.5V, SOIC package

f) 24LC01BT -I/OT: Industrial Temperature,

1.7V, SOT-23 package, tape and reel

24AA01/24LC01B

NOTES:

Information contained in this publication regarding device

applications a nd the lik e is pro vid ed only fo r yo ur c onvenien ce

and may be supers eded by updates. It is y our resp o ns i bil it y to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron,

dsPIC, KEELOQ, KEELOQ logo, microID, MPLAB, PIC,

PICmic ro, PI C START, PRO MATE, Pow e rSm a rt , rfPIC, and

SmartShunt are registered trademark s of Microchip

Technology Incorporated in the U.S.A. and other countries.

AmpLab, FilterLab, Linear Active Thermistor, Migratable

Memory, MXDEV, MXLAB, PS logo, SEEVAL, SmartSensor

and The Embedded Control Solutions Company are

registered trademarks of Microchip Technology Incorporated

in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard,

dsPICDEM, dsPICDEM.net, dsPICworks, ECAN,

ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,

In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi,

MPASM, MPLAB Certified logo, MPLIB, MPLINK, PICkit,

PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,

PowerInf o, PowerMate, PowerTool, REAL ICE , rfLAB,

rfPICDEM, Select Mode, Smart Serial, SmartTel, Total

Endurance, UNI/O, WiperLock and ZENA are trademarks of

Microchip Technology Incorporat ed in the U.S.A. and other

countries.

SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that i ts family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is c onstantly evolving. We a t Microchip are commit ted to continuously improving the code protect ion f eatures of our

products. Attempts to break Microchip’ s code protection f eature may be a violati on of t he Digit al Millennium Copyright Act. If such act s

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

T empe, Arizona, Gresham, Oregon and Mountain View , California. The

Company’s quality system processes and procedures are for its PIC®

MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial

EEPROMs, microperipherals, nonvolatile memory and analog

products. In addition, Microchip’s quality system for the design and

manufacture of development systems is ISO 9001:2000 certified.

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12/08/06