Virtex-E Extended Memory: Detailed Functional Description - Xilinx, Inc.

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Architectural Description

Virtex-E Array

The Virtex-E user-programmable gate array (see Figure 1)

comprises two major configurable elements: configurable

logic blocks (CLBs) and input/output blocks (IOBs).

• CLBs provide the functional elements for constructing

logic.

• IOBs provide the interface between the package pins

and the CLBs.

CLBs interconnect through a general routing matrix (GRM).

The GRM comprises an array of routing switches located at

the intersections of horizontal and vertical routing channels.

Each CLB nests into a VersaBlock™ that also provides local

routing resources to connect the CLB to the GRM.

The VersaRing™ I/O interface provides additional routing

resources around the periphery of the device. This routing

improves I/O routability and facilitates pin locking.

The Virtex-E architecture also includes the following circuits

that connect to the GRM:

• Dedicated block memories of 4096 bits each

• Clock DLLs for clock-distribution delay compensation

and clock domain control

• 3-State buffers (BUFTs) associated with each CLB that

drive dedicated segmentable horizontal routing resources

Values stored in static memory cells control the configurable

logic elements and interconnect resources. These values

load into the memory cells on power-up, and can reload if

necessary to change the function of the device.

Input/Output Block

The Virtex-E IOB, Figure 2, features SelectIO+™ inputs and

outputs that support a wide variety of I/O signalling stan-

dards (see Table 1).

The three IOB storage elements function either as

edge-triggered D-type flip-flops or as level-sensitive latches.

Each IOB has a clock signal (CLK) shared by the three

flip-flops and independent clock enable signals for each

flip-flop.

Virtex™-E 1.8 V Extended Memory

Field Programmable Gate Arrays

DS025-2 (v2.0) November 16, 2001 00Preliminary Product Specification

Figure 1: Virtex-E Architecture Overview

DLLDLL

IOBs

VersaRing

ds022_001_121099

CLBs

BRAMs

CLBs

BRAMs

CLBs

DLLDLL

Figure 2: Virtex-E Input/Output Block (IOB)

OBUFT

IBUF

Vref

ds022_02_091300

CLK

ICE

OCE

PAD

Programmable

Delay

Weak

Keeper

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In addition to the CLK and CE control signals, the three

flip-flops share a Set/Reset (SR). For each flip-flop, this sig-

nal can be independently configured as a synchronous Set,

a synchronous Reset, an asynchronous Preset, or an asyn-

chronous Clear.

The output buffer and all of the IOB control signals have

independent polarity controls.

All pads are protected against damage from electrostatic

discharge (ESD) and from over-voltage transients. When

PCI 3.3 V compliance is required, a conventional clamp

diode is connected to the output supply voltage, VCCO.

Optional pull-up, pull-down and weak-keeper circuits are

attached to each pad. Prior to configuration all outputs not

involved in configuration are forced into their high-imped-

ance state. The pull-down resistors and the weak-keeper

circuits are inactive, but IOs can optionally be pulled up.

The activation of pull-up resistors prior to configuration is

controlled on a global basis by the configuration mode pins.

If the pull-up resistors are not activated, all the pins are in a

high-impedance state. Consequently, external pull-up or

pull-down resistors must be provided on pins required to be

at a well-defined logic level prior to configuration.

All Virtex-E IOBs support IEEE 1149.1-compatible bound-

ary scan testing.

Input Path

The Virtex-E IOB input path routes the input signal directly

to internal logic and/ or through an optional input flip-flop.

An optional delay element at the D-input of this flip-flop elim-

inates pad-to-pad hold time. The delay is matched to the

internal clock-distribution delay of the FPGA, and when

used, assures that the pad-to-pad hold time is zero.

Each input buffer can be configured to conform to any of the

low-voltage signalling standards supported. In some of

these standards the input buffer utilizes a user-supplied

threshold voltage, VREF

. The need to supply VREF imposes

constraints on which standards can be used in close prox-

imity to each other. See "I/O Banking" on page 2.

There are optional pull-up and pull-down resistors at each

input for use after configuration. Their value is in the range

50 - 100 k

Output Path

The output path includes a 3-state output buffer that drives

the output signal onto the pad. The output signal can be

routed to the buffer directly from the internal logic or through

an optional IOB output flip-flop.

The 3-state control of the output can also be routed directly

from the internal logic or through a flip-flip that provides syn-

chronous enable and disable.

Each output driver can be individually programmed for a

wide range of low-voltage signalling standards. Each output

buffer can source up to 24 mA and sink up to 48 mA. Drive

strength and slew rate controls minimize bus transients.

In most signalling standards, the output High voltage

depends on an externally supplied VCCO voltage. The need

to supply VCCO imposes constraints on which standards

can be used in close proximity to each other. See "I/O Bank-

ing" on page 2.

An optional weak-keeper circuit is connected to each out-

put. When selected, the circuit monitors the voltage on the

pad and weakly drives the pin High or Low to match the

input signal. If the pin is connected to a multiple-source sig-

nal, the weak keeper holds the signal in its last state if all

drivers are disabled. Maintaining a valid logic level in this

way eliminates bus chatter.

Since the weak-keeper circuit uses the IOB input buffer to

monitor the input level, an appropriate VREF voltage must be

provided if the signalling standard requires one. The provi-

sion of this voltage must comply with the I/O banking rules.

I/O Banking

Some of the I/O standards described above require VCCO

and/or VREF voltages. These voltages are externally sup-

plied and connected to device pins that serve groups of

IOBs, called banks. Consequently, restrictions exist about

which I/O standards can be combined within a given bank.

Table 1: Supported I/O Standards

I/O

Standard

Output

VCCO

Input

VCCO

Input

VREF

Board

Termination

Voltage

(VTT)

LVTTL 3.3 3.3 N/A N/A

LVCMOS2 2.5 2.5 N/A N/A

LVCMOS18 1.8 1.8 N/A N/A

SSTL3 I & II 3.3 N/A 1.50 1.50

SSTL2 I & II 2.5 N/A 1.25 1.25

GTL N/A N/A 0.80 1.20

GTL+ N/A N/A 1.0 1.50

HSTL I 1.5 N/A 0.75 0.75

HSTL III & IV 1.5 N/A 0.90 1.50

CTT 3.3 N/A 1.50 1.50

AGP-2X 3.3 N/A 1.32 N/A

PCI33_3 3.3 3.3 N/A N/A

PCI66_3 3.3 3.3 N/A N/A

BLVDS & LVDS 2.5 N/A N/A N/A

LVPECL 3.3 N/A N/A N/A

Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays

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Eight I/O banks result from separating each edge of the

FPGA into two banks, as shown in Figure 3. Each bank has

multiple VCCO pins, all of which must be connected to the

same voltage. This voltage is determined by the output

standards in use.

Within a bank, output standards can be mixed only if they

use the same VCCO. Compatible standards are shown in

Table 2. GTL and GTL+ appear under all voltages because

their open-drain outputs do not depend on VCCO.

Some input standards require a user-supplied threshold

voltage, VREF

. In this case, certain user-I/O pins are auto-

matically configured as inputs for the VREF voltage. Approx-

imately one in six of the I/O pins in the bank assume this

role.

The VREF pins within a bank are interconnected internally

and consequently only one VREF voltage can be used within

each bank. All VREF pins in the bank, however, must be con-

nected to the external voltage source for correct operation.

Within a bank, inputs that require VREF can be mixed with

those that do not. However, only one VREF voltage can be

used within a bank.

In Virtex-E, input buffers with LVTTL, LVCMOS2,

LVCMOS18, PCI33_3, PCI66_3 standards are supplied by

VCCO rather than VCCINT

. For these standards, only input

and output buffers that have the same VCCO can be mixed

together.

The VCCO and VREF pins for each bank appear in the device

pin-out tables and diagrams. The diagrams also show the

bank affiliation of each I/O.

Within a given package, the number of VREF and VCCO pins

can vary depending on the size of device. In larger devices,

more I/O pins convert to VREF pins. Since these are always

a super set of the VREF pins used for smaller devices, it is

possible to design a PCB that permits migration to a larger

device if necessary. All the VREF pins for the largest device

anticipated must be connected to the VREF voltage, and not

used for I/O.

In smaller devices, some VCCO pins used in larger devices

do not connect within the package. These unconnected pins

can be left unconnected externally, or they can be con-

nected to the VCCO voltage to permit migration to a larger

device, if necessary.

Configurable Logic Block

The basic building block of the Virtex-E CLB is the logic cell

(LC). An LC includes a 4-input function generator, carry

logic, and a storage element. The output from the function

generator in each LC drives both the CLB output and the D

input of the flip-flop. Each Virtex-E CLB contains four LCs,

organized in two similar slices, as shown in Figure 4.

Figure 5 shows a more detailed view of a single slice.

Figure 3: Virtex-E I/O Banks

Table 2: Compatible Output Standards

VCCO Compatible Standards

3.3 V PCI, LVTTL, SSTL3 I, SSTL3 II, CTT, AGP, GTL,

GTL+, LVPECL

2.5 V SSTL2 I, SSTL2 II, LVCMOS2, GTL, GTL+,

BLVDS, LVDS

1.8 V LVCMOS18, GTL, GTL+

1.5 V HSTL I, HSTL III, HSTL IV, GTL, GTL+

ds022_03_121799

Bank 0

GCLK3 GCLK2

GCLK1 GCLK0

Bank 1

Bank 5 Bank 4

VirtexE

Device

Bank 7Bank 6

Bank 2Bank 3

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In addition to the four basic LCs, the Virtex-E CLB contains

logic that combines function generators to provide functions

of five or six inputs. Consequently, when estimating the

number of system gates provided by a given device, each

CLB counts as 4.5 LCs.

Look-Up Tables

Virtex-E function generators are implemented as 4-input

look-up tables (LUTs). In addition to operating as a function

generator, each LUT can provide a 16 x 1-bit synchronous

RAM. Furthermore, the two LUTs within a slice can be com-

Figure 4: 2-Slice Virtex-E CLB

Carry &

Control

Carry &

Control

Carry &

Control

Carry &

Control

LUT

CINCIN

COUT COUT

YBYB

Slice 1 Slice 0

LUT

LUT D

ds022_04_121799

Figure 5: Detailed View of Virtex-E Slice

F5IN

CLK

CIN

F5 F5

ds022_05_092000

COUT

CK WSO

WSH

BY DG

BX DI

LUT

INIT

REV

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1-800-255-7778 5

bined to create a 16 x 2-bit or 32 x 1-bit synchronous RAM,

or a 16 x 1-bit dual-port synchronous RAM.

The Virtex-E LUT can also provide a 16-bit shift register that

is ideal for capturing high-speed or burst-mode data. This

mode can also be used to store data in applications such as

Digital Signal Processing.

Storage Elements

The storage elements in the Virtex-E slice can be config-

ured either as edge-triggered D-type flip-flops or as

level-sensitive latches. The D inputs can be driven either by

the function generators within the slice or directly from slice

inputs, bypassing the function generators.

In addition to Clock and Clock Enable signals, each Slice

has synchronous set and reset signals (SR and BY). SR

forces a storage element into the initialization state speci-

fied for it in the configuration. BY forces it into the opposite

state. Alternatively, these signals can be configured to oper-

ate asynchronously. All of the control signals are indepen-

dently invertible, and are shared by the two flip-flops within

the slice.

Additional Logic

The F5 multiplexer in each slice combines the function gen-

erator outputs. This combination provides either a function

generator that can implement any 5-input function, a 4:1

multiplexer, or selected functions of up to nine inputs.

Similarly, the F6 multiplexer combines the outputs of all four

function generators in the CLB by selecting one of the

F5-multiplexer outputs. This permits the implementation of

any 6-input function, an 8:1 multiplexer, or selected func-

tions of up to 19 inputs.

Each CLB has four direct feedthrough paths, two per slice.

These paths provide extra data input lines or additional local

routing that does not consume logic resources.

Arithmetic Logic

Dedicated carry logic provides fast arithmetic carry capabil-

ity for high-speed arithmetic functions. The Virtex-E CLB

supports two separate carry chains, one per Slice. The

height of the carry chains is two bits per CLB.

The arithmetic logic includes an XOR gate that allows a

2-bit full adder to be implemented within a slice. In addition,

a dedicated AND gate improves the efficiency of multiplier

implementation.

The dedicated carry path can also be used to cascade func-

tion generators for implementing wide logic functions.

BUFTs

Each Virtex-E CLB contains two 3-state drivers (BUFTs)

that can drive on-chip busses. See "Dedicated Routing" on

page 7. Each Virtex-E BUFT has an independent 3-state

control pin and an independent input pin.

Block SelectRAM

Virtex-E FPGAs incorporate large block SelectRAM memo-

ries. These complement the Distributed SelectRAM memo-

ries that provide shallow RAM structures implemented in

CLBs.

Block SelectRAM memory blocks are organized in columns,

starting at the left (column 0) and right outside edges and

inserted every four CLB columns (see notes for smaller

devices). Each memory block is four CLBs high, and each

memory column extends the full height of the chip, immedi-

ately adjacent (to the right, except for column 0) of the CLB

column locations indicated in Table 3.

Table 4 shows the amount of block SelectRAM memory that

is available in each Virtex-E device.

Each block SelectRAM cell, as illustrated in Figure 6, is a

fully synchronous dual-ported (True Dual Port

) 4096-bit

RAM with independent control signals for each port. The

data widths of the two ports can be configured indepen-

dently, providing built-in bus-width conversion.

Table 3: CLB/Block RAM Column Locations

Virtex-E Device 04812162024283236404448525660646872768084

XCV405E

ÖÖÖÖÖÖÖ ÖÖÖÖÖÖÖ

XCV812E

ÖÖÖÖÖÖÖÖÖÖ ÖÖÖÖÖÖÖÖÖÖ

Table 4: Virtex-E Block SelectRAM Amounts

Virtex-E Device # of Blocks Block SelectRAM Bits

XCV405E 140 573,440

XCV812E 280 1,146,880

Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays

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Table 5 shows the depth and width aspect ratios for the

block SelectRAM. The Virtex-E block SelectRAM also

includes dedicated routing to provide an efficient interface

with both CLBs and other block SelectRAM modules.

Programmable Routing Matrix

It is the longest delay path that limits the speed of any

worst-case design. Consequently, the Virtex-E routing

architecture and its place-and-route software were defined

in a joint optimization process. This joint optimization mini-

mizes long-path delays, and consequently, yields the best

system performance.

The joint optimization also reduces design compilation

times because the architecture is software-friendly. Design

cycles are correspondingly reduced due to shorter design

iteration times.

Local Routing

The VersaBlock, shown in Figure 7, provides local routing

resources with the following types of connections:

•Interconnections among the LUTs, flip-flops, and GRM

•Internal CLB feedback paths that provide high-speed

connections to LUTs within the same CLB, chaining

them together with minimal routing delay

•Direct paths that provide high-speed connections

between horizontally adjacent CLBs, eliminating the

delay of the GRM

General Purpose Routing

Most Virtex-E signals are routed on the general purpose

routing, and consequently, the majority of interconnect

resources are associated with this level of the routing hier-

archy. The general routing resources are located in horizon-

tal and vertical routing channels associated with the CLB

rows and columns. The general-purpose routing resources

are listed below.

•Adjacent to each CLB is a General Routing Matrix

(GRM). The GRM is the switch matrix through which

horizontal and vertical routing resources connect, and

is also the means by which the CLB gains access to

the general purpose routing.

•24 single-length lines route GRM signals to adjacent

GRMs in each of the four directions.

•72 buffered Hex lines route GRM signals to another

GRMs six-blocks away in each one of the four

directions. Organized in a staggered pattern, Hex lines

are driven only at their endpoints. Hex-line signals can

be accessed either at the endpoints or at the midpoint

(three blocks from the source). One third of the Hex

lines are bidirectional, while the remaining ones are

uni-directional.

•12 Longlines are buffered, bidirectional wires that

distribute signals across the device quickly and

efficiently. Vertical Longlines span the full height of the

device, and horizontal ones span the full width of the

device.

I/O Routing

Virtex-E devices have additional routing resources around

their periphery that form an interface between the CLB array

and the IOBs. This additional routing, called the VersaRing,

facilitates pin-swapping and pin-locking, such that logic

redesigns can adapt to existing PCB layouts. Time-to-mar-

ket is reduced, since PCBs and other system components

can be manufactured while the logic design is still in

progress.

Figure 6: Dual-Port Block SelectRAM

Table 5: Block SelectRAM Port Aspect Ratios

Width Depth ADDR Bus Data Bus

1 4096 ADDR<11:0> DATA<0>

2 2048 ADDR<10:0> DATA<1:0>

4 1024 ADDR<9:0> DATA<3:0>

8 512 ADDR<8:0> DATA<7:0>

16 256 ADDR<7:0> DATA<15:0>

WEB

ENB

RSTB

CLKB

ADDRB[#:0]

DIB[#:0]

WEA

ENA

RSTA

CLKA

ADDRA[#:0]

DIA[#:0]

DOA[#:0]

DOB[#:0]

RAMB4_S#_S#

ds022_06_121699

Figure 7: Virtex-E Local Routing

XCVE_ds_007

CLB

GRM

Adjacent

GRM

To Adjacent

GRM

Direct

Connection

To Adjacent

CLB

To Adjacent

GRM

To Adjacent

GRM

Direct Connection

To Adjacent

CLB

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Dedicated Routing

Some signal classes require dedicated routing resources to

maximize performance. In the Virtex-E architecture, dedi-

cated routing resources are provided for two signal classes.

•Horizontal routing resources are provided for on-chip

3-state busses. Four partitionable bus lines are

provided per CLB row, permitting multiple busses

within a row, as shown in Figure 8.

•Two dedicated nets per CLB propagate carry signals

vertically to the adjacent CLB. Global Clock Distribution

Network.

•DLL Location

Clock Routing

Clock Routing resources distribute clocks and other signals

with very high fanout throughout the device. Virtex-E

devices include two tiers of clock routing resources referred

to as global and local clock routing resources.

•The global routing resources are four dedicated global

nets with dedicated input pins that are designed to

distribute high-fanout clock signals with minimal skew.

Each global clock net can drive all CLB, IOB, and block

RAM clock pins. The global nets can be driven only by

global buffers. There are four global buffers, one for

each global net.

•The local clock routing resources consist of 24

backbone lines, 12 across the top of the chip and 12

across bottom. From these lines, up to 12 unique

signals per column can be distributed via the 12

longlines in the column. These local resources are

more flexible than the global resources since they are

not restricted to routing only to clock pins.

Global Clock Distribution

Virtex-E provides high-speed, low-skew clock distribution

through the global routing resources described above. A

typical clock distribution net is shown in Figure 9.

Four global buffers are provided, two at the top center of the

device and two at the bottom center. These drive the four

global nets that in turn drive any clock pin.

Four dedicated clock pads are provided, one adjacent to

each of the global buffers. The input to the global buffer is

selected either from these pads or from signals in the gen-

eral purpose routing.

Digital Delay-Locked Loops

There are eight DLLs (Delay-Locked Loops) per device,

with four located at the top and four at the bottom,

Figure 10. The DLLs can be used to eliminate skew

between the clock input pad and the internal clock input pins

throughout the device. Each DLL can drive two global clock

networks.The DLL monitors the input clock and the distrib-

uted clock, and automatically adjusts a clock delay element.

Additional delay is introduced such that clock edges arrive

at internal flip-flops synchronized with clock edges arriving

at the input.

In addition to eliminating clock-distribution delay, the DLL

provides advanced control of multiple clock domains. The

Figure 8: BUFT Connections to Dedicated Horizontal Bus LInes

CLB CLB CLB CLB

buft_c.eps

Tri-State

Lines

Figure 9: Global Clock Distribution Network

Global Clock Spine

Global Clock Column

GCLKPAD2

GCLKBUF2

GCLKPAD3

GCLKBUF3

GCLKBUF1

GCLKPAD1

GCLKBUF0

GCLKPAD0

Global Clock Rows

XCVE_009

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DLL provides four quadrature phases of the source clock,

and can double the clock or divide the clock by 1.5, 2, 2.5, 3,

4, 5, 8, or 16.

The DLL also operates as a clock mirror. By driving the output

from a DLL off-chip and then back on again, the DLL can be

used to de-skew a board level clock among multiple devices.

In order to guarantee that the system clock is operating cor-

rectly prior to the FPGA starting up after configuration, the

DLL can delay the completion of the configuration process

until after it has achieved lock.

For more information about DLL functionality, see the

Design Consideration section of the data sheet.

Boundary Scan

Virtex-E devices support all the mandatory boundary-scan

instructions specified in the IEEE standard 1149.1. A Test

Access Port (TAP) and registers are provided that imple-

ment the EXTEST, INTEST, SAMPLE/PRELOAD, BYPASS,

IDCODE, USERCODE, and HIGHZ instructions. The TAP

also supports two internal scan chains and configura-

tion/readback of the device.

The JTAG input pins (TDI, TMS, TCK) do not have a VCCO

requirement, and operate with either 2.5 V or 3.3 V input

signalling levels. The output pin (TDO) is sourced from the

VCCO in bank 2, and for proper operation of LVTTL 3.3 V

levels, the bank should be supplied with 3.3 V.

Boundary-scan operation is independent of individual IOB

configurations, and unaffected by package type. All IOBs,

including un-bonded ones, are treated as independent

3-state bidirectional pins in a single scan chain. Retention of

the bidirectional test capability after configuration facilitates

the testing of external interconnections.

Table 6 lists the boundary-scan instructions supported in

Virtex-E FPGAs. Internal signals can be captured during

EXTEST by connecting them to un-bonded or unused IOBs.

They can also be connected to the unused outputs of IOBs

defined as unidirectional input pins.

Before the device is configured, all instructions except

USER1 and USER2 are available. After configuration, all

instructions are available. During configuration, it is recom-

mended that those operations using the boundary-scan

performed.

In addition to the test instructions outlined above, the

boundary-scan circuitry can be used to configure the

FPGA, and also to read back the configuration data.

Figure 10: DLL Locations

XCVE_0010

DLLDLL

Primary DLLs

Secondary DLLs

DLLDLL

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Figure 11 is a diagram of the Virtex-E Series boundary scan logic. It includes three bits of Data Register per IOB, the IEEE

1149.1 Test Access Port controller, and the Instruction Register with decodes.

Figure 11: Virtex-E Family Boundary Scan Logic

D Q

IOB

BYPASS

IOB IOB

TDO

TDI

IOB IOB IOB

D Q

IOB

D Q

0DQ

IOB.T

DATA IN

IOB.I

IOB.Q

IOB.T

IOB.I

SHIFT/

CAPTURE CLOCK DATA

DATAOUT UPDATE EXTEST

X9016

INSTRUCTION REGISTER

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Instruction Set

The Virtex-E Series boundary scan instruction set also

includes instructions to configure the device and read back

configuration data (CFG_IN, CFG_OUT, and JSTART). The

complete instruction set is coded as shown in Table 6.

Data Registers

The primary data register is the boundary scan register. For

each IOB pin in the FPGA, bonded or not, it includes three

bits for In, Out, and 3-State Control. Non-IOB pins have

appropriate partial bit population if input-only or output-only.

Each EXTEST CAPTURED-OR state captures all In, Out,

and 3-state pins.

The other standard data register is the single flip-flop

BYPASS register. It synchronizes data being passed

through the FPGA to the next downstream boundary scan

device.

The FPGA supports up to two additional internal scan

chains that can be specified using the BSCAN macro. The

macro provides two user pins (SEL1 and SEL2) which are

decodes of the USER1 and USER2 instructions respec-

tively. For these instructions, two corresponding pins (T

DO1 and TDO2) allow user scan data to be shifted out of

TDO.

Likewise, there are individual clock pins (DRCK1 and

DRCK2) for each user register. There is a common input pin

(TDI) and shared output pins that represent the state of the

TAP controller (RESET, SHIFT, and UPDATE).

Bit Sequence

The order within each IOB is: In, Out, 3-State. The

input-only pins contribute only the In bit to the boundary

scan I/O data register, while the output-only pins contributes

all three bits.

From a cavity-up view of the chip (as shown in EPIC), start-

ing in the upper right chip corner, the boundary scan

data-register bits are ordered as shown in Figure 12.

BSDL (Boundary Scan Description Language) files for Vir-

tex-E Series devices are available on the Xilinx web site in

the File Download area.

Table 6: Boundary Scan Instructions

Boundary-Scan

Command

Binary

Code (4:0) Description

EXTEST 00000 Enable boundary-scan

EXTEST operation.

SAMPLE/

PRELOAD

00001 Enable boundary-scan

SAMPLE/PRELOAD

operation.

USER1 00010 Access user-defined

USER2 00011 Access user-defined

CFG_OUT 00100 Access the

configuration bus for

read operations.

CFG_IN 00101 Access the

configuration bus for

write operations.

INTEST 00111 Enable boundary-scan

INTEST operation.

USERCODE 01000 Enable shifting out

USER code.

IDCODE 01001 Enable shifting out of ID

Code.

HIGHZ 01010 3-state output pins while

enabling the Bypass

JSTART 01100 Clock the start-up

sequence when

StartupClk is TCK.

BYPASS 11111 Enable BYPASS.

RESERVED All other

codes

Xilinx reserved

instructions.

Figure 12: Boundary Scan Bit Sequence

Bit 0 ( TDO end)

Bit 1

Bit 2

Right half of top-edge IOBs (Right to Left)

GCLK2

GCLK3

Left half of top-edge IOBs (Right to Left)

Left-edge IOBs (Top to Bottom)

Left half of bottom-edge IOBs (Left to Right)

GCLK1

GCLK0

Right half of bottom-edge IOBs (Left to Right)

DONE

PROG

Right-edge IOBs (Bottom to Top)

CCLK

(TDI end)

990602001

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Identification Registers

The IDCODE register is supported. By using the IDCODE,

the device connected to the JTAG port can be determined.

The IDCODE register has the following binary format:

vvvv:ffff:fffa:aaaa:aaaa:cccc:cccc:ccc1

where

v = the die version number

f = the family code (05 for Virtex-E family)

a = the number of CLB rows (ranges from 16 for

XCV50E to 104 for XCV3200E)

c = the company code (49h for Xilinx)

The USERCODE register is supported. By using the USER-

CODE, a user-programmable identification code can be

loaded and shifted out for examination. The identification

code (see Table 7) is embedded in the bitstream during bit-

stream generation and is valid only after configuration.

Note:

Attempting to load an incorrect bitstream causes

configuration to fail and can damage the device.

Including Boundary Scan in a Design

Since the boundary scan pins are dedicated, no special ele-

ment needs to be added to the design unless an internal

data register (USER1 or USER2) is desired.

If an internal data register is used, insert the boundary scan

symbol and connect the necessary pins as appropriate.

Development System

Virtex-E FPGAs are supported by the Xilinx Foundation and

Alliance Series CAE tools. The basic methodology for Vir-

tex-E design consists of three interrelated steps: design

entry, implementation, and verification. Industry-standard

tools are used for design entry and simulation (for example,

Synopsys FPGA Express), while Xilinx provides proprietary

architecture-specific tools for implementation.

The Xilinx development system is integrated under the Xil-

inx Design Manager (XDM™) software, providing designers

with a common user interface regardless of their choice of

entry and verification tools. The XDM software simplifies the

selection of implementation options with pull-down menus

and on-line help.

Application programs ranging from schematic capture to

Placement and Routing (PAR) can be accessed through the

XDM software. The program command sequence is gener-

ated prior to execution, and stored for documentation.

Several advanced software features facilitate Virtex-E design.

RPMs, for example, are schematic-based macros with relative

location constraints to guide their placement. They help

ensure optimal implementation of common functions.

For HDL design entry, the Xilinx FPGA Foundation develop-

ment system provides interfaces to the following synthesis

design environments.

•Synopsys (FPGA Compiler, FPGA Express)

•Exemplar (Spectrum)

•Synplicity (Synplify)

For schematic design entry, the Xilinx FPGA Foundation

and Alliance development system provides interfaces to the

following schematic-capture design environments.

•Mentor Graphics V8 (Design Architect, QuickSim II)

•Viewlogic Systems (Viewdraw)

Third-party vendors support many other environments.

A standard interface-file specification, Electronic Design

Interchange Format (EDIF), simplifies file transfers into and

out of the development system.

Virtex-E FPGAs are supported by a unified library of stan-

dard functions. This library contains over 400 primitives and

macros, ranging from 2-input AND gates to 16-bit accumu-

lators, and includes arithmetic functions, comparators,

counters, data registers, decoders, encoders, I/O functions,

latches, Boolean functions, multiplexers, shift registers, and

barrel shifters.

The “soft macro” portion of the library contains detailed

descriptions of common logic functions, but does not con-

tain any partitioning or placement information. The perfor-

mance of these macros depends, therefore, on the

partitioning and placement obtained during implementation.

RPMs, on the other hand, do contain predetermined parti-

tioning and placement information that permits optimal

implementation of these functions. Users can create their

own library of soft macros or RPMs based on the macros

and primitives in the standard library.

The design environment supports hierarchical design entry,

with high-level schematics that comprise major functional

blocks, while lower-level schematics define the logic in

these blocks. These hierarchical design elements are auto-

matically combined by the implementation tools. Different

design entry tools can be combined within a hierarchical

design, thus allowing the most convenient entry method to

be used for each portion of the design.

Design Implementation

The place-and-route tools (PAR) automatically provide the

implementation flow described in this section. The parti-

tioner takes the EDIF net list for the design and maps the

logic into the architectural resources of the FPGA (CLBs

and IOBs, for example). The placer then determines the

best locations for these blocks based on their interconnec-

Table 7: IDCODEs Assigned to Virtex-E FPGAs

FPGA IDCODE

XCV405EM v0C28093h

XCV812EM v0C38093h

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tions and the desired performance. Finally, the router inter-

connects the blocks.

The PAR algorithms support fully automatic implementation

of most designs. For demanding applications, however, the

user can exercise various degrees of control over the pro-

cess. User partitioning, placement, and routing information

is optionally specified during the design-entry process. The

implementation of highly structured designs can benefit

greatly from basic floor planning.

The implementation software incorporates Timing Wizard®

timing-driven placement and routing. Designers specify tim-

ing requirements along entire paths during design entry.

The timing path analysis routines in PAR then recognize

these user-specified requirements and accommodate them.

Timing requirements are entered on a schematic in a form

directly relating to the system requirements, such as the tar-

geted clock frequency, or the maximum allowable delay

between two registers. In this way, the overall performance

of the system along entire signal paths is automatically tai-

lored to user-generated specifications. Specific timing infor-

mation for individual nets is unnecessary.

Design Verification

In addition to conventional software simulation, FPGA users

can use in-circuit debugging techniques. Because Xilinx

devices are infinitely reprogrammable, designs can be veri-

fied in real time without the need for extensive sets of soft-

ware simulation vectors.

The development system supports both software simulation

and in-circuit debugging techniques. For simulation, the

system extracts the post-layout timing information from the

design database, and back-annotates this information into

the net list for use by the simulator. Alternatively, the user

can verify timing-critical portions of the design using the

TRCE® static timing analyzer.

For in-circuit debugging, an optional download and read-

back cable is available. This cable connects the FPGA in the

target system to a PC or workstation. After downloading the

design into the FPGA, the designer can single-step the

logic, readback the contents of the flip-flops, and so observe

the internal logic state. Simple modifications can be down-

loaded into the system in a matter of minutes.

Configuration

Virtex-E devices are configured by loading configuration

data into the internal configuration memory. Note that

attempting to load an incorrect bitstream causes configura-

tion to fail and can damage the device.

Some of the pins used for configuration are dedicated pins,

while others can be re-used as general purpose inputs and

outputs once configuration is complete.

The following are dedicated pins:

•Mode pins (M2, M1, M0)

•Configuration clock pin (CCLK)

•PROGRAM pin

•DONE pin

•Boundary-scan pins (TDI, TDO, TMS, TCK)

Depending on the configuration mode chosen, CCLK can

be an output generated by the FPGA, or it can be generated

externally and provided to the FPGA as an input. For correct

operation, these pins require a VCCO of 3.3 V to permit

LVTTL operation. All of the pins affected are in banks 2 or 3.

Configuration Modes

Virtex-E supports the following four configuration modes.

•Slave-serial mode

•Master-serial mode

•SelectMAP mode

•Boundary-scan mode (JTAG)

The Configuration mode pins (M2, M1, M0) select among

these configuration modes with the option in each case of

having the IOB pins either pulled up or left floating prior to

configuration. The selection codes are listed in Table 8.

Configuration through the boundary-scan port is always

available, independent of the mode selection. Selecting the

boundary-scan mode simply turns off the other modes. The

three mode pins have internal pull-up resistors, and default

to a logic High if left unconnected.

Table 8: Configuration Codes

Configuration Mode M2 M1 M0 CCLK Direction Data Width Serial Dout Configuration Pull-ups

Master-serial mode 0 0 0 Out 1 Yes No

Boundary-scan mode 1 0 1 N/A 1 No No

SelectMAP mode 1 1 0 In 8 No No

Slave-serial mode 1 1 1 In 1 Yes No

Master-serial mode 1 0 0 Out 1 Yes Yes

Boundary-scan mode 0 0 1 N/A 1 No Yes

SelectMAP mode 0 1 0 In 8 No Yes

Slave-serial mode 0 1 1 In 1 Yes Yes

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1-800-255-7778 13

Table 9 lists the total number of bits required to configure

each device.

Slave-Serial Mode

In slave-serial mode, the FPGA receives configuration data

in bit-serial form from a serial PROM or other source of

serial configuration data. The serial bitstream must be set

up at the DIN input pin a short time before each rising edge

of an externally generated CCLK.

For more information on serial PROMs, see the PROM data

sheet at http://www.xilinx.com/partinfo/ds026.pdf.

Multiple FPGAs can be daisy-chained for configuration from

a single source. After a particular FPGA has been config-

ured, the data for the next device is routed to the DOUT pin.

Data on the DOUT pin changes on the rising edge of CCLK.

The change of DOUT on the rising edge of CCLK differs

from previous families but does not cause a problem for

mixed configuration chains. This change was made to

improve serial configuration rates for Virtex and Virtex-E

only chains.

Figure 13 shows a full master/slave system. A Virtex-E

device in slave-serial mode should be connected as shown

in the right-most device.

Slave-serial mode is selected by applying <111> or <011>

to the mode pins (M2, M1, M0). A weak pull-up on the mode

pins makes slave-serial the default mode if the pins are left

unconnected. Figure 14 shows slave-serial configuration

timing.

Table 10 provides more detail about the characteristics

shown in Figure 14. Configuration must be delayed until the

INIT pins of all daisy-chained FPGAs are High.

Table 9: Virtex-E Bitstream Lengths

Device # of Configuration Bits

XCV405E 3,430,400

XCV812E 6,519,648

Table 10: Master/Slave Serial Mode Programming Switching

Description

Figure

References Symbol Values Units

CCLK

DIN setup/hold, slave mode 1/2 TDCC/TCCD 5.0/0.0 ns, min

DIN setup/hold, master mode 1/2 TDSCK/TCKDS 5.0/0.0 ns, min

DOUT 3T

CCO 12.0 ns, max

High time 4T

CCH 5.0 ns, min

Low time 5T

CCL 5.0 ns, min

Maximum Frequency FCC 66 MHz, max

Frequency Tolerance, master mode with respect to nominal +45% –30%

Figure 13: Master/Slave Serial Mode Circuit Diagram

VIRTEX-E

MASTER

SERIAL VIRTEX-E,

XC4000XL,

SLAVE

XC1701L

PROGRAM

M0 M1

DOUT

CCLK CLK

3.3V

DATA

CE CEO

RESET/OE DONE

DIN

INIT INIT

DONE

PROGRAM PROGRAM

CCLK

DIN DOUT

M0 M1

(Low Reset Option Used)

4.7 K

XCVE_ds_013

N/C

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14 1-800-255-7778

Master-Serial Mode

In master-serial mode, the CCLK output of the FPGA drives

a Xilinx Serial PROM that feeds bit-serial data to the DIN

input. The FPGA accepts this data on each rising CCLK

edge. After the FPGA has been loaded, the data for the next

device in a daisy-chain is presented on the DOUT pin after

the rising CCLK edge.

The interface is identical to slave-serial except that an inter-

nal oscillator is used to generate the configuration clock

(CCLK). A wide range of frequencies can be selected for

CCLK which always starts at a slow default frequency. Con-

figuration bits then switch CCLK to a higher frequency for

the remainder of the configuration. Switching to a lower fre-

quency is prohibited.

The CCLK frequency is set using the ConfigRate option in

the bitstream generation software. The maximum CCLK fre-

quency that can be selected is 60 MHz. When selecting a

CCLK frequency, ensure that the serial PROM and any

daisy-chained FPGAs are fast enough to support the clock

rate.

On power-up, the CCLK frequency is approximately

2.5 MHz. This frequency is used until the ConfigRate bits

have been loaded when the frequency changes to the

selected ConfigRate. Unless a different frequency is speci-

fied in the design, the default ConfigRate is 4 MHz.

Figure 13 shows a full master/slave system. In this system,

the left-most device operates in master-serial mode. The

remaining devices operate in slave-serial mode. The SPROM

RESET pin is driven by INIT, and the CE input is driven by

DONE. There is the potential for contention on the DONE pin,

depending on the start-up sequence options chosen.

The sequence of operations necessary to configure a

Virtex-E FPGA serially appears in Figure 15.

Figure 16 shows the timing of master-serial configuration.

Master-serial mode is selected by a <000> or <100> on the

mode pins (M2, M1, M0). Table 10 shows the timing infor-

mation for Figure 16

Figure 14: Slave-Serial Mode Programming Switching Characteristics

4TCCH

3TCCO

5TCCL

2TCCD

1TDCC

DIN

CCLK

DOUT

(Output)

X5379_a

Figure 15: Serial Configuration Flowchart

Apply Power

Set PROGRAM = High

Release INIT If used to delay

configuration

Load a Configuration Bit

High

Low

FPGA makes a final

clearing pass and releases

INIT when finished.

FPGA starts to clear

configuration memory.

ds009_15_111799

Configuration Completed

End of

Bitstream?

Yes

Once per bitstream,

FPGA checks data using CRC

and pulls INIT Low on error.

If no CRC errors found,

FPGA enters start-up phase

causing DONE to go High.

INIT?

Figure 16: Master-Serial Mode Programming Switching Characteristics

Serial Data In

CCLK

(Output)

Serial DOUT

(Output)

1TDSCK

TCKDS

DS022_44_071201

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At power-up, VCC must rise from 1.0 V to VCC min in less

than 50 ms, otherwise delay configuration by pulling

PROGRAM Low until VCC is valid.

SelectMAP Mode

The SelectMAP mode is the fastest configuration option.

Byte-wide data is written into the FPGA with a BUSY flag

controlling the flow of data.

An external data source provides a byte stream, CCLK, a

Chip Select (CS) signal and a Write signal (WRITE). If

BUSY is asserted (High) by the FPGA, the data must be

held until BUSY goes Low.

Data can also be read using the SelectMAP mode. If

WRITE is not asserted, configuration data is read out of the

FPGA as part of a readback operation.

After configuration, the pins of the SelectMAP port can be

used as additional user I/O. Alternatively, the port can be

retained to permit high-speed 8-bit readback.

Retention of the SelectMAP port is selectable on a

design-by-design basis when the bitstream is generated. If

retention is selected, PROHIBIT constraints are required to

prevent SelectMAP-port pins from being used as user I/O.

Multiple Virtex-E FPGAs can be configured using the

SelectMAP mode, and be made to start-up simultaneously.

To configure multiple devices in this way, wire the individual

CCLK, Data, WRITE, and BUSY pins of all the devices in

parallel. The individual devices are loaded separately by

asserting the CS pin of each device in turn and writing the

appropriate data. See Table 11 for SelectMAP Write Timing

Characteristics.

Write

Write operations send packets of configuration data into the

FPGA. The sequence of operations for a multi-cycle write

operation is shown below. Note that a configuration packet

can be split into many such sequences. The packet does

not have to complete within one assertion of CS, illustrated

in Figure 17.

1. Assert WRITE and CS Low. Note that when CS is

asserted on successive CCLKs, WRITE must remain

either asserted or de-asserted. Otherwise an abort is

initiated, as described below.

2. Drive data onto D[7:0]. Note that to avoid contention,

the data source should not be enabled while CS is Low

and WRITE is High. Similarly, while WRITE is High, no

more that one CS should be asserted.

3. At the rising edge of CCLK: If BUSY is Low, the data is

accepted on this clock. If BUSY is High (from a previous

write), the data is not accepted. Acceptance instead

occurs on the first clock after BUSY goes Low, and the

data must be held until this has happened.

4. Repeat steps 2 and 3 until all the data has been sent.

5. De-assert CS and WRITE.

Table 11: SelectMAP Write Timing Characteristics

Description Symbol Values Units

CCLK

D0-7 Setup/Hold 1/2 TSMDCC/TSMCCD 5.0 / 1.0 ns, min

CS Setup/Hold 3/4 TSMCSCC/TSMCCCS 7.0 / 1.0 ns, min

WRITE Setup/Hold 5/6 TSMCCW/TSMWCC 7.0 / 1.0 ns, min

BUSY Propagation Delay 7 TSMCKBY 12.0 ns, max

Maximum Frequency FCC 66 MHz, max

Maximum Frequency with no handshake FCCNH 50 MHz, max

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A flowchart for the write operation appears in Figure 18.

Note that if CCLK is slower than fCCNH, the FPGA never

asserts BUSY, In this case, the above handshake is unnec-

essary, and data can simply be entered into the FPGA every

CCLK cycle.

Abort

During a given assertion of CS, the user cannot switch from

a write to a read, or vice-versa. This action causes the cur-

rent packet command to be aborted. The device remains

BUSY until the aborted operation has completed. Following

an abort, data is assumed to be unaligned to word bound-

aries, and the FPGA requires a new synchronization word

prior to accepting any new packets.

To initiate an abort during a write operation, de-assert

WRITE. At the rising edge of CCLK, an abort is initiated, as

shown in Figure 19.

Figure 17: Write Operations

DS022_45_071201

CCLK

No Write Write No Write Write

DATA[7:0]

WRITE

BUSY

Figure 18: SelectMAP Flowchart for Write Operations

Apply Power

Set PROGRAM = High

Release INIT If used to delay

configuration

On first FPGA

Set WRITE = Low

Enter Data Source

Set CS = Low

On first FPGA

Set CS = High

Apply Configuration Byte

INIT?

High

Low

Busy?

Low

High

Disable Data Source

Set WRITE = High

When all DONE pins

are released, DONE goes High

and start-up sequences complete.

If no errors,

later FPGAs enter start-up phase

releasing DONE.

If no errors,

first FPGAs enter start-up phase

releasing DONE.

Once per bitstream,

FPGA checks data using CRC

and pulls INIT Low on error.

FPGA makes a final

clearing pass and releases

INIT when finished.

FPGA starts to clear

configuration memory.

For any other FPGAs

ds009_18_111799

Repeat Sequence A

Configuration Completed

Sequence A

End of Data?

Yes

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Boundary-Scan Mode

In the boundary-scan mode, no non-dedicated pins are

required, configuration being done entirely through the

IEEE 1149.1 Test Access Port.

Configuration through the TAP uses the CFG_IN instruc-

tion. This instruction allows data input on TDI to be con-

verted into data packets for the internal configuration bus.

The following steps are required to configure the FPGA

through the boundary-scan port (when using TCK as a

start-up clock).

1. Load the CFG_IN instruction into the boundary-scan

instruction register (IR)

2. Enter the Shift-DR (SDR) state

3. Shift a configuration bitstream into TDI

4. Return to Run-Test-Idle (RTI)

5. Load the JSTART instruction into IR

6. Enter the SDR state

7. Clock TCK through the startup sequence

8. Return to RTI

Configuration and readback via the TAP is always available.

The boundary-scan mode is selected by a <101> or <001>

on the mode pins (M2, M1, M0).

Configuration Sequence

The configuration of Virtex-E devices is a three-phase pro-

cess. First, the configuration memory is cleared. Next, con-

figuration data is loaded into the memory, and finally, the

logic is activated by a start-up process.

Configuration is automatically initiated on power-up unless

it is delayed by the user, as described below. The configura-

tion process can also be initiated by asserting PROGRAM.

The end of the memory-clearing phase is signalled by INIT

going High, and the completion of the entire process is sig-

nalled by DONE going High.

The power-up timing of configuration signals is shown in

Figure 20.

Figure 19: SelectMAP Write Abort Waveforms

CCLK

WRITE

Abort

DATA[7:0]

BUSY

DS022_46_071201

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The corresponding timing characteristics are listed in

Table 12.

Delaying Configuration

INIT can be held Low using an open-drain driver. An

open-drain is required since INIT is a bidirectional

open-drain pin that is held Low by the FPGA while the con-

figuration memory is being cleared. Extending the time that

the pin is Low causes the configuration sequencer to wait.

Thus, configuration is delayed by preventing entry into the

phase where data is loaded.

Start-Up Sequence

The default Start-up sequence is that one CCLK cycle after

DONE goes High, the global 3-state signal (GTS) is

released. This permits device outputs to turn on as neces-

sary.

One CCLK cycle later, the Global Set/Reset (GSR) and Glo-

bal Write Enable (GWE) signals are released. This permits

the internal storage elements to begin changing state in

response to the logic and the user clock.

The relative timing of these events can be changed. In addi-

tion, the GTS, GSR, and GWE events can be made depen-

dent on the DONE pins of multiple devices all going High,

forcing the devices to start synchronously. The sequence

can also be paused at any stage until lock has been

achieved on any or all DLLs.

Readback

The configuration data stored in the Virtex-E configuration

memory can be readback for verification. Along with the

configuration data it is possible to readback the contents all

flip-flops/latches, LUT RAMs, and block RAMs. This capa-

bility is used for real-time debugging. For more detailed

information, see application note XAPP138 “Virtex FPGA

Series Configuration and Readback”.

Figure 20: Power-Up Timing Configuration Signals

VALI

PROGRAM

Vcc

CCLK OUTPUT or INPUT

M0, M1, M2

(Required)

TPL

TICCK

ds022_020_071201

TPOR

INIT

Table 12: Power-up Timing Characteristics

Description Symbol Value Units

Power-on Reset1TPOR 2.0 ms, max

Program Latency TPL 100.0

s, max

CCLK (output) Delay TICCK

0.5

s, min

4.0

s, max

Program Pulse Width TPROGRAM 300 ns, min

Notes:

1. TPOR delay is the initialization time required after VCCINT

reaches the recommended operating voltage.

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Design Considerations

This section contains more detailed design information on

the following features.

•Delay-Locked Loop . . . see page 19

•BlockRAM . . . see page 23

•Select I/O . . . see page 30

Using DLLs

The Virtex-E FPGA series provides up to eight fully digital

dedicated on-chip Delay-Locked Loop (DLL) circuits which

provide zero propagation delay, low clock skew between

output clock signals distributed throughout the device, and

advanced clock domain control. These dedicated DLLs can

be used to implement several circuits which improve and

simplify system level design.

Introduction

As FPGAs grow in size, quality on-chip clock distribution

becomes increasingly important. Clock skew and clock

delay impact device performance and the task of managing

clock skew and clock delay with conventional clock trees

becomes more difficult in large devices. The Virtex-E series

of devices resolve this potential problem by providing up to

eight fully digital dedicated on-chip DLL circuits which pro-

vide zero propagation delay and low clock skew between

output clock signals distributed throughout the device.

Each DLL can drive up to two global clock routing networks

within the device. The global clock distribution network min-

imizes clock skews due to loading differences. By monitor-

ing a sample of the DLL output clock, the DLL can

compensate for the delay on the routing network, effectively

eliminating the delay from the external input port to the indi-

vidual clock loads within the device.

In addition to providing zero delay with respect to a user

source clock, the DLL can provide multiple phases of the

source clock. The DLL can also act as a clock doubler or it

can divide the user source clock by up to 16.

Clock multiplication gives the designer a number of design

alternatives. For instance, a 50 MHz source clock doubled

by the DLL can drive an FPGA design operating at 100

MHz. This technique can simplify board design because the

clock path on the board no longer distributes such a

high-speed signal. A multiplied clock also provides design-

ers the option of time-domain-multiplexing, using one circuit

twice per clock cycle, consuming less area than two copies

of the same circuit. Two DLLs in can be connected in series

to increase the effective clock multiplication factor to four.

The DLL can also act as a clock mirror. By driving the DLL

output off-chip and then back in again, the DLL can be used

to de-skew a board level clock between multiple devices.

In order to guarantee the system clock establishes prior to

the device “waking up,” the DLL can delay the completion of

the device configuration process until after the DLL

achieves lock.

By taking advantage of the DLL to remove on-chip clock

delay, the designer can greatly simplify and improve system

level design involving high-fanout, high-performance clocks.

Library DLL Symbols

Figure 21 shows the simplified Xilinx library DLL macro

symbol, BUFGDLL. This macro delivers a quick and effi-

cient way to provide a system clock with zero propagation

delay throughout the device. Figure 22 and Figure 23 show

the two library DLL primitives. These symbols provide

access to the complete set of DLL features when imple-

menting more complex applications.

Figure 21: Simplified DLL Macro Symbol BUFGDLL

Figure 22: Standard DLL Symbol CLKDLL

Figure 23: High Frequency DLL Symbol

0ns

ds022_25_121099

CLK0

CLK90

CLK180

CLK270

CLK2X

CLKDV

LOCKED

CLKIN

CLKFB

RST

ds022_26_121099

CLKDLL

CLK0

CLK180

CLKDV

LOCKED

CLKIN

CLKFB

RST

ds022_027_121099

CLKDLLHF

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BUFGDLL Pin Descriptions

Use the BUFGDLL macro as the simplest way to provide

zero propagation delay for a high-fanout on-chip clock from

an external input. This macro uses the IBUFG, CLKDLL and

BUFG primitives to implement the most basic DLL applica-

tion as shown in Figure 24.

This symbol does not provide access to the advanced clock

domain controls or to the clock multiplication or clock divi-

sion features of the DLL. This symbol also does not provide

access to the RST, or LOCKED pins of the DLL. For access

to these features, a designer must use the library DLL prim-

itives described in the following sections.

Source Clock Input — I

The I pin provides the user source clock, the clock signal on

which the DLL operates, to the BUFGDLL. For the BUF-

GDLL macro the source clock frequency must fall in the low

frequency range as specified in the data sheet. The BUF-

GDLL requires an external signal source clock. Therefore,

only an external input port can source the signal that drives

the BUFGDLL I pin.

Clock Output — O

The clock output pin O represents a delay-compensated

version of the source clock (I) signal. This signal, sourced by

a global clock buffer BUFG symbol, takes advantage of the

dedicated global clock routing resources of the device.

The output clock has a 50-50 duty cycle unless you deacti-

vate the duty cycle correction property.

CLKDLL Primitive Pin Descriptions

The library CLKDLL primitives provide access to the com-

plete set of DLL features needed when implementing more

complex applications with the DLL.

Source Clock Input — CLKIN

The CLKIN pin provides the user source clock (the clock

signal on which the DLL operates) to the DLL. The CLKIN

frequency must fall in the ranges specified in the data sheet.

A global clock buffer (BUFG) driven from another CLKDLL,

one of the global clock input buffers (IBUFG), or an

IO_LVDS_DLL pin on the same edge of the device (top or

bottom) must source this clock signal. There are four

IO_LVDS_DLL input pins that can be used as inputs to the

DLLs. This makes a total of eight usable input pins for DLLs

in the Virtex-E family.

Feedback Clock Input — CLKFB

The DLL requires a reference or feedback signal to provide

the delay-compensated output. Connect only the CLK0 or

CLK2X DLL outputs to the feedback clock input (CLKFB)

pin to provide the necessary feedback to the DLL. The feed-

back clock input can also be provided through one of the fol-

lowing pins.

IBUFG - Global Clock Input Pad

IO_LVDS_DLL - the pin adjacent to IBUF

If an IBUFG sources the CLKFB pin, the following special

rules apply.

1. An external input port must source the signal that drives

the IBUFG I pin.

2. The CLK2X output must feedback to the device if both

the CLK0 and CLK2X outputs are driving off chip

devices.

3. That signal must directly drive only OBUFs and nothing

else.

These rules enable the software determine which DLL clock

output sources the CLKFB pin.

Reset Input — RST

When the reset pin RST activates the LOCKED signal deac-

tivates within four source clock cycles. The RST pin, active

High, must either connect to a dynamic signal or tied to

ground. As the DLL delay taps reset to zero, glitches can

occur on the DLL clock output pins. Activation of the RST

pin can also severely affect the duty cycle of the clock out-

put pins. Furthermore, the DLL output clocks no longer

de-skew with respect to one another. For these reasons,

rarely use the reset pin unless re-configuring the device or

changing the input frequency.

2x Clock Output — CLK2X

The output pin CLK2X provides a frequency-doubled clock

with an automatic 50/50 duty-cycle correction. Until the

CLKDLL has achieved lock, the CLK2X output appears as a

1x version of the input clock with a 25/75 duty cycle. This

behavior allows the DLL to lock on the correct edge with

respect to source clock. This pin is not available on the

CLKDLLHF primitive.

Clock Divide Output — CLKDV

The clock divide output pin CLKDV provides a lower fre-

quency version of the source clock. The CLKDV_DIVIDE

property controls CLKDV such that the source clock is

divided by N where N is either 1.5, 2, 2.5, 3, 4, 5, 8, or 16.

This feature provides automatic duty cycle correction such

that the CLKDV output pin always has a 50/50 duty cycle,

with the exception of noninteger divides in HF mode, where

the duty cycle is 1/3 for N=1.5 and 2/5 for N=2.5.

Figure 24: BUFGDLL Schematic

CLK0

CLK90

CLK180

CLK270

CLK2X

CLKDV

LOCKED

CLKIN

CLKFB

RST

ds022_28_121099

CLKDLL BUFG

IBUFG

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1-800-255-7778 21

1x Clock Outputs — CLK[0|90|180|270]

The 1x clock output pin CLK0 represents a delay-compen-

sated version of the source clock (CLKIN) signal. The

CLKDLL primitive provides three phase-shifted versions of

the CLK0 signal while CLKDLLHF provides only the 180

phase-shifted version. The relationship between phase shift

and the corresponding period shift appears in Table 13.

The timing diagrams in Figure 25 illustrate the DLL clock

output characteristics.

The DLL provides duty cycle correction on all 1x clock out-

puts such that all 1x clock outputs by default have a 50/50

duty cycle. The DUTY_CYCLE_CORRECTION property

(TRUE by default), controls this feature. In order to deacti-

vate the DLL duty cycle correction, attach the

DUTY_CYCLE_CORRECTION=FALSE property to the

DLL symbol. When duty cycle correction deactivates, the

output clock has the same duty cycle as the source clock.

The DLL clock outputs can drive an OBUF, a BUFG, or they

can route directly to destination clock pins. The DLL clock

outputs can only drive the BUFGs that reside on the same

edge (top or bottom).

Locked Output — LOCKED

To achieve lock, the DLL might need to sample several thou-

sand clock cycles. After the DLL achieves lock, the

LOCKED signal activates. The DLL timing parameter sec-

tion of the data sheet provides estimates for locking times.

To guarantee that the system clock is established prior to

the device “waking up,” the DLL can delay the completion of

the device configuration process until after the DLL locks.

The STARTUP_WAIT property activates this feature.

Until the LOCKED signal activates, the DLL output clocks

are not valid and can exhibit glitches, spikes, or other spuri-

ous movement. In particular the CLK2X output appears as a

1x clock with a 25/75 duty cycle.

DLL Properties

Properties provide access to some of the Virtex-E series

DLL features, (for example, clock division and duty cycle

correction).

Duty Cycle Correction Property

The 1x clock outputs, CLK0, CLK90, CLK180, and CLK270,

use the duty-cycle corrected default, exhibiting a 50/50 duty

cycle. The DUTY_CYCLE_CORRECTION property (by

default TRUE) controls this feature. To deactivate the DLL

duty-cycle correction for the 1x clock outputs, attach the

DUTY_CYCLE_CORRECTION=FALSE property to the

DLL symbol. When duty-cycle correction deactivates, the

output clock has the same duty cycle as the source clock.

Clock Divide Property

The CLKDV_DIVIDE property specifies how the signal on

the CLKDV pin is frequency divided with respect to the

CLK0 pin. The values allowed for this property are 1.5, 2,

2.5, 3, 4, 5, 8, or 16; the default value is 2.

Startup Delay Property

This property, STARTUP_WAIT, takes on a value of TRUE

or FALSE (the default value). When TRUE the device con-

figuration DONE signal waits until the DLL locks before

going to High.

Virtex-E DLL Location Constraints

As shown in Figure 26, there are four additional DLLs in the

Virtex-E devices, for a total of eight per Virtex-E device.

These DLLs are located in silicon, at the top and bottom of

the two innermost block SelectRAM columns. The location

constraint LOC, attached to the DLL symbol with the identi-

fier DLL0S, DLL0P, DLL1S, DLL1P, DLL2S, DLL2P, DLL3S,

or DLL3P, controls the DLL location.

The LOC property uses the following form:

LOC = DLL0P

Table 13: Relationship of Phase-Shifted Output Clock

to Period Shift

Phase (degrees) Period Shift (percent)

00%

90 25%

180 50%

270 75%

Figure 25: DLL Output Characteristics

ds022_29_121099

CLKIN

CLK2X

CLK0

CLK90

CLK180

CLK270

CLKDV

CLKDV_DIVIDE=2

DUTY_CYCLE_CORRECTION=FALSE

CLK0

CLK90

CLK180

CLK270

DUTY_CYCLE_CORRECTION=TRUE

0 90 180 270 0 90 180 270

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Design Factors

Use the following design considerations to avoid pitfalls and

improve success designing with Xilinx devices.

Input Clock

The output clock signal of a DLL, essentially a delayed ver-

sion of the input clock signal, reflects any instability on the

input clock in the output waveform. For this reason the qual-

ity of the DLL input clock relates directly to the quality of the

output clock waveforms generated by the DLL. The DLL

input clock requirements are specified in the data sheet.

In most systems a crystal oscillator generates the system

clock. The DLL can be used with any commercially available

quartz crystal oscillator. For example, most crystal oscilla-

tors produce an output waveform with a frequency tolerance

of 100 PPM, meaning 0.01 percent change in the clock

period. The DLL operates reliably on an input waveform with

a frequency drift of up to 1 ns — orders of magnitude in

excess of that needed to support any crystal oscillator in the

industry. However, the cycle-to-cycle jitter must be kept to

less than 300 ps in the low frequencies and 150 ps for the

high frequencies.

Input Clock Changes

Changing the period of the input clock beyond the maximum

drift amount requires a manual reset of the CLKDLL. Failure

to reset the DLL produces an unreliable lock signal and out-

put clock.

It is possible to stop the input clock with little impact to the

DLL. Stopping the clock should be limited to less than

100

s to keep device cooling to a minimum. The clock

should be stopped during a Low phase, and when restored

the full High period should be seen. During this time

LOCKED stays High and remains High when the clock is

restored.

When the clock is stopped, one to four more clocks are still

observed as the delay line is flushed. When the clock is

restarted, the output clocks are not observed for one to four

clocks as the delay line is filled. The most common case is

two or three clocks.

In a similar manner, a phase shift of the input clock is also

possible. The phase shift propagates one to four clocks to

the output after the original shift, with no disruption to the

CLKDLL control.

Output Clocks

As mentioned earlier in the DLL pin descriptions, some

restrictions apply regarding the connectivity of the output

pins. The DLL clock outputs can drive an OBUF, a global

clock buffer BUFG, or they can route directly to destination

clock pins. The only BUFGs that the DLL clock outputs can

drive are the two on the same edge of the device (top or bot-

tom). In addition, the CLK2X output of the secondary DLL

can connect directly to the CLKIN of the primary DLL in the

same quadrant.

Do not use the DLL output clock signals until after activation

of the LOCKED signal. Prior to the activation of the

LOCKED signal, the DLL output clocks are not valid and

can exhibit glitches, spikes, or other spurious movement.

Useful Application Examples

The Virtex-E DLL can be used in a variety of creative and

useful applications. The following examples show some of

the more common applications. The Verilog and VHDL

example files are available at:

ftp://ftp.xilinx.com/pub/applications/xapp/xapp132.zip

Standard Usage

The circuit shown in Figure 27 resembles the BUFGDLL

macro implemented to provide access to the RST and

LOCKED pins of the CLKDLL.

Board Level De-Skew of Multiple Non-Virtex-E

Devices

The circuit shown in Figure 28 can be used to de-skew a

system clock between a Virtex-E chip and other non-Vir-

tex-E chips on the same board. This application is com-

monly used when the Virtex-E device is used in conjunction

with other standard products such as SRAM or DRAM

devices. While designing the board level route, ensure that

the return net delay to the source equals the delay to the

other chips involved.

Figure 26: Virtex Series DLLs

x132_14_100799

DLL-3P

DLL-1P

DLL-3S

DLL-1S

DLL-2S

DLL-0S

DLL-2P

DLL-0P

Bottom Right

Half Edge

Figure 27: Standard DLL Implementation

CLK0

CLK90

CLK180

CLK270

CLK2X

CLKDV

LOCKED

CLKIN

CLKFB

RST

ds022_028_121099

CLKDLL BUFG

IBUFG

IBUF OBUF

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1-800-255-7778 23

Board-level de-skew is not required for low-fanout clock net-

works. It is recommended for systems that have fanout lim-

itations on the clock network, or if the clock distribution chip

cannot handle the load.

Do not use the DLL output clock signals until after activation

of the LOCKED signal. Prior to the activation of the

LOCKED signal, the DLL output clocks are not valid and

can exhibit glitches, spikes, or other spurious movement.

The dll_mirror_1 files in the xapp132.zip file show the VHDL

and Verilog implementation of this circuit.

De-Skew of Clock and Its 2x Multiple

The circuit shown in Figure 29 implements a 2x clock multi-

plier and also uses the CLK0 clock output with zero ns skew

between registers on the same chip. A clock divider circuit

could alternatively be implemented using similar connec-

tions.

Because any single DLL can access only two BUFGs at

most, any additional output clock signals must be routed

from the DLL in this example on the high speed backbone

routing.

The dll_2x files in the xapp132.zip file show the VHDL and

Verilog implementation of this circuit.

Virtex-E 4x Clock

Two DLLs located in the same half-edge (top-left, top-right,

bottom-right, bottom-left) can be connected together, with-

out using a BUFG between the CLKDLLs, to generate a 4x

clock as shown in Figure 30. Virtex-E devices, like the Virtex

devices, have four clock networks that are available for inter-

nal de-skewing of the clock. Each of the eight DLLs have

access to two of the four clock networks. Although all the

DLLs can be used for internal de-skewing, the presence of

two GCLKBUFs on the top and two on the bottom indicate

that only two of the four DLLs on the top (and two of the four

DLLs on the bottom) can be used for this purpose.

The dll_4xe files in the xapp 32.zip file show the DLL imple-

mentation in Verilog for Virtex-E devices. These files can be

found at:

ftp://ftp.xilinx.com/pub/applications/xapp/xapp132.zip

Using Block SelectRAM+ Features

The Virtex FPGA Series provides dedicated blocks of

on-chip, true dual-read/write port synchronous RAM, with

4096 memory cells. Each port of the block SelectRAM+

memory can be independently configured as a read/write

port, a read port, a write port, and can be configured to a

specific data width. block SelectRAM+ memory offers new

capabilities, allowing FPGA designers to simplify designs.

Figure 28: DLL De-skew of Board Level Clock

Figure 29: DLL De-skew of Clock and 2x Multiple

ds022_029_121099

CLK0

CLK90

CLK180

CLK270

CLK2X

CLKDV

LOCKED

CLKIN

CLKFB

RST

CLKDLL OBUFIBUFG

CLK0

CLK90

CLK180

CLK270

CLK2X

CLKDV

LOCKED

CLKIN

CLKFB

RST

CLKDLL BUFG

IBUFG

Non-Virtex-E Chip

Other Non_Virtex-E Chips

Virtex-E Device

CLK0

CLK90

CLK180

CLK270

CLK2X

CLKDV

LOCKED

CLKIN

CLKFB

RST

ds022_030_121099

CLKDLL BUFG

IBUFG

IBUF OBUF

BUFG

Figure 30: DLL Generation of 4x Clock in Virtex-E

Devices

ds022_031_041901

RST

CLKFB

CLKIN

CLKDLL-S

LOCKED

CLKDV

INV

BUFG

OBUF

IBUFG

CLK2X

CLK0

CLK90

CLK180

CLK270

RST

CLKFB

CLKIN

CLKDLL-P

LOCKED

CLKDV

CLK2X

CLK0

CLK90

CLK180

CLK270

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24 1-800-255-7778

Operating Modes

Virtex-E block SelectRAM+ memory supports two operating

modes.

•Read Through

•Write Back

Read Through (one clock edge)

The read address is registered on the read port clock edge

and data appears on the output after the RAM access time.

Some memories might place the latch/register at the out-

puts, depending on the desire to have a faster clock-to-out

versus set-up time. This is generally considered to be an

inferior solution, since it changes the read operation to an

asynchronous function with the possibility of missing an

address/control line transition during the generation of the read

pulse clock.

Write Back (one clock edge)

The write address is registered on the write port clock edge

and the data input is written to the memory and mirrored on

the output.

Block SelectRAM+ Characteristics

1. All inputs are registered with the port clock and have a

set-up to clock timing specification.

2. All outputs have a read through or write back function

depending on the state of the port WE pin. The outputs

relative to the port clock are available after the

clock-to-out timing specification.

3. The block SelectRAM elements are true SRAM

memories and do not have a combinatorial path from

the address to the output. The LUT SelectRAM+ cells in

the CLBs are still available with this function.

4. The ports are completely independent from each other

(i.e., clocking, control, address, read/write function, and

data width) without arbitration.

5. A write operation requires only one clock edge.

6. A read operation requires only one clock edge.

The output ports are latched with a self-timed circuit to guar-

antee a glitch-free read. The state of the output port does

not change until the port executes another read or write

operation.

Library Primitives

Figure 31 and Figure 32 show the two generic library block

SelectRAM+ primitives. Table 14 describes all of the avail-

able primitives for synthesis and simulation.

Figure 31: Dual-Port Block SelectRAM+ Memory

Figure 32: Single-Port Block SelectRAM+ Memory

Table 14: Available Library Primitives

Primitive Port A Width Port B Width

RAMB4_S1

RAMB4_S1_S1

RAMB4_S1_S2

RAMB4_S1_S4

RAMB4_S1_S8

RAMB4_S1_S16

1N/A

RAMB4_S2

RAMB4_S2_S2

RAMB4_S2_S4

RAMB4_S2_S8

RAMB4_S2_S16

2N/A

RAMB4_S4

RAMB4_S4_S4

RAMB4_S4_S8

RAMB4_S4_S16

4N/A

RAMB4_S8

RAMB4_S8_S8

RAMB4_S8_S16

8N/A

RAMB4_S16

RAMB4_S16_S16

16 N/A

WEB

ENB

RSTB

CLKB

ADDRB[#:0]

DIB[#:0]

WEA

ENA

RSTA

CLKA

ADDRA[#:0]

DIA[#:0]

DOA[#:0]

DOB[#:0]

RAMB4_S#_S#

ds022_032_121399

ds022_033_121399

DO[#:0]

RST

CLK

ADDR[#:0]

DI[#:0]

RAMB4_S#

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Port Signals

Each block SelectRAM+ port operates independently of the

others while accessing the same set of 4096 memory cells.

Table 15 describes the depth and width aspect ratios for the

block SelectRAM+ memory.

Clock—CLK[A|B]

Each port is fully synchronous with independent clock pins.

All port input pins have setup time referenced to the port

CLK pin. The data output bus has a clock-to-out time refer-

enced to the CLK pin.

Enable—EN[A|B]

The enable pin affects the read, write and reset functionality

of the port. Ports with an inactive enable pin keep the output

pins in the previous state and do not write data to the mem-

ory cells.

Write Enable—WE[A|B]

Activating the write enable pin allows the port to write to the

memory cells. When active, the contents of the data input

bus are written to the RAM at the address pointed to by the

address bus, and the new data also reflects on the data out

bus. When inactive, a read operation occurs and the con-

tents of the memory cells referenced by the address bus

reflect on the data out bus.

Reset—RST[A|B]

The reset pin forces the data output bus latches to zero syn-

chronously. This does not affect the memory cells of the

RAM and does not disturb a write operation on the other

port.

Address Bus—ADDR[A|B]<#:0>

The address bus selects the memory cells for read or write.

The width of the port determines the required width of this

bus as shown in Table 15.

Data In Bus—DI[A|B]<#:0>

The data in bus provides the new data value to be written

into the RAM. This bus and the port have the same width, as

shown in Ta ble 15 .

Data Output Bus—DO[A|B]<#:0>

The data out bus reflects the contents of the memory cells

referenced by the address bus at the last active clock edge.

During a write operation, the data out bus reflects the data

in bus. The width of this bus equals the width of the port.

The allowed widths appear in Ta ble 15.

Inverting Control Pins

The four control pins (CLK, EN, WE and RST) for each port

have independent inversion control as a configuration option.

Address Mapping

Each port accesses the same set of 4096 memory cells

using an addressing scheme dependent on the width of the

port. The physical RAM location addressed for a particular

width are described in the following formula (of interest only

when the two ports use different aspect ratios).

Start = ((ADDRport +1) * Widthport) –1

End = ADDRport * Widthport

Table 16 shows low order address mapping for each port

width.

Creating Larger RAM Structures

The block SelectRAM+ columns have specialized routing to

allow cascading blocks together with minimal routing

delays. This achieves wider or deeper RAM structures with

a smaller timing penalty than when using normal routing

channels.

Location Constraints

Block SelectRAM+ instances can have LOC properties

attached to them to constrain the placement. The block

SelectRAM+ placement locations are separate from the

CLB location naming convention, allowing the LOC proper-

ties to transfer easily from array to array.

The LOC properties use the following form.

LOC = RAMB4_R#C#

RAMB4_R0C0 is the upper left RAMB4 location on the

device.

Table 15: Block SelectRAM+ Port Aspect Ratios

Width Depth ADDR Bus Data Bus

1 4096 ADDR<11:0> DATA<0>

2 2048 ADDR<10:0> DATA<1:0>

4 1024 ADDR<9:0> DATA<3:0>

8 512 ADDR<8:0> DATA<7:0>

16 256 ADDR<7:0> DATA<15:0>

Table 16: Port Address Mapping

Port

Width

Port

Addresses

1 4095...

2 2047... 07 06 05 04 03 02 01 00

4 1023... 03 02 01 00

8 511... 01 00

16 255... 00

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26 1-800-255-7778

Conflict Resolution

The block SelectRAM+ memory is a true dual-read/write

port RAM that allows simultaneous access of the same

memory cell from both ports. When one port writes to a

given memory cell, the other port must not address that

memory cell (for a write or a read) within the clock-to-clock

setup window. The following lists specifics of port and mem-

ory cell write conflict resolution.

•If both ports write to the same memory cell

simultaneously, violating the clock-to-clock setup

requirement, consider the data stored as invalid.

•If one port attempts a read of the same memory cell

the other simultaneously writes, violating the

clock-to-clock setup requirement, the following occurs.

- The write succeeds

- The data out on the writing port accurately reflects

the data written.

- The data out on the reading port is invalid.

Conflicts do not cause any physical damage.

Single Port Timing

Figure 33 shows a timing diagram for a single port of a block

SelectRAM+ memory. The block SelectRAM+ AC switching

characteristics are specified in the data sheet. The block

SelectRAM+ memory is initially disabled.

At the first rising edge of the CLK pin, the ADDR, DI, EN,

WE, and RST pins are sampled. The EN pin is High and the

WE pin is Low indicating a read operation. The DO bus con-

tains the contents of the memory location, 0x00, as indi-

cated by the ADDR bus.

At the second rising edge of the CLK pin, the ADDR, DI, EN,

WR, and RST pins are sampled again. The EN and WE pins

are High indicating a write operation. The DO bus mirrors

the DI bus. The DI bus is written to the memory location

0x0F.

At the third rising edge of the CLK pin, the ADDR, DI, EN,

WR, and RST pins are sampled again. The EN pin is High

and the WE pin is Low indicating a read operation. The DO

bus contains the contents of the memory location 0x7E as

indicated by the ADDR bus.

At the fourth rising edge of the CLK pin, the ADDR, DI, EN,

WR, and RST pins are sampled again. The EN pin is Low

indicating that the block SelectRAM+ memory is now dis-

abled. The DO bus retains the last value.

Dual Port Timing

Figure 34 shows a timing diagram for a true dual-port

read/write block SelectRAM+ memory. The clock on port A

has a longer period than the clock on Port B. The timing

parameter TBCCS, (clock-to-clock set-up) is shown on this

diagram. The parameter, TBCCS is violated once in the dia-

gram. All other timing parameters are identical to the single

port version shown in Figure 33.

TBCCS is only of importance when the address of both ports

are the same and at least one port is performing a write

operation. When the clock-to-clock set-up parameter is vio-

lated for a WRITE-WRITE condition, the contents of the

memory at that location are invalid. When the clock-to-clock

set-up parameter is violated for a WRITE-READ condition,

the contents of the memory are correct, but the read port

has invalid data. At the first rising edge of CLKA, memory

location 0x00 is to be written with the value 0xAAAA and is

mirrored on the DOA bus. The last operation of Port B was

a read to the same memory location 0x00. The DOB bus of

Port B does not change with the new value on Port A, and

retains the last read value. A short time later, Port B exe-

cutes another read to memory location 0x00, and the DOB

bus now reflects the new memory value written by Port A.

At the second rising edge of CLKA, memory location 0x7E

is written with the value 0x9999 and is mirrored on the DOA

bus. Port B then executes a read operation to the same

memory location without violating the TBCCS parameter and

the DOB reflects the new memory values written by Port A.

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1-800-255-7778 27

At the third rising edge of CLKA, the TBCCS parameter is

violated with two writes to memory location 0x0F. The DOA

and DOB busses reflect the contents of the DIA and DIB

busses, but the stored value at 0x0F is invalid.

At the fourth rising edge of CLKA, a read operation is per-

formed at memory location 0x0F and invalid data is present

on the DOA bus. Port B also executes a read operation to

memory location 0x0F and also reads invalid data.

At the fifth rising edge of CLKA a read operation is per-

formed that does not violate the TBCCS parameter to the

previous write of 0x7E by Port B. THe DOA bus reflects the

recently written value by Port B.

Figure 33: Timing Diagram for Single Port Block SelectRAM+ Memory

ds022_0343_121399

CLK

TBPWH

TBACK

ADDR 00

DDDD

MEM (00) CCCC MEM (7E)

CCCC

7E 8F

BBBB 2222

DIN

DOUT

RST

DISABLED READ WRITE READ DISABLED

TBDCK

TBECK

TBWCK

TBCKO

TBPWL

Figure 34: Timing Diagram for a True Dual-port Read/Write Block SelectRAM+ Memory

ds022_035_121399

CLK_A

PORT APORT B

ADDR_A 00 7E 0F

00 00 7E 7E 1A0F 0F

0F 7E

AAAA 9999 AAAA 0000 1111

2222

AAAA 9999 AAAA UNKNOWN

EN_A

WE_A

DI_A

DO_A

1111 1111 1111 2222 FFFFBBBB 1111

AAAAMEM (00) 9999 2222 FFFFBBBB UNKNOWN

CLK_B

ADDR_B

EN_B

WE_B

DI_B

DO_B

TBCCS

VIOLATION

TBCCS TBCCS

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28 1-800-255-7778

Initialization

The block SelectRAM+ memory can initialize during the

device configuration sequence. The 16 initialization properties

of 64 hex values each (a total of 4096 bits) set the initialization

of each RAM. These properties appear in Tabl e 17. Any initial-

ization properties not explicitly set configure as zeros. Partial

initialization strings pad with zeros. Initialization strings

greater than 64 hex values generate an error. The RAMs can

be simulated with the initialization values using generics in

VHDL simulators and parameters in Verilog simulators.

Initialization in VHDL and Synopsys

The block SelectRAM+ structures can be initialized in VHDL

for both simulation and synthesis for inclusion in the EDIF

output file. The simulation of the VHDL code uses a generic

to pass the initialization. Synopsys FPGA compiler does not

presently support generics. The initialization values instead

attach as attributes to the RAM by a built-in Synopsys

dc_script. The translate_off statement stops synthesis

translation of the generic statements. The following code

illustrates a module that employs these techniques.

Initialization in Verilog and Synopsys

The block SelectRAM+ structures can be initialized in Verilog

for both simulation and synthesis for inclusion in the EDIF

output file. The simulation of the Verilog code uses a def-

param to pass the initialization. The Synopsys FPGA com-

piler does not presently support defparam. The initialization

values instead attach as attributes to the RAM by a built-in

Synopsys dc_script. The translate_off statement stops syn-

thesis translation of the defparam statements. The following

code illustrates a module that employs these techniques.

Design Examples

Creating a 32-bit Single-Port RAM

The true dual-read/write port functionality of the block

SelectRAM+ memory allows a single port, 128 deep by

32-bit wide RAM to be created using a single block

SelectRAM+ cell as shown inTable 35.

Interleaving the memory space, setting the LSB of the

address bus of Port A to 1 (VCC), and the LSB of the

address bus of Port B to 0 (GND), allows a 32-bit wide sin-

gle port RAM to be created.

Creating Two Single-Port RAMs

The true dual-read/write port functionality of the block Selec-

tRAM+ memory allows a single RAM to be split into two sin-

gle port memories of 2K bits each as shown in Figure 36.

In this example, a 512K x 4 RAM (Port A) and a 128 x 16

RAM (Port B) are created out of a single block SelectRAM+.

The address space for the RAM is split by fixing the MSB of

Port A to 1 (VCC) for the upper 2K bits and the MSB of Port

B to 0 (GND) for the lower 2K bits.

Block Memory Generation

The CoreGen program generates memory structures using

the block SelectRAM+ features. This program outputs

VHDL or Verilog simulation code templates and an EDIF file

for inclusion in a design.

Table 17: RAM Initialization Properties

Property Memory Cells

INIT_00 255 to 0

INIT_01 511 to 256

INIT_02 767 to 512

INIT_03 1023 to 768

INIT_04 1279 to 1024

INIT_05 1535 to 1280

INIT_06 1791 to 2047

INIT_07 2047 to 1792

INIT_08 2303 to 2048

INIT_09 2559 to 2304

INIT_0a 2815 to 2560

INIT_0b 3071 to 2816

INIT_0c 3327 to 3072

INIT_0d 3583 to 3328

INIT_0e 3839 to 3584

INIT_0f 4095 to 3840

Figure 35: Single Port 128 x 32 RAM

Figure 36: 512 x 4 RAM and 128 x 16 RAM

WEB

ENB

RSTB

CLKB

ADDRB[7:0]

DIB[15:0]

WEA

ENA

RSTA

CLKA

ADDRA[7:0]

DIA[15:0]

ADDR[6:0], VCC

CLK

RST

CLK

RST

DI[31:16]

ADDR[6:0], GND

DI[15:0]

DOA[15:0] DO[31:16]

DO[15:0]

DOB[15:0]

RAMB4_S16_S16

ds022_036_121399

WEB

ENB

RSTB

CLKB

ADDRB[7:0]

DIB[15:0]

WEA

ENA

RSTA

CLKA

ADDRA[9:0]

DIA[3:0]

, ADDR1[8:0]

DI1[3:0]

WE1

EN1

RST1

CLK1

WE2

EN2

RST2

CLK2

GND, ADDR2[6:0]

DI2[15:0]

DOA[3:0] DO1[3:0]

DO2[15:0]

DOB[15:0]

RAMB4_S4_S16

ds022_037_121399

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VHDL Initialization Example

library IEEE;

use IEEE.std_logic_1164.all;

entity MYMEM is

port (CLK, WE:in std_logic;

ADDR: in std_logic_vector(8 downto 0);

DIN: in std_logic_vector(7 downto 0);

DOUT: out std_logic_vector(7 downto 0));

end MYMEM;

architecture BEHAVE of MYMEM is

signal logic0, logic1: std_logic;

component RAMB4_S8

--synopsys translate_off

generic( INIT_00,INIT_01, INIT_02, INIT_03, INIT_04, INIT_05, INIT_06, INIT_07,

INIT_08, INIT_09, INIT_0a, INIT_0b, INIT_0c, INIT_0d, INIT_0e, INIT_0f : BIT_VECTOR(255

downto 0)

:= X"0000000000000000000000000000000000000000000000000000000000000000");

--synopsys translate_on

port (WE, EN, RST, CLK: in STD_LOGIC;

ADDR: in STD_LOGIC_VECTOR(8 downto 0);

DI: in STD_LOGIC_VECTOR(7 downto 0);

DO: out STD_LOGIC_VECTOR(7 downto 0));

end component;

--synopsys dc_script_begin

--set_attribute ram0 INIT_00

"0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF" -type string

--set_attribute ram0 INIT_01

"FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210" -type string

--synopsys dc_script_end

begin

logic0 <=’0’;

logic1 <=’1’;

ram0: RAMB4_S8

--synopsys translate_off

generic map (

INIT_00 => X"0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF",

INIT_01 => X"FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210")

--synopsys translate_on

port map (WE=>WE, EN=>logic1, RST=>logic0, CLK=>CLK,ADDR=>ADDR, DI=>DIN, DO=>DOUT);

end BEHAVE;

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Verilog Initialization Example

module MYMEM (CLK, WE, ADDR, DIN, DOUT);

input CLK, WE;

input [8:0] ADDR;

input [7:0] DIN;

output [7:0] DOUT;

wire logic0, logic1;

//synopsys dc_script_begin

//set_attribute ram0 INIT_00

"0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF" -type string

//set_attribute ram0 INIT_01

"FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210" -type string

//synopsys dc_script_end

assign logic0 = 1’b0;

assign logic1 = 1’b1;

RAMB4_S8 ram0 (.WE(WE), .EN(logic1), .RST(logic0), .CLK(CLK), .ADDR(ADDR), .DI(DIN),

.DO(DOUT));

//synopsys translate_off

defparam ram0.INIT_00 =

256h’0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF;

defparam ram0.INIT_01 =

256h’FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210;

//synopsys translate_on

endmodule

Using Select I/O

The Virtex-E FPGA series includes a highly configurable,

high-performance I/O resource, called SelectI/O™ to pro-

vide support for a wide variety of I/O standards. The

SelectI/O resource is a robust set of features including pro-

grammable control of output drive strength, slew rate, and

input delay and hold time. Taking advantage of the flexibility

and SelectI/O features and the design considerations

described in this document can improve and simplify sys-

tem level design.

Introduction

As FPGAs continue to grow in size and capacity, the larger

and more complex systems designed for them demand an

increased variety of I/O standards. Furthermore, as system

clock speeds continue to increase, the need for high perfor-

mance I/O becomes more important. While chip-to-chip

delays have an increasingly substantial impact on overall

system speed, the task of achieving the desired system per-

formance becomes more difficult with the proliferation of

low-voltage I/O standards.

SelectI/O, the revolutionary input/output resource of Vir-

tex-E devices, has resolved this potential problem by provid-

ing a highly configurable, high-performance alternative to

the I/O resources of more conventional programmable

devices. The Virtex-E SelectI/O features combine the flexi-

bility and time-to-market advantages of programmable logic

with the high performance previously available only with

ASICs and custom ICs.

Each SelectI/O block can support up to 20 I/O standards.

Supporting such a variety of I/O standards allows the support

of a wide variety of applications, from general purpose stan-

dard applications to high-speed low-voltage memory busses.

SelectI/O blocks also provide selectable output drive

strengths and programmable slew rates for the LVTTL out-

put buffers, as well as an optional, programmable weak

pull-up, weak pull-down, or weak “keeper” circuit ideal for

use in external bussing applications.

Each input/output block (IOB) includes three registers, one

each for the input, output, and 3-state signals within the

IOB. These registers are optionally configurable as either a

D-type flip-flop or as a level sensitive latch.

The input buffer has an optional delay element used to guar-

antee a zero hold time requirement for input signals regis-

tered within the IOB.

The Virtex-E SelectI/O features also provide dedicated

resources for input reference voltage (VREF) and output

source voltage (VCCO), along with a convenient banking

system that simplifies board design.

By taking advantage of the built-in features and wide variety

of I/O standards supported by the SelectI/O features, sys-

tem-level design and board design can be greatly simplified

and improved.

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Fundamentals

Modern bus applications, pioneered by the largest and most

influential companies in the digital electronics industry, are

commonly introduced with a new I/O standard tailored spe-

cifically to the needs of that application. The bus I/O stan-

dards provide specifications to other vendors who create

products designed to interface with these applications.

Each standard often has its own specifications for current,

voltage, I/O buffering, and termination techniques.

The ability to provide the flexibility and time-to-market

advantages of programmable logic is increasingly depen-

dent on the capability of the programmable logic device to

support an ever increasing variety of I/O standards

The SelectI/O resources feature highly configurable input

and output buffers which provide support for a wide variety

of I/O standards. As shown in Table 18, each buffer type can

support a variety of voltage requirements.

Overview of Supported I/O Standards

This section provides a brief overview of the I/O standards

supported by all Virtex-E devices.

While most I/O standards specify a range of allowed volt-

ages, this document records typical voltage values only.

Detailed information on each specification can be found on

the Electronic Industry Alliance Jedec website at:

http://www.jedec.org

LVTTL — Low-Voltage TTL

The Low-Voltage TTL, or LVTTL standard is a general pur-

pose EIA/JESDSA standard for 3.3 V applications that uses

an LVTTL input buffer and a Push-Pull output buffer. This

standard requires a 3.3 V output source voltage (VCCO), but

does not require the use of a reference voltage (VREF) or a

termination voltage (VTT).

LVCMOS2 — Low-Voltage CMOS for 2.5 Volts

The Low-Voltage CMOS for 2.5 Volts or lower, or LVCMOS2

standard is an extension of the LVCMOS standard (JESD

8.-5) used for general purpose 2.5 V applications. This stan-

dard requires a 2.5 V output source voltage (VCCO), but

does not require the use of a reference voltage (VREF) or a

board termination voltage (VTT).

LVCMOS18

— 1.8 V Low Voltage CMOS

This standard is an extension of the LVCMOS standard. It is

used in general purpose 1.8 V applications. The use of a

reference voltage (VREF) or a board termination voltage

(VTT) is not required.

PCI — Peripheral Component Interface

The Peripheral Component Interface, or PCI standard spec-

ifies support for both 33 MHz and 66 MHz PCI bus applica-

tions. It uses a LVTTL input buffer and a Push-Pull output

buffer. This standard does not require the use of a reference

voltage (VREF) or a board termination voltage (VTT), how-

ever, it does require a 3.3 V output source voltage (VCCO).

GTL — Gunning Transceiver Logic Terminated

The Gunning Transceiver Logic, or GTL standard is a

high-speed bus standard (JESD8.3) invented by Xerox. Xil-

inx has implemented the terminated variation for this stan-

dard. This standard requires a differential amplifier input

buffer and a Open Drain output buffer.

GTL+ — Gunning Transceiver Logic Plus

The Gunning Transceiver Logic Plus, or GTL+ standard is a

high-speed bus standard (JESD8.3) first used by the Pen-

tium Pro processor.

HSTL — High-Speed Transceiver Logic

The High-Speed Transceiver Logic, or HSTL standard is a

general purpose high-speed, 1.5 V bus standard sponsored

by IBM (EIA/JESD 8-6). This standard has four variations or

classes. SelectI/O devices support Class I, III, and IV. This

Table 18: Virtex-E Supported I/O Standards

I/O

Standard

Output

VCCO

Input

VCCO

Input

VREF

Board

Termination

Voltage (VTT)

LVTTL 3.3 3.3 N/A N/A

LVCMOS2 2.5 2.5 N/A N/A

LVCMOS18 1.8 1.8 N/A N/A

SSTL3 I & II 3.3 N/A 1.50 1.50

SSTL2 I & II 2.5 N/A 1.25 1.25

GTL N/A N/A 0.80 1.20

GTL+ N/A N/A 1.0 1.50

HSTL I 1.5 N/A 0.75 0.75

HSTL III & IV 1.5 N/A 0.90 1.50

CTT 3.3 N/A 1.50 1.50

AGP-2X 3.3 N/A 1.32 N/A

PCI33_3 3.3 3.3 N/A N/A

PCI66_3 3.3 3.3 N/A N/A

BLVDS & LVDS 2.5 N/A N/A N/A

LVPECL 3.3 N/A N/A N/A

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standard requires a Differential Amplifier input buffer and a

Push-Pull output buffer.

SSTL3 — Stub Series Terminated Logic for 3.3V

The Stub Series Terminated Logic for 3.3 V, or SSTL3 stan-

dard is a general purpose 3.3 V memory bus standard also

sponsored by Hitachi and IBM (JESD8-8). This standard has

two classes, I and II. SelectI/O devices support both classes

for the SSTL3 standard. This standard requires a Differential

Amplifier input buffer and an Push-Pull output buffer.

SSTL2 — Stub Series Terminated Logic for 2.5V

The Stub Series Terminated Logic for 2.5 V, or SSTL2 stan-

dard is a general purpose 2.5 V memory bus standard

sponsored by Hitachi and IBM (JESD8-9). This standard

has two classes, I and II. SelectI/O devices support both

classes for the SSTL2 standard. This standard requires a

Differential Amplifier input buffer and an Push-Pull output

buffer.

CTT — Center Tap Terminated

The Center Tap Terminated, or CTT standard is a 3.3 V

memory bus standard sponsored by Fujitsu (JESD8-4).

This standard requires a Differential Amplifier input buffer

and a Push-Pull output buffer.

AGP-2X — Advanced Graphics Port

The Intel AGP standard is a 3.3 V Advanced Graphics

Port-2X bus standard used with the Pentium II processor for

graphics applications. This standard requires a Push-Pull

output buffer and a Differential Amplifier input buffer.

LVDS

— Low Voltage Differential Signal

LVDS is a differential I/O standard. It requires that one data

bit is carried through two signal lines. As with all differential

signaling standards, LVDS has an inherent noise immunity

over single-ended I/O standards. The voltage swing

between two signal lines is approximately 350 mV. The use

of a reference voltage (VREF) or a board termination voltage

(VTT) is not required. LVDS requires the use of two pins per

input or output. LVDS requires external resistor termination.

BLVDS

— Bus LVDS

This standard allows for bidirectional LVDS communication

between two or more devices. The external resistor termi-

nation is different than the one for standard LVDS.

LVPECL

— Low Voltage Positive Emitter Coupled

Logic

LVPECL is another differential I/O standard. It requires two

signal lines for transmitting one data bit. This standard

specifies two pins per input or output. The voltage swing

between these two signal lines is approximately 850 mV.

The use of a reference voltage (VREF) or a board termina-

tion voltage (VTT) is not required. The LVPECL standard

requires external resistor termination.

Library Symbols

The Xilinx library includes an extensive list of symbols

designed to provide support for the variety of SelectI/O fea-

tures. Most of these symbols represent variations of the five

generic SelectI/O symbols.

•IBUF (input buffer)

•IBUFG (global clock input buffer)

•OBUF (output buffer)

•OBUFT (3-state output buffer)

•IOBUF (input/output buffer)

IBUF

Signals used as inputs to the Virtex-E device must source

an input buffer (IBUF) via an external input port. The generic

Virtex-E IBUF symbol appears in Figure 37. The extension

to the base name defines which I/O standard the IBUF

uses. The assumed standard is LVTTL when the generic

IBUF has no specified extension.

The following list details the variations of the IBUF symbol:

•IBUF

•IBUF_LVCMOS2

•IBUF_PCI33_3

•IBUF_PCI66_3

•IBUF_GTL

•IBUF_GTLP

•IBUF_HSTL_I

•IBUF_HSTL_III

•IBUF_HSTL_IV

•IBUF_SSTL3_I

•IBUF_SSTL3_II

•IBUF_SSTL2_I

•IBUF_SSTL2_II

•IBUF_CTT

•IBUF_AGP

•IBUF_LVCMOS18

•IBUF_LVDS

•IBUF_LVPECL

When the IBUF symbol supports an I/O standard that

requires a VREF

, the IBUF automatically configures as a dif-

ferential amplifier input buffer. The VREF voltage must be

supplied on the VREF pins. In the case of LVDS, LVPECL,

and BLVDS, VREF is not required.

Figure 37: Input Buffer (IBUF) Symbols

IBUF

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The voltage reference signal is “banked” within the Virtex-E

device on a half-edge basis such that for all packages there

are eight independent VREF banks internally. See Figure 38

for a representation of the Virtex-E I/O banks. Within each

bank approximately one of every six I/O pins is automati-

cally configured as a VREF input. After placing a differential

amplifier input signal within a given VREF bank, the same

external source must drive all I/O pins configured as a VREF

input.

IBUF placement restrictions require that any differential

amplifier input signals within a bank be of the same stan-

dard. How to specify a specific location for the IBUF via the

LOC property is described below. Table 19 summarizes the

Virtex-E input standards compatibility requirements.

An optional delay element is associated with each IBUF.

When the IBUF drives a flip-flop within the IOB, the delay

element by default activates to ensure a zero hold-time

requirement. The NODELAY=TRUE property overrides this

default.

When the IBUF does not drive a flip-flop within the IOB, the

delay element de-activates by default to provide higher per-

formance. To delay the input signal, activate the delay ele-

ment with the DELAY=TRUE property.

IBUFG

Signals used as high fanout clock inputs to the Virtex-E

device should drive a global clock input buffer (IBUFG) via

an external input port in order to take advantage of one of

the four dedicated global clock distribution networks. The

output of the IBUFG symbol can only drive a CLKDLL,

CLKDLLHF, or a BUFG symbol. The generic Virtex-E

IBUFG symbol appears in Figure 39.

The extension to the base name determines which I/O stan-

dard is used by the IBUFG. With no extension specified for

the generic IBUFG symbol, the assumed standard is

LVTTL.

The following list details variations of the IBUFG symbol.

•IBUFG

•IBUFG_LVCMOS2

•IBUFG_PCI33_3

•IBUFG_PCI66_3

•IBUFG_GTL

•IBUFG_GTLP

•IBUFG_HSTL_I

•IBUFG_HSTL_III

•IBUFG_HSTL_IV

•IBUFG_SSTL3_I

•IBUFG_SSTL3_II

•IBUFG_SSTL2_I

•IBUFG_SSTL2_II

•IBUFG_CTT

•IBUFG_AGP

•IBUFG_LVCMOS18

•IBUFG_LVDS

•IBUFG_LVPECL

When the IBUFG symbol supports an I/O standard that

requires a differential amplifier input, the IBUFG automati-

cally configures as a differential amplifier input buffer. The

low-voltage I/O standards with a differential amplifier input

require an external reference voltage input VREF

The voltage reference signal is “banked” within the Virtex-E

device on a half-edge basis such that for all packages there

are eight independent VREF banks internally. See Figure 38

for a representation of the Virtex-E I/O banks. Within each

bank approximately one of every six I/O pins is automati-

cally configured as a VREF input. After placing a differential

amplifier input signal within a given VREF bank, the same

external source must drive all I/O pins configured as a VREF

input.

IBUFG placement restrictions require any differential ampli-

fier input signals within a bank be of the same standard. The

LOC property can specify a location for the IBUFG.

Figure 38: Virtex-E I/O Banks

Table 19: Xilinx Input Standards Compatibility

Requirements

Rule 1 Standards with the same input VCCO, output VCCO,

and VREF can be placed within the same bank.

ds022_42_012100

Bank 0

GCLK3 GCLK2

GCLK1 GCLK0

Bank 1

Bank 5 Bank 4

Virtex-E

Device

Bank 7Bank 6

Bank 2Bank 3

Figure 39: Virtex-E Global Clock Input Buffer (IBUFG)

Symbol

IBUFG

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As an added convenience, the BUFGP can be used to

instantiate a high fanout clock input. The BUFGP symbol

represents a combination of the LVTTL IBUFG and BUFG

symbols, such that the output of the BUFGP can connect

directly to the clock pins throughout the design.

Unlike previous architectures, the Virtex-E BUFGP symbol

can only be placed in a global clock pad location. The LOC

property can specify a location for the BUFGP.

OBUF

An OBUF must drive outputs through an external output

port. The generic output buffer (OBUF) symbol appears in

Figure 40.

The extension to the base name defines which I/O standard

the OBUF uses. With no extension specified for the generic

OBUF symbol, the assumed standard is slew rate limited

LVTTL with 12 mA drive strength.

The LVTTL OBUF additionally can support one of two slew

rate modes to minimize bus transients. By default, the slew

rate for each output buffer is reduced to minimize power bus

transients when switching non-critical signals.

LVTTL output buffers have selectable drive strengths.

The format for LVTTL OBUF symbol names is as follows.

OBUF_<slew_rate>_<drive_strength>

<slew_rate> is either F (Fast), or S (Slow) and

<drive_strength> is specified in milliamps (2, 4, 6, 8, 12, 16,

or 24).

The following list details variations of the OBUF symbol.

•OBUF

•OBUF_S_2

•OBUF_S_4

•OBUF_S_6

•OBUF_S_8

•OBUF_S_12

•OBUF_S_16

•OBUF_S_24

•OBUF_F_2

•OBUF_F_4

•OBUF_F_6

•OBUF_F_8

•OBUF_F_12

•OBUF_F_16

•OBUF_F_24

•OBUF_LVCMOS2

•OBUF_PCI33_3

•OBUF_PCI66_3

•OBUF_GTL

•OBUF_GTLP

•OBUF_HSTL_I

•OBUF_HSTL_III

•OBUF_HSTL_IV

•OBUF_SSTL3_I

•OBUF_SSTL3_II

•OBUF_SSTL2_I

•OBUF_SSTL2_II

•OBUF_CTT

•OBUF_AGP

•OBUF_LVCMOS18

•OBUF_LVDS

•OBUF_LVPECL

The Virtex-E series supports eight banks for the HQ and PQ

packages. The CS packages support four VCCO banks.

OBUF placement restrictions require that within a given

VCCO bank each OBUF share the same output source drive

voltage. Input buffers of any type and output buffers that do

not require VCCO can be placed within any VCCO bank.

Table 20 summarizes the Virtex-E output compatibility

requirements. The LOC property can specify a location for

the OBUF.

OBUFT

The generic 3-state output buffer OBUFT, shown in

Figure 41, typically implements 3-state outputs or bidirec-

tional I/O.

The extension to the base name defines which I/O standard

OBUFT uses. With no extension specified for the generic

OBUFT symbol, the assumed standard is slew rate limited

LVTTL with 12 mA drive strength.

Figure 40: Virtex-E Output Buffer (OBUF) Symbol

OBUF

x133_04_111699

Table 20: Output Standards Compatibility

Requirements

Rule 1 Only outputs with standards that share compatible

VCCO can be used within the same bank.

Rule 2 There are no placement restrictions for outputs

with standards that do not require a VCCO.

VCCO Compatible Standards

3.3 LVTTL, SSTL3_I, SSTL3_II, CTT, AGP, GTL,

GTL+, PCI33_3, PCI66_3

2.5 SSTL2_I, SSTL2_II, LVCMOS2, GTL, GTL+

1.5 HSTL_I, HSTL_III, HSTL_IV, GTL, GTL+

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The LVTTL OBUFT additionally can support one of two slew

rate modes to minimize bus transients. By default, the slew

rate for each output buffer is reduced to minimize power bus

transients when switching non-critical signals.

LVTTL 3-state output buffers have selectable drive

strengths.

The format for LVTTL OBUFT symbol names is as follows.

OBUFT_<slew_rate>_<drive_strength>

<slew_rate> can be either F (Fast), or S (Slow) and

<drive_strength> is specified in milliamps (2, 4, 6, 8, 12, 16,

or 24).

The following list details variations of the OBUFT symbol.

•OBUFT

•OBUFT_S_2

•OBUFT_S_4

•OBUFT_S_6

•OBUFT_S_8

•OBUFT_S_12

•OBUFT_S_16

•OBUFT_S_24

•OBUFT_F_2

•OBUFT_F_4

•OBUFT_F_6

•OBUFT_F_8

•OBUFT_F_12

•OBUFT_F_16

•OBUFT_F_24

•OBUFT_LVCMOS2

•OBUFT_PCI33_3

•OBUFT_PCI66_3

•OBUFT_GTL

•OBUFT_GTLP

•OBUFT_HSTL_I

•OBUFT_HSTL_III

•OBUFT_HSTL_IV

•OBUFT_SSTL3_I

•OBUFT_SSTL3_II

•OBUFT_SSTL2_I

•OBUFT_SSTL2_II

•OBUFT_CTT

•OBUFT_AGP

•OBUFT_LVCMOS18

•OBUFT_LVDS

•OBUFT_LVPECL

The Virtex-E series supports eight banks for the HQ and PQ

packages. The CS package supports four VCCO banks.

The SelectI/O OBUFT placement restrictions require that

within a given VCCO bank each OBUFT share the same out-

put source drive voltage. Input buffers of any type and out-

put buffers that do not require VCCO can be placed within

the same VCCO bank.

The LOC property can specify a location for the OBUFT.

3-state output buffers and bidirectional buffers can have

either a weak pull-up resistor, a weak pull-down resistor, or

a weak “keeper” circuit. Control this feature by adding the

appropriate symbol to the output net of the OBUFT (PUL-

LUP, PULLDOWN, or KEEPER).

The weak “keeper” circuit requires the input buffer within the

IOB to sample the I/O signal. So, OBUFTs programmed for

an I/O standard that requires a VREF have automatic place-

ment of a VREF in the bank with an OBUFT configured with

a weak “keeper” circuit. This restriction does not affect most

circuit design as applications using an OBUFT configured

with a weak “keeper” typically implement a bidirectional I/O.

In this case the IBUF (and the corresponding VREF) are

explicitly placed.

The LOC property can specify a location for the OBUFT.

IOBUF

Use the IOBUF symbol for bidirectional signals that require

both an input buffer and a 3-state output buffer with an

active high 3-state pin. The generic input/output buffer

IOBUF appears in Figure 42.

The extension to the base name defines which I/O standard

the IOBUF uses. With no extension specified for the generic

IOBUF symbol, the assumed standard is LVTTL input buffer

and slew rate limited LVTTL with 12 mA drive strength for

the output buffer.

The LVTTL IOBUF additionally can support one of two slew

rate modes to minimize bus transients. By default, the slew

rate for each output buffer is reduced to minimize power bus

transients when switching non-critical signals.

LVTTL bidirectional buffers have selectable output drive

strengths.

The format for LVTTL IOBUF symbol names is as follows.

IOBUF_<slew_rate>_<drive_strength>

<slew_rate> can be either F (Fast), or S (Slow) and

<drive_strength> is specified in milliamps (2, 4, 6, 8, 12, 16,

or 24).

Figure 41: 3-State Output Buffer Symbol (OBUFT)

OBUFT

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36 1-800-255-7778

The following list details variations of the IOBUF symbol.

•IOBUF

•IOBUF_S_2

•IOBUF_S_4

•IOBUF_S_6

•IOBUF_S_8

•IOBUF_S_12

•IOBUF_S_16

•IOBUF_S_24

•IOBUF_F_2

•IOBUF_F_4

•IOBUF_F_6

•IOBUF_F_8

•IOBUF_F_12

•IOBUF_F_16

•IOBUF_F_24

•IOBUF_LVCMOS2

•IOBUF_PCI33_3

•IOBUF_PCI66_3

•IOBUF_GTL

•IOBUF_GTLP

•IOBUF_HSTL_I

•IOBUF_HSTL_III

•IOBUF_HSTL_IV

•IOBUF_SSTL3_I

•IOBUF_SSTL3_II

•IOBUF_SSTL2_I

•IOBUF_SSTL2_II

•IOBUF_CTT

•IOBUF_AGP

•IOBUF_LVCMOS18

•IOBUF_LVDS

•IOBUF_LVPECL

When the IOBUF symbol used supports an I/O standard

that requires a differential amplifier input, the IOBUF auto-

matically configures with a differential amplifier input buffer.

The low-voltage I/O standards with a differential amplifier

input require an external reference voltage input VREF

The voltage reference signal is “banked” within the Virtex-E

device on a half-edge basis such that for all packages there

are eight independent VREF banks internally. See Figure 38

on page 33 for a representation of the Virtex-E I/O banks.

Within each bank approximately one of every six I/O pins is

automatically configured as a VREF input. After placing a dif-

ferential amplifier input signal within a given VREF bank, the

same external source must drive all I/O pins configured as a

VREF input.

IOBUF placement restrictions require any differential ampli-

fier input signals within a bank be of the same standard.

The Virtex-E series supports eight banks for the HQ and PQ

packages. The CS package supports four VCCO banks.

Additional restrictions on the Virtex-E SelectI/O IOBUF

placement require that within a given VCCO bank each

IOBUF must share the same output source drive voltage.

Input buffers of any type and output buffers that do not

require VCCO can be placed within the same VCCO bank.

The LOC property can specify a location for the IOBUF.

An optional delay element is associated with the input path

in each IOBUF. When the IOBUF drives an input flip-flop

within the IOB, the delay element activates by default to

ensure a zero hold-time requirement. Override this default

with the NODELAY=TRUE property.

In the case when the IOBUF does not drive an input flip-flop

within the IOB, the delay element de-activates by default to

provide higher performance. To delay the input signal, acti-

vate the delay element with the DELAY=TRUE property.

3-state output buffers and bidirectional buffers can have

either a weak pull-up resistor, a weak pull-down resistor, or

a weak “keeper” circuit. Control this feature by adding the

appropriate symbol to the output net of the IOBUF (PUL-

LUP, PULLDOWN, or KEEPER).

SelectI/O Properties

Access to some of the SelectI/O features (for example, loca-

tion constraints, input delay, output drive strength, and slew

rate) is available through properties associated with these

features.

Input Delay Properties

An optional delay element is associated with each IBUF.

When the IBUF drives a flip-flop within the IOB, the delay

element activates by default to ensure a zero hold-time

requirement. Use the NODELAY=TRUE property to over-

ride this default.

In the case when the IBUF does not drive a flip-flop within

the IOB, the delay element by default de-activates to pro-

vide higher performance. To delay the input signal, activate

the delay element with the DELAY=TRUE property.

Figure 42: Input/Output Buffer Symbol (IOBUF)

IOBUF

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IOB Flip-Flop/Latch Property

The Virtex-E series I/O block (IOB) includes an optional reg-

ister on the input path, an optional register on the output

path, and an optional register on the 3-state control pin. The

design implementation software automatically takes advan-

tage of these registers when the following option for the Map

program is specified.

map -pr b <filename>

Alternatively, the IOB = TRUE property can be placed on a

Location Constraints

Specify the location of each SelectI/O symbol with the loca-

tion constraint LOC attached to the SelectI/O symbol. The

external port identifier indicates the value of the location

constrain. The format of the port identifier depends on the

package chosen for the specific design.

The LOC properties use the following form.

LOC=A42

LOC=P37

Output Slew Rate Property

As mentioned above, a variety of symbol names provide the

option of choosing the desired slew rate for the output buff-

ers. In the case of the LVTTL output buffers (OBUF, OBUFT,

and IOBUF), slew rate control can be alternatively pro-

gramed with the SLEW= property. By default, the slew rate

for each output buffer is reduced to minimize power bus

transients when switching non-critical signals. The SLEW=

property has one of the two following values.

SLEW=SLOW

SLEW=FAST

Output Drive Strength Property

The desired output drive strength can be additionally speci-

fied by choosing the appropriate library symbol. The Xilinx

library also provides an alternative method for specifying

this feature. For the LVTTL output buffers (OBUF, OBUFT,

and IOBUF, the desired drive strength can be specified with

the DRIVE= property. This property could have one of the

following seven values.

DRIVE=2

DRIVE=4

DRIVE=6

DRIVE=8

DRIVE=12 (Default)

DRIVE=16

DRIVE=24

Design Considerations

Reference Voltage (VREF) Pins

Low-voltage I/O standards with a differential amplifier input

buffer require an input reference voltage (VREF). Provide the

VREF as an external signal to the device.

The voltage reference signal is “banked” within the device on

a half-edge basis such that for all packages there are eight

independent VREF banks internally. See Figure 38 for a rep-

resentation of the Virtex-E I/O banks. Within each bank

approximately one of every six I/O pins is automatically con-

figured as a VREF input. After placing a differential amplifier

input signal within a given VREF bank, the same external

source must drive all I/O pins configured as a VREF input.

Within each VREF bank, any input buffers that require a

VREF signal must be of the same type. Output buffers of any

type and input buffers can be placed without requiring a ref-

erence voltage within the same VREF bank.

Output Drive Source Voltage (VCCO) Pins

Many of the low voltage I/O standards supported by

SelectI/O devices require a different output drive source

voltage (VCCO). As a result each device can often have to

support multiple output drive source voltages.

The Virtex-E series supports eight banks for the HQ and PQ

packages. The CS package supports four VCCO banks.

Output buffers within a given VCCO bank must share the

same output drive source voltage. Input buffers for LVTTL,

LVCMOS2, LVCMOS18, PCI33_3, and PCI 66_3 use the

VCCO voltage for Input VCCO voltage.

Transmission Line Effects

The delay of an electrical signal along a wire is dominated

by the rise and fall times when the signal travels a short dis-

tance. Transmission line delays vary with inductance and

capacitance, but a well-designed board can experience

delays of approximately 180 ps per inch.

Transmission line effects, or reflections, typically start at

1.5" for fast (1.5 ns) rise and fall times. Poor (or non-exis-

tent) termination or changes in the transmission line imped-

ance cause these reflections and can cause additional

delay in longer traces. As system speeds continue to

increase, the effect of I/O delays can become a limiting fac-

tor and therefore transmission line termination becomes

increasingly more important.

Termination Techniques

A variety of termination techniques reduce the impact of

transmission line effects.

The following are output termination techniques:

•None

•Series

•Parallel (Shunt)

•Series and Parallel (Series-Shunt)

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Input termination techniques include the following:

•None

•Parallel (Shunt)

These termination techniques can be applied in any combi-

nation. A generic example of each combination of termina-

tion methods appears in Figure 43.

Simultaneous Switching Guidelines

Ground bounce can occur with high-speed digital ICs when

multiple outputs change states simultaneously, causing

undesired transient behavior on an output, or in the internal

logic. This problem is also referred to as the Simultaneous

Switching Output (SSO) problem.

Ground bounce is primarily due to current changes in the

combined inductance of ground pins, bond wires, and

ground metallization. The IC internal ground level deviates

from the external system ground level for a short duration (a

few nanoseconds) after multiple outputs change state

simultaneously.

Ground bounce affects stable Low outputs and all inputs

because they interpret the incoming signal by comparing it

to the internal ground. If the ground bounce amplitude

exceeds the actual instantaneous noise margin, then a

non-changing input can be interpreted as a short pulse with

a polarity opposite to the ground bounce.

Table 21 provides the guidelines for the maximum number

of simultaneously switching outputs allowed per output

power/ground pair to avoid the effects of ground bounce.

Refer to Table 22 for the number of effective output

power/ground pairs for each Virtex-E device and package

combination.

Figure 43: Overview of Standard Input and Output

Termination Methods

x133_07_111699

Unterminated Double Parallel Terminated

Series-Parallel Terminated Output

Driving a Parallel Terminated Input

VTT

VREF

Series Terminated Output Driving

a Parallel Terminated Input

VTT

VREF

Unterminated Output Driving

a Parallel Terminated Input

VTT

VREF

VTT

VREF

Series Terminated Output

VREF

Z=50

Table 21: Guidelines for Maximum Number of

Simultaneously Switching Outputs per

Power/Ground Pair

Standard

Package

BGA, FGA

LVTTL Slow Slew Rate, 2 mA drive 68

LVTTL Slow Slew Rate, 4 mA drive 41

LVTTL Slow Slew Rate, 6 mA drive 29

LVTTL Slow Slew Rate, 8 mA drive 22

LVTTL Slow Slew Rate, 12 mA drive 17

LVTTL Slow Slew Rate, 16 mA drive 14

LVTTL Slow Slew Rate, 24 mA drive 9

LVTTL Fast Slew Rate, 2 mA drive 40

LVTTL Fast Slew Rate, 4 mA drive 24

LVTTL Fast Slew Rate, 6 mA drive 17

LVTTL Fast Slew Rate, 8 mA drive 13

LVTTL Fast Slew Rate, 12 mA drive 10

LVTTL Fast Slew Rate, 16 mA drive 8

LVTTL Fast Slew Rate, 24 mA drive 5

LVCMOS2 10

PCI 8

GTL 4

GTL+ 4

HSTL Class I 18

HSTL Class III 9

HSTL Class IV 5

SSTL2 Class I 15

SSTL2 Class II 10

SSTL3 Class I 11

SSTL3 Class II 7

CTT 14

AGP 9

Note: This analysis assumes a 35 pF load for each output.

Table 22: Virtex-E Extended Memory Family

Equivalent Power/Ground Pairs

Pkg/Part XCV405E XCV812E

BG560 56

FG676 56

FG900

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Application Examples

Creating a design with the SelectI/O features requires the

instantiation of the desired library symbol within the design

code. At the board level, designers need to know the termi-

nation techniques required for each I/O standard.

This section describes some common application examples

illustrating the termination techniques recommended by

each of the standards supported by the SelectI/O features.

Termination Examples

Circuit examples involving typical termination techniques for

each of the SelectI/O standards follow. For a full range of

accepted values for the DC voltage specifications for each

standard, refer to the table associated with each figure.

The resistors used in each termination technique example

and the transmission lines depicted represent board level

components and are not meant to represent components

on the device.

GTL

A sample circuit illustrating a valid termination technique for

GTL is shown in Figure 44. Tabl e 23 lists DC voltage speci-

fications.

GTL+

A sample circuit illustrating a valid termination technique for

GTL+ appears in Figure 45. DC voltage specifications

appear in Table 24.

Figure 44: Terminated GTL

VREF = 0.8V

VTT = 1.2V

50Ω

VCCO = N/A Z = 50

GTL

x133_08_111699

VTT = 1.2V

Table 23: GTL Voltage Specifications

Parameter Min Typ Max

VCCO -N/A-

VREF = N

VTT10.74 0.8 0.86

VTT 1.14 1.2 1.26

VIH = VREF + 0.05 0.79 0.85 -

VIL = VREF – 0.05 - 0.75 0.81

VOH ---

VOL -0.20.4

IOH at VOH(mA) ---

IOLat VOL(mA) at 0.4V 32 - -

IOLat VOL(mA) at 0.2V - - 40

Note: N must be greater than or equal to 0.653 and less than

or equal to 0.68.

Figure 45: Terminated GTL+

Table 24: GTL+ Voltage Specifications

Parameter Min Typ Max

VCCO -- -

VREF = N

VTT10.88 1.0 1.12

VTT 1.35 1.5 1.65

VIH = VREF + 0.1 0.98 1.1 -

VIL = VREF – 0.1 - 0.9 1.02

VOH -- -

VOL 0.3 0.45 0.6

IOH at VOH (mA) - - -

IOLat VOL (mA) at 0.6V 36 - -

IOLat VOL (mA) at 0.3V - - 48

Note: N must be greater than or equal to 0.653 and less than

or equal to 0.68.

VREF = 1.0V

VTT = 1.5V

50Ω

VCCO = N/A Z = 50

GTL+

x133_09_012400

50Ω

VTT = 1.5V

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HSTL

A sample circuit illustrating a valid termination technique for

HSTL_I appears in Figure 46. A sample circuit illustrating a

valid termination technique for HSTL_III appears in

Figure 47.

A sample circuit illustrating a valid termination technique for

HSTL_IV appears in Figure 48.

Figure 46: Terminated HSTL Class I

Table 25: HSTL Class I Voltage Specification

Parameter Min Typ Max

VCCO 1.40 1.50 1.60

VREF 0.68 0.75 0.90

VTT -V

CCO

0.5 -

VIH VREF + 0.1 - -

VIL --V

REF – 0.1

VOH VCCO – 0.4 - -

VOL 0.4

IOH at VOH (mA)

8- -

IOLat VOL (mA) 8 - -

Figure 47: Terminated HSTL Class III

VREF = 0.75V

VTT= 0.75V

50Ω

VCCO = 1.5V

Z = 50

HSTL Class I

x133_10_111699

VREF = 0.9V

VTT= 1.5V

50Ω

VCCO = 1.5V

Z = 50

HSTL Class III

x133_11_111699

Table 26: HSTL Class III Voltage Specification

Parameter Min Typ Max

VCCO 1.40 1.50 1.60

VREF (1) -0.90-

VTT -V

CCO -

VIH VREF + 0.1 - -

VIL --V

REF – 0.1

VOH VCCO – 0.4 - -

VOL --0.4

IOH at VOH (mA)

8--

IOLat VOL (mA) 24 - -

Note: Per EIA/JESD8-6, “The value of VREF is to be selected

by the user to provide optimum noise margin in the use

conditions specified by the user.”

Figure 48: Terminated HSTL Class IV

Table 27: HSTL Class IV Voltage Specification

Parameter Min Typ Max

VCCO 1.40 1.50 1.60

VREF -0.90 -

VTT -V

CCO -

VIH VREF + 0.1 - -

VIL --V

REF – 0.1

VOH VCCO – 0.4 - -

VOL --0.4

IOH at VOH (mA)

8- -

IOLat VOL (mA) 48 - -

Note: Per EIA/JESD8-6, “The value of VREF is to be selected

by the user to provide optimum noise margin in the use

conditions specified by the user.

50Ω

Z = 50

HSTL Class IV

x133_12_111699

50Ω

VREF = 0.9V

VTT= 1.5VVTT= 1.5V

VCCO = 1.5V

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SSTL3_I

A sample circuit illustrating a valid termination technique for

SSTL3_I appears in Figure 49. DC voltage specifications

appear in Table 28.

SSTL3_II

A sample circuit illustrating a valid termination technique for

SSTL3_II appears in Figure 50. DC voltage specifications

appear in Table 29.

SSTL2_I

A sample circuit illustrating a valid termination technique for

SSTL2_I appears in Figure 51. DC voltage specifications

appear in Table 30.

Figure 49: Terminated SSTL3 Class I

Table 28: SSTL3_I Voltage Specifications

Parameter Min Typ Max

VCCO 3.0 3.3 3.6

VREF = 0.45

VCCO 1.3 1.5 1.7

VTT = VREF 1.3 1.5 1.7

VIH = VREF + 0.2 1.5 1.7 3.9(1)

VIL = VREF – 0.2

0.3(2) 1.3 1.5

VOH = VREF + 0.6 1.9 - -

VOL = VREF – 0.6 - - 1.1

IOH at VOH (mA)

8- -

IOLat VOL (mA) 8 - -

Notes:

1. VIH maximum is VCCO + 0.3

2. VIL minimum does not conform to the formula

Figure 50: Terminated SSTL3 Class II

50Ω

Z = 50

SSTL3 Class I

x133_13_111699

25Ω

REF

= 1.5V

CCO

= 3.3V

50Ω

Z = 50

SSTL3 Class II

x133_14_111699

25Ω50Ω

VREF = 1.5V

VTT= 1.5VVTT= 1.5V

VCCO = 3.3V

Table 29: SSTL3_II Voltage Specifications

Parameter Min Typ Max

VCCO 3.0 3.3 3.6

VREF = 0.45

VCCO 1.3 1.5 1.7

VTT = VREF 1.3 1.5 1.7

VIH = VREF + 0.2 1.5 1.7 3.9(1)

VIL= VREF – 0.2

0.3(2) 1.3 1.5

VOH = VREF + 0.8 2.1 - -

VOL= VREF – 0.8 - - 0.9

IOH at VOH (mA)

16 - -

IOLat VOL (mA) 16 - -

Notes:

1. VIH maximum is VCCO + 0.3

2. VIL minimum does not conform to the formula

Figure 51: Terminated SSTL2 Class I

Table 30: SSTL2_I Voltage Specifications

Parameter Min Typ Max

VCCO 2.3 2.5 2.7

VREF = 0.5

VCCO 1.15 1.25 1.35

VTT = VREF + N(1) 1.11 1.25 1.39

VIH = VREF + 0.18 1.33 1.43 3.0(2)

VIL = VREF – 0.18

0.3(3) 1.07 1.17

VOH = VREF + 0.61 1.76 - -

VOL= VREF – 0.61 - - 0.74

IOH at VOH (mA)

7.6 - -

IOLat VOL (mA) 7.6 - -

Notes:

1. N must be greater than or equal to –0.04 and less than or

equal to 0.04.

2. VIH maximum is VCCO + 0.3.

3. VIL minimum does not conform to the formula.

50Ω

Z = 50

SSTL2 Class I

xap133_15_011000

25Ω

VREF = 1.25V

VTT= 1.25V

VCCO = 2.5V

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SSTL2_II

A sample circuit illustrating a valid termination technique for

SSTL2_II appears in Figure 52. DC voltage specifications

appear in Table 31.

CTT

A sample circuit illustrating a valid termination technique for

CTT appear in Figure 53. DC voltage specifications appear

in Table 32.

PCI33_3 & PCI66_3

PCI33_3 or PCI66_3 require no termination. DC voltage

specifications appear in Ta ble 33.

Figure 52: Terminated SSTL2 Class II

Table 31: SSTL2_II Voltage Specifications

Parameter Min Typ Max

VCCO 2.3 2.5 2.7

VREF = 0.5

VCCO 1.15 1.25 1.35

VTT = VREF + N(1) 1.11 1.25 1.39

VIH = VREF + 0.18 1.33 1.43 3.0(2)

VIL = VREF – 0.18

0.3(3) 1.07 1.17

VOH = VREF + 0.8 1.95 - -

VOL = VREF – 0.8 - - 0.55

IOH at VOH (mA)

15.2 - -

IOLat VOL (mA) 15.2 - -

Notes:

1. N must be greater than or equal to –0.04 and less than or

equal to 0.04.

2. VIH maximum is VCCO + 0.3.

3. VIL minimum does not conform to the formula.

Figure 53: Terminated CTT

50Ω

Z = 50

SSTL2 Class II

x133_16_111699

25Ω

50Ω

VREF = 1.25V

VTT= 1.25VVTT= 1.25V

VCCO = 2.5V

VREF= 1.5V

VTT = 1.5V

50Ω

VCCO = 3.3V

Z = 50

CTT

x133_17_111699

Table 32: CTT Voltage Specifications

Parameter Min Typ Max

VCCO 2.05(1) 3.3 3.6

VREF 1.35 1.5 1.65

VTT 1.35 1.5 1.65

VIH = VREF + 0.2 1.55 1.7 -

VIL = VREF – 0.2 - 1.3 1.45

VOH = VREF + 0.4 1.75 1.9 -

VOL= VREF – 0.4 - 1.1 1.25

IOH at VOH (mA)

8--

IOLat VOL (mA) 8 - -

Notes:

1. Timing delays are calculated based on VCCO min of 3.0V.

Table 33: PCI33_3 and PCI66_3 Voltage

Specifications

Parameter Min Typ Max

VCCO 3.0 3.3 3.6

VREF -- -

VTT -- -

VIH = 0.5

VCCO 1.5 1.65 VCCO+ 0.5

VIL = 0.3

VCCO

0.5 0.99 1.08

VOH = 0.9

VCCO 2.7 - -

VOL= 0.1

VCCO - - 0.36

IOH at VOH (mA) Note 1 - -

IOLat VOL (mA) Note 1 - -

Note 1: Tested according to the relevant specification.

Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays

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1-800-255-7778 43

LVTTL

LVTTL requires no termination. DC voltage specifications

appears in Table 34.

LVCMOS2

LVCMOS2 requires no termination. DC voltage specifica-

tions appear in Table 35 .

LVCMOS18

LVCMOS18 does not require termination. Table 36 lists DC

voltage specifications.

AGP-2X

The specification for the AGP-2X standard does not docu-

ment a recommended termination technique. DC voltage

specifications appear in Table 37.

Table 34: LVTTL Voltage Specifications

Parameter Min Typ Max

VCCO 3.0 3.3 3.6

VREF ---

VTT ---

VIH 2.0 - 3.6

VIL

0.5 - 0.8

VOH 2.4 - -

VOL --0.4

IOH at VOH (mA)

24 - -

IOLat VOL (mA) 24 - -

Note: VOLand VOH for lower drive currents sample tested.

Table 35: LVCMOS2 Voltage Specifications

Parameter Min Typ Max

VCCO 2.3 2.5 2.7

VREF ---

VTT ---

VIH 1.7 - 3.6

VIL

0.5 - 0.7

VOH 1.9 - -

VOL --0.4

IOH at VOH (mA)

12 - -

IOLat VOL (mA) 12 - -

Table 36: LVCMOS18 Voltage Specifications

Parameter Min Typ Max

VCCO 1.70 1.80 1.90

VREF ---

VTT ---

VIH 0.7 x VCCO -1.95

VIL – 0.5 - 0.2 x VCCO

VOH VCCO – 0.4 - -

VOL --0.4

IOH at VOH (mA) –8- -

IOLat VOL (mA) 8 - -

Table 37: AGP-2X Voltage Specifications

Parameter Min Typ Max

VCCO 3.0 3.3 3.6

VREF = N

VCCO(1) 1.17 1.32 1.48

VTT ---

VIH = VREF + 0.2 1.37 1.52 -

VIL = VREF – 0.2 - 1.12 1.28

VOH = 0.9

VCCO 2.7 3.0 -

VOL = 0.1

VCCO - 0.33 0.36

IOH at VOH (mA) Note 2 - -

IOLat VOL (mA) Note 2 - -

Notes:

1. N must be greater than or equal to 0.39 and less than or

equal to 0.41.

2. Tested according to the relevant specification.

Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays

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44 1-800-255-7778

LVDS

Depending on whether the device is transmitting an LVDS

signal or receiving an LVDS signal, there are two different

circuits used for LVDS termination. A sample circuit illustrat-

ing a valid termination technique for transmitting LVDS sig-

nals appears in Figure 54. A sample circuit illustrating a

valid termination for receiving LVDS signals appears in

Figure 55. Table 38 lists DC voltage specifications. Further

information on the specific termination resistor packs shown

can be found on Table 40.

LVPECL

Depending on whether the device is transmitting or receiv-

ing an LVPECL signal, two different circuits are used for

LVPECL termination. A sample circuit illustrating a valid ter-

mination technique for transmitting LVPECL signals

appears in Figure 56. A sample circuit illustrating a valid ter-

mination for receiving LVPECL signals appears in

Figure 57. Table 39 lists DC voltage specifications. Further

information on the specific termination resistor packs shown

can be found on Table 40.

Figure 54: Transmitting LVDS Signal Circuit

Figure 55: Receiving LVDS Signal Circuit

Table 38: LVDS Voltage Specifications

Parameter Min Typ Max

VCCO 2.375 2.5 2.625

VICM(2) 0.2 1.25 2.2

VOCM(1) 1.125 1.25 1.375

VIDIFF (1) 0.1 0.35 -

VODIFF (1) 0.25 0.35 0.45

VOH(1) 1.25 - -

VOL(1) - - 1.25

Notes:

1. Measured with a 100

resistor across Q and Q.

2. Measured with a differential input voltage =

350 mV.

x133_19_122799

QZ0 = 50Ω

Z0 = 50Ω

Virtex-E

FPGA

to LVDS Receiver

RDIV

140

165

2.5V

VCCO = 2.5V

LVDS

Output

DATA

Transmit

1/4 of Bourns

Part Number

CAT16-LV4F12

x133_29_122799

QZ0 = 50ΩLVDS_IN

LVDS_IN

Z0 = 50Ω

100Ω

DATA

Receive

from

LVDS

Driver

VIRTEX-E

FPGA

–

Figure 56: Transmitting LVPECL Signal Circuit

Figure 57: Receiving LVPECL Signal Circuit

Table 39: LVPECL Voltage Specifications

Parameter Min Typ Max

VCCO 3.0 3.3 3.6

VREF -- -

VTT -- -

VIH 1.49 - 2.72

VIL 0.86 - 2.125

VOH 1.8 - -

VOL - - 1.57

Note: For more detailed information, see LVPECL DC

Specifications

x133_20_122799

QZ0 = 50ΩLVPECL_OUT

LVPECL_OUT

Z0 = 50Ω

Virtex-E

FPGA

to LVPECL Receiver

RDIV

187

100

3.3V

DATA

Transmit

1/4 of Bourns

Part Number

CAT16-PC4F12

x133_21_122799

QZ0 = 50Ω

LVPECL_IN

Z0 = 50Ω

100Ω

DATA

Receive

from

LVPECL

Driver

VIRTEX-E

FPGA

–

Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays

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1-800-255-7778 45

Termination Resistor Packs

Resistor packs are available with the values and the config-

uration required for LVDS and LVPECL termination from

Bourns, Inc., as listed in Table. For pricing and availability,

please contact Bourns directly at www.bourns.com.

LVDS Design Guide

The SelectI/O library elements have been expanded for Vir-

tex-E devices to include new LVDS variants. At this time all

of the cells might not be included in the Synthesis libraries.

The 2.1i-Service Pack 2 update for Alliance and Foundation

software includes these cells in the VHDL and Verilog librar-

ies. It is necessary to combine these cells to create the

P-side (positive) and N-side (negative) as described in the

input, output, 3-state and bidirectional sections.

Creating LVDS Global Clock Input Buffers

The global clock input buffer can be combined with the adja-

cent IOB to form an LVDS clock input buffer. The P-side

resides in the GCLKPAD location and the N-side resides in

the adjacent IO_LVDS_DLL site.

HDL Instantiation

Only one global clock input buffer is required to be instanti-

ated in the design and placed on the correct GCLKPAD

location. The N-side of the buffer is reserved and no other

IOB is allowed to be placed on this location.

In the physical device, a configuration option is enabled that

routes the pad wire to the differential input buffer located in

the GCLKIOB. The output of this buffer then drives the out-

put of the GCLKIOB cell. In EPIC it appears that the second

buffer is unused. Any attempt to use this location for another

purpose leads to a DRC error in the software.

VHDL Instantiation

gclk0_p : IBUFG_LVDS port map

(I=>clk_external, O=>clk_internal);

Verilog Instantiation

IBUFG_LVDS gclk0_p (.I(clk_external),

.O(clk_internal));

Location Constraints

All LVDS buffers must be explicitly placed on a device. For

the global clock input buffers this can be done with the fol-

lowing constraint in the UCF or NCF file.

NET clk_external LOC = GCLKPAD3;

GCLKPAD3 can also be replaced with the package pin

name, such as D17 for the BG432 package.

Optional N-Side

Some designers might prefer to also instantiate the N-side

buffer for the global clock buffer. This allows the top-level net

list to include net connections for both PCB layout and sys-

tem-level integration. In this case, only the output P-side

IBUFG connection has a net connected to it. Since the

N-side IBUFG does not have a connection in the EDIF net

list, it is trimmed from the design in MAP.

VHDL Instantiation

gclk0_p : IBUFG_LVDS port map

(I=>clk_p_external, O=>clk_internal);

gclk0_n : IBUFG_LVDS port map

(I=>clk_n_external, O=>clk_internal);

Verilog Instantiation

IBUFG_LVDS gclk0_p (.I(clk_p_external),

.O(clk_internal));

IBUFG_LVDS gclk0_n (.I(clk_n_external),

.O(clk_internal));

Location Constraints

All LVDS buffers must be explicitly placed on a device. For

the global clock input buffers this can be done with the fol-

lowing constraint in the UCF or NCF file.

NET clk_p_external LOC = GCLKPAD3;

NET clk_n_external LOC = C17;

Table 40: Bourns LVDS/LVPECL Resistor Packs

Part Number I/O Standard

Term.

for:

Pairs/

Pack Pins

CAT16

LV2F6 LVDS Driver 2 8

CAT16

LV4F12 LVDS Driver 4 16

CAT16

PC2F6 LVPECL Driver 2 8

CAT16

PC4F12 LVPECL Driver 4 16

CAT16

PT2F2 LVDS/LVPECL Receiver 2 8

CAT16

PT4F4 LVDS/LVPECL Receiver 4 16

Figure 58: LVDS Elements

Table 41: Global Clock Input Buffer Pair Locations

Pkg

Pair 3 Pair 2 Pair 2 Pair 0

PNPN P N P N

BG560 A17 C18 D17 E17 AJ17 AM18 AL17 AM17

FG676 E13 B13 C13 F14 AB13 AF13 AA14 AC14

FG900C15A15E15E16AK16AH16 AJ16 AF16

IBUF_LVDS

OBUF_LVDS IOBUF_LVDS

OBUFT_LVDS

IBUFG_LVDS

x133_22_122299

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46 1-800-255-7778

GCLKPAD3 can also be replaced with the package pin

name, such as D17 for the BG432 package.

Creating LVDS Input Buffers

An LVDS input buffer can be placed in a wide number of IOB

locations. The exact location is dependent on the package

that is used. The Virtex-E package information lists the pos-

sible locations as IO_L#P for the P-side and IO_L#N for the

N-side where # is the pair number.

HDL Instantiation

Only one input buffer is required to be instantiated in the

design and placed on the correct IO_L#P location. The

N-side of the buffer is reserved and no other IOB is allowed

to be placed on this location. In the physical device, a con-

figuration option is enabled that routes the pad wire from the

IO_L#N IOB to the differential input buffer located in the

IO_L#P IOB. The output of this buffer then drives the output

of the IO_L#P cell or the input register in the IO_L#P IOB. In

EPIC it appears that the second buffer is unused. Any

attempt to use this location for another purpose leads to a

DRC error in the software.

VHDL Instantiation

data0_p : IBUF_LVDS port map (I=>data(0),

O=>data_int(0));

Verilog Instantiation

IBUF_LVDS data0_p (.I(data[0]),

.O(data_int[0]));

Location Constraints

All LVDS buffers must be explicitly placed on a device. For

the input buffers this can be done with the following con-

straint in the UCF or NCF file.

NET data<0> LOC = D28; # IO_L0P

Optional N-side

Some designers might prefer to also instantiate the N-side

buffer for the input buffer. This allows the top-level net list to

include net connections for both PCB layout and sys-

tem-level integration. In this case, only the output P-side

IBUF connection has a net connected to it. Since the N-side

IBUF does not have a connection in the EDIF net list, it is

trimmed from the design in MAP.

VHDL Instantiation

data0_p : IBUF_LVDS port map

(I=>data_p(0), O=>data_int(0));

data0_n : IBUF_LVDS port map

(I=>data_n(0), O=>open);

Verilog Instantiation

IBUF_LVDS data0_p (.I(data_p[0]),

.O(data_int[0]));

IBUF_LVDS data0_n (.I(data_n[0]), .O());

Location Constraints

All LVDS buffers must be explicitly placed on a device. For

the global clock input buffers this can be done with the fol-

lowing constraint in the UCF or NCF file.

NET data_p<0> LOC = D28; # IO_L0P

NET data_n<0> LOC = B29; # IO_L0N

Adding an Input Register

All LVDS buffers can have an input register in the IOB. The

input register is in the P-side IOB only. All the normal IOB

FDPE, FDR, FDRE, FDS, FDSE, LD, LDE, LDC, LDCE,

LDP, LDPE). The register elements can be inferred or

explicitly instantiated in the HDL code.

The register elements can be packed in the IOB using the

IOB property to TRUE on the register or by using “map -pr

[i|o|b]”, where “i” is inputs only, “o” is outputs only, and “b” is

both inputs and outputs.

To improve design coding times VHDL and Verilog synthe-

sis macro libraries available to explicitly create these struc-

tures. The input library macros are listed in Ta ble 42. The I

and IB inputs to the macros are the external net connec-

tions.

Table 42: Input Library Macros

Name Inputs Outputs

IBUFDS_FD_LVDS I, IB, C Q

IBUFDS_FDE_LVDS I, IB, CE, C Q

IBUFDS_FDC_LVDS I, IB, C, CLR Q

IBUFDS_FDCE_LVDS I, IB, CE, C, CLR Q

IBUFDS_FDP_LVDS I, IB, C, PRE Q

IBUFDS_FDPE_LVDS I, IB, CE, C, PRE Q

IBUFDS_FDR_LVDS I, IB, C, R Q

IBUFDS_FDRE_LVDS I, IB, CE, C, R Q

IBUFDS_FDS_LVDS I, IB, C, S Q

IBUFDS_FDSE_LVDS I, IB, CE, C, S Q

IBUFDS_LD_LVDS I, IB, G Q

IBUFDS_LDE_LVDS I, IB, GE, G Q

IBUFDS_LDC_LVDS I, IB, G, CLR Q

IBUFDS_LDCE_LVDS I, IB, GE, G, CLR Q

IBUFDS_LDP_LVDS I, IB, G, PRE Q

IBUFDS_LDPE_LVDS I, IB, GE, G, PRE Q

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1-800-255-7778 47

Creating LVDS Output Buffers

LVDS output buffer can be placed in wide number of IOB

locations. The exact location are dependent on the package

that is used. The Virtex-E package information lists the pos-

sible locations as IO_L#P for the P-side and IO_L#N for the

N-side where # is the pair number.

HDL Instantiation

Both output buffers are required to be instantiated in the

design and placed on the correct IO_L#P and IO_L#N loca-

tions. The IOB must have the same net source the following

pins, clock (C), set/reset (SR), output (O), output clock

enable (OCE). In addition, the output (O) pins must be

inverted with respect to each other, and if output registers

are used, the INIT states must be opposite values (one

HIGH and one LOW). Failure to follow these rules leads to

DRC errors in software.

VHDL Instantiation

data0_p : OBUF_LVDS port map

(I=>data_int(0), O=>data_p(0));

data0_inv: INV port map

(I=>data_int(0), O=>data_n_int(0));

data0_n : OBUF_LVDS port map

(I=>data_n_int(0), O=>data_n(0));

Verilog Instantiation

OBUF_LVDS data0_p (.I(data_int[0]),

.O(data_p[0]));

INV data0_inv (.I(data_int[0],

.O(data_n_int[0]);

OBUF_LVDS data0_n (.I(data_n_int[0]),

.O(data_n[0]));

Location Constraints

All LVDS buffers must be explicitly placed on a device. For

the output buffers this can be done with the following con-

straint in the UCF or NCF file.

NET data_p<0> LOC = D28; # IO_L0P

NET data_n<0> LOC = B29; # IO_L0N

Synchronous vs. Asynchronous Outputs

If the outputs are synchronous (registered in the IOB), then

any IO_L#P|N pair can be used. If the outputs are asynchro-

nous (no output register), then they must use one of the

pairs that are part of the same IOB group at the end of a

ROW or at the top/bottom of a COLUMN in the device.

The LVDS pairs that can be used as asynchronous outputs

are listed in the Virtex-E pinout tables. Some pairs are

marked as asynchronous-capable for all devices in that

package, and others are marked as available only for that

device in the package. If the device size might change at

some point in the product lifetime, then only the common

pairs for all packages should be used.

Adding an Output Register

All LVDS buffers can have an output register in the IOB. The

output registers must be in both the P-side and N-side IOBs.

All the normal IOB register options are available (FD, FDE,

FDC, FDCE, FDP, FDPE, FDR, FDRE, FDS, FDSE, LD,

LDE, LDC, LDCE, LDP, LDPE). The register elements can

be inferred or explicitly instantiated in the HDL code.

Special care must be taken to insure that the D pins of the

registers are inverted and that the INIT states of the regis-

ters are opposite. The clock pin (C), clock enable (CE) and

set/reset (CLR/PRE or S/R) pins must connect to the same

source. Failure to do this leads to a DRC error in the soft-

ware.

The register elements can be packed in the IOB using the

IOB property to TRUE on the register or by using the “map

-pr [i|o|b]” where “i” is inputs only, “o” is outputs only and “b”

is both inputs and outputs.

To improve design coding times VHDL and Verilog synthe-

sis macro libraries have been developed to explicitly create

these structures. The output library macros are listed in

Table 43. The O and OB inputs to the macros are the exter-

nal net connections.

Table 43: Output Library Macros

Name Inputs Outputs

OBUFDS_FD_LVDS D, C O, OB

OBUFDS_FDE_LVDS DD, CE, C O, OB

OBUFDS_FDC_LVDS D, C, CLR O, OB

OBUFDS_FDCE_LVDS D, CE, C, CLR O, OB

OBUFDS_FDP_LVDS D, C, PRE O, OB

OBUFDS_FDPE_LVDS D, CE, C, PRE O, OB

OBUFDS_FDR_LVDS D, C, R O, OB

OBUFDS_FDRE_LVDS D, CE, C, R O, OB

OBUFDS_FDS_LVDS D, C, S O, OB

OBUFDS_FDSE_LVDS D, CE, C, S O, OB

OBUFDS_LD_LVDS D, G O, OB

OBUFDS_LDE_LVDS D, GE, G O, OB

OBUFDS_LDC_LVDS D, G, CLR O, OB

OBUFDS_LDCE_LVDS D, GE, G, CLR O, OB

OBUFDS_LDP_LVDS D, G, PRE O, OB

OBUFDS_LDPE_LVDS D, GE, G, PRE O, OB

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48 1-800-255-7778

Creating LVDS Output 3-State Buffers

LVDS output 3-state buffers can be placed in a wide number

of IOB locations. The exact locations are dependent on the

package used. The Virtex-E package information lists the

possible locations as IO_L#P for the P-side and IO_L#N for

the N-side, where # is the pair number.

HDL Instantiation

Both output 3-state buffers are required to be instantiated in

the design and placed on the correct IO_L#P and IO_L#N

locations. The IOB must have the same net source the fol-

lowing pins, clock (C), set/reset (SR), 3-state (T), 3-state

clock enable (TCE), output (O), output clock enable (OCE).

In addition, the output (O) pins must be inverted with

respect to each other, and if output registers are used, the

INIT states must be opposite values (one High and one

Low). If 3-state registers are used, they must be initialized to

the same state. Failure to follow these rules leads to DRC

errors in the software.

VHDL Instantiation

data0_p: OBUFT_LVDS port map

(I=>data_int(0), T=>data_tri,

O=>data_p(0));

data0_inv: INV port map

(I=>data_int(0), O=>data_n_int(0));

data0_n: OBUFT_LVDS port map

(I=>data_n_int(0), T=>data_tri,

O=>data_n(0));

Verilog Instantiation

OBUFT_LVDS data0_p (.I(data_int[0]),

.T(data_tri), .O(data_p[0]));

INV data0_inv (.I(data_int[0],

.O(data_n_int[0]);

OBUFT_LVDS data0_n (.I(data_n_int[0]),

.T(data_tri), .O(data_n[0]));

Location Constraints

All LVDS buffers must be explicitly placed on a device. For

the output buffers this can be done with the following con-

straint in the UCF or NCF file.

NET data_p<0> LOC = D28; # IO_L0P

NET data_n<0> LOC = B29; # IO_L0N

Synchronous vs. Asynchronous 3-State Outputs

If the outputs are synchronous (registered in the IOB), then

any IO_L#P|N pair can be used. If the outputs are asynchro-

nous (no output register), then they must use one of the

pairs that are part of the same IOB group at the end of a

ROW or at the top/bottom of a COLUMN in the device. This

applies for either the 3-state pin or the data out pin.

LVDS pairs that can be used as asynchronous outputs are

listed in the Virtex-E pinout tables. Some pairs are marked

as “asynchronous capable” for all devices in that package,

and others are marked as available only for that device in

the package. If the device size might be changed at some

point in the product lifetime, then only the common pairs for

all packages should be used.

Adding Output and 3-State Registers

All LVDS buffers can have an output register in the IOB. The

output registers must be in both the P-side and N-side IOBs.

All the normal IOB register options are available (FD, FDE,

FDC, FDCE, FDP, FDPE, FDR, FDRE, FDS, FDSE, LD,

LDE, LDC, LDCE, LDP, LDPE). The register elements can

be inferred or explicitly instantiated in the HDL code.

Special care must be taken to insure that the D pins of the

registers are inverted and that the INIT states of the regis-

ters are opposite. The 3-state (T), 3-state clock enable

(CE), clock pin (C), output clock enable (CE) and set/reset

(CLR/PRE or S/R) pins must connect to the same source.

Failure to do this leads to a DRC error in the software.

The register elements can be packed in the IOB using the

IOB property to TRUE on the register or by using the “map

-pr [i|o|b]” where “i” is inputs only, “o” is outputs only and “b”

is both inputs and outputs.

To improve design coding times VHDL and Verilog synthe-

sis macro libraries have been developed to explicitly create

these structures. The input library macros are listed below.

The 3-state is configured to be 3-stated at GSR and when

the PRE,CLR,S or R is asserted and shares it's clock

enable with the output register. If this is not desirable, the

library can be updated by the user for the desired function-

ality. The O and OB inputs to the macros are the external

net connections.

Creating LVDS Bidirectional Buffer

LVDS bidirectional buffers can be placed in a wide number

of IOB locations. The exact locations are dependent on the

package used. The Virtex-E package information lists the

possible locations as IO_L#P for the P-side and IO_L#N for

the N-side, where # is the pair number.

HDL Instantiation

Both bidirectional buffers are required to be instantiated in

the design and placed on the correct IO_L#P and IO_L#N

locations. The IOB must have the same net source the fol-

lowing pins, clock (C), set/reset (SR), 3-state (T), 3-state

clock enable (TCE), output (O), output clock enable (OCE).

In addition, the output (O) pins must be inverted with

respect to each other, and if output registers are used, the

INIT states must be opposite values (one HIGH and one

LOW). If 3-state registers are used, they must be initialized

to the same state. Failure to follow these rules leads to DRC

errors in the software.

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VHDL Instantiation

data0_p: IOBUF_LVDS port map

(I=>data_out(0), T=>data_tri,

IO=>data_p(0), O=>data_int(0));

data0_inv: INV port map

(I=>data_out(0), O=>data_n_out(0));

data0_n : IOBUF_LVDS port map

(I=>data_n_out(0), T=>data_tri,

IO=>data_n(0), O=>open);

Verilog Instantiation

IOBUF_LVDS data0_p(.I(data_out[0]),

.T(data_tri), .IO(data_p[0]),

.O(data_int[0]);

INV data0_inv (.I(data_out[0],

.O(data_n_out[0]);

IOBUF_LVDS

data0_n(.I(data_n_out[0]),.T(data_tri),.

IO(data_n[0]).O());

Location Constraints

All LVDS buffers must be explicitly placed on a device. For

the output buffers this can be done with the following con-

straint in the UCF or NCF file.

NET data_p<0> LOC = D28; # IO_L0P

NET data_n<0> LOC = B29; # IO_L0N

Synchronous vs. Asynchronous Bidirectional

Buffers

If the output side of the bidirectional buffers are synchro-

nous (registered in the IOB), then any IO_L#P|N pair can be

used. If the output side of the bidirectional buffers are asyn-

chronous (no output register), then they must use one of the

pairs that is a part of the asynchronous LVDS IOB group.

This applies for either the 3-state pin or the data out pin.

The LVDS pairs that can be used as asynchronous bidirec-

tional buffers are listed in the Virtex-E pinout tables. Some

pairs are marked as asynchronous capable for all devices in

that package, and others are marked as available only for

that device in the package. If the device size might change

at some point in the product’s lifetime, then only the com-

mon pairs for all packages should be used.

Adding Output and 3-State Registers

All LVDS buffers can have output and input registers in the

IOB. The output registers must be in both the P-side and

N-side IOBs, the input register is only in the P-side. All the

normal IOB register options are available (FD, FDE, FDC,

FDCE, FDP, FDPE, FDR, FDRE, FDS, FDSE, LD, LDE,

LDC, LDCE, LDP, LDPE). The register elements can be

inferred or explicitly instantiated in the HDL code. Special

care must be taken to insure that the D pins of the registers

are inverted and that the INIT states of the registers are

opposite. The 3-state (T), 3-state clock enable (CE), clock

pin (C), output clock enable (CE), and set/reset (CLR/PRE

or S/R) pins must connect to the same source. Failure to do

this leads to a DRC error in the software.

The register elements can be packed in the IOB using the

IOB property to TRUE on the register or by using the “map

-pr [i|o|b]”, where “i” is inputs only, “o” is outputs only, and “b”

is both inputs and outputs. To improve design coding times,

VHDL and Verilog synthesis macro libraries have been

developed to explicitly create these structures. The bidirec-

tional I/O library macros are listed in Table 44.

The 3-state is configured to be 3-stated at GSR and when

the PRE, CLR, S, or R is asserted and shares its clock

enable with the output and input register. If this is not desir-

able, then the library can be updated with the desired func-

tionality by the user. The I/O and IOB inputs to the macros

are the external net connections.

Table 44: Bidirectional I/O Library Macros

Name Inputs Bidirectional Outputs

IOBUFDS_FD_LVDS D, T, C IO, IOB Q

IOBUFDS_FDE_LVDS D, T, CE, C IO, IOB Q

IOBUFDS_FDC_LVDS D, T, C, CLR IO, IOB Q

IOBUFDS_FDCE_LVDS D, T, CE, C, CLR IO, IOB Q

IOBUFDS_FDP_LVDS D, T, C, PRE IO, IOB Q

IOBUFDS_FDPE_LVDS D, T, CE, C, PRE IO, IOB Q

IOBUFDS_FDR_LVDS D, T, C, R IO, IOB Q

IOBUFDS_FDRE_LVDS D, T, CE, C, R IO, IOB Q

IOBUFDS_FDS_LVDS D, T, C, S IO, IOB Q

Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays

Module 2 of 4 www.xilinx.com DS025-2 (v2.0) November 16, 2001

50 1-800-255-7778

Revision History

The following table shows the revision history for this document.

Virtex-E Extended Memory Data Sheet

The Virtex-E Extended Memory Data Sheet contains the following modules:

•DS025-1, Virtex-E 1.8V Extended Memory FPGAs:

Introduction and Ordering Information (Module 1)

•DS025-2, Virtex-E 1.8V Extended Memory FPGAs:

Functional Description (Module 2)

•DS025-3, Virtex-E 1.8V Extended Memory FPGAs:

DC and Switching Characteristics (Module 3)

•DS025-4, Virtex-E 1.8V Extended Memory FPGAs:

Pinout Tables (Module 4)

IOBUFDS_FDSE_LVDS D, T, CE, C, S IO, IOB Q

IOBUFDS_LD_LVDS D, T, G IO, IOB Q

IOBUFDS_LDE_LVDS D, T, GE, G IO, IOB Q

IOBUFDS_LDC_LVDS D, T, G, CLR IO, IOB Q

IOBUFDS_LDCE_LVDS D, T, GE, G, CLR IO, IOB Q

IOBUFDS_LDP_LVDS D, T, G, PRE IO, IOB Q

IOBUFDS_LDPE_LVDS D, T, GE, G, PRE IO, IOB Q

Date Version Revision

03/23/00 1.0 Initial Xilinx release.

08/01/00 1.1 Accumulated edits and fixes. Upgrade to Preliminary. Preview -8 numbers added.

Reformatted to adhere to corporate documentation style guidelines. Minor changes in

BG560 pin-out table.

09/19/00 1.2 •In Table 3 (Module 4), FG676 Fine-Pitch BGA — XCV405E, the following pins are no

longer labeled as VREF: B7, G16, G26, W26, AF20, AF8, Y1, H1.

•Min values added to Virtex-E Electrical Characteristics tables.

11/20/00 1.3 •Updated speed grade -8 numbers in Virtex-E Electrical Characteristics tables

(Module 3).

•Updated minimums in Table 11 (Module 2), and added notes to Table 12 (Module 2).

•Added to note 2 of Absolute Maximum Ratings (Module 3).

•Changed all minimum hold times to –0.4 for Global Clock Set-Up and Hold for LVTTL

Standard, with DLL (Module 3).

•Revised maximum TDLLPW in -6 speed grade for DLL Timing Parameters (Module 3).

04/02/01 1.4 •In Table 4, FG676 Fine-Pitch BGA — XCV405E, pin B19 is no longer labeled as VREF,

and pin G16 is now labeled as VREF.

•Updated values in Virtex-E Switching Characteristics tables.

•Converted data sheet to modularized format.

04/19/01 1.5 •Modified Figure 30, which shows “DLL Generation of 4x Clock in Virtex-E Devices.”

07/23/01 1.6 •Made minor edits to text under Configuration.

11/16/01 2.0 •Added warning under Configuration section that attempting to load an incorrect

bitstream causes configuration to fail and can damage the device.

Table 44: Bidirectional I/O Library Macros (Continued)

Name Inputs Bidirectional Outputs