Freescale Semiconductor
Data Sheet: Technical Data
Contents
© Freescale Semiconductor, Inc., 2008,2012. All rights reserved.
Document Number: MPC5554
Rev. 4, May 2012
This document provides electrical specifications, pin
assignments, and package diagrams for the MPC5554
microcontroller device. For functional characteristics,
refer to the MPC5553/MPC5554 Microcontroller
Reference Manual.
1 Overview
The MPC5554 microcontroller (MCU) is a member of
the MPC5500 family of microcontrollers built on the
Power Architectureembedded technology. This family
of parts has many new features coupled with high
performance CMOS technology to provide substantial
reduction of cost per feature and significant performance
improvement over the MPC500 family.
The host processor core of this device complies with the
Power Architecture embedded category that is 100%
user-mode compatible (including floating point library)
with the original PowerPC instruction set. The embedded
architecture enhancements improve the performance in
embedded applications. The core also has additional
instructions, including digital signal processing (DSP)
instructions, beyond the original PowerPC instruction
set.
1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.2 Thermal Characteristics. . . . . . . . . . . . . . . . . . . . . . 5
3.3 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.4 EMI (Electromagnetic Interference) Characteristics 8
3.5 ESD (Electromagnetic Static Discharge) Characteris-
tics9
3.6 Voltage Regulator Controller (VRC) and
Power-On Reset (POR) Electrical Specifications9
3.7 Power-Up/Down Sequencing . . . . . . . . . . . . . . . . 10
3.8 DC Electrical Specifications. . . . . . . . . . . . . . . . . . 14
3.9 Oscillator and FMPLL Electrical Characteristics . . 20
3.10 eQADC Electrical Characteristics . . . . . . . . . . . . . 22
3.11 H7Fa Flash Memory Electrical Characteristics . . . 23
3.12 AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.13 AC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4 Mechanicals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.1 MPC5553546667 416 PBGA Pinout . . . . . . . . . . . 45
4.2 MPC5554 416-Pin Package Dimensions . . . . . . . 52
5 Revision History for the MPC5554 Data Sheet . . . . . . 54
5.1 Changes between Revision 3 and Revision 4 . . . . 54
5.2 Changes between Revision 2 and Revision 3 . . . . 54
MPC5554
Microcontroller Data Sheet
by: Microcontroller Division
MPC5554 Microcontroller Data Sheet, Rev. 4
Overview
Freescale Semiconductor2
The MPC5500 family of parts contains many new features coupled with high performance CMOS
technology to provide significant performance improvement over the MPC565.
The MPC5554 has two levels of memory hierarchy. The fastest accesses are to the 32-kilobytes (KB)
unified cache. The next level in the hierarchy contains the 64-KB on-chip internal SRAM and
two-megabytes (MB) internal flash memory. The internal SRAM and flash memory hold instructions and
data. The external bus interface is designed to support most of the standard memories used with the
MPC5xx family.
The complex input/output timer functions of the MPC5554 are performed by two enhanced time processor
unit (eTPU) engines. Each eTPU engine controls 32 hardware channels, providing a total of 64 hardware
channels. The eTPU has been enhanced over the TPU by providing: 24-bit timers, double-action hardware
channels, variable number of parameters per channel, angle clock hardware, and additional control and
arithmetic instructions. The eTPU is programmed using a high-level programming language.
The less complex timer functions of the MPC5554 are performed by the enhanced modular input/output
system (eMIOS). The eMIOS’ 24 hardware channels are capable of single-action, double-action,
pulse-width modulation (PWM), and modulus-counter operations. Motor control capabilities include
edge-aligned and center-aligned PWM.
Off-chip communication is performed by a suite of serial protocols including controller area networks
(FlexCANs), enhanced deserial/serial peripheral interfaces (DSPIs), and enhanced serial communications
interfaces (eSCIs). The DSPIs support pin reduction through hardware serialization and deserialization of
timer channels and general-purpose input/output (GPIOs) signals.
The MCU has an on-chip enhanced queued dual analog-to-digital converter (eQADC). 324 s40-channels.
The system integration unit (SIU) performs several chip-wide configuration functions. Pad configuration
and general-purpose input and output (GPIO) are controlled from the SIU. External interrupts and reset
control are also determined by the SIU. The internal multiplexer submodule provides multiplexing of
eQADC trigger sources, daisy chaining the DSPIs, and external interrupt signal multiplexing.
Ordering Information
MPC5554 Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor 3
2 Ordering Information
Figure 1. MPC5500 Family Part Number Example
Unless noted in this data sheet, all specifications apply from TL to TH.
Table 1. Orderable Part Numbers
Freescale Part Number1
1All devices are PPC5554, rather than MPC5554, until product qualifications are complete. Not all configurations are available in
the PPC parts.
Package Description
Speed (MHz) Operating Temperature 2
2The lowest ambient operating temperature is referenced by TL; the highest ambient operating temperature is referenced by TH.
Nominal Max. 3 (fMAX)
3Speed is the nominal maximum frequency. Max. speed is the maximum speed allowed including frequency modulation (FM).
82 MHz parts allow for 80 MHz system clock + 2% FM; 114 MHz parts allow for 112 MHz system clock + 2% FM; and132 MHz
parts allow for 128 MHz system clock + 2% FM.
Min. (TL)Max. (T
H)
MPC5554MVR132
MPC5554 416 package
Lead-free (PbFree)
132 132
–40° C 125° CMPC5554MVR112 112 114
MPC5554MVR80 80 82
MPC5554AVR132 132 132 –55° C 125° C
MPC5554MZP132
MPC5554 416 package
Leaded (SnPb)
132 132
–40° C 125° CMPC5554MZP112 112 114
MPC5554MZP80 80 82
MPC5554AZP132 132 132 –55° C 125° C
MPC M 80
R
Qualification status
Core code
Device number
Temperature range
Package identifier
Operating frequency (MHz)
Tape and reel status
Temperature Range
M = –40° C to 125° C
A = –55° C to 125° C
Package Identifier
ZP = 416PBGA SnPb
VR = 416PBGA Pb-free
Operating Frequency
80 = 80 MHz
112 = 112 MHz
132 = 132 MHz
Tape and Reel Status
R2 = Tape and reel
(blank) = Trays
Qualification Status
P = Pre qualification
M = Fully spec. qualified
5554 ZP
Note: Not all options are available on all devices. Refer to Ta bl e 1.
2
MPC5554 Microcontroller Data Sheet, Rev. 4
Electrical Characteristics
Freescale Semiconductor4
3 Electrical Characteristics
This section contains detailed information on power considerations, DC/AC electrical characteristics, and
AC timing specifications for the MCU.
3.1 Maximum Ratings
Table 2. Absolute Maximum Ratings 1
Spec Characteristic Symbol Min. Max. Unit
1 1.5 V core supply voltage 2VDD –0.3 1.7 V
2 Flash program/erase voltage VPP –0.3 6.5 V
4 Flash read voltage VFLASH –0.3 4.6 V
5 SRAM standby voltage VSTBY –0.3 1.7 V
6 Clock synthesizer voltage VDDSYN –0.3 4.6 V
7 3.3 V I/O buffer voltage VDD33 –0.3 4.6 V
8 Voltage regulator control input voltage VRC33 –0.3 4.6 V
9 Analog supply voltage (reference to VSSA)V
DDA –0.3 5.5 V
10 I/O supply voltage (fast I/O pads) 3VDDE –0.3 4.6 V
11 I/O supply voltage (slow and medium I/O pads) 3VDDEH –0.3 6.5 V
12 DC input voltage 4
VDDEH powered I/O pads
VDDE powered I/O pads
VIN
–1.0 5
–1.0 5
6.5 6
4.6 7
V
13 Analog reference high voltage (reference to VRL)V
RH –0.3 5.5 V
14 VSS to VSSA differential voltage VSS – VSSA –0.1 0.1 V
15 VDD to VDDA differential voltage VDD – VDDA –VDDA VDD V
16 VREF differential voltage VRH – VRL –0.3 5.5 V
17 VRH to VDDA differential voltage VRH – VDDA –5.5 5.5 V
18 VRL to VSSA differential voltage VRL – VSSA –0.3 0.3 V
19 VDDEH to VDDA differential voltage VDDEH – VDDA –VDDA VDDEH V
20 VDDF to VDD differential voltage VDDF – VDD –0.3 0.3 V
21 VRC33 to VDDSYN differential voltage spec has been moved to Ta b le 9 DC Electrical Specifications, Spec 43a.
22 VSSSYN to VSS differential voltage VSSSYN – VSS –0.1 0.1 V
23 VRCVSS to VSS differential voltage VRCVSS – VSS –0.1 0.1 V
24 Maximum DC digital input current 8
(per pin, applies to all digital pins) 4 IMAXD –2 2 mA
25 Maximum DC analog input current 9
(per pin, applies to all analog pins)
IMAXA –3 3 mA
26 Maximum operating temperature range 10
Die junction temperature
TJTL150.0 oC
27 Storage temperature range TSTG –55.0 150.0 oC
Electrical Characteristics
MPC5554 Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor 5
3.2 Thermal Characteristics
The shaded rows in the following table indicate information specific to a four-layer board.
28 Maximum solder temperature 11
Lead free (Pb-free)
Leaded (SnPb)
TSDR —
—
260.0
245.0
oC
29 Moisture sensitivity level 12 MSL — 3
1Functional operating conditions are given in the DC electrical specifications. Absolute maximum ratings are stress ratings only,
and functional operation at the maxima is not guaranteed. Stress beyond any of the listed maxima can affect device reliability
or cause permanent damage to the device.
21.5 V ± 10% for proper operation. This parameter is specified at a maximum junction temperature of 150 oC.
3All functional non-supply I/O pins are clamped to VSS and VDDE, or VDDEH.
4AC signal overshoot and undershoot of up to ± 2.0 V of the input voltages is permitted for an accumulative duration of
60 hours over the complete lifetime of the device (injection current not limited for this duration).
5Internal structures hold the voltage greater than –1.0 V if the injection current limit of 2 mA is met. Keep the negative DC
voltage greater than –0.6 V on eTPUB[15] and SINB during the internal power-on reset (POR) state.
6Internal structures hold the input voltage less than the maximum voltage on all pads powered by VDDEH supplies, if the
maximum injection current specification is met (2 mA for all pins) and VDDEH is within the operating voltage specifications.
7Internal structures hold the input voltage less than the maximum voltage on all pads powered by VDDE supplies, if the maximum
injection current specification is met (2 mA for all pins) and VDDE is within the operating voltage specifications.
8Total injection current for all pins (including both digital and analog) must not exceed 25 mA.
9Total injection current for all analog input pins must not exceed 15 mA.
10 Lifetime operation at these specification limits is not guaranteed.
11 Moisture sensitivity profile per IPC/JEDEC J-STD-020D.
12 Moisture sensitivity per JEDEC test method A112.
Table 3. MPC5554 Thermal Characteristics
Spec MPC5554 Thermal Characteristic Symbol 416 PBGA Unit
1 Junction to ambient 1, 2, natural convection (one-layer board)
1Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal
resistance.
2Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board horizontal.
RJA 24 °C/W
2Junction to ambient 1, 3, natural convection (four-layer board 2s2p)
3Per JEDEC JESD51-6 with the board horizontal.
RJA 18 °C/W
3 Junction to ambient 1, 3 (@200 ft./min., one-layer board) RJMA 19 °C/W
4Junction to ambient 1, 3 (@200 ft./min., four-layer board 2s2p) RJMA 15 °C/W
5Junction to board 4 (four-layer board 2s2p)
4Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on
the top surface of the board near the package.
RJB 9°C/W
6 Junction to case 5
5Indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method
(MIL SPEC-883 Method 1012.1) with the cold plate temperature used for the case temperature.
RJC 5°C/W
7 Junction to package top 6, natural convection
6Thermal characterization parameter indicating the temperature difference between package top and the junction temperature
per JEDEC JESD51-2.
JT 2°C/W
Table 2. Absolute Maximum Ratings 1 (continued)
Spec Characteristic Symbol Min. Max. Unit
MPC5554 Microcontroller Data Sheet, Rev. 4
Electrical Characteristics
Freescale Semiconductor6
3.2.1 General Notes for Specifications at Maximum Junction Temperature
An estimation of the device junction temperature, TJ, can be obtained from the equation:
TJ = TA + (RJA PD)
where:
TA = ambient temperature for the package (oC)
RJA = junction to ambient thermal resistance (oC/W)
PD = power dissipation in the package (W)
The thermal resistance values used are based on the JEDEC JESD51 series of standards to provide
consistent values for estimations and comparisons. The difference between the values determined for the
single-layer (1s) board compared to a four-layer board that has two signal layers, a power and a ground
plane (2s2p), demonstrate that the effective thermal resistance is not a constant. The thermal resistance
depends on the:
• Construction of the application board (number of planes)
• Effective size of the board which cools the component
• Quality of the thermal and electrical connections to the planes
• Power dissipated by adjacent components
Connect all the ground and power balls to the respective planes with one via per ball. Using fewer vias to
connect the package to the planes reduces the thermal performance. Thinner planes also reduce the thermal
performance. When the clearance between the vias leave the planes virtually disconnected, the thermal
performance is also greatly reduced.
As a general rule, the value obtained on a single-layer board is within the normal range for the tightly
packed printed circuit board. The value obtained on a board with the internal planes is usually within the
normal range if the application board has:
• One oz. (35 micron nominal thickness) internal planes
• Components are well separated
• Overall power dissipation on the board is less than 0.02 W/cm2
The thermal performance of any component depends on the power dissipation of the surrounding
components. In addition, the ambient temperature varies widely within the application. For many natural
convection and especially closed box applications, the board temperature at the perimeter (edge) of the
package is approximately the same as the local air temperature near the device. Specifying the local
ambient conditions explicitly as the board temperature provides a more precise description of the local
ambient conditions that determine the temperature of the device.
Electrical Characteristics
MPC5554 Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor 7
At a known board temperature, the junction temperature is estimated using the following equation:
TJ = TB + (RJB PD)
where:
TJ = junction temperature (oC)
TB = board temperature at the package perimeter (oC/W)
RJB = junction-to-board thermal resistance (oC/W) per JESD51-8
PD = power dissipation in the package (W)
When the heat loss from the package case to the air does not factor into the calculation, an acceptable value
for the junction temperature is predictable. Ensure the application board is similar to the thermal test
condition, with the component soldered to a board with internal planes.
The thermal resistance is expressed as the sum of a junction-to-case thermal resistance plus a
case-to-ambient thermal resistance:
RJA = RJC + RCA
where:
RJA = junction-to-ambient thermal resistance (oC/W)
RJC = junction-to-case thermal resistance (oC/W)
RCA = case-to-ambient thermal resistance (oC/W)
RJC is device related and is not affected by other factors. The thermal environment can be controlled to
change the case-to-ambient thermal resistance, RCA. For example, change the air flow around the device,
add a heat sink, change the mounting arrangement on the printed circuit board, or change the thermal
dissipation on the printed circuit board surrounding the device. This description is most useful for
packages with heat sinks where 90% of the heat flow is through the case to heat sink to ambient.
For most packages, a better model is required.
A more accurate two-resistor thermal model can be constructed from the junction-to-board thermal
resistance and the junction-to-case thermal resistance. The junction-to-case thermal resistance describes
when using a heat sink or where a substantial amount of heat is dissipated from the top of the package. The
junction-to-board thermal resistance describes the thermal performance when most of the heat is
conducted to the printed circuit board. This model can be used to generate simple estimations and for
computational fluid dynamics (CFD) thermal models.
To determine the junction temperature of the device in the application on a prototype board, use the
thermal characterization parameter (JT) to determine the junction temperature by measuring the
temperature at the top center of the package case using the following equation:
TJ = TT + (JT PD)
where:
TT = thermocouple temperature on top of the package (oC)
JT = thermal characterization parameter (oC/W)
PD = power dissipation in the package (W)
MPC5554 Microcontroller Data Sheet, Rev. 4
Electrical Characteristics
Freescale Semiconductor8
The thermal characterization parameter is measured in compliance with the JESD51-2 specification using
a 40-gauge type T thermocouple epoxied to the top center of the package case. Position the thermocouple
so that the thermocouple junction rests on the package. Place a small amount of epoxy on the thermocouple
junction and approximately 1 mm of wire extending from the junction. Place the thermocouple wire flat
against the package case to avoid measurement errors caused by the cooling effects of the thermocouple
wire.
References:
Semiconductor Equipment and Materials International
3081 Zanker Rd.
San Jose, CA., 95134
(408) 943-6900
MIL-SPEC and EIA/JESD (JEDEC) specifications are available from Global Engineering Documents at
800-854-7179 or 303-397-7956.
JEDEC specifications are available on the web at http://www.jedec.org.
1. C.E. Triplett and B. Joiner, “An Experimental Characterization of a 272 PBGA Within an Automotive
Engine Controller Module,” Proceedings of SemiTherm, San Diego, 1998, pp. 47–54.
2. G. Kromann, S. Shidore, and S. Addison, “Thermal Modeling of a PBGA for Air-Cooled Applica-
tions,” Electronic Packaging and Production, pp. 53–58, March 1998.
3. B. Joiner and V. Adams, “Measurement and Simulation of Junction to Board Thermal Resistance and
Its Application in Thermal Modeling,” Proceedings of SemiTherm, San Diego, 1999, pp. 212–220.
3.3 Package
The MPC5554 is available in packaged form. Read the package options in Section 2, “Ordering
Information.” Refer to Section 4, “Mechanicals,” for pinouts and package drawings.
3.4 EMI (Electromagnetic Interference) Characteristics
Table 4. EMI Testing Specifications 1
1EMI testing and I/O port waveforms per SAE J1752/3 issued 1995-03. Qualification testing was performed on the MPC5554
and applied to the MPC5500 family as generic EMI performance data.
Spec Characteristic Minimum Typical Maximum Unit
1 Scan range 0.15 — 1000 MHz
2 Operating frequency — — fMAX MHz
3V
DD operating voltages — 1.5 — V
4V
DDSYN, VRC33, VDD33, VFLASH, VDDE operating voltages — 3.3 — V
5V
PP
, VDDEH, VDDA operating voltages — 5.0 — V
6 Maximum amplitude — — 14 2
32 3
2Measured with the single-chip EMI program.
3Measured with the expanded EMI program.
dBuV
7 Operating temperature — — 25 oC
Electrical Characteristics
MPC5554 Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor 9
3.5 ESD (Electromagnetic Static Discharge) Characteristics
3.6 Voltage Regulator Controller (VRC) and
Power-On Reset (POR) Electrical Specifications
The following table lists the VRC and POR electrical specifications:
Table 5. ESD Ratings 1, 2
1All ESD testing conforms to CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits.
2Device failure is defined as: ‘If after exposure to ESD pulses, the device does not meet the device specification requirements,
which includes the complete DC parametric and functional testing at room temperature and hot temperature.
Characteristic Symbol Value Unit
ESD for human body model (HBM) 2000 V
HBM circuit description R1 1500
C100 pF
ESD for field induced charge model (FDCM) 500 (all pins)
V
750 (corner pins)
Number of pulses per pin:
Positive pulses (HBM)
Negative pulses (HBM)
—
—
1
1
—
—
Interval of pulses — 1 second
Table 6. VRC and POR Electrical Specifications
Spec Characteristic Symbol Min. Max. Units
11.5 V (V
DD) POR 1Negated (ramp up)
Asserted (ramp down) VPOR15
1.1
1.1
1.35
1.35 V
23.3 V (V
DDSYN) POR 1
Asserted (ramp up)
Negated (ramp up)
Asserted (ramp down)
Negated (ramp down)
VPOR33
0.0
2.0
2.0
0.0
0.30
2.85
2.85
0.30
V
3RESET pin supply
(VDDEH6) POR 1, 2
Negated (ramp up)
Asserted (ramp down) VPOR5
2.0
2.0
2.85
2.85 V
4
VRC33 voltage
Before VRC allows the pass
transistor to start turning on VTRANS_START 1.0 2.0 V
5When VRC allows the pass
transistor to completely turn on 3, 4VTRANS_ON 2.0 2.85 V
6
When the voltage is greater than
the voltage at which the VRC keeps
the 1.5 V supply in regulation 5, 6
VVRC33REG 3.0 — V
– 55o C711.0 — mA
Current can be sourced –40o C11.0—mA
7 by VRCCTL at Tj: 25o CI
VRCCTL 89.0 — mA
150o C 7.5 — mA
MPC5554 Microcontroller Data Sheet, Rev. 4
Electrical Characteristics
Freescale Semiconductor10
3.7 Power-Up/Down Sequencing
Power sequencing between the 1.5 V power supply and VDDSYN or the RESET power supplies is required
if using an external 1.5 V power supply with VRC33 tied to ground (GND). To avoid power-sequencing,
VRC33 must be powered up within the specified operating range, even if the on-chip voltage regulator
controller is not used. Refer to Section 3.7.2, “Power-Up Sequence (VRC33 Grounded),” and
Section 3.7.3, “Power-Down Sequence (VRC33 Grounded).”
Power sequencing requires that VDD33 must reach a certain voltage where the values are read as ones
before the POR signal negates. Refer to Section 3.7.1, “Input Value of Pins During POR Dependent on
VDD33.”
Although power sequencing is not required between VRC33 and VDDSYN during power up, VRC33 must
not lead VDDSYN by more than 600 mV or lag by more than 100 mV for the VRC stage turn-on to operate
within specification. Higher spikes in the emitter current of the pass transistor occur if VRC33 leads or lags
VDDSYN by more than these amounts. The value of that higher spike in current depends on the board power
supply circuitry and the amount of board level capacitance.
8
Voltage differential during power up such that:
VDD33 can lag VDDSYN or VDDEH6 before VDDSYN and VDDEH6 reach the
VPOR33 and VPOR5 minimums respectively.
VDD33_LAG —1.0V
9 Absolute value of slew rate on power supply pins — — 50 V/ms
10
Required gain at Tj:
IDD IVRCCTL (@ fsys = fMAX)6, 8, 9, 10
– 55o C7
BETA11
70 — —
– 40o C70——
25o C85
11 ——
150o C 10511 500 —
1The internal POR signals are VPOR15, VPOR33, and VPOR5. On power up, assert RESET before the internal POR negates.
RESET must remain asserted until the power supplies are within the operating conditions as specified in Ta b l e 9 DC Electrical
Specifications. On power down, assert RESET before any power supplies fall outside the operating conditions and until the
internal POR asserts.
2VIL_S (Ta b l e 9 , Spec15) is guaranteed to scale with VDDEH6 down to VPOR5.
3Supply full operating current for the 1.5 V supply when the 3.3 V supply reaches this range.
4It is possible to reach the current limit during ramp up—do not treat this event as short circuit current.
5At peak current for device.
6Requires compliance with Freescale’s recommended board requirements and transistor recommendations. Board signal
traces/routing from the VRCCTL package signal to the base of the external pass transistor and between the emitter of the pass
transistor to the VDD package signals must have a maximum of 100 nH inductance and minimal resistance
(less than 1 ). VRCCTL must have a nominal 1 F phase compensation capacitor to ground. VDD must have a 20 F (nominal)
bulk capacitor (greater than 4 F over all conditions, including lifetime). Place high-frequency bypass capacitors consisting of
eight 0.01 F, two 0.1 F, and one 1 F capacitors around the package on the VDD supply signals.
7Only available on devices that support -55o C.
8IVRCCTL is measured at the following conditions: VDD = 1.35 V, VRC33 = 3.1 V, VVRCCTL = 2.2 V.
9Refer to Ta b l e 1 for the maximum operating frequency.
10 Values are based on IDD from high-use applications as explained in the IDD Electrical Specification.
11 BETA represents the worst-case external transistor. It is measured on a per-part basis and calculated as (IDD IVRCCTL).
Table 6. VRC and POR Electrical Specifications (continued)
Spec Characteristic Symbol Min. Max. Units
Electrical Characteristics
MPC5554 Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor 11
Furthermore, when all of the PORs negate, the system clock starts to toggle, adding another large increase
of the current consumed by VRC33. If VRC33 lags VDDSYN by more than 100 mV, the increase in current
consumed can drop VDD low enough to assert the 1.5 V POR again. Oscillations are possible when the
1.5 V POR asserts and stops the system clock, causing the voltage on VDD to rise until the 1.5 V POR
negates again. All oscillations stop when VRC33 is powered sufficiently.
When powering down, VRC33 and VDDSYN have no delta requirement to each other, because the bypass
capacitors internal and external to the device are already charged. When not powering up or down, no delta
between VRC33 and VDDSYN is required for the VRC to operate within specification.
There are no power up/down sequencing requirements to prevent issues such as latch-up, excessive current
spikes, and so on. Therefore, the state of the I/O pins during power up and power down varies depending
on which supplies are powered.
Table 7 gives the pin state for the sequence cases for all pins with pad type pad_fc (fast type).
Table 8 gives the pin state for the sequence cases for all pins with pad type pad_mh (medium type) and
pad_sh (slow type).
The values in Table 7 and Table 8 do not include the effect of the weak-pull devices on the output pins
during power up.
Before exiting the internal POR state, the voltage on the pins go to a high-impedance state until POR
negates. When the internal POR negates, the functional state of the signal during reset applies and the
weak-pull devices
(up or down) are enabled as defined in the device reference manual. If VDD is too low to correctly
propagate the logic signals, the weak-pull devices can pull the signals to VDDE and VDDEH.
Table 7. Pin Status for Fast Pads During the Power Sequence
VDDE VDD33 VDD POR
Pin Status for Fast Pad Output Driver
pad_fc (fast)
Low — — Asserted Low
VDDE Low Low Asserted High
VDDE Low VDD Asserted High
VDDE VDD33 Low Asserted High impedance (Hi-Z)
VDDE VDD33 VDD Asserted Hi-Z
VDDE VDD33 VDD Negated Functional
Table 8. Pin Status for Medium and Slow Pads During the Power Sequence
VDDEH VDD POR
Pin Status for Medium and Slow Pad Output Driver
pad_mh (medium) pad_sh (slow)
Low — Asserted Low
VDDEH Low Asserted High impedance (Hi-Z)
VDDEH VDD Asserted Hi-Z
VDDEH VDD Negated Functional
MPC5554 Microcontroller Data Sheet, Rev. 4
Electrical Characteristics
Freescale Semiconductor12
To avoid this condition, minimize the ramp time of the VDD supply to a time period less than the time
required to enable the external circuitry connected to the device outputs.
During initial power ramp-up, when Vstby is 0.6v or above. a typical current of 1-3mA and maximum of
4mA may be seen until VDD is applied. This current will not reoccur until Vstby is lowered below Vstby
min. specification.
Figure 2 shows an approximate interpolation of the ISTBY worst-case specification to estimate values at
different voltages and temperatures. The vertical lines shown at 25 C, 60 C, and 150 C in Figure 2 are
the actual IDD_STBY specifications (27d) listed in Table 9.
Figure 2. fISTBY Worst-case Specifications
Electrical Characteristics
MPC5554 Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor 13
3.7.1 Input Value of Pins During POR Dependent on VDD33
When powering up the device, VDD33 must not lag the latest VDDSYN or RESET power pin (VDDEH6) by
more than the VDD33 lag specification listed in Table 6, spec 8. This avoids accidentally selecting the
bypass clock mode because the internal versions of PLLCFG[0:1] and RSTCFG are not powered and
therefore cannot read the default state when POR negates. VDD33 can lag VDDSYN or the RESET power
pin (VDDEH6), but cannot lag both by more than the VDD33 lag specification. This VDD33 lag specification
applies during power up only. VDD33 has no lead or lag requirements when powering down.
3.7.2 Power-Up Sequence (VRC33 Grounded)
The 1.5 V VDD power supply must rise to 1.35 V before the 3.3 V VDDSYN power supply and the RESET
power supply rises above 2.0 V. This ensures that digital logic in the PLL for the 1.5 V power supply does
not begin to operate below the specified operation range lower limit of 1.35 V. Because the internal 1.5 V
POR is disabled, the internal 3.3 V POR or the RESET power POR must hold the device in reset. Since
they can negate as low as 2.0 V, VDD must be within specification before the 3.3 V POR and the RESET
POR negate.
Figure 3. Power-Up Sequence (VRC33 Grounded)
3.7.3 Power-Down Sequence (VRC33 Grounded)
The only requirement for the power-down sequence with VRC33 grounded is if VDD decreases to less than
its operating range, VDDSYN or the RESET power must decrease to less than 2.0 V before the VDD power
increases to its operating range. This ensures that the digital 1.5 V logic, which is reset only by an ORed
POR and can cause the 1.5 V supply to decrease less than its specification value, resets correctly. See
Table 6, footnote 1.
VDDSYN and RESET Power
VDD
2.0 V
1.35 V
VDD must reach 1.35 V before VDDSYN and the RESET power reach 2.0 V
MPC5554 Microcontroller Data Sheet, Rev. 4
Electrical Characteristics
Freescale Semiconductor14
3.8 DC Electrical Specifications
Table 9. DC Electrical Specifications (TA = TL to TH)
Spec Characteristic Symbol Min Max. Unit
1 Core supply voltage (average DC RMS voltage) VDD 1.35 1.65 V
2 Input/output supply voltage (fast input/output) 1VDDE 1.62 3.6 V
3 Input/output supply voltage (slow and medium input/output) VDDEH 3.0 5.25 V
4 3.3 V input/output buffer voltage VDD33 3.0 3.6 V
5 Voltage regulator control input voltage VRC33 3.0 3.6 V
6 Analog supply voltage 2VDDA 4.5 5.25 V
8 Flash programming voltage 3VPP 4.5 5.25 V
9 Flash read voltage VFLASH 3.0 3.6 V
10 SRAM standby voltage 4VSTBY 0.8 1.2 V
11 Clock synthesizer operating voltage VDDSYN 3.0 3.6 V
12 Fast I/O input high voltage VIH_F 0.65 VDDE VDDE + 0.3 V
13 Fast I/O input low voltage VIL_F VSS – 0.3 0.35 VDDE V
14 Medium and slow I/O input high voltage VIH_S 0.65 VDDEH VDDEH + 0.3 V
15 Medium and slow I/O input low voltage VIL_S VSS – 0.3 0.35 VDDEH V
16 Fast input hysteresis VHYS_F 0.1 VDDE V
17 Medium and slow I/O input hysteresis VHYS_S 0.1 VDDEH V
18 Analog input voltage VINDC VSSA – 0.3 VDDA + 0.3 V
19 Fast output high voltage (IOH_F = –2.0 mA) VOH_F 0.8 VDDE —V
20 Slow and medium output high voltage
IOH_S = –2.0 mA
IOH_S = –1.0 mA
VOH_S 0.80 VDDEH
0.85 VDDEH
—V
21 Fast output low voltage (IOL_F = 2.0 mA) VOL_F —0.2 VDDE V
22 Slow and medium output low voltage
IOL_S = 2.0 mA
IOL_S = 1.0 mA
VOL_S
—
0.20 VDDEH
0.15 VDDEH
V
23 Load capacitance (fast I/O) 5
DSC (SIU_PCR[8:9]) = 0b00
= 0b01
= 0b10
= 0b11
CL
—
—
—
—
10
20
30
50
pF
pF
pF
pF
24 Input capacitance (digital pins) CIN —7pF
25 Input capacitance (analog pins) CIN_A —10pF
26 Input capacitance:
(Shared digital and analog pins AN[12]_MA[0]_SDS,
AN[13]_MA[1]_SDO, AN[14]_MA[2]_SDI, and AN[15]_FCK)
CIN_M —12pF
Electrical Characteristics
MPC5554 Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor 15
27a Operating Current 1.5 V Supplies @ 132 MHz: 6
VDD (including VDDF max current) @1.65 V typical use 7, 8
VDD (including VDDF max current) @1.4 V typical use 7, 8
VDD (including VDDF max current) @1.65 V high use 8, 9
VDD (including VDDF max current) @1.4 V high use 8, 9
IDD
IDD
IDD
IDD
—
—
—
—
700
600
875
740
mA
mA
mA
mA
27b Operating Current 1.5 V Supplies @ 114 MHz: 6
VDD (including VDDF max current) @1.65 V typical use 7, 8
VDD (including VDDF max current) @1.4 V typical use 7, 8
VDD (including VDDF max current) @1.65 V high use 8, 9
VDD (including VDDF max current) @1.4 V high use 8, 9
IDD
IDD
IDD
IDD
—
—
—
—
609
522
760
643
mA
mA
mA
mA
27c Operating Current 1.5 V Supplies @ 82 MHz: 6
VDD (including VDDF max current) @1.65 V typical use 7, 8
VDD (including VDDF max current) @1.40 V typical use 7, 8
VDD (including VDDF max current) @1.65 V high use 8, 9
VDD (including VDDF max current) @1.40 V high use 8, 9
IDD
IDD
IDD
IDD
—
—
—
—
446
384
555
471
mA
mA
mA
mA
27d RAM standby current.10
IDD_STBY @ 25o C
VSTBY @ 0.8 V
VSTBY @ 1.0 V
VSTBY @ 1.2 V
IDD_STBY @ 60o C
VSTBY @ 0.8 V
VSTBY @ 1.0 V
VSTBY @ 1.2 V
IDD_STBY @ 150o C (Tj)
VSTBY @ 0.8 V
VSTBY @ 1.0 V
VSTBY @ 1.2 V
IDD_STBY
IDD_STBY
IDD_STBY
IDD_STBY
IDD_STBY
IDD_STBY
IDD_STBY
IDD_STBY
IDD_STBY
—
—
—
—
—
—
—
—
—
20
30
50
70
100
200
1200
1500
2000
A
A
A
A
A
A
A
A
A
28 Operating current 3.3 V supplies @ fMAX MHz
VDD33 11 IDD_33 — 2 + (values
derived from
procedure of
footnote 11)
mA
VFLASH IVFLASH —10mA
VDDSYN IDDSYN —15mA
29 Operating current 5.0 V supplies (12 MHz ADCLK):
VDDA (VDDA0 + VDDA1)
Analog reference supply current (VRH, VRL)
VPP
IDD_A
IREF
IPP
—
—
—
20.0
1.0
25.0
mA
mA
mA
Table 9. DC Electrical Specifications (TA = TL to TH) (continued)
Spec Characteristic Symbol Min Max. Unit
MPC5554 Microcontroller Data Sheet, Rev. 4
Electrical Characteristics
Freescale Semiconductor16
30 Operating current VDDE supplies: 12
VDDEH1
VDDE2
VDDE3
VDDEH4
VDDE5
VDDEH6
VDDE7
VDDEH8
VDDEH9
IDD1
IDD2
IDD3
IDD4
IDD5
IDD6
IDD7
IDD8
IDD9
—
—
—
—
—
—
—
—
—
Refer to
footnote 12
mA
mA
mA
mA
mA
mA
mA
mA
mA
31 Fast I/O weak pullup current 13
1.62–1.98 V
2.25–2.75 V
3.00–3.60 V
IACT_F
10
20
20
110
130
170
A
A
A
Fast I/O weak pulldown current 13
1.62–1.98 V
2.25–2.75 V
3.00–3.60 V
10
20
20
100
130
170
A
A
A
32 Slow and medium I/O weak pullup/down current 13
3.0–3.6 V
4.5–5.5 V
IACT_S 10
20
150
170
A
A
33 I/O input leakage current 14 IINACT_D –2.5 2.5 A
34 DC injection current (per pin) IIC –2.0 2.0 mA
35 Analog input current, channel off 15 IINACT_A –150 150 nA
35a Analog input current, shared analog / digital pins
(AN[12], AN[13], AN[14], AN[15]) IINACT_AD –2.5 2.5 A
36 VSS to VSSA differential voltage 16 V
SS – VSSA –100 100 mV
37 Analog reference low voltage VRL VSSA – 0.1 VSSA + 0.1 V
38 VRL differential voltage VRL – VSSA –100 100 mV
39 Analog reference high voltage VRH VDDA – 0.1 VDDA + 0.1 V
40 VREF differential voltage VRH – VRL 4.5 5.25 V
41 VSSSYN to VSS differential voltage VSSSYN – VSS –50 50 mV
42 VRCVSS to VSS differential voltage VRCVSS – VSS –50 50 mV
43 VDDF to VDD differential voltage VDDF – VDD –100 100 mV
43a VRC33 to VDDSYN differential voltage VRC33 – VDDSYN –0.1 0.1 17 V
44 Analog input differential signal range (with common mode 2.5 V) VIDIFF –2.5 2.5 V
45 Operating temperature range, ambient (packaged) TA = (TL to TH)T
LTHC
46 Slew rate on power-supply pins — — 50 V/ms
1VDDE2 and VDDE3 are limited to 2.25–3.6 V only if SIU_ECCR[EBTS] = 0; VDDE2 and VDDE3 have a range of 1.6–3.6 V if
SIU_ECCR[EBTS] = 1.
Table 9. DC Electrical Specifications (TA = TL to TH) (continued)
Spec Characteristic Symbol Min Max. Unit
Electrical Characteristics
MPC5554 Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor 17
2| VDDA0 – VDDA1 | must be < 0.1 V.
3VPP can drop to 3.0 V during read operations.
4If standby operation is not required, connect VSTBY to ground.
5Applies to CLKOUT, external bus pins, and Nexus pins.
6Maximum average RMS DC current.
7Average current measured on automotive benchmark.
8Peak currents can be higher on specialized code.
9High use current measured while running optimized SPE assembly code with all code and data 100% locked in cache
(0% miss rate) with all channels of the eMIOS and eTPU running autonomously, plus the eDMA transferring data continuously from
SRAM to SRAM. Higher currents are possible if an “idle” loop that crosses cache lines is run from cache. Write code that avoids this
condition.
10 The current specification relates to average standby operation after SRAM has been loaded with data. For power up current see
Section 3.7, “Power-Up/Down Sequencing”, Figure 2.
11 Power requirements for the VDD33 supply depend on the frequency of operation, load of all I/O pins, and the voltages on the I/O
segments. Refer to Ta b l e 1 1 for values to calculate the power dissipation for a specific operation.
12 Power requirements for each I/O segment are dependent on the frequency of operation and load of the I/O pins on a particular I/O
segment, and the voltage of the I/O segment. Refer to Ta b l e 1 0 for values to calculate power dissipation for specific operation. The
total power consumption of an I/O segment is the sum of the individual power consumptions for each pin on the segment.
13 Absolute value of current, measured at VIL and VIH.
14 Weak pullup/down inactive. Measured at VDDE = 3.6 V and VDDEH = 5.25 V. Applies to pad types: pad_fc, pad_sh, and pad_mh.
15 Maximum leakage occurs at maximum operating temperature. Leakage current decreases by approximately one-half for each 8 oC
to 12 oC, in the ambient temperature range of 50 oC to 125 oC. Applies to pad types: pad_a and pad_ae.
16 VSSA refers to both VSSA0 and VSSA1. | VSSA0 – VSSA1 | must be < 0.1 V.
17 Up to 0.6 V during power up and power down.
MPC5554 Microcontroller Data Sheet, Rev. 4
Electrical Characteristics
Freescale Semiconductor18
3.8.1 I/O Pad Current Specifications
The power consumption of an I/O segment depends on the usage of the pins on a particular segment. The
power consumption is the sum of all output pin currents for a segment. The output pin current can be
calculated from Table 10 based on the voltage, frequency, and load on the pin. Use linear scaling to
calculate pin currents for voltage, frequency, and load parameters that fall outside the values given in
Table 10.
Table 10. I/O Pad Average DC Current (TA = TL to TH)1
1These values are estimates from simulation and are not tested. Currents apply to output pins only.
Spec Pad Type Symbol Frequency
(MHz) Load2 (pF)
2All loads are lumped.
Voltage (V)
Drive Select /
Slew Rate
Control Setting
Current (mA)
1
Slow IDRV_SH
25 50 5.25 11 8.0
210505.25013.2
3 2 50 5.25 00 0.7
4 2 200 5.25 00 2.4
5
Medium IDRV_MH
50 50 5.25 11 17.3
620505.25016.5
7 3.33 50 5.25 00 1.1
8 3.33 200 5.25 00 3.9
9
Fast IDRV_FC
66 10 3.6 00 2.8
10 66 20 3.6 01 5.2
11 66 30 3.6 10 8.5
12 66 50 3.6 11 11.0
13 66 10 1.98 00 1.6
14 66 20 1.98 01 2.9
15 66 30 1.98 10 4.2
16 66 50 1.98 11 6.7
17 56 10 3.6 00 2.4
18 56 20 3.6 01 4.4
19 56 30 3.6 10 7.2
20 56 50 3.6 11 9.3
21 56 10 1.98 00 1.3
22 56 20 1.98 01 2.5
23 56 30 1.98 10 3.5
24 56 50 1.98 11 5.7
25 40 10 3.6 00 1.7
26 40 20 3.6 01 3.1
27 40 30 3.6 10 5.1
28 40 50 3.6 11 6.6
29 40 10 1.98 00 1.0
30 40 20 1.98 01 1.8
31 40 30 1.98 10 2.5
32 40 50 1.98 11 4.0
Electrical Characteristics
MPC5554 Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor 19
3.8.2 I/O Pad VDD33 Current Specifications
The power consumption of the VDD33 supply dependents on the usage of the pins on all I/O segments. The
power consumption is the sum of all input and output pin VDD33 currents for all I/O segments. The output
pin VDD33 current can be calculated from Table 11 based on the voltage, frequency, and load on all fast
(pad_fc) pins. The input pin VDD33 current can be calculated from Table 11 based on the voltage,
frequency, and load on all pad_sh and pad_mh pins. Use linear scaling to calculate pin currents for voltage,
frequency, and load parameters that fall outside the values given in Table 11.
Table 11. VDD33 Pad Average DC Current (TA = TL to TH) 1
1These values are estimated from simulation and not tested. Currents apply to output pins for the fast pads only and to input
pins for the slow and medium pads only.
Spec Pad Type Symbol Frequency
(MHz)
Load 2
(pF)
2All loads are lumped.
VDD33
(V)
VDDE
(V)
Drive
Select
Current
(mA)
Inputs
1SlowI
33_SH 66 0.5 3.6 5.5 NA 0.003
2 Medium I33_MH 66 0.5 3.6 5.5 NA 0.003
Outputs
3
Fast I33_FC
66 10 3.6 3.6 00 0.35
466203.63.6010.53
566303.63.6100.62
666503.63.6110.79
7 66 10 3.6 1.98 00 0.35
8 66 20 3.6 1.98 01 0.44
9 66 30 3.6 1.98 10 0.53
10 66 50 3.6 1.98 11 0.70
11 56 10 3.6 3.6 00 0.30
12 56 20 3.6 3.6 01 0.45
13 56 30 3.6 3.6 10 0.52
14 56 50 3.6 3.6 11 0.67
15 56 10 3.6 1.98 00 0.30
16 56 20 3.6 1.98 01 0.37
17 56 30 3.6 1.98 10 0.45
18 56 50 3.6 1.98 11 0.60
19 40 10 3.6 3.6 00 0.21
20 40 20 3.6 3.6 01 0.31
21 40 30 3.6 3.6 10 0.37
22 40 50 3.6 3.6 11 0.48
23 40 10 3.6 1.98 00 0.21
24 40 20 3.6 1.98 01 0.27
25 40 30 3.6 1.98 10 0.32
26 40 50 3.6 1.98 11 0.42
MPC5554 Microcontroller Data Sheet, Rev. 4
Electrical Characteristics
Freescale Semiconductor20
3.9 Oscillator and FMPLL Electrical Characteristics
Table 12. FMPLL Electrical Specifications
(VDDSYN = 3.0–3.6 V; VSS = VSSSYN = 0.0 V; TA = TL to TH)
Spec Characteristic Symbol Minimum Maximum Unit
1
PLL reference frequency range: 1
Crystal reference
External reference
Dual controller (1:1 mode)
fref_crystal
fref_ext
fref_1:1
8
8
24
20
20
fsys 2
MHz
2 System frequency 2fsys f
ICO(MIN) 2RFD fMAX 3MHz
3 System clock period tCYC —1 fsys ns
4 Loss of reference frequency 4fLOR 100 1000 kHz
5 Self-clocked mode (SCM) frequency 5fSCM 7.4 17.5 MHz
6
EXTAL input high voltage crystal mode 6
All other modes
[dual controller (1:1), bypass, external reference]
VIHEXT
VIHEXT
VXTAL + 0.4 V
(VDDE5 2) + 0.4 V
—
—
V
V
7
EXTAL input low voltage crystal mode 7
All other modes
[dual controller (1:1), bypass, external reference]
VILEXT
VILEXT
—
—
VXTAL – 0.4 V
(VDDE5 2) – 0.4 V
V
V
8XTAL current 8IXTAL 0.8 3 mA
9 Total on-chip stray capacitance on XTAL CS_XTAL —1.5pF
10 Total on-chip stray capacitance on EXTAL CS_EXTAL —1.5pF
11 Crystal manufacturer’s recommended capacitive
load
CLRefer to crystal
specification
Refer to crystal
specification
pF
12 Discrete load capacitance to connect to EXTAL CL_EXTAL —(2 CL) – CS_EXTAL
– CPCB_EXTAL 9
pF
13 Discrete load capacitance to connect to XTAL CL_XTAL —(2 CL) – CS_XTAL
– CPCB_XTAL 9
pF
14 PLL lock time 10 tlpll — 750 s
15 Dual controller (1:1) clock skew
(between CLKOUT and EXTAL) 11, 12
tskew –2 2 ns
16 Duty cycle of reference tDC 40 60 %
17 Frequency unLOCK range fUL –4.0 4.0 % fSYS
18 Frequency LOCK range fLCK –2.0 2.0 % fSYS
Electrical Characteristics
MPC5554 Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor 21
19
CLKOUT period jitter, measured at fSYS max: 13, 14
Peak-to-peak jitter (clock edge to clock edge)
Long term jitter (averaged over a 2 ms interval)
CJITTER
—
—
5.0
0.01
%
fCLKOUT
20 Frequency modulation range limit 15
(do not exceed fsys maximum) CMOD 0.8 2.4 %fSYS
21
ICO frequency
fico = [fref_crystal (MFD + 4)] (PREDIV + 1) 16
fico = [fref_ext (MFD + 4) ] (PREDIV + 1)
fico 48 fMAX MHz
22 Predivider output frequency (to PLL) fPREDIV 420
17 MHz
1Nominal crystal and external reference values are worst-case not more than 1%. The device operates correctly if the frequency
remains within ± 5% of the specification limit. This tolerance range allows for a slight frequency drift of the crystals over time.
The designer must thoroughly understand the drift margin of the source clock.
2All internal registers retain data at 0 Hz.
3Up to the maximum frequency rating of the device (refer to Tabl e 1).
4Loss of reference frequency is defined as the reference frequency detected internally, which transitions the PLL into self-clocked
mode.
5The PLL operates at self-clocked mode (SCM) frequency when the reference frequency falls below fLOR. SCM frequency is
measured on the CLKOUT ball with the divider set to divide-by-two of the system clock.
NOTE: In SCM, the MFD and PREDIV have no effect and the RFD is bypassed.
6Use the EXTAL input high voltage parameter when using the FlexCAN oscillator in crystal mode (no quartz crystals or
resonators). (Vextal – Vxtal) must be 400 mV for the oscillator’s comparator to produce the output clock.
7Use the EXTAL input low voltage parameter when using the FlexCAN oscillator in crystal mode (no quartz crystals or
resonators). (Vxtal –V
extal) must be 400 mV for the oscillator’s comparator to produce the output clock.
8Ixtal is the oscillator bias current out of the XTAL pin with both EXTAL and XTAL pins grounded.
9CPCB_EXTAL and CPCB_XTAL are the measured PCB stray capacitances on EXTAL and XTAL, respectively.
10 This specification applies to the period required for the PLL to relock after changing the MFD frequency control bits in the
synthesizer control register (SYNCR). From power up with crystal oscillator reference, the lock time also includes the crystal
startup time.
11