FC80486DX4WB75 - Intel - searchdatasheet.com

EMBEDDED IntelDX2™ PROCESSOR

Figure 1. Embedded IntelDX2™ Processor Block Diagram

■Integrated Floating- Point Unit

■Speed-Multiplying Technology

■32-Bit RISC Technolog y Core

■8-Kbyte Write-Through Cache

■Fou r Intern al Write Buffers

■Burst Bus Cycl es

■Dynami c Bus Sizi ng for 8- and 16-bit

Data Bus Devices

■SL Technology

■Data Bus Parity Generation and Checking

■Boundary Scan (JTAG)

■3.3-Vol t Processor , 50 MHz, 25 MHz CLK

— 208-Lead Shrink Quad Fla t Pack (SQFP)

■5-Volt Processor, 66 MHz, 33 MHz CLK

— 168-Pin Pi n Grid Array (PGA)

■Binary Compatible with Large Software

Base

Paging

Unit

Prefetcher

32-Byte Code

Queue

2x16 Bytes

Code

Stream

Floating

Point Unit

Barrel

Shifter

Cache Unit

Burst Bus

Control

Bus Control

Write Buffers

4 x 32

64-Bit Interunit Transfer Bus

File

ALU

Segmentation

Unit

Descriptor

Registers

Limit and

Attribute PLA

Base/

Index

Bus

Translation

Lookaside

Buffer

8 Kbyte

Cache

Clock

Multiplier

Floating

Point

Control &

Protection

Test Unit

Control

ROM

Address

Drivers

CLK

Core

Clock

Data Bus

Transceivers

Request

Sequencer

Bus Size

Control

Cache

Control

Parity

Generation

and Control

Boundary

Scan

Control

Bus Interface

D31-D0

A31-A2

BE3#- BE0#

ADS# W/R# D/C# M/IO#

PCD PWT RDY# LOCK#

PLOCK# BOFF# A20M#

BREQ HOLD HLDA

RESET SRESET INTR

NMI SMI# SMIACT#

FERR# IGNNE#

STPCLK#

A3223-01

BRDY# BLAST#

BS16# BS8#

KEN# FLUSH#

AHOLD EADS#

DP3-DP0 PCHK#

TCK TMS

TDI TD0

128

Instruction

Decode

Decoded

Instruction

Path

PCD

PWT

Physical

Address

32-Bit Data Bus

Linear Address

Micro-

Instruction

Displacement Bus

Information in this document is provided in connection with Intel products. No license, express or implied, by

estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in

Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel

disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or

warra nt ies rel ating to fit ness for a parti cula r pu rpose , merc hant ab ility, or infrin gem ent of an y pate nt, co pyr ight

or other intellectual property right. Intel products are not intended for use in medical, life saving, or life

sustaining applications.

Intel may make changes to specifications and pr oduct descr iptions at any time, without notice.

Designer s must not rel y on the absence or characteristics of any features or instruc tions marked "reserved" or

"undefined." In tel reserves these for future definition and shall have no responsibility whatsoever for conflicts or

incompatibilities arising from future changes to them.

The E m be dd ed In telDX2 ™ proces s or m ay c on ta in d es i gn defects or erro rs k n ow n as err a ta w hi ch m ay ca us e

the product to deviate from published specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your

product order.

Copies of documents which have an ordering number and are referenced in this document, or other Intel

literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com.

*Third -party brands and names ar e the property of their resp ective owners.

Contents
iii
EMBEDDED IntelDX2™ PROCESSOR
1.0  INTR OD U CTIO N  ........... ............ ................... ................... ........... ................... ....................... ................... ... 1
1.1  Features  .............................................................................................................................................1
1.2  Family Members .................................................................................................................................2
2.0  HOW TO USE THIS DOCUMENT .............................................................................................................3
3.0  PIN DESCR IP TIO NS .... .... .... ................... ........... .................... ................... ........... ................... .... .... .......... 3
3.1  Pin Assignme nts .......................................................................................................... .......................3
3.2  Pin Quick Reference .........................................................................................................................16
4.0  ARCHITECTURAL AND FUNCTIONAL OVERVIEW .............................................................................25
4.1  CPUID  Instru c tio n .. ............ ................... ........... ................... ................... ............ ............... .... ............25
4.1.1  Operation of the CPUID Instruction  .......................................................................................25
4.2  Identification Afte r Reset  ..................................................................................................................26
4.3  Bound a ry Scan (JT AG )  . .... ................... ........... ................... ................... ............ ................... .... .... ... .26
4.3.1  Device Identification ...............................................................................................................26
4.3.2  Boundary Scan Register Bits and Bit Order ...........................................................................27
5.0  ELECTRICAL SPECIFICATIONS  ........................................................................................................... 28
5.1  Maxi mum Ratings .............................................................................................................................28
5.2  DC Specifications .............................................................................................................................28
5.3  AC Specifications  .............................................................................................................................33
5.4  Capacitive Derating Curves ..............................................................................................................39
6.0  MECHANICAL DATA ..............................................................................................................................41
6.1  Pack ag e Dimen si on s ............. ................... ........... ................... ................... ............ ....................... ....41
6.2  Pack ag e Ther mal  Spec if ic ati on s .. .... ........... .................... ................... ........... ................... ............ ... . 44
FIGURES
Figu r e 1. Embedded IntelDX2™ Processor Block Diagram  ...................................................................... i
Figure 2. Package Diagram for 208-Lead SQFP Embedded IntelDX2™ Processor ................................4
Figure 3. Package Diagram for 168-Pin PGA Embedded IntelDX2™ Processor ...................................10
Figu re 4. CL K Wav e form   .. .... .... .... ........... ................... ............ ................... ................... ........... .... .... .... ...35
Figu re 5. I np ut Set up and  Hold Tim in g  ........ ................... ........... ................... .................... ........... ...........3 5
Figu re 6. I np ut Set up and  Hold Tim in g  ........ ................... ........... ................... .................... ........... ...........3 6
Figu re 7. P CH K# Val id  Delay  Tim ing ... .... ................... ............ ................... ................... ........... ...............3 6
Figu re 8. Ou tp ut Val id  Delay  Timin g ................... ............ ................... ................... ............ ............... .......3 7
Figure 9. Maximum Float Delay Timing ..................................................................................................37
Figu re 10 . TC K Wav ef orm .. .... .... ................... ........... ................... ................... ............ ..............................38
Figure 11. Test Signal Timing Diagram  ....................................................................................................38

Contents

Figure 12. Typical Loading Delay versu s Load Capacitance under Worst-Case Co nditions

for a Low-to-High Transi tion, 3.3 V Processor .........................................................................39

Figure 13. Typical Loading Delay versu s Load Capacitance under Worst-Case Co nditions

for a High-to-Low Transition, 3.3 V Processor .........................................................................39

Figure 14. Typical Loading Delay versu s Load Capacitance under

Worst-Case Conditions for a Low-to-Hi gh Transition, 5 V Processor ......................................40

Figure 15. Typical Loading Delay versu s Load Capacitance under

Worst-Case Condi tions for a High-to-Low Transition, 5 V Processo r ......................................40

Figure 16 . 208-Lead SQFP Package Dimensions .................................................................................... 41

Figure 17. Principal Dimensions and Data for 168-Pin Pin Grid Array Package .......................................42

TABLES

Table 1. The Embedded IntelD X2™ Process or Fa mily ... .... .... .... ........... ............ ................... ...................2

Table 2. Pinout Di fferences for 208-Lead SQFP Package ......................................................................5

Tab le 3. Pin Ass ignm en t for 20 8-L ea d SQFP Pac k age .. ............ ................... ................... ........... ............6

Table 4. Pin Cross Reference for 208-Lead SQFP Packa ge ...................................................................8

Table 5. Pinout Di fferences for 168-Pin PGA Package .........................................................................11

Tab le 6. Pin Ass ignm en t for 16 8-P in PG A Pac kage ... .... ............ ................... ................... ........... ..........12

Table 7. Pin Cross Reference for 168-Pin PGA Package ......................................................................14

Table 8. Embe dd ed Inte lDX2 ™ Proc e ssor Pin De scri pti on s .. .... ........... ................... ................... ..........16

Table 9. Output Pins ..............................................................................................................................23

Table 10 . Input/Output Pins .....................................................................................................................23

Table 11 . Test Pins ..................................................................................................................................23

Table 12 . Input Pins .................................................................................................................................24

Tab le 13. CPUID In str uc tio n Des c rip tio n ....... .... .... ................... ................... ........... .................... ....... .... ..25

Table 14 . Boundary Scan Component Identification Code (3.3 Volt Processor) .....................................26

Table 15 . Boundary Scan Component Identification Code (5 Volt Processor) ........................................27

Table 16 . Absolute Maximum Ratings .....................................................................................................28

Table 17 . Operating Supply Voltages ......................................................................................................28

Table 18 . 3.3 V DC Specifications ...........................................................................................................29

Ta ble 19. 3 .3V ICC Values ......................................................................................................................30

Table 20 . 5 V DC Specifications ..............................................................................................................31

Table 21. 5 V ICC Values .........................................................................................................................32

Table 22 . AC Characteristics ...................................................................................................................33

Table 23 . AC Specifications for the Test Access Port .............................................................................34

Table 24 . 168-Pin Ceramic PGA Package Dimensions ...........................................................................42

Table 25 . Ceramic PGA Packa ge Di mension Symb ols ...........................................................................43

Table 26. Therm al R esista nce, θJA (°C/W) ............................................................................................. 44

Table 27. Therm al R esista nce, θJC (°C/W) ........... ................... ........................... ................... .................44

Table 28. Maxi m um Tambient, TA max (°C) . .... .... ........... .................... ................... ........... ................... ......44

Embedd ed IntelDX2™ Processor

1.0 INTRODUCTION

The embedded IntelDX2™ processor provides high

performance to 32-bit, embedded applications.

Designed for applications that need a floating-point

unit, the processor is ideal for embedded designs

ru nnin g DOS *, Micr osoft W ind ows*, O S/2*, or UNIX*

applications written for the Intel architecture.

Projects can be completed quickly by utilizing the

wide range of software tools, utilities, assemblers

and compilers that are available for desktop

computer systems. Also, developers can find

advantages in using existing chipsets and peripheral

components in their em bedded designs .

The embedded IntelDX2 processor is binary

compatible with the Intel386™ and earlier Intel

proce ssors. Compared with the Intel386 proces sor, it

provides faster execution of many commonly-used

instructions. It also provides the benefits of an

integrated, 8-Kbyte, write-through cache for code

and data. Its data bus can operate in burst mode

which provides up to 106-Mbyte-per-second

transfers for cache-line fills and instruction

prefetches.

Intel’s SL technology is incorporated in the

embedded IntelDX2 processor. Utilizing Intel’s

System Management Mode (SMM), it enables

des igner s to de ve lo p energ y- eff ic ient sys tem s .

Two component packages are available. A 168-pin

Pin Grid Array (PGA) is available for 5-Volt designs

and a 208-lead Shrink Quad Flat Pack (SQFP) is

available for 3.3-Volt designs.

The processor operates at twice the external-bus

frequency. The 5 V processor operates up to 66

MHz (33-MHz CLK). The 3.3 V processor operates

up to 50 MHz (25- MH z CLK).

1.1 Features

The embedded IntelDX2 processor offers these

features:

•32-bit RISC-Technology Core — The embedded

IntelDX2 processor performs a complete set of

arithmetic and logical operations on 8-, 16-, and

32-bit data types using a full-width ALU and eight

general purpose registers.

•Single Cycle Execution — Many instructions

ex ecut e in a single clock cycle.

* Other brands and names are the property of their

respective owners.

•Instr u cti on Pipe lin ing — Overl apped instruction

fetching, decoding, address translation and

execution.

•On-Chip Floating-Point Unit — Intel486™

processors support the 32-, 64-, and 80-bit formats

specified in I EEE standard 754. The unit is binary

compatib le with the 8087, Intel287™, Intel387™

coprocessors, and Intel OverDrive® processor.

•On-Chip Cache with Cache Consistency

Support — An 8-Kbyte, write-through, internal

cache is used for bo th data and instructions.

Cache hits provide zero wait-state ac cess times

for data within the cache. Bus activity is tracked to

detect alterations in the memory represe nted by

the internal cache. The internal cache can be

invalida ted or flushed so that an ext ernal cache

controller can maintain cache consistency.

•External Cache Control — Write-back and flush

controls for an extern al cache are p rovi ded so the

proce ssor can maintain c ache consistency.

•On-Chip Memory Management Unit — Address

managemen t and memo ry space protection

mechanisms maintain the integrity of memory in a

mult ita sking an d virtua l memory e nviro nment . Bot h

memory segmentation and paging are supported.

•Burst Cycl es — Burst transfers allow a new

double-w ord to be read fro m memor y on ea ch bus

clock cycle. This capability is especially useful for

instruction prefetch and for filling the internal

cache.

•Write Buffers — The processor contains four

write buffers to enhance the performance of

consecutive writes to memory. The processor can

continue internal operations after a write to these

buffers, without waiting for the write to be

completed on the external bus.

•Bus Backoff — When anot her b us mast er n eeds

control of the bus during a processor in itiated bus

cy cle, the em bedded Inte lDX2 processor floa ts its

bus signals, then restarts the cycle when the b us

be c om e s av ai la ble a ga in .

•In structi on Res t art — Programs can conti nue

ex ecution fol lowing an ex ception generated by an

unsuccessful attempt to acc ess memory. This

feature is important for supporting demand-paged

virtual memory applications.

•Dynamic Bus Sizing — Exte rnal cont rollers can

dy namically alter the effectiv e w idth of the dat a

bus. Bu s widths of 8, 16, or 32 bits can be used.

Embedded IntelDX2™ Processor

•Boundary Sc an (JTAG) — Boundary Scan

provides in-circuit t esting of components on

printed circu it boards. Th e Intel Boundary Scan

implementation conforms with the IEEE Standard

Test Access Po rt and Boundary Scan Archi tecture.

Intel’s SL technology provides these features:

•Intel Syste m Management Mode (SMM) — A

unique Intel architecture operating mode provides

a dedicated special purpose interrupt and address

space that can be used to implement intelligent

power management and other enhanced functions

in a manner that is completely transparent to the

operating system and ap plicat ions softw are.

•I/O Restart — An I/O instruction interrupted by a

System Management Interrupt (SMI#) can

automatically be restarted following the execution

of the RSM instruction.

•St o p Cl oc k — The embedde d IntelDX2 proc essor

has a stop c lock con trol mechanism that prov ides

two low -powe r sta tes: a Stop Grant state (2 0–45

mA typical, depending on input clock frequency)

and a Stop Clock state (~100-200 µA typical, with

input clock frequency of 0 MHz).

•Auto HALT Power Down — After the execution of

a HA LT ins truction, the embedded In telDX2

proc essor issues a normal Halt bus cycle and t he

clock input to the processor core is automatically

stopped, causing the proces sor to enter the Auto

HALT Power Do wn state (20–45 mA typical,

depending on input clock frequency).

•Auto Idle Powe r Down — Th is f un ct io n al lo w s th e

processor to red uce the core freq uency to the bus

frequency when both the core and bus are idle.

Auto Idle Power Down is software transparent and

does not affect proc essor performa nce. Auto Idle

Power Down p rovi des an average power savings

of 10% and is only applicable to clock multiplied

processors.

1.2 Family Members

Table 1 shows the embedded IntelDX2 processors

and briefly describes their characteristics.

Table 1. The Embedded IntelDX2™ Processor Family

Product Suppl y Volta ge

VCC

Maximu m

Processor

Frequency

Maximu m

External Bus

Frequency Package

SB80486DX2SC50 3.3 V 50 MHz 25 MHz 208-Lead S QFP

A80486DX2SA66 5.0 V 66 MHz 33 MHz 168-Pin PGA

Embedd ed IntelDX2™ Processor
 3
2.0 HO W TO USE THIS DOCUMENT
For a complete set of documentation related to the
embedded IntelDX2 processor, use this document in
con ju nc t io n with  t he  follo win g r ef erence do cu m en t s :
•
Embedded Intel 486™  Processor Family 
Developer’s Manual 
— O rde r No. 273021
•
Emb edde d Intel48 6™ Processor  Hardware 
Referenc e Manual  
— Order No. 273025
•
Intel486 Microprocessor Family Programmer’s 
Referenc e Manual
 — Ord er N o. 24 04 86
• Intel Application Note AP-485 — 
Intel Processor 
Identification with the CPUID Instruction
 — 
Order No. 24 16 18
The information in the reference documents for the
IntelDX2 processor applies to the embedded
IntelDX2 processor. Some of the IntelDX2 processor
information is duplicated in this document to
minimize the dependence on the reference
documents.
3.0 PIN DESCRIPTIONS
3.1 Pin Assignments
The following figures and tables show  the pin assign-
ments of each package type for the embedded
IntelDX2 processor. Tables are provided showing
the pin  di fference s  b etwee n  the  e m be dd ed  IntelD X 2
processor and other embedded Intel486 processor
products.
208-Lead SQFP - Quad Flat Pack
• Fig ure 2, Package Diag ram for 208-Lead SQFP 
Embedded IntelDX 2™ Processor (pg. 4)
• Table 2, Pinout Differe nces for 208- Lead SQF P 
Package (pg. 5)
• Table 3, Pin Assignment for 208-Lead SQFP 
Package (pg. 6)
• Table 4, Pin Cross Reference for 208-Lead SQFP 
Package (pg. 8)
168-Pin PGA - Pin  Grid Array
• Fig ure 3, Package Diag ram for 168-Pin PGA 
Embedded IntelDX 2™ Processor (pg. 10)
• Table 5, Pinout Differences for 168-Pin PGA 
Pac kage (pg. 11)
• Table 6, Pin Assignment for 168-Pin PGA 
Pac kage (pg. 12)
• Table 7, Pin Cross Reference for 168-Pin PGA 
Pac kage (pg. 14)

Embedded IntelDX2™ Processor

Figure 2. P ackage Diagram for 208-Lead SQFP Embedded IntelDX2™ Processor

156

155

154

153

152

151

150

149

148

147

146

145

144

143

142

141

140

139

138

137

136

135

134

133

132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

208-Lead SQFP

Embedded IntelDX2™ Processor

Top View

100

101

102

103

104

208

207

206

205

204

203

202

201

200

199

198

197

196

195

194

193

192

191

190

189

188

187

186

185

184

183

182

181

180

179

178

177

176

175

174

173

172

171

170

169

168

167

166

165

164

163

162

161

160

159

158

157

LOCK#

PLOCK#

BLAST#

ADS#

RESERVED#

A10

A11

A12

A13

A14

A15

A16

A17

TDI

TMS

A18

A19

A20

A21

A22

A23

A24

PCHK#

BRDY#

BOFF#

BS16#

BS8#

INC

RDY#

KEN#

HOLD

AHOLD

TCK

CLK

HLDA

W/R#

BREQ

BE0#

BE1#

BE2#

BE3#

M/IO#

D/C#

PWT

PCD

EADS#

A20M#

RESET

FLUSH#

INTR

NMI

A25

A26

A27

A28

A29

A30

A31

DP0

DP1

D10

D11

D12

D13

D14

D15

DP2

D16

SRESET

SMIACT#

INC

SMI#

FERR#

TDO

INC

IGNNE#

STPCLK#

D31

D30

D29

D28

D27

D26

D25

D24

DP3

D23

D22

D21

D20

D19

D18

D17

A3227-01

Embedd ed IntelDX2™ Processor

Table 2. Pinout Differences for 208-Lead SQFP Package

P in # Embedded

Intel486™ SX

Processor

Embedded

IntelDX2™

Processor

Embedded Write-Back

Enha nce d Inte lD X4 ™

Processor

3VCC1VCC VCC5

11 INC2INC CLKMUL

63 INC INC HITM#

64 INC INC WB/WT#

66 INC FERR# FERR#

70 INC INC CACHE#

71 INC INC INV

72 INC IGNNE# IGNNE#

NOTES:

1. This pin location is for the VCC5 pin on the embedded IntelDX4 processor. For compatibility with 3.3V processors that

have 5V-tolerant input buffers (i.e., embedded IntelDX4 processors), this pin should be connected to a VCC trac e, not to

the VCC plane.

2. INC. Internal No Connect. These pins are not connected to any internal pad in the embedded IntelDX2 processor. How-

ever, new signals are defined for the location of the INC pins in the embedded IntelDX4 processor. One system design

can accommodate any one of these processors provided the purpose of each INC pin is understood before it is used.

Embedded IntelDX2™ Processor

Table 3. Pin Assignment for 208-Lead SQFP Pack age (Sheet 1 of 2)

Pin# Description Pin# Description Pin# Description Pin# Description

SS 53 VSS 105 VSS 157 VSS

CC 54 VCC 106 VCC 158 A24

CC155 VSS 107 VSS 159 A23

4 PCHK# 56 VCC 108 D16 160 A22

5 BRDY#57V

SS 109 DP2 161 A21

6 BOFF# 58 SRESET 110 VSS 162 VCC

7 BS16# 59 SMIACT# 111 VCC 163 VCC

8BS8#60

VCC 112 D15 164 A20

CC 61 VSS 113 D14 165 A19

10 VSS 62 VCC 114 VCC 166 A18

11 INC263 INC2115 VSS 167 TMS

12 RDY# 64 INC2116 D13 168 TDI

13 KEN# 65 SMI# 117 D12 169 VCC

14 VCC 66 FERR# 118 D11 170 VSS

15 VSS 67 NC3119 D10 171 A17

16 HOLD 68 TDO 120 VSS 172 VCC

17 AHOLD 69 VCC 121 VCC 173 A16

18 TCK 70 INC2122 VSS 174 A15

19 VCC 71 INC2123D9175V

20 VCC 72 IGNNE# 124 D8 176 VCC

21 VSS 73 STPCLK# 125 DP1 177 A14

22 VCC 74 D31 126 D7 178 A13

23 VCC 75 D30 127 NC3179 VCC

24 CLK 76 VSS 128 VCC 180 A12

25 VCC 77 VCC 129D6181V

26 HLDA 78 D29 130 D5 182 A11

27 W/R# 79 D28 131 VCC 183 VCC

28 VSS 80 VCC 132 VSS 184 VSS

29 VCC 81 VSS 133 VCC 185 VCC

30 BREQ 82 VCC 134 VCC 186 A10

31 BE0# 83 D27 135 VSS 187 A9

32 BE1# 84 D26 136 VCC 188 VCC

33 BE2# 85 D25 137 VCC 189 VSS

34 BE3# 86 VCC 138 VSS 190 A8

35 VCC 87 D24 139 VCC 191 VCC

Embedd ed IntelDX2™ Processor

36 VSS 88 VSS 140 D4 192 A7

37 M/IO# 89 VCC 141 D3 193 A6

38 VCC 90 DP3 142 D2 194 RESERVED#

39 D/C# 91 D23 143 D1 195 A5

40 PWT 92 D22 144 D0 196 A4

41 PCD 93 D21 145 DP0 197 A3

42 VCC 94 VSS 146 VSS 198 VCC

43 VSS 95 VCC 147 A31 199 VSS

44 VCC 96 NC3148 A30 200 VCC

45 VCC 97 VSS 149 A29 201 VSS

46 EADS# 98 VCC 150 VCC 202 A2

47 A20M# 99 D20 151 A28 203 ADS#

48 RESET 100 D19 152 A27 204 BLAST#

49 FLUSH# 101 D18 153 A26 205 VCC

50 INTR 102 VCC 154 A25 206 PLOCK#

51 NMI 103 D17 155 VCC 207 LOCK#

52 VSS 104 VSS 156 VSS 208 VSS

NOTES:

1. This pin location is for the VCC5 pin on the embedded IntelDX4 processor. For compatibility with 3.3V processors that have

5V-tolerant input buffers (i.e., embedded IntelDX4 processors), this pin s hould be connected to a VCC trace, not to the VCC

plane.

2. INC. Internal No Connect. These pins are not connected to any internal pad in the embedded IntelDX2 processors. How-

ever, signals are defined for the location of the INC pins in the IntelDX4 processor. O ne system design can accommodate

any one of these processors provided the purpose of each INC pin is unders tood before it is used.

3. NC. Do Not Connect. These pins should always remain unconnected. Connec tion of NC pins to VCC, or VSS or to any other

signal can result in component malfunction or incompatibility with future steppings of the Intel486 proces sors.

Table 3. Pin Assignment for 208-Lead SQFP Package (Sheet 2 of 2)

Pin# Description Pin# Description Pin# Description Pin# Description

Embedded IntelDX2™ Processor

Table 4. Pin Cross Reference for 208-Lead SQFP Package (Sheet 1 of 2)

Address Pin # Data Pin # Control Pin # NC INC VCC VSS

A2 202 D0 144 A20M# 47 67 11 2 1

A3 197 D1 143 ADS# 203 96 63 3 10

A4 196 D2 142 AHOLD 17 127 64 9 15

A5 195 D3 141 BE0# 31 70 14 21

A6 193 D4 140 BE1# 32 71 19 28

A7 192 D5 130 BE2# 33 20 36

A8 190 D6 129 BE3# 34 22 43

A9 187 D7 126 BLAST# 204 23 52

A10 186 D8 124 BOFF# 6 25 53

A11 182 D9 123 BRDY# 5 29 55

A12 180 D10 119 BREQ 30 35 57

A13 178 D11 118 BS16# 7 38 61

A14 177 D12 117 BS8# 8 42 76

A15 174 D13 116 CLK 24 44 81

A16 173 D14 113 D/C# 39 45 88

A17 171 D15 112 DP0 145 54 94

A18 166 D16 108 DP1 125 56 97

A19 165 D17 103 DP2 109 60 104

A20 164 D18 101 DP3 90 62 105

A21 161 D19 100 EADS# 46 69 107

A22 160 D20 99 FERR# 66 77 110

A23159D2193 FLUSH# 49 80 115

A24158D2292 HLDA 26 82 120

A25154D2391 HOLD 16 86 122

A26153D2487 IGNNE# 72 89 132

A27152D2585 INTR 50 95 135

A28151D2684 KEN# 13 98 138

A29149D2783 LOCK# 207 102146

A30148D2879 M/IO# 37 106156

A31147D2978 NMI 51 111157

D30 75 PCD 41 114 170

D31 74 PCHK# 4 121 175

PLOCK# 206 128 181

PWT 40 131 184

RDY# 12 133 189

RESERVED# 194

RESET 48

SMI# 65 134 199

SMIACT# 59 136 201

Embedd ed IntelDX2™ Processor

SRESET 58 137 208

STPCLK# 73 139

TCK 18 150

TDI 168 155

TDO 68 162

TMS 167 163

W/R# 27 169

172

176

179

183

185

188

191

198

200

205

Table 4. Pin Cross Reference for 208-Lead SQFP Package (Sheet 2 of 2)

Address Pin # Data Pin # Control Pin # NC INC VCC VSS

Embedded IntelDX2™ Processor

Figure 3. Package Diagram for 16 8-Pin PGA Embedded IntelDX2™ Processor

A3226-01

D20

D19

D11

D22 D21 D18

D13 V

DP1

D8 V

D3 D5

A31

A29 V

A28

A27

A25 A26

TCK V

CLK D17 D10 D15 D12 DP2 D16 D14 D7 D4 DP0 A30 A17

A23

D23 V

A19

6 6

12 12

13 13

14 14

17 17

DP3 V

D24 D25 D27

D26

A21 A18 A14

A24 V

A22 A15 A12

A20

A16

A13

A5 A11 V

A7 A8 A10

A2 V

D29 D31 D28

D30

INC SMI# SRESET

RESERVED#

INC INC SMIACT#

INC INC NC

TDI TMS FERR#

IGNNE# NMI FLUSH# A20M# HOLD KEN# STPCLK# BRDY# BE2# BE0# PWT D/C# LOCK# HLDA BREQ A3 A6

INTR TDO RESET BS8# RDY# BE1# M/IO# PLOCK# BLAST# A4

AHOLD EADS# BS16# BOFF# BE3# PCD W/R# PCHK# INC ADS#

ABCDEFGHJKLMNPQRS

168-Pin PGA

Embedded IntelDX2™ Processor

Pin Side View

Embedd ed IntelDX2™ Processor

Table 5. Pinout Differences for 168-Pin PGA Package

Pin # Embedded IntelDX2™ Processor Embedded Write-Back Enhanced

IntelDX4™ Processo r

A10 INC INV

A12 INC HITM#

B12 INC CACHE#

B13 INC WB/WT#

J1 VCC VCC5

R17 INC CLKMUL

S4 NC VOLDET

Embedded IntelDX2™ Processor

Table 6. Pin Assignment for 168-Pin PGA Package (Sheet 1 of 2)

Pin # Description Pin # Description Pin # Description

A1 D20 D17 BOFF# P2 A29

A2 D22 E1 VSS P3 A30

A3 TCK E2 VCC P15 HLDA

A4D23E3D10P16

VCC

A5 DP3 E15 HOLD P17 VSS

A6 D24 E16 VCC Q1 A31

A7 VSS E17 VSS Q2 VSS

A8 D29 F1 DP1 Q3 A17

A9 VSS F2 D8 Q4 A19

A10 INC1F3D15Q5A21

A11 VSS F15 KEN# Q6 A24

A12 INC1F16 RDY# Q7 A22

A13 INC1F17 BE3# Q8 A20

A14 TDI G1 VSS Q9 A16

A15 IGNNE# G2 VCC Q10 A13

A16 INTR G3 D12 Q11 A9

A17 AHOLD G15 STPCLK# Q12 A5

B1 D19 G16 VCC Q13 A7

B2 D21 G17 VSS Q14 A2

B3 VSS H1 VSS Q15 BREQ

B4 VSS H2 D3 Q16 PLOCK#

B5 VSS H3 DP2 Q17 PCHK#

B6 D25 H15 BRDY# R1 A28

B7 VCC H16 VCC R2 A25

B8 D31 H17 VSS R3 VCC

B9 VCC J1 VCC R4 VSS

B10 SMI# J2 D5 R5 A18

B11 VCC J3 D16 R6 VCC

B12 INC1J15 BE2# R7 A15

B13 INC1J16 BE1# R8 VCC

B14 TMS J17 PCD R9 VCC

B15 NMI K1 VSS R10 VCC

B16 TDO K2 VCC R11 VCC

Embedd ed IntelDX2™ Processor

B17 EADS# K3 D14 R12 A11

C1 D11 K15 BE0# R13 A8

C2 D18 K16 VCC R14 VCC

C3 CLK K17 VSS R15 A3

C4 VCC L1 VSS R16 BLAST#

C5 VCC L2 D6 R17 INC1

C6 D27 L3 D7 S1 A27

C7 D26 L15 PWT S2 A26

C8 D28 L16 VCC S3 A23

C9 D30 L17 VSS S4 NC2

C10 SRESET M1 VSS S5 A14

C11 RESERVED# M2 VCC S6 VSS

C12 SMIACT# M3 D4 S7 A12

C13 NC2M15 D/C# S8 VSS

C14 FERR# M16 VCC S9 VSS

C15 FLUSH# M17 VSS S10 VSS

C16 RESET N1 D2 S11 VSS

C17 BS16# N2 D1 S12 VSS

D1 D9 N3 DP0 S13 A10

D2 D13 N15 LOCK# S14 VSS

D3 D17 N16 M/IO# S15 A6

D15 A20M# N17 W/R# S16 A4

D16 BS8# P1 D0 S17 ADS#

NOTES:

1. INC. Internal No Connect. These pins are not connected to any internal pad in the embedded

IntelDX2 processors . However, signals are defined for the location of the INC pins in the IntelDX4

processor. One system design can accommodate any one of these proc essors provided the pur-

pose of each INC pin is understood before it is used.

2. NC. Do Not Connect. These pins should always remain unconnected. Connection of NC pins to

VCC, or VSS or to any other signal can result in component malfunction or incompatib ili ty with

future steppings of the Intel486 processors.

Ta ble 6. Pin Assignment for 168-Pin PGA Package (Sheet 2 of 2)

Pin # Description Pin # Description Pin # Description

Embedded IntelDX2™ Processor

Ta ble 7. Pin Cross Reference for 168-Pin PGA Package (Sheet 1 of 2)

Address Pin # Data Pin # Control Pin # NC INC Vcc Vss

A2 Q14 D0 P1 A20M# D15 C13 A10 B7 A7

A3 R15 D1 N2 ADS# S17 S4 A12 B9 A9

A4 S16 D2 N1 AHOLD A17 A13 B11 A11

A5 Q12 D3 H2 BE0# K15 B12 C4 B3

A6 S15 D4 M3 BE1# J16 B13 C5 B4

A7 Q13 D5 J2 BE2# J15 R17 E2 B5

A8 R13 D6 L2 BE3# F17 E16 E1

A9 Q11 D7 L3 BLAST# R16 G2 E17

A10 S13 D8 F2 BOFF# D17 G16 G1

A11 R12 D9 D1 BRDY# H15 H16 G17

A12 S7 D10 E3 BREQ Q15 J1 H1

A13 Q10 D11 C1 BS16# C17 K2 H17

A14 S5 D12 G3 BS8# D16 K16 K1

A15 R7 D13 D2 CLK C3 L16 K17

A16 Q9 D14 K3 D/C# M15 M2 L1

A17 Q3 D15 F3 DP0 N3 M16 L17

A18 R5 D16 J3 DP1 F1 P16 M1

A19 Q4 D17 D3 DP2 H3 R3 M17

A20 Q8 D18 C2 DP3 A5 R6 P17

A21 Q5 D19 B1 EADS# B17 R8 Q2

A22 Q7 D20 A1 FERR# C14 R9 R4

A23 S3 D21 B2 FLUSH# C15 R10 S6

A24 Q6 D22 A2 HLDA P15 R11 S8

A25 R2 D23 A4 HOLD E15 R14 S9

A26 S2 D24 A6 IGNNE# A15 S10

A27 S1 D25 B6 INTR A16 S11

A28 R1 D26 C7 KEN# F15 S12

A29 P2 D27 C6 LOCK# N15 S14

A30 P3 D28 C8 M/IO# N16

A31 Q1 D29 A8 NMI B15

D30 C9 PCD J17

D31 B8 PCHK# Q17

PLOCK# Q16

PWT L15

RDY# F16

RESERVED# C11

RESET C16

SMI# B10

SMIACT# C12

Embedd ed IntelDX2™ Processor

SRESET C10

STPCLK# G15

TCK A3

TDI A14

TDO B16

TMS B14

W/R# N17

Table 7. Pin Cross Reference for 168-Pin PGA Package (S he et 2 of 2)

Address Pin # Data Pin # Control Pin # NC INC Vcc Vss

Embedded IntelDX2™ Processor

3.2 Pin Quick Reference

The follo wing is a brief pin descripti on. For detailed sig nal descriptions refe r to Appendix A, “Signal Descrip-

tions,” in the

Embedded Intel4 86™ Proc essor Family Develop er’s Manual,

order No. 273021.

Table 8. Embedded IntelDX2™ Processor Pin Descriptions (Sheet 1 of 7)

Symbol Type Name and Function

CLK IClock

provides the fundamental timing and internal operating frequency for the

embedded IntelDX2 processor. All external timing parameters are specified with

respect to the rising edge o f C LK.

ADDRESS BUS

A31-A4

A3–A2 I/O

OAddress Lines A31–A2, together with th e byte enable signa ls, BE3#–BE0#,

define th e physical area of memory or i nput/output space access ed. A ddress

lines A31–A4 are used to drive addresses into the embedded IntelDX2 processor

to perform cache line invalidation. Input signals must meet setup and hold times

t22 and t23. A31 –A2 ar e not driven during bus or ad dre ss hold.

BE3#

BE2#

BE1#

BE0#

Byte Enable

signals indicate active bytes during read and write cycles. During

the first cycle of a cache fill, the ex ternal sys tem shou ld assume that all byte

enables are active. BE 3#–BE0# are active LOW and are no t dr iven during bus

hold.

BE3# applies to D31–D24

BE2# applies to D23–D16

BE1# applies to D15–D8

BE0# applies to D7–D0

DATA BUS

D31–D0 I/O Data Lines. D7–D0 define th e least significant byte of the d ata bus; D31 –D2 4

define the most significant byte of the data bus. These signals must meet setup

and hold times t22 and t23 for proper operation on reads. These pins are driven

during the sec on d an d su bs eq ue nt cloc k s of wr it e cy cl es .

DATA PARITY

DP3–DP0 I/O There is one Data Parity pi n for each byte of the data bus. Data parity is

generated on all write data cycles wit h the same timin g as the data driv en by th e

embedded IntelDX2 processor. E v en parity i nformation must be driv en back into

the processor on the data parit y pins with t he same ti ming as read information t o

ensure that the correct parity check statu s is indicated by the embedded IntelDX2

processor. The signals read on thes e pins do not affect program execution.

Input signals must meet setup and hold times t22 and t23. DP3–DP0 must be

connected to VCC through a pull-up resistor in systems that do not use parity.

DP3 –DP0 are active HI GH and are driven during the second and subsequent

clocks of wr ite cycles.

PCHK# OParity Status is driven on the PCHK# pin the clock after ready for read

operat ions. The parit y status is for dat a sample d at the end of the previous c lock.

A parity error is indicated by PCHK# being LOW. Parity status is only checked for

enabled bytes as indicated by the byte enable and bus size signals. PCHK# is

valid only in the clock immediately after read data is returned to the processor. At

all other times PCHK# is inactive (HIGH). PCHK# is never floated.

Embedd ed IntelDX2™ Processor

BUS CYCLE DEFINITION

M/IO#

D/C#

W/R#

Memory/Input-Output

Data/Control

and Write/Read

lines ar e the prima ry bus

definition signals. These signals are driven valid as the ADS# signal is asserted.

M/IO# D/C# W/R# Bus Cycle Initiated

0 0 0 Interrupt Acknowledge

0 0 1 HALT/Special Cycle (see details below)

0 1 0 I/O Read

0 1 1 I/O Write

1 0 0 Cod e Read

1 0 1 Reserved

1 1 0 Memory Read

1 1 1 Memory Write

HALT/Special Cycle

Cycle Name BE3# - BE0# A4-A2

Shutdown 1110 000

HALT 1011 000

Stop Grant bus cycle 10 11 100

LOCK# OBus Lock

indicates that th e cur ren t bus cyc le is lo cked. The embedded In telDX2

processor does not allow a bus hold when LOCK# is asserted (address holds are

allowed) . LOC K# go es active in the first clock of th e fir st lock ed bus cycle and

goes in ac ti ve af t er t he l ast cl ock o f t he l as t l ock ed bu s c ycl e. T he la st l ock ed cycle

ends when Ready is returned. LOCK# is active LOW and not driven during bus

hold. Locked read c ycles are not transf orme d int o cache fill cycles when KEN# i s

returne d active .

PLOCK# OPseudo-Lock in dicate s that the cur re nt bus transaction requir es more than one

bus cycle to complete. For the embedded IntelDX2 processor, examples of such

opera tions are se gment table descriptor rea ds (6 4 bits) and ca che line fills (128

bi ts). For Intel4 86 proc essors with on-ch ip Floa ting-Point Unit, f loatin g-point long

reads and writes (64 bits) also require more than one bus cycle to complete.

The embedded IntelDX2 processor drives PLOCK# active until the addresses for

the last bus cycle of the transaction are driven, regardless of whether RDY# or

BR DY# have b een r eturned.

Normally PL OCK# and BLAST# are i nverse of each other . However, during th e

first bus cycle of a 64-bit floatin g-point write (for In tel486 processors with on-chip

Floating-Point Un it) both PLO CK# and BLAST# are asserted .

PLOCK# is a function of the BS8#, BS16# and KEN# inputs. PLOCK# should be

sampled only in the clock in which Ready is returned. PLOCK# is active LOW and

is not dri ve n dur in g bu s ho ld.

BUS CONTROL

ADS# OAddress Status

output indicates that a valid bus cycle definition and address are

available on the cycle definition lines and address bus. ADS# is driven active in

the same cloc k in which the addresses are driven. ADS# is active LOW and not

driven during bus hold.

Table 8. Embedded IntelDX2™ Processor Pin Descriptions (Sheet 2 of 7)

Symbol Type Name and Function

Embedded IntelDX2™ Processor

RDY# INon-burst Ready

input indicates that the current bus cycle is complete. RDY#

indicate s that the external system ha s presented valid data on the data pins in

respon se to a read or th at t he external s ystem has accept ed dat a from the

embedded IntelDX2 processor in response to a write. RDY# is ignored when the

bus is idle and at the end of the first clock of the bus cycle.

RDY# is active during address hold. Data can be return ed to the embedded

IntelDX2 proces sor while AH OLD is active.

RDY# is active LOW and is not pr ovided wit h an internal pull-up resistor. RDY#

must satisfy setup and hold times t16 and t17 for proper chip op erat ion.

BURST CONTROL

BRDY# IBurst Ready

input performs t he same function du ring a burst cycle that R DY#

performs d uri ng a non-bu rst cycle. BRD Y# i ndicates that the external sy stem has

presented valid data in response to a read or that the ex ternal sy stem has

accepted data in response to a write. BRDY# is ignored when the bus is idle and

at the end of the first clock in a bus cycle.

BRDY# is sampled in the second and subsequent clocks of a burst cycle. Data

presente d on the data bus i s str o bed in to the embe dded IntelD X2 proces sor

when BR DY# is sampled active. If RDY # is returned simultaneously with B RDY #,

BRDY# is ignored and the bur s t cycle is prematurely abo rted.

BRDY# is active LOW and is provided with a smal l pull-up r esisto r. BRDY# must

satisfy the setup and ho ld times t16 an d t17.

BLAST# OBu rst Last

signal indicates that the next time BRDY# is returned, the burst bus

cycle is complete. BLAST# is active for both burst and non-burst bus cycles.

BLAST# is active LOW and is not driven during bus hold.

INTERRUPTS

RESET IReset input forc es the embedded IntelDX2 processor to begin execution at a

known state . The processor ca nnot begin executing i nstr uctions until at l east

1ms after V

CC, and CLK have reached their proper DC and A C spe c ific ations .

The RESET pin must remain activ e dur ing this time to ensu re proper pr ocessor

operation. However, for warm resets, RESET should remain active for at least 15

CLK periods. RESET is active HIGH. RESET is asynchronous but must meet

setup and hold times t20 and t21 for recognition in any specific clock.

INTR IMa sk ab le Inte r rupt

indicat es that an external interrupt has been genera ted.

Wh en the internal interrupt flag is set in EFLAGS, active interrupt processing is

initiated. The embedded IntelDX2 processor generates two locked interrupt

ack nowledge bus cycles in response to the INTR pin going acti ve. INTR must

remain active until the interrupt acknowledges have been performed to ensure

processor recognition of t he interr upt.

INTR is active HIG H a nd is not prov ided with a n internal pull-down re sistor. INTR

is asynchronous, but must meet setup and hold times t20 an d t 21 for recognition in

any specific clock.

NMI INon-M a sk abl e Inte rr upt

requ est signal indicates that an external non-maskable

interrupt has been generated. NMI is rising-edge sensitive and must be held LOW

for at least four CLK periods before this rising edge. NMI is not provided with an

inter nal pull-d own resi stor. NMI is asynchrono us, but must me et set up and hold

ti mes t20 and t21 for recognition in a ny specific cloc k.

Table 8. Embedded IntelDX2™ Processor Pin Descriptions (Sheet 3 of 7)

Symbol Type Name and Function

Embedd ed IntelDX2™ Processor

SRESET ISoft Reset pin du pl ic ate s all functio na lity of the RE S ET pi n exc e pt th at the

SMBASE registe r retains its previou s value. For soft resets, SRESET must

remain active for at least 15 CLK periods. SRESET is active HIGH. SRESET is

asynchronous but must meet setup and hold times t20 and t21 for recognition in

any specific cl ock.

SMI# ISy ste m Mana ge me nt Inte rr upt inp ut in vokes System Ma nagement Mode

(SMM). SMI# is a falling-edge triggered signal which forces the embedded

IntelDX2 processor into SMM at the completion of the current instruction. SMI# is

recognized on an instruction boundary and at each iteration for repeat string

instr uctions. SMI# does no t break LOCK ed bus cycles and cann ot interrupt a

currently executing SMM. The embedded IntelDX2 processor latches the falling

edge of one pendin g SMI # signal whi le it is ex ecuti ng an existing S MI#. The

nested SMI# is not rec ognized until after the execu tion of a Resume (RSM)

instruction.

SMIACT# OSyst em Managemen t I nte rrupt Acti ve, an active LOW output, indicates that the

em bedded IntelDX 2 pr ocessor is operating in SMM. It i s asserted when the

processor begins to execute the SMI# state save sequence and remains active

LOW until the processor executes the last state restore cycle out of SMRAM.

STPCLK# IStop Clock Request input signal indic ates a request was made to turn off or

change the CLK inpu t frequenc y. When the embedded IntelDX2 pr ocessor

recognizes a STPCLK#, it stops execution on the next instruction boundary

(unless superseded by a higher priority interrupt), empties all internal pipelines

and write buf fer s, and gene r at es a Stop Gr ant b us cycle . S TPC L K# is act iv e

LOW. Though STPCLK# has an internal pull-up resistor, an external 10-KΩ pull-

up resistor is needed if the STP CLK# pi n is unused. STPCLK# is an

asynchronous signal, but must re main active until the embedded IntelDX2

pr oc es sor i ss ues t he St op G ra n t bus cy cl e. S T PC LK# ma y b e de -as se r ted a t

any ti me after the processo r ha s issued the Stop Gr ant bus cycle.

BUS ARBITRATION

BREQ OBus Request

signal indica tes that the embedded IntelDX2 processor has

inter nally genera ted a bus request. BREQ is generat ed whether or not th e

processor is driving the bus. BREQ is active HIGH and is never floated.

HOLD IBus Hold Request allows another bus master complete control of the embedded

IntelDX2 processor bus . In response to HOLD going active, the processor floats

most of its output and input/output pins. HLDA is asserted after completing the

current bus cycl e, bu rst cycle or seque nce of locked cycles. The embedded

IntelDX2 pro c essor rema ins in th is stat e until HOLD is de- asser ted. HOLD is

active HIGH and is not provided with an internal pull-down resistor. HOLD must

satisfy s etup and hold times t18 and t19 for p roper operation.

HLDA OHold Acknowledge

goes active in response to a hold request pres ented on the

HOLD pin. HL DA indicates that the embe dded IntelDX2 pr ocessor has give n the

bus to another local bus master. HLDA is driven active in the same clock that the

processor floats its bus. HLDA is driven inactive when leaving bus hold. HLDA is

ac tive HIGH and remain s dri v en during bu s hold.

Table 8. Embedded IntelDX2™ Processor Pin Descriptions (Sheet 4 of 7)

Symbol Type Name and Function

Embedded IntelDX2™ Processor

BOFF# IBackoff

input forces the embedded IntelDX2 processor to float its bus in the next

clock. The processor floats all pins normally floated during bus hold but HLDA is

not asserted in response to BOFF#. BOFF# has higher priority than RDY# or

BRDY#; if both are returned in the sam e cloc k, BOFF# takes effect. The

embedded IntelDX2 processor remains in bus hold until BOFF# is negated. If a

bus cycle is in progress when BO FF# is asserted the cycle is r estarted. BO FF# is

active LOW and must meet setu p and hold times t18 an d t19 for proper operat ion.

CACHE INVALIDATION

AHOLD IAddress H old

re qu es t al lows an oth er bus mas ter ac c es s to th e em be dd ed

IntelDX2 processor’ s addr ess bus for a c ache inv alidation cycle. The processor

stops driving its address bus in the clock following AHOLD going active. Only the

address bus is floa ted dur ing address hold, t he remainde r of the bus remains

active. AHOLD is active HIG H and is provided with a small internal pull-do wn

resistor. For prop er o pera tion, AHO LD must meet setup and hold times t18 and

t19.

EADS# IExternal Address - This signal indicates that a

valid

external address has been

dri ven on to t he emb edde d I nte lD X2 p roc ess or a ddre ss pi ns. T hi s a dd ress is use d

to perform an internal cache invalidation cycle. EADS# is active LOW and is

provided with an in ternal pull-up resistor. EAD S# must satis fy set up and ho ld

ti mes t12 and t13 for p rop er operati on.

CACHE CONTROL

KEN# ICache Enable

pin is used to determin e whether the curr ent cyc le is cach eable.

When the embedded IntelDX2 processor generates a cycle that can be cached

and KEN# is act ive one cl ock before RDY# or BRDY# du rin g the first transfer of

the cycle, the cycle becomes a cac he line fill cycle. Retur ning KEN# active one

clock before RDY# during the last read in the cache line fill causes the line to be

placed in the on-chip ca che. KEN# is active LOW and is pr ovided with a small

inter nal pull-u p resistor. KEN # must satisfy set up and hold times t14 and t15 fo r

proper oper ation.

FLUSH# ICa c h e Flu sh

input forces the embedded IntelDX2 processor to flush its entire

inter nal cache. FLUSH# is ac tive LO W and need only be asser ted f or on e clock.

FLUSH# is asynchronous but setup and hold times t20 and t21 mu st be met for

recognition in any specific clock.

PAGE CACHEABILITY

PWT

PCD O

OP ag e Write -Th roug h

and Pa ge Cache D isa ble pins reflect the state of the page

attribute bits, PWT and PCD, in the page table entry, page directory entry or

control register 3 (CR3) when paging is enabled. When paging is disabled, the

em bedded I nt elD X2 pro c es so r ig nores the PC D and PWT bits an d as s um e s they

are zero for the purpose of caching and driving PCD and PWT pins. PWT and

P CD ha ve th e s am e tim ing as th e c yc le de finitio n p ins (M/IO#, D/C#, an d W/R#).

PWT and PCD are active HIGH and are not driven during bus hold. PCD is

mas k ed by the cache disable bit (CD) in Control Register 0.

Table 8. Embedded IntelDX2™ Processor Pin Descriptions (Sheet 5 of 7)

Symbol Type Name and Function

Embedd ed IntelDX2™ Processor

BUS SIZE CONTROL

BS16#

BS8# I

IBu s Size 16

and Bus Size 8

pins (bus sizing pins) cause the embedded IntelDX2

processor to run multiple bus cycles to complete a request from devices that

cannot provide or accept 32 bits of data in a single cycle. The bus sizing pins are

sampled every clock. The processor uses the state of these pins in the clock

before Ready to determine bus size. These signals are active LOW and are

pr ov id ed w i th i nte r n al p ull - u p res is tors. T he se in pu ts m us t sati sfy s etu p and h old

times t14 a nd t15 for proper operation.

ADDRESS MASK

A20M# IAddress Bit 20 Mask pin, when asserted, causes the embedded IntelDX2

processor to mask physical address bit 20 (A20) before performing a lookup to

the internal cache or driving a memory cycle on the bus. A20M# emulates the

address wraparound at 1 Mbyte, which occurs on the 8086 processor. A20M# is

active LOW and should be asserted only when the embedded IntelDX2 processor

is in real mode. This pin is asynchronous but should meet setup and hold times

t20 and t21 for recognition in any specific clock. For proper operation, A20M#

should be sampled HIGH at the falling edge of RESET.

TEST ACCESS PORT

TCK ITest Cloc k, an in pu t to the em be dded In telDX2 proces so r , p ro vi de s the c loc k in g

function required by the JTA G Bou ndary scan feature. TCK is used to clock state

infor matio n (via TMS) and data (vi a TDI) into the compon ent on the rising edge of

TCK. Data is clocked out of the component (via TDO) on the falling ed ge of TCK.

TCK is provided with an internal pull-up resistor.

TDI ITest Data Input is the serial input used to shift JTAG inst ructions and d ata into

the processor. TDI is sampled on the rising edge of TCK, during the SHIFT-IR

and SHIFT-DR Test Access Port (TAP) controller states. During all other TAP

controller states, TDI is a “don’t care.” TDI is provided with an internal pull-up

resistor.

TDO O Test Data Output is the ser ial output used to shift JTAG instructions an d data out

of th e co m po ne nt. TD O is d riv en on the fallin g edge of TCK during the S HIFT-IR

and S HIFT-DR TAP c o ntro ller sta te s. At all o ther t im es TD O is dri v en to th e high

im pedanc e stat e.

TMS ITest Mode Select is decoded by the JTAG TAP to select test logic operation.

TMS is sampled on the rising edge of TCK. To guarantee deterministic behavior

of the TAP controller, TMS is provided with an internal pull-up resistor.

Table 8. Embedded IntelDX2™ Processor Pin Descriptions (Sheet 6 of 7)

Symbol Type Name and Function

Embedded IntelDX2™ Processor

NUMERIC ERROR REPORTING

FERR# OThe Floati ng P oint Error pin is driven active when a floating point error occurs.

FERR# is similar to the ERROR# pin on the Intel387™ Math CoProcessor.

FERR# is included for compatibility with systems using DOS type floating point

error re porting. FERR# will not go act ive if FP errors are masked in FPU register.

FERR# is active LOW, and is not floated during bus hold.

IGNNE# I When the Ignore Numeric Error pin is asserted the processor will ignore a

numeric error and continue executing non-control floating point instructions, but

F ER R# w i ll s t i ll b e ac tivated by the pr o ce s so r. Wh en IG N NE # i s de - a ss erted the

processor will freeze on a non-control floating point instruction, if a previous

f lo ati ng p oi nt ins tr u ct ion caus ed a n er ror. IGNNE# ha s no effect w he n th e NE bit

in control register 0 is set. IGNNE# is active LOW and is provided with a small

internal pull-up resistor. IGNNE# is asynchronous but setup and hold times t20

and t21 must be met to ensure recognition on any specific clock.

RESERVED PINS

RESERVED# IReserved i s r es erv e d fo r fu tur e use. Th is pi n M U ST be connec te d to an e xt er n al

pull- up r esistor circuit. The recommended resistor value is 1 0 kOhms. The pull-up

resistor must be connected only to the RESERVED# pin. Do not share this

resistor with other pins requiring pull-ups.

Table 8. Embedded IntelDX2™ Processor Pin Descriptions (Sheet 7 of 7)

Symbol Type Name and Function

Embedd ed IntelDX2™ Processor

Table 9. Output Pins

Name Active Level Outp ut Sign al

Floated During

Address Hold Floated During

Bus Hold During Stop Grant and

Stop Clock States

BREQ HIGH Previous State

HLDA HIGH As per HOL D

BE3#-BE0# LOW • Previous Sta te

PWT, PCD HIGH • Previous State

W/R#, M/IO#, D/C# HIGH/LOW • Previous State

LOCK# LOW • HIGH (inactive)

PLOCK# LOW • HIGH (inactive)

ADS# LOW • HIGH (inactive)

BLAST# LOW • Previous State

PCHK# LO W Previous Sta te

FERR# LOW Previ ous S tate

A3-A2 HIGH • • Previous State

SMIACT# LOW Previous State

NOTES: The term “Previous State” means that the processor maintains the logic level applied to the signal pin just before

the processor entered the Stop Grant state. This cons erves power by preventing the signal pin fr om floating.

Table 10. Input/Output Pins

Name Active Level

Output Signal

Floated During

Address Hold Floated During

Bus Hold During Stop Grant and

S top Cloc k States

D31-D0 HIGH • Floated

DP3–DP0 HIGH • Floated

A31-A4 HIGH • • Previous Sta te

NOTES: The term “Previous S tate” means that the processor maintains the logic level applied to the signal pin just befor e the

processor entered the Stop Grant state. This conserves power by preventing the signal pin from floating.

Ta ble 11. Te st P ins

Name Input or Output Sampled/ Driven On

TCK Input N/A

TDI Input Rising Edge of TCK

TDO Ou tput Failing Edge of TCK

TMS Input Rising Edge of TCK

Embedded IntelDX2™ Processor

Ta ble 12. Input Pins

Name Active Level Synchronous/

Asynchronous Internal Pull-Up/

Pull-Down

CLK

RESET HIGH Asynchronous

SRESET HIGH Asynchronous Pull-Down

HOLD HIGH Synchronous

AHOLD HIGH Synchronous Pull-Down

EADS# LOW Synchronous Pull-Up

BOFF# LOW Synchronous Pull-Up

FLUSH# LOW Asynchronous Pull-Up

A20M# LOW Asynchronous Pull-Up

BS16#, BS8# LOW Synchronous Pull-Up

KEN# LOW Synchronous Pull-Up

RDY# LOW Synchronous

BRDY# LOW Synchronous Pull-Up

INTR HIGH Asynchronous

NMI HIGH Asynchronous

IGNNE# LOW Asynchronous Pull-Up

RESERVED#

SMI# LOW Asynchronous Pull-Up

STPCLK# LOW Asynchronous Pull-Up1

TCK HIGH Pull-Up

TDI HIGH Pull-Up

TMS HIGH Pull-Up

NOTES:

1. Though STPCLK# has an internal pull-up resistor, an external 10-KΩ pull-up resistor is needed if the STPCLK# pin is

unused.

Embedd ed IntelDX2™ Processor

4.0 ARCHITECT URAL AND

FUNCTIONAL OVERVIEW

The embedded IntelDX2 processor architecture is

essentially the same as the IntelDX2 processor.

Refer to the Embedded Intel486™ Processor Family

Developer’s Manual for a description of the IntelDX2

processor.

Note that the embedded IntelDX2 processor has one

pin reserved for possible future use. This pin, an

input signal, is called RESERVED# and must be

connected to a 10-KΩ pull-up resistor. The pull-up

resistor must be connected only to th e RESE RVED#

pin. Do not share this resistor with other pins

req uiri ng pull-ups.

4.1 CPUID Instruction

The embedded IntelDX2 processor supports the

CPUID instruction (see Table 13). Because not all

Intel processors support the CPUID instruction, a

simple test can determine if the instruction is

supported. The test involves the processor’s ID Flag,

which is bit 21 of the EFLAGS register. If software

can change the value of this flag, the CPUID

instruction is available. The actual state of the ID

Flag bit is irrelevant and provides no significance to

the hardware. This bit is cleare d (rese t to zero) upo n

device reset (RESET or SRESET) for compatibility

with Intel486 processor designs that do not support

the CPUID instruct ion.

CPUID-instruction details are provided here for the

embedded IntelDX2 processor. Refer to Intel Appli-

cation Note AP-485

Intel Processor Identification

with the CP UID Instru ction

(Order No. 2416 18) for a

description that covers all aspects of the CPUID

instruction and how it pertains to other Intel

processors.

4.1.1 Operation of the CPUID Instruction

The CPUID instruction requires the software

developer to pass an input parameter to the

processor in the EAX register. The processor

response is returned in registers EAX, EBX, EDX,

and ECX.

Vendor ID String - When the parameter passed in EAX is 0 (zero), the register values returned upon

instruction execut ion are shown in the fo llowing table.

The v alues in EB X, E DX an d EC X in dic a te an I nte l proces s or. Wh en tak en in th e pr o pe r or d er, th ey decode to

the string “GenuineIntel.”

Table 13. CPUID Instruction Description

OP CO DE Instr uc tio n Processor

Core Clocks

Parameter passed in

EAX

(Input Value) Description

0F A2 CPUID 9 0 Vendor (Intel) ID String

14 1 Processor Identification

9 > 1 Undefined (Do Not Use)

31-------------24 23-----------16 15--------------8 7--------------0

High Value (= 1) EAX 0000 0000 0000 0001

Vendor ID String EBX u (75) n (6E) e (65) G (47 )

(ASCII EDX I (49) e (65) n (6E) i (69)

Characters) ECX l (6C) e (65) t (74) n (6E)

Embedded IntelDX2™ Processor

P roces sor I dentif ica tion - When th e paramet er pas sed to EAX i s 1 (on e), the registe r va lues return ed upo n

ins t ru c tion exec ution ar e :

4.2 Identif ication After Reset

P roc es sor Ide nti fica tion - Upon reset, the EDX register contains the processor signature:

4 .3 Bou ndary Sca n (J TA G)

4.3.1 D evic e Identification

Tables 14 and 15 show the 32-bit code for the embedded IntelDX2 processor. This code is loaded into the

Device Identification Register.

31---------------------------14 13,12 11----8 7----4 3----0

Processor

Signature EAX (Do Not Use)

Intel Reserv ed 0 0

Processor

Type

0 1 0 0

Family 0 0 1 1

Model XXXX

Stepping

(Intel releases information about stepping numbers as needed)

31--------------------------------------------------------------------------------------------------0

Intel Rese rved EBX Intel Reserved

(Do Not Use) ECX Intel Reserved

31----------------------------------------------------------------------------2 1 0

Feature Flags EDX 0------------------------------------------------------------------------------0 1

VME 0

FPU

31---------------------------14 13,12 11----8 7----4 3----0

Processor

Signature EDX (Do Not Use)

Intel Reserv ed 0 0

Processor

Type

0 1 0 0

Family 0 0 1 1

Model XXXX

Stepping

(Intel releases information about stepping numbers as needed)

Table 14. Boundary Scan Component Identification Code (3.3 Volt Processor)

Version Part Number Mfg ID

009H = Intel 1

VCC

0=5 V

1=3.3 V

Intel

Architecture

Ty pe

Family

0100 = Intel486

CPU Family

Model

00101 =

embedded IntelDX2

processor

31----28 27 26-----------21 20----17 16--------12 11------------1 0

XXXX 1 000001 0100 00101 00000001001 1

(Intel releases information about version numbers as needed)

Boundary Scan Component Identification Code = x828 5013 (Hex)

Embedd ed IntelDX2™ Processor

4.3.2 Boundary Scan Register Bits and Bit

Order

The bo undary scan register conta ins a cell for each

pin as well as cells for control of bidirectional and

three-state pins. There are “Reserved” bits which

correspond to no-connect (N/C) signals of the

embedded IntelDX2 processor. Control registers

WRCTL, ABUSCTL, BUSCTL, and MISCCTL are

used to select the direction of bid irectional or three-

state output signal pins. A “1” in these cells

designates that the associated bus or bits are floated

if the pins are three-state, or selected as input if they

are bidirectional.

• WRCTL controls D31-D0 and DP3–DP0

• ABUSCTL controls A31-A2

• BUSCTL cont rols ADS#, BLAST# , PLOCK#,

LOCK#, W/R#, BE0#, BE1#, BE2#, BE3#, M/IO#,

D/C# , PWT, and PCD

• MISCCTL controls PCHK#, HLDA, and BREQ

The following is the bit order of the embedded

IntelDX2 processor boundary scan register:

Table 15. Boundary Scan Component Identification Code (5 Volt Processor)

Version Part Number Mfg ID

009H = Intel 1

VCC

0=5 V

1=3.3 V

Intel

Architect ure

Type

Family

0100 = Intel486

CPU Family

Model

00101 =

embedded IntelDX2

processor

31----28 27 26-----------21 20----17 16--------12 11------------1 0

XXXX 0 000001 0100 00101 00000001001 1

(Intel releases information about version numbers as needed)

Boundary Scan Component Identification Code = x028 5013 (Hex)

TDO ←A2, A3, A4, A5, RESERVED#, A6,

A7, A8, A9, A10, A11, A12, A13,

A14, A15, A16, A17, A18, A19,

A20, A21, A22, A23, A24, A25,

A26, A27, A28, A29, A30, A31,

DP0, D0, D1, D2, D3, D4, D5, D6,

D7, DP1, D8, D 9, D10, D11, D12,

D13, D14, D15, DP2, D16, D17,

D18, D19, D20, D21, D22, D23,

DP3, D24, D25, D26, D27, D28,

D29, D30, D31, STPCLK#,

IGNNE#, FERR#, SMI#,

SMIACT#, SRESET, NMI, INTR,

FLUSH#, RESET, A20M#,

EADS#, PCD, PWT, D/C#, M/IO#,

BE3#, BE2#, BE1#, BE0#, BREQ,

W/R#, HLDA, CL K, RESERVED#,

AHOLD, HOLD, KEN#, RDY#,

BS8#, BS16#, BOFF#, BRDY#,

PCHK#, LOCK#, PLOCK#,

BLAST#, ADS#, MISCCTL,

BUSCTL, ABUSCTL, WRCTL ← TDI

Embedded IntelDX2™ Processor

5.0 ELECTRICAL SPECIFICATIONS

5.1 Maximum Ratings

Table 16 is a stress rating only. Extended exposure

to the Maximum Ratings may affect device reliability.

Furthermore, although the embedded IntelDX2

processor contains protective circuitry to resist

damage from electrostatic discharge, always take

precautions to avoid high static voltages or electric

fields.

Functional operating conditions are given in Section

5.2, DC Specifications and Se ction 5.3, AC Speci-

fications.

5.2 DC Specifications

The following tables show the operating supply

voltages, DC I/O specifications, and component

power consumption for the embedded IntelDX2

processor.

T ab le 16 . Abso lut e Ma xim um Ra t in gs

Case Temperature under

Bias -65 °C to +110 °C

Storage Temperature -65 °C to +150 °C

DC Voltage on Any Pin with

Respect to Ground -0.5 V to VCC + 0.5 V

Supply Voltage VCC with

Respect to VSS -0.5 V to +6.5 V

Table 17. Operating Supply Voltages

Product VCC

SB80486DX2SC50 3.3 V ± 0.3V

A80486DX2SA66 5.0 V ± 0.25 V

Embedd ed IntelDX2™ Processor

Table 18. 3.3 V DC Specifications

Functional Operating Range: VCC =3.3V±0.3V,T

CASE=0 °C to +8 5 ° C

Symbol Parameter Min. Max. Unit Notes

VIL Input LOW Voltage -0.3 +0.8 V

VIH Input HIGH Voltage 2.0 VCC +0.3 V Note 1

VIHC Input HIGH Voltage of CLK VCC -0.6 VCC +0.3 V

VOL Output LOW Voltage

IOL = 2.0 mA

IOL = 100 µA 0.4

0.2 V

VOH Output HIGH Voltage

IOH = -2.0 mA

IOH = -1 00 µA 2.4

VCC -0.2 V

ILI Input Leakage Current 15 µA Note 2

IIH Input Leakage Current

SRESET 200

300 µA

µANote 3

Note 3

IIL Input Leakage Current 400 µA Note 4

ILO Output Leakage Current 15 µA

CIN Input Capacitance 10 pF Note 5

COUT I/O or Output Capacitance 10 pF Note 5

CCLK CLK Capacitance 6 pF Note 5

NOTES:

1. All inputs except CLK.

2. This parameter is for inputs without pull-up or pull-down resistors and 0V ≤ VIN ≤ VCC.

3. This parameter is for inputs with pull-down resistors and VIH = 2.4V.

4. This parameter is for inputs with pull-up resistors and VIL = 0.4V.

5. FC=1 MHz. Not 100% tested.

Embedded IntelDX2™ Processor

Table 19. 3.3 V ICC Values

Functi onal Operating Range: V CC = 3.3 V ±0.3 V; TCASE = 0°C to +85°C

Parameter Operating

Frequency Typ Maximum Notes

ICC Active

(Power Supply) 40 MHz

50 MHz 450 mA

550 mA Note 1

ICC Active

(Thermal Design) 40 MHz

50 MHz 318 mA

395 mA 416 mA

507 mA Notes 2, 3, 4

ICC Stop Grant 40 MHz

50 MHz 20 mA

23 mA 40 mA

50 mA Note 5

ICC Stop Clock 0 MHz 100 µA 1 mA Note 6

NOTES:

1. This parameter is for proper power supply selection. It is measured using the worst case instruction mix at VCC = 3.6V.

2. The maximum current column is for thermal design power dissipation. It is measured using the worst case instruction mix

at VCC = 3.3V.

3. The typical current column is the typical operating current in a system. This value is measured in a system using a typical

device at VCC = 3.3V, running Microsoft Windows 3.1 at an idle conditi on. This typical value is dependent upon the specific

system configuration.

4. Typical values are not 100% tested.

5. The ICC Stop Grant specification refers to the ICC value once the embedded IntelDX2 processor enters the Stop Grant or

Auto HAL T P ower Down state.

6. The ICC Stop Clock specification refers to the ICC value once the embedded IntelDX2 processor enters the Stop Clock

state. T he VIH and VIL levels must be equal to VCC and 0 V, respectively, to meet the ICC Stop Clock specifications.

Embedd ed IntelDX2™ Processor

Table 20. 5 V DC Specifications

Functional operating range: VCC = 5V ± 0.2 5V; TCASE = 0°C to +85°C

Symbol Parameter Min Max Unit Notes

VIL Input LOW Voltage -0.3 +0.8 V

VIH I np ut HIG H Vo lt ag e 2. 0 VCC+0.3 V

VOL Ou tp ut LO W Vol ta ge 0.45 V Note 1

VOH Ou tp ut H IG H Voltage 2.4 V Note 2

ILI Input Leak ag e C urrent 15 µA N o te 3

IIH I np ut Le ak ag e C urr ent

SRESET 200

300 µA

µA Note 4

Note 4

IIL Input Leak ag e C urrent 400 µA No te 5

ILO Ou tp ut Le ak ag e C urr e nt 15 µA

CIN Input Capacitance 20 pF Note 6

COUT Output or I/O Capacitance 20 pF Note 6

CCLK CLK Capaci tance 20 pF Note 6

NOTES:

1. This parameter is measured at:

Address, Data, BE

# 4.0 mA

Definition, Control 5.0 #mA

2. This parameter is measured at:

Address, Data, BE

# -1.0 mA

Definition, Control -0.9 mA

3. This parameter is for inputs without pull-ups or pull-downs and 0V ≤ VIN ≤ VCC.

4. This parameter is for inputs with pull-downs and VIH = 2.4V.

5. This parameter is for inputs with pull-ups and VIL = 0.45V.

6. FC=1 MHz; Not 100% tested.

Embedded IntelDX2™ Processor

Table 21. 5 V ICC Values

Functional Operating Range: VCC = 5V ±0.25V; TCASE = 0°C to +85°C

Parameter Operating

Frequency Typ Maximum Notes

ICC Active

(Power Supply) 50 MHz

66 MHz 950 mA

1200 mA No te 1

ICC Active

(Thermal Design) 50 MHz

66 MHz 680 mA

901 mA 906 mA

1145 mA Notes 2, 3, 4

ICC Stop Grant 50 MHz

66 MHz 35 mA

40 mA 70 mA

90 mA No te 5

ICC Stop Clock 0 MHz 20 0 µA 2 mA Note 6

NOTES:

1. This parameter is for proper power supply selection. It is measured using the worst case instruction mix at VCC = 5.25V.

2. The maxi mum current column is for thermal design power dissipation. It i s measured using the worst case i nstruction mix

at VCC = 5V.

3. The typi cal current column is the typical operating current i n a system. This value is measur ed in a system using a typical

device at VCC = 5V, r unning Microsoft Windows 3.1 at an idle c ondition. This typical value is dependent upon the specific

system configuration.

4. Typical values are not 100% tested.

5. The ICC Stop Grant specification refers to the ICC value once the embedded IntelDX 2 processor enters the Stop Grant or

Auto HALT Power Down state.

6. The ICC Stop Clock specification refers to the ICC value once the processor enters the Stop Clock state. The VIH and VIL

levels must be equal to VCC and 0V, respectively, in order to meet the I CC Stop Clock specifications.

Embedd ed IntelDX2™ Processor
 33
5.3 AC Specifications
The AC specifications for the embedded IntelDX2 processor are given in this section.
Table 22.  AC Characteris tics
TCASE = 0 °C to +85°C; CL = 50pF, unless otherwise specified.  (Sheet 1 of 2)
Symbol Parameter
Vcc (Package)
3.3V
(208-Lead 
SQFP)
5V
(168-Pin 
PGA)
Min Max Min Max Unit Figure Notes
CLK Frequency 8 25 8 33 MHz  Note 1
t1CLK Period 40 12 5 30 125 ns 4
t1a CLK Period Stabil ity ±250 ±250 ps 4 Adjacent 
clocks
t2CLK High Time 14 11 ns 4 at 2V
t3CLK Low Time 14 11 ns 4 at 0.8V
t4CLK Fall Time 4 3 ns 4 2V to 0.8V
t5CLK Rise Time 4 3 ns 4 0.8V to 2V
t6A31– A2, PWT, PCD, BE3–BE0#, 
M/IO #, D/C#,  W/R#, ADS#, L OCK# , 
BREQ, HLDA, SMIACT#, FE RR# 
V ali d D el ay
3 19 3 16 ns 8
t7A31– A2, PWT, PCD, BE3–BE0#, 
M/IO #, D/C#,  W/R#, ADS#, L OCK# , 
BREQ, HLDA Float Delay
28 20 ns 9 Note 2
t8PCHK# Valid Delay 3 24 3 22 ns 7
t8a BLAST#, PLOCK# Valid Dela y 3 24 3 20 ns 8
t9BLAST#, PLOCK#  Float Delay 28 20 ns 9 No te 2
t10 D31–D0, DP3–DP0 Write Data Valid 
Delay 3 20 3 18 ns 8
t11 D31–D0, DP3–DP0 Write Data Float 
Delay 28 20 ns 9 Note 2
t12 EADS# Setup Time 8 5 ns 5
t13 EADS# Hold Time 3 3 ns 5
t14 KEN#, BS16#, BS8# Setup Time 8 5 ns 5
t15 KEN#, BS16#, BS8# Hold Time 3 3 ns 5
t16 RDY#, BRDY# Setup Time 8 5 ns 6
t17 RDY#, BRDY# Hold Time 3 3 ns 6
t18 HOLD, AHOLD Setup Time 10 6 ns 5
t18a BOFF# Setup Time 10 8 ns 5
t19 HOLD, AHOLD, BOFF# Hold Time 3 3 ns 5

Embedded IntelDX2™ Processor
34  
t20 FLUSH#, A20M#, NMI, INTR, SMI#, 
STPCL K#, SRESET, RESET, 
IGNNE# Setup Time
10 5 ns 5 N o te 3
t21 FLUSH#, A20M#, NMI, INTR, SMI#, 
STPCL K#, SRESET, RESET, 
IGNNE# Hold Time
3 3 ns 5 N o te 3
t22 D31–D0, DP3–DP0, 
A31–A4 Read Setup Time 65 ns6
5
t23 D31–D0, DP3–DP0, 
A3 1– A4 R ea d Hold T im e 33 ns6
5
NOTES:  
1. 0-MHz operation is guaranteed when the STPCLK# and Stop Grant bus cycle protocol is used.
2. Not 100% tes ted, guaranteed by design characterization.
3. A reset puls e  width of 15 CLK cycles is required for warm resets (RESET or SRESET). Power-up resets (cold resets) 
require RESET to be asserted for at least 1 ms after VCC and CLK are stable.
Table 23.  AC Specifications for the Test Access Port
(Both 3.3V SQFP and 5V PGA Process ors)
TCASE = 0°C to +85°C; CL = 50 pF
Sy mbol  Para meter Min Max Unit Figure Notes
t24  TCK Frequency   8 MHz Note 1
t25  TCK Period 125   ns 10  
t26  TCK Hi gh Time 40   ns 10 @ 2.0V
t27  TCK Low Time 40   ns 10 @ 0.8V
t28  TCK Rise Time   8 ns 10 Note 2
t29  TCK Fall Time   8 ns 10 Note 2
t30  T DI, TMS Setup Time 8   ns 11 Note 3
t31  T DI, TMS Hold Time 10   ns 1 1 N ote 3
t32  TDO Vali d Delay 3 30 ns 11 Note 3
t33  TDO Float Delay   36 ns 11 Note 3
t34  All Outputs (except TDO) Valid Delay 3 30 ns 11 Note 3
t35  All Outputs (except TDO) Floa t De lay   36 ns 11 Note 3
t36  All Inputs (except TDI, TMS, TCK) Setup Time 8   ns 11 Note 3
t37  All Inputs (except TDI, TMS, TCK) Hold Time 10   ns 11 Note  3
NOTES:  
1. TCK period ≤ CLK period.
2. Rise/Fall times are measured between 0.8V and 2.0V. Rise/Fall times can be relaxed by 1 ns per 10-ns increase in TCK 
period.
3. Parameters t30 – t37 are measured from TCK.
Table 22 .  AC C haracteristics
TCASE = 0°C to +85°C; CL = 50pF, unless  otherwise specified.  (Sheet 2 of 2)
Symbol Parameter
Vcc (Package)
3.3V
(208 -Lead 
SQFP)
5V
(168 -Pin 
PGA)
Min Max Min Max Unit Figure Notes

Embedd ed IntelDX2™ Processor

Figure 4. CLK Waveform

Figure 5. Input Setup and Hold Timing

1.5 V

t4t3

0.8 V

CLK 2.0 V

txty

1.5 V

tx = input setup times

ty = input hold times, output float, valid and hold times

1.5 V

0.8 V

2.0 V

TxTxTxTx

CLK

EADS#

BS8#, BS16#, KEN#

BOFF#, AHOLD, HOLD

RESET, FLUSH#,

A31-A4

(READ)

A20M#, INTR, NMI, SMI#,

STPCLK#, SRESET, IGNNE#

t12

t14

t13

t15

t18 t19

t20 t21

t22 t23

Embedded IntelDX2™ Processor

Figure 6. Input Setup and Hold Timing

Figure 7. PCHK# Valid Delay Timing

T2Tx

CLK

RDY#, BRDY#

D31-D0, DP3–DP 0

1.5 V

t16 t17

t22 t23

RDY#, BRDY#

D31-D0,

DP3-DP0

VALID

MIN MAX

PCHK#

T2TxTxTx

CLK

VALID

Embedd ed IntelDX2™ Processor

Figure 8. Output Valid Delay Timing

Figure 9. Maximum Float Delay Timing

BLAST#,

PLOCK#

TxTxTxTx

CLK

A2-A31, PWT, PCD,

D31-D0, DP3–DP 0

VALID n+1

MAX

VALID n

t10

t8a

BE0-3#, M/IO#,

D/ C#, W/R#, ADS# ,

LOCK#, BREQ, HLDA,

VALID n+1

MIN

MAX

VALID n

VALID n+1

MIN

MAX

VALID n

MIN

SMIACT#

TxTxTx

CLK

A2-A31, PWT, PCD,

D31-D0, DP3–DP0

BLAST#,

MIN

VALID

BE0-3#, M/IO#, D/C#,

W/R#, ADS#, LOCK#,

BREQ, HLDA, FERR#

PLOCK#

t10 t11

t8a t9

MIN

VALID

MIN

VALID

Embedded IntelDX2™ Processor

Figure 10. TCK Waveform

Figure 11. Test Signal Timing Diagram

0.8 V

t26

t25

2.0 V

TCK t27

t28 t29

0.8 V

2.0 V

t31

t30

TCK

TMS,

TDI

TDO

OUTPUT

INPUT

VALID

t32 t33

VALID

t35

VALIDVALID

VALID

t34

t37

t36

1.5 V

Embedd ed IntelDX2™ Processor

5.4 Capaciti ve Deratin g Cu rves

The following graphs are the capacitive derating c urves for the em bedded IntelDX2 processor .

Figure 12. Typical Loading Delay versus Load Capacitance under Worst-Case Conditions

for a Low-to-High Transition, 3.3 V Processor

Figure 13. Typical Loading Delay versus Load Capacitance under Worst-Case Conditions

for a High-to-Low Transition, 3.3 V Processor

nom+7

nom+6

nom+5

nom+4

nom+3

nom+2

nom+1

nom

nom-1

nom-225 50 75 100 125 150

Capacitive Load (pF)

Delay (ns)

NOTE: This graph will not be linear outs ide of the capacitive range sh own.

nom = nominal value from t he AC Characteristics table.

nom+5

nom+4

nom+3

nom+2

nom+1

nom

nom-1

nom-225 50 75 100 125 150

Capacitive Load (pF)

Delay (ns)

NOTE: This graph will not be linear outs ide of the capacitive range sh own.

nom = nominal value from t he AC Characteristics table.

Embedded IntelDX2™ Processor

Figure 14. Typical Loading Delay versus Load Capacitance under

Worst-Cas e Conditions for a Low-to-High Transition, 5 V Proc essor

Figure 15. Typical Loading Delay versus Load Capacitance under

Worst-Cas e Conditions for a High-to-Low Transition, 5 V Proc essor

nom+5

nom+4

nom+3

nom+2

nom+1

nom

nom-1

nom-2

Delay (ns)

Note: This graph will not be linear outside of the capacitive range shown.

nom = nominal value from the AC Characteristics table.

Capacitive Load (pF)

25 50 75 100 125 150

A3234-01

nom+5

nom+4

nom+3

nom+2

nom+1

nom

nom-1

nom-2

Delay (ns)

Note: This graph will not be linear outside of the capacitive range shown.

nom = nominal value from the AC Characteristics table.

Capacitive Load (pF)

25 50 75 100 125 150

nom+7

nom+6

A3235-01

Embedd ed IntelDX2™ Processor

6.0 M ECHANICA L DATA

This section describes the packaging dimensions and thermal specifications for the embedded IntelDX2

processor.

6.1 Package Dimen sion s

Figure 16. 208-Lead SQFP Package Dimensions

A3262-01

1.14

(ref)

28.0 ± 0.10

30.6 ± 0.25

25.50 (ref)

208 157

156

105

10453

NOTE: Length measurements same as width measurements

0.50

0.13 + 0.12-0.08

0˚ Min

7˚ Max

0.60 ± 0.10

3.37 ± 0.08

3.70 Max

0.13 Min

0.25 Max

1.76 Max

0.10 Max

Tolerance Window for

Lead Skew from Theoretical

True Position

1.30 Ref

.40 Min

Units: mm

Top View

Embedded IntelDX2™ Processor

Figure 17. Principal Dimensions and Data for 168-Pin Pi n Grid Array Package

Table 24. 168-Pin Ceramic PGA Package Dimensions

Symbol Millimeters Inches

Min Max Notes Min Max Notes

A 3.56 4.57 0.140 0.180

A10.64 1.14 S O LID LID 0.0 25 0 .0 45 SOLID LI D

A22. 8 3.5 S O LID LID 0.1 10 0 .1 40 SOLID LI D

A31.14 1.40 0.045 0.055

B 0.43 0.51 0.017 0.020

D 44.07 44.83 1.735 1.765

D140.51 40.77 1.595 1.605

e12.29 2.79 0.090 0.110

L 2.54 3.30 0.100 0.130

N168 168

S11.52 2.54 0.060 0.100

Embedd ed IntelDX2™ Processor

Table 25. Cera mic PGA Pac ka ge Dime ns ion Sym bo ls

Letter or Symbol Description of Dimensions

A Distance from seating plane to highest point of body

A1Distanc e between seat ing plane and base pl ane (l id)

A2Distance from base plane to highest point of body

A3Distance from seating plane to bottom of body

B Diameter of terminal lead pin

D Largest ov eral l package dimension of length

D1A body length dimension, outer lead center to outer lead center

e1Linear spaci ng between true lead po sition centerlines

L Distance from seating plane to end of lead

S1Other body dimension, outer lead center to edge of body

NOTES:

1. Controll ing dimension: millimeter.

2. Dimension “e1” (“e”) is no n-cumulative .

3. Seating plane (standoff) is defined by P.C. board hole size: 0.0415–0.0430 inch.

4. Dimensions “B”, “B1” and “C” are nominal.

5. Details of Pin 1 identifier are optional.

Embedded IntelDX2™ Processor

6.2 Package Thermal Specificatio ns

The embedded IntelDX2 processor is specified for

operation when the case temperature (TC) is within

the range of 0°C to 85°C. TC may be measured in

any environment to dete rmine whether the processor

is within the specified operating range.

The ambient temperature (TA) can be calculated

from θJC an d θJA from the following eq uation s :

TJ = T C + P * θJC

TA = T J - P * θJA

TC = T A + P * [θJA - θJC]

TA = TC - P * [θJA - θJC]

Where TJ, TA, TC equals Junction, Ambient and

Case Temperature respectively. θ

JC, θJA equals

Junction-to-Case and Junction-to-Ambient thermal

Resistance, respectively. P is defined as Maximum

Power Consumption.

Values for θJA and θJC are given in the following

tables for each product at its maximum operating

freq ue nc i es . Maxim um TA is shown f or each product

operating at various processor frequencies (twice

the CLK f requencies) .

Table 26. Thermal Resistance, θJA (°C/W)

θJA vs. Airflow — ft/min. (m/sec)

(0) 200

(1.01) 400

(2.03) 600

(3.04) 800

(4.06) 1000

(5.07)

208-Lead SQFP (3.3V) - Without Heat Sink 24.0 17.0 15.0 13.0 ––

168-Pin PGA (5V) - Without Heat Sink 17.0 14.5 12.5 11.0 10.0 9.5

168-P in PGA (5V) - With Heat Sink* 13.0 8.0 6.0 5.0 4 .5 4.25

*0.350" high omnidirecti onal heat sink.

Table 27. Thermal Resistance, θJC (°C/W)

θJC vs. Airflow — ft/min. (m/s ec)

(0) 200

(1.01) 400

(2.03) 600

(3.04)

0 200 400 600

2 08-Lead SQFP (3.3V) 3.5 6.0 6.0 6.0

168-Pin PGA (5V) 1.5 –––

Table 28 . Maximum Tambient, TA max ( °C)

Airflow — ft/min. (m/sec)

Freq.

(MHz) 0

(0) 200

(1.01) 400

(2.03) 600

(3.04)

Int elDX2™ Processor

208-Lead SQFP (3.3V) 40 57 70 73 75

Wi tho ut He at Sin k 50 51 67 70 73

168-Pin PGA (5V) 50 15 26 35 46

Wi tho ut He at Sin k 66 -4 11 22 36

168-Pin PGA (5V) 50 33 56 65 69

With Heat Sink 66 19 48 59 65