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LM556
SNAS549A MARCH 2000REVISED OCTOBER 2015
LM556 Dual Timer
1 Features 3 Description
The LM556 dual-timing circuit is a highly-stable
1 Direct Replacement for SE556/NE556 controller capable of producing accurate time delays
Timing From Microseconds Through Hours or oscillation. The LM556 device is a dual-timing
Operates in Both Astable and Monostable Modes version of the LM555 device. Timing is provided by
an external resistor and capacitor for each timing
Replaces Two 555 Timers function. The two timers operate independently of
Adjustable Duty Cycle each other, sharing only VCC and ground. The circuits
Output Can Source or Sink 200 mA may be triggered and reset on falling waveforms. The
output structures may sink or source 200 mA.
Output and Supply TTL-Compatible
Temperature Stability Better Than 0.005% per °C Device Information(1)
Normally On and Normally Off Output PART NUMBER PACKAGE BODY SIZE (NOM)
SOIC (14) 3.91 mm × 8.65 mm
2 Applications LM556 PDIP (14) 6.35 mm × 19.177 mm
Precision Timing (1) For all available packages, see the orderable addendum at
Pulse Generation the end of the data sheet.
Sequential Timing
Time Delay Generation
Pulse Width Modulation
Pulse Position Modulation
Linear Ramp Generator
Schematic Diagram
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM556
SNAS549A MARCH 2000REVISED OCTOBER 2015
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Table of Contents
7.4 Device Functional Modes.......................................... 8
1 Features.................................................................. 18 Application and Implementation ........................ 10
2 Applications ........................................................... 18.1 Application Information............................................ 10
3 Description............................................................. 18.2 Typical Application ................................................. 10
4 Revision History..................................................... 29 Power Supply Recommendations...................... 12
5 Pin Configuration and Functions......................... 310 Layout................................................................... 12
6 Specifications......................................................... 410.1 Layout Guidelines ................................................. 12
6.1 Absolute Maximum Ratings ...................................... 410.2 Layout Example .................................................... 12
6.2 ESD Ratings.............................................................. 411 Device and Documentation Support................. 13
6.3 Recommended Operating Conditions....................... 411.1 Documentation Support ........................................ 13
6.4 Thermal Information.................................................. 411.2 Community Resources.......................................... 13
6.5 Electrical Characteristics........................................... 511.3 Trademarks........................................................... 13
6.6 Typical Characteristics.............................................. 611.4 Electrostatic Discharge Caution............................ 13
7 Detailed Description.............................................. 811.5 Glossary................................................................ 13
7.1 Overview................................................................... 812 Mechanical, Packaging, and Orderable
7.2 Functional Block Diagram......................................... 8Information ........................................................... 13
7.3 Feature Description................................................... 8
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (March 2000) to Revision A Page
Added ESD Ratings table, Feature Description section, Device Functional Modes,Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................ 1
Deleted the VCC = 5 V and ISINK = 8 mA test condition row for the Output voltage drop parameter in the Electrical
Characteristics table............................................................................................................................................................... 5
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1
2
3
4
5
6
7
14
13
12
11
10
9
8
DISCHARGE
THRESHOLD
CTRL VOLTAGE
RESET
OUTPUT
TRIGGER
GND TRIGGER
OUTPUT
RESET
CTRL VOLTAGE
THRESHOLD
VCC
DISCHARGE
LM556
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SNAS549A MARCH 2000REVISED OCTOBER 2015
5 Pin Configuration and Functions
D or NFF Package
14-Pin SOIC or PDIP
Top View
Pin Functions
PIN I/O DESCRIPTION
NAME NO.
CONTROL Controls the threshold and trigger levels. It determines the pulse width of the output
VOLTAGE 3 I waveform. An external voltage applied to this pin can also be used to modulate the output
(Timer 0) waveform.
CONTROL Controls the threshold and trigger levels. It determines the pulse width of the output
VOLTAGE 11 I waveform. An external voltage applied to this pin can also be used to modulate the output
(Timer 1) waveform.
DISCHARGE Open collector output which discharges a capacitor between intervals (in phase with output).
1 I
(Timer 0) It toggles the output from high to low when voltage reaches 2/3 of supply voltage.
DISCHARGE Open collector output which discharges a capacitor between intervals (in phase with output).
13 I
(Timer 1) It toggles the output from high to low when voltage reaches 2/3 of supply voltage.
GND 7 O Ground reference voltage
OUTPUT 5 O Output driven waveform
(Timer 0)
OUTPUT 9 O Output driven waveform
(Timer 1)
RESET Negative pulse applied to this pin to disable or reset the timer. When not used for reset
4 I
(Timer 0) purposes, it should be connected to Vcc to avoid false triggering.
RESET Negative pulse applied to this pin to disable or reset the timer. When not used for reset
10 I
(Timer 1) purposes, it should be connected to Vcc to avoid false triggering.
THRESHOLD Compares the voltage applied to the terminal with a reference voltage of 2/3 VCC. The
2 I
(Timer 0) amplitude of voltage applied to this terminal is responsible for the set state of the flip-flop.
TRIGGER Responsible for transition of the flip-flop from set to reset. The output of the timer depends
6 I
(Timer 0) on the amplitude of the external trigger pulse applied to this pin.
THRESHOLD Compares the voltage applied to the terminal with a reference voltage of 2/3 VCC. The
12 I
(Timer 1) amplitude of voltage applied to this terminal is responsible for the set state of the flip-flop.
TRIGGER Responsible for transition of the flip-flop from set to reset. The output of the timer depends
8 I
(Timer 1) on the amplitude of the external trigger pulse applied to this pin.
VCC 14 I Supply voltage with respect to GND
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)(2)
MIN MAX UNIT
Supply voltage 18 V
LM556CM 410
Power dissipation(3) mW
LM556CN 1620
Operating temperature, LM556C 0 70 °C
PDIP package soldering (10 seconds) 260
Soldering information SOIC package vapor phase (60 seconds) 215 °C
SOIC package infrared (15 seconds) 220
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability
and specifications.
(3) For operating at elevated temperatures the device must be derated based on a 150°C maximum junction temperature and a thermal
resistance of 77°C/W (Plastic Dip), and 110°C/W (SO-14 Narrow).
6.2 ESD Ratings VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±500 V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT
VCC Supply voltage 4.5 16 V
TAOperating temperature 0 70 °C
6.4 Thermal Information LM556
THERMAL METRIC(1) D (SOIC) NFF (PDIP) UNIT
14 PINS 14 PINS
RθJA Junction-to-ambient thermal resistance 85.3 48.0 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 45.8 34.9 °C/W
RθJB Junction-to-board thermal resistance 39.6 27.9 °C/W
ψJT Junction-to-top characterization parameter 11.7 19.3 °C/W
ψJB Junction-to-board characterization parameter 39.4 27.8 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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6.5 Electrical Characteristics
TA= 25°C, VCC = 5 V to 15 V, unless otherwise specified
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Supply voltage 4.5 16 V
VCC = 5 V, RL= ¥ 3 6
Supply current (each timer section) mA
VCC = 15 V, RL= ¥ (low state)(1) 10 14
Initial accuracy 0.75%
Drift with temperature 50 ppm/°C
Timing error, RA= 1 k to 100 kΩ,
monostable C = 0.1 μF(2)
Accuracy over temperature 1.5%
Drift with supply 0.1 %/V
Initial accuracy 2.25%
Drift with temperature 150
Timing error, RA, RB= 1 k to 100 kΩ,ppm/°C
astable C = 0.1 μF(2)
Accuracy over temperature 3%
Drift with supply 0.30 %/V
VCC = 15 V 4.5 5 5.5
Trigger voltage V
VCC = 5 V 1.25 1.67 2
Trigger current 0.2 1 µA
Reset voltage 0.4 0.5 1 V
Reset current 0.1 0.6 mA
VTH = V-control(3) 0.03 0.1 µA
Threshold current VTH = 11.2 V 250 nA
VCC = 15 V 9 10 11
Control voltage level and threshold voltage V
VCC = 5 V 2.6 3.33 4
Pin 1, 13 leakage output high 1 100 nA
VCC = 15 V, I = 15 mA 180 300
Pin 1, 13 sat output low(4) mV
VCC = 4.5 V, I = 4.5 mA 80 200
ISINK = 10 mA 0.1 0.25
ISINK = 50 mA 0.4 0.75
VCC = 15 V
Output voltage drop (low) ISINK = 100 mA 2 2.75 V
ISINK = 200 mA 2.5
VCC = 5 V, ISINK = 5 mA 0.25 0.35
ISOURCE = 200 mA, VCC = 15 V 12.5
Output voltage drop (high) ISOURCE = 100 mA, VCC = 15 V 12.75 13.3 V
VCC = 5 V 2.75 3.3
Rise time of output 100 ns
Fall time of output 100 ns
Initial timing accuracy 0.1% 2% ppm/°C
Matching Timing drift with temperature See (5) ±10
characteristics Drift with supply voltage 0.2 0.5 %/V
(1) Supply current when output high typically 1 mA less at VCC = 5 V.
(2) Tested at VCC = 5 V and VCC = 15 V.
(3) This will determine the maximum value of RA+ RBfor 15-V operation. The maximum total (RA+ RB) is 20 MΩ.
(4) No protection against excessive pin 1, 13 current is necessary providing the package dissipation rating will not be exceeded.
(5) Matching characteristics refer to the difference between performance characteristics of each timer section.
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6.6 Typical Characteristics
Figure 2. Supply Current vs Supply Voltage (Each Section)
Figure 1. Minimum Pulse Width Required for Triggering
Figure 3. High Output Voltage vs Output Source Current Figure 4. Low Output Voltage vs Output Sink Current
Figure 5. Low Output Voltage vs Output Sink Current Figure 6. Low Output Voltage vs Output Sink Current
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DS007852-10
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Typical Characteristics (continued)
Figure 8. Output Propagation Delay vs Voltage Level of
Figure 7. Output Propagation Delay vs Voltage Level of Trigger Pulse
Trigger Pulse
Figure 10. Discharge Transistor (Pin 1, 13) Voltage vs Sink
Figure 9. Discharge Transistor (Pin 1, 13) Voltage vs Sink Current
Current
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7 Detailed Description
7.1 Overview
The LM556 dual-timing circuit is a highly stable device for generating accurate time delays or oscillations. The
two timers operate independently from one another, only sharing VCC and ground. For each individual timer,
additional terminals are provided for triggering or resetting. In the monostable mode of operation, the time is
precisely controlled by one external resistor and capacitor. For astable mode operation as an oscillator, the free
running frequency and duty cycle are accurately controlled with two external resistors and one capacitor. The
circuit may be triggered and reset on falling waveforms and the output circuit can source or sink up to 200 mA.
7.2 Functional Block Diagram
7.3 Feature Description
7.3.1 Operating Characteristics
The LM556 is specified for operation from 4.5 V to 16 V. Many of the specifications apply from 0C to 70C.
Parameters that can exhibit significant variance with regard to operating voltage or temperature are presented
Electrical Characteristics section and in and Typical Characteristics.
7.3.2 Timing from Microseconds Through Hours
The LM556 has the ability to have timing parameters from the microseconds range to hours. The time delay of
the system can be determined by the time constant of the R and C values used for either the monostable or
astable configuration. A nomograph is available for easy determination of R and C values for various time delays.
7.4 Device Functional Modes
The LM556 can operate in both astable and monostable mode depending on the application requirements.
7.4.1 Monostable Mode
The LM556 timer acts as a one-shot pulse generator. The pulse begins when the LM556 timer receives a signal
at the trigger input that falls below 1/3 of the voltage supply. The width of the output pulse is determined by the
time constant of an RC network. The output pulse ends when the voltage on the capacitor equals 2/3 of the
supply voltage. The output pulse width can be extended or shortened depending on the application by adjusting
the R and C values. More details are given in the LM555 datasheet (SNAS548).
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Device Functional Modes (continued)
Figure 11. Monostable
7.4.2 Astable (Free-Running) Mode
The LM556 timer can operate as an oscillator and puts out a continuous stream of rectangular pulses having a
specified frequency. The frequency of the pulse stream depends on the values of RA, RB, and C. Again, more
details are given in the LM555 datasheet (SNAS548).
Figure 12. Astable
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o
A A
f
R R C
1 2
1.44
(( 2 ) )
=
+
1
2
3
4
5
6
714
13
12
11
10
9
8
LM556 Vout
Vin
0.01 µF
10 µF
100 µF
0.01 µF
0.01 µF
R2A
R1A
R1B
R2B
LM556
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LM556 timer can be used in various configurations. A typical application for the LM556 timer in astable
mode is to drive an audio device (such as a beeper) to provide a pulsed sound. This simple application can be
modified to fit any application requirement.
8.2 Typical Application
Figure 13. Typical Application
8.2.1 Design Requirements
The main design requirements for this application require setting one of the timers (Timer A in this case) to the
same resonant frequency as the piezo transducer which can be set by choosing R1A, R2A, and CAwith
Equation 1:
(1)
The other design choice is to decide how often and long to produce the bleeping sound. This can be set by
choosing R1B and R2B of Timer B (acts as the reset button for Timer A) with Equation 2:
(2)
Other useful design equations like Equation 3 and Equation 4 are given below where threpresents the time it
takes to charge the capacitor of each individual timer and tlrepresents the time it takes to discharge the
capacitor.
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TS
th
tl
0 V
VCC
VCC
0 V
2/3 VCC
1/3 VCC
Output Waveform
Capacitor Voltage Waveform
l 2
t = 0.693R C
h 1 2
t = 0.693(R +R )C
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Typical Application (continued)
where
threpresents the time it takes to charge the capacitor of each individual timer (3)
where
tlrepresents the time it takes to discharge the capacitor. (4)
8.2.2 Detailed Design Procedure
Given that the resonant frequency of the piezo transducer is about 3 kHz, by choosing R1, C and using
Equation 1, R2can be determined to be 23.5 k.
In order to have the sound be audible for half the period, the duty cycle for the triggering timer should be 50%.
However, this is difficult to achieve because the recommended minimum value for R1is 1 k. Therefore, a duty
cycle of 49% was chosen for this application. By choosing R1to be 1 kand using Equation 2, R2is found to be
24.5 k.
8.2.3 Application Curve
Figure 14. Capacitor Voltage and Output Waveforms in Astable Mode
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1: DIS_A
2: THR_A
3: CVOLT_A
4: OUT_B
5: OUT_A
6: THR_A
7: GND
2
GND
1
VCC
14: VCC
13: DIS_B
12: THR_B
11: CVOLT_B
10: RST_B
9: OUT_B
8: THR_B
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9 Power Supply Recommendations
The LM556 requires a voltage supply within 4.5 V to 16 V. Adequate power supply bypassing is necessary to
protect associated circuitry. The minimum recommended capacitor value is 0.1 µF in parallel with a 1-µF
electrolytic capacitor. Place the bypass capacitors as close as possible to the LM556 and minimize the trace
length
CAUTION
Supply voltages larger than 18 V can permanently damage the device; see the
Absolute Maximum Ratings table.
10 Layout
10.1 Layout Guidelines
Standard PCB rules apply to routing the LM556. The parallel combination of a 0.1-µF capacitor and a 1-µF
electrolytic capacitor should be as close as possible to the LM556. The capacitor used for the time delay should
also be placed as close as possible to the discharge pin. A ground plane on the bottom layer can be used to
provide better noise immunity and signal integrity.
10.2 Layout Example
Figure 15. Layout Example
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation, see the following:
LM555 Timer,SNAS548
11.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LM556 MWC LIFEBUY WAFERSALE YS 0 1 Green (RoHS
& no Sb/Br) Call TI Level-1-NA-UNLIM -40 to 85
LM556CM/NOPB LIFEBUY SOIC D 14 55 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM 0 to 70 LM556CM
LM556CMX/NOPB LIFEBUY SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM 0 to 70 LM556CM
LM556CN/NOPB LIFEBUY PDIP NFF 14 25 Green (RoHS
& no Sb/Br) CU SN Level-1-NA-UNLIM 0 to 70 LM556CN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
PACKAGE OPTION ADDENDUM
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Addendum-Page 2
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LM556CMX/NOPB SOIC D 14 2500 330.0 16.4 6.5 9.35 2.3 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 28-Oct-2015
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LM556CMX/NOPB SOIC D 14 2500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
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Pack Materials-Page 2
MECHANICAL DATA
N0014A
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N14A (Rev G)
NFF0014A
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