A6818EEP-T - Allegro Microsystems

Description

The A6818 device combines a 32-bit CMOS shift register,

accompanying data latches and control circuitry, with bipolar

sourcing outputs and PNP active pull-downs. Designed

primarily to drive vacuum-fluorescent displays, the 60 V and

–40 mA output ratings also allow this device to be used in

many other peripheral power driver applications. The A6818

features an increased data-input rate (compared with the older

UCN/UCQ5818x) and a controlled output slew rate.

The CMOS shift register and latches allow direct interfacing

with microprocessor-based systems. With a 3.3 or 5 V logic

supply, typical serial data-input rates are up to 33 MHz.

A CMOS serial data output permits cascaded connections in

applications requiring additional drive lines. Similar devices

are available as the A6810 (10-bit) and A6812 (20-bit).

The A6818 output source drivers are NPN Darlingtons,

capable of sourcing up to 40 mA. The controlled output slew

rate reduces electromagnetic noise, which is an important

consideration in systems that include telecommunications

and/or microprocessors and to meet government emissions

26182.128F

Features and Benefits

▪ Controlled output slew rate

▪ 60 V minimum output break down

▪ PNP active pull-downs

▪ Low-power CMOS logic and latches

▪ High-speed data storage

▪ High data-input rate

▪ Low output-saturation voltages

▪ Improved replacements for SN75518N, SN75518NF,

UCN5818x, and UCQ5818x

DABiC-IV 32-Bit Serial Input

Latched Source Driver

Continued on the next page…

Package: 44 pin PLCC (suffix EP)

Functional Block Diagram

Not to scale

A6818

MOS

BIPOLAR

OUT1OUT2

GROUND Dwg. FP-013-1

OUT 3OUTN

CLOCK

SERIAL

DATA IN

STROBE

BLANKING

SERIAL

DATA OUT

SERIAL-PARALLEL SHIFT REGISTER

LATCHES

VDD

VBB

LOGIC

SUPPLY

LOAD

SUPPLY

DABiC-IV 32-Bit Serial Input

Latched Source Driver

A6818

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

regulations. For inter-digit blanking, all output drivers can be

disabled and all sink drivers turned on with a BLANKING input

high. The PNP active pull-downs will sink at least 2.5 mA.

Three temperature ranges are available for optimum performance

in commercial (suffix S-), industrial (E-), and extended industrial

(K-) applications. The package style provided is the minimum-area

surface-mount PLCC (suffix -EP). Copper lead frames, low logic-

power dissipation, and low output-saturation voltages allow these

devices to drive most multiplexed vacuum-fluorescent displays

over the maximum operating temperature range.

The lead (Pb) free versions have 100% matte tin leadframe

plating.

Description (continued)

Selection Guide

Part Number Pb-free Packing Ambient Temperature

TA (°C)

A6818EEPTR-T Yes 450 pieces/13-in. reel –40 to 85

A6818KEPTR – 450 pieces/13-in. reel –40 to 125

A6818SEPTR-T Yes 450 pieces/13-in. reel –20 to 85

Absolute Maximum Ratings*

Characteristic Symbol Notes Rating Units

Logic Supply Voltage VDD 7.0 V

Driver Supply Voltage VBB 60 V

Input Voltage Range VIN –0.3 to VDD + 0.3 V

Continuous Output Current Range IOUT –40 to 15 mA

Operating Ambient Temperature TA

Range E –40 to 85 ºC

Range K –40 to 125 ºC

Range S –20 to 85 ºC

Maximum Junction Temperature TJ(max) 150 ºC

Storage Temperature Tstg –55 to 125 ºC

*Caution: These CMOS devices have input static protection (Class 2) but are still susceptible to damage if exposed to extremely high

static electrical charges.

DABiC-IV 32-Bit Serial Input

Latched Source Driver

A6818

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Thermal Characteristics

Characteristic Symbol Test Conditions* Value Units

Package Thermal Resistance RθJA 1-layer PCB with copper limited to solder pads 54 ºC/W

*Additional thermal information available on the Allegro website.

Pin-out Diagram

TYPICAL OUTPUT DRIVERTYPICAL INPUT CIRCUIT

50 75 100 125 150

2.5

0.5

ALLOWABLE PACKAGE POWER

DISSIPATION IN WATTS

AMBIENT TEMPERATURE IN oo

ooC

2.0

1.5

1.0

3.0

SUFFIX 'EP', R

QJA

= 54oC/W

DABiC-IV 32-Bit Serial Input

Latched Source Driver

A6818

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

TRUTH TABLE

Serial Shift Register Contents Serial Latch Contents Output Contents

Data Clock Data Strobe

Input Input I1 I

2 I

3 ... IN-1 I

N Output Input I1 I

2 I

3 ... IN-1 I

N Blanklng I1 I

2 I

3 ... IN-1 IN

H H R1 R2 ... RN-2 R

N-1 R

N-1

L L R1 R2 ... RN-2 R

N-1 RN-1

X R1 R2 R3 ... RN-1 RN RN

X X X ... X X X L R1 R2 R3 ... RN-1 RN

1 P2 P3 ... PN-1 PN P

N H P1 P2 P3 ... PN-1 PN L P1 P

2 P

3 ... PN-1 PN

X X X ... X X H L L L ... L L

L = Low Logic Level H = High Logic Level X = Irrelevant P = Present State R = Previous State

DABiC-IV 32-Bit Serial Input

Latched Source Driver

A6818

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

ELECTRICAL CHARACTERISTICS at TA = +25°C (A6818S-) or over operating temperature range (A6818E-

and A6818K-), VBB = 60 V, unless otherwise noted

Limits @ VDD = 3.3 V Limits @ VDD = 5 V

Characteristic Symbol Test Conditions Mln. Typ. Max. Min. Typ. Max. Units

Output Leakage Current ICEX V

OUT = 0 V — <-0.1 -15 — <-0.1 -15 μA

Output Voltage VOUT(1) I

OUT = -25 mA 57.5 58.3 — 57.5 58.3 — V

OUT(0) I

OUT = 1 mA — 1.0 1.5 — 1.0 1.5 V

Output Pull-Down Current IOUT(0) V

OUT = 5 V to VBB 2.5 5.0 — 2.5 5.0 — mA

Input Voltage VIN(1) 2.2 — — 3.3 — — V

IN(0) — — 1.1 — — 1.7 V

Input Current IIN(1) V

IN = VDD — <0.01 1.0 — <0.01 1.0 μA

IN(0) V

IN = 0.8 V — <-0.01 -1.0 — <-0.01 -1.0 μA

Input Clamp Voltage VIK I

IN = -200 μA — -0.8 -1.5 — -0.8 -1.5 V

Serial Data Output Voltage VOUT(1) I

OUT = -200 μA 2.8 3.05 — 4.5 4.75 — V

OUT(0) I

OUT = 200 μA — 0.15 0.3 — 0.15 0.3 V

Maximum Clock Frequency fc 10 33 — 10 33 — MHz

Logic Supply Current IDD(1) All Outputs High — 0.25 0.75 — 0.3 1.0 mA

DD(0) All Outputs Low — 0.25 0.75 — 0.3 1.0 mA

Load Supply Current IBB(1) All Outputs High, No Load — 4.5 9.0 — 4.5 9.0 mA

BB(0) All Outputs Low — 0.2 20 — 0.2 20 μA

Blanking

-to-

Output Delay tdis(BQ) C

L = 30 pF, 50% to 50% — 0.7 2.0 — 0.7 2.0 μs

en(BQ) CL = 30 pF, 50% to 50% — 1.8 3.0 — 1.8 3.0 μs

Strobe

-to-

Output Delay tp(STH-QL) R

L = 2.3 k, CL 30 pF — 0.7 2.0 — 0.7 2.0 μs

p(STH-QH) R

L = 2.3 k, CL 30 pF — 1.8 3.0 — 1.8 3.0 μs

Output Fall Time tf R

L = 2.3 k, CL 30 pF 2.4 — 12 2.4 — 12 μs

Output Rise Time tr R

L = 2.3 k, CL 30 pF 2.4 — 12 2.4 — 12 μs

Output Slew Rate dV/dt RL = 2.3 k, CL 30 pF 4.0 — 20 4.0 — 20 V/μs

Clock

-to-

Serial Data Out Delay tp(CH-SQX) I

OUT = ±200 μA — 50 — — 50 — ns

Negative current is deﬁ ned as coming out of (sourcing) the speciﬁ ed device terminal.

Typical data is is for design information only and is at TA = +25°C.

DABiC-IV 32-Bit Serial Input

Latched Source Driver

A6818

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

TIMING REQUIREMENTS and SPECIFICATIONS

(Logic Levels are VDD and Ground)

Serial Data present at the input is transferred to the shift

put pulse. On succeeding CLOCK pulses, the registers shift data

information towards the SERIAL DATA OUTPUT. The SERIAL

DATA must appear at the input prior to the rising edge of the

CLOCK input waveform.

Information present at any register is transferred to the

respective latch when the STROBE is high (serial-to-parallel

conversion). The latches will continue to accept new data as long

as the STROBE is held high. Applications where the latches are

bypassed (STROBE tied high) will require that the BLANKING

input be high during serial data entry.

When the BLANKING input is high, the output source driv-

ers are disabled (OFF); the pnp active pull-down sink drivers are

ON. The information stored in the latches is not affected by the

BLANKING input. With the BLANKING input low, the outputs

are controlled by the state of their respective latches.

A. Data Active Time Before Clock Pulse

(Data Set-Up Time), tsu(D) ........................................... 25 ns

B. Data Active Time After Clock Pulse

(Data Hold Time), th(D) ................................................ 25 ns

C. Clock Pulse Width, tw(CH) ................................................. 50 ns

D. Time Between Clock Activation and Strobe, tsu(C) ......... 100 ns

E. Strobe Pulse Width, tw(STH) .............................................. 50 ns

NOTE – Timing is representative of a 10 MHz clock. Signiﬁ cantly

higher speeds are attainable.

DABiC-IV 32-Bit Serial Input

Latched Source Driver

A6818

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

For the latest version of this document, visit our website:

www.allegromicro.com

The products described here are manufactured under one or more U.S. patents or U.S. patents pending.

Allegro MicroSystems, Inc. reserves the right to make, from time to time, such de par tures from the detail spec i ﬁ ca tions as may be required to per-

mit improvements in the per for mance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the

information being relied upon is current.

Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the

failure of that life support device or system, or to affect the safety or effectiveness of that device or system.

The in for ma tion in clud ed herein is believed to be ac cu rate and reliable. How ev er, Allegro MicroSystems, Inc. assumes no re spon si bil i ty for its use;

nor for any in fringe ment of patents or other rights of third parties which may result from its use.

Package EP, 44-Pin PLCC

2144

Dimensions exclusive of mold flash, gate burrs, and dambar protrusions

Exact case and lead configuration at supplier discretion within limits shown

ATerminal #1 mark area

For Reference Only

(reference JEDEC MS-018 AC)

Dimensions in inches, metric dimensions (mm) in brackets, for reference only

SEATING

PLANE

0.51

4.57 MAX

16.59 ±0.08

7.75 ±0.36

7.75 ±0.367.75 ±0.36

C0.10

44X

0.74 ±0.08

17.53 ±0.13

1.27

0.43 ±0.10