MPC5602P Microcontroller Reference Manual, Rev. 4
Freescale Semiconductor 1
Qorivva MPC5602P Microcontroller
Reference Manual
Devices Supported:
MPC5601P
MPC5602P
MPC5602PRM
Rev. 4
28 Feb 2012
MPC5602P Microcontroller Reference Manual, Rev. 4
2Freescale Semiconductor
MPC5602P Microcontroller Reference Manual, Rev. 4
Freescale Semiconductor 3
Preface
Overview
The primary objective of this document is to define the functionality of the MPC5602P family of
microcontrollers for use by software and hardware developers. The MPC5602P family is built on
Power Architecture® technology and integrates technologies that are important for today’s electrical
hydraulic power steering (EHPS), electric power steering (EPS), airbag applications, anti-lock braking
systems (ABS), and motor control applications.
As with any technical documentation, it is the readers responsibility to be sure he or she is using the most
recent version of the documentation.
To locate any published errata or updates for this document, visit the Freescale Web site at
http://www.freescale.com/.
Audience
This manual is intended for system software and hardware developers and applications programmers who
want to develop products with the MPC5602P device. It is assumed that the reader understands operating
systems, microprocessor system design, basic principles of software and hardware, and basic details of the
Power Architecture.
Chapter organization and device-specific information
This document includes chapters that describe:
The device as a whole
The functionality of the individual modules on the device
In the latter, any device-specific information is presented in the section “Information Specific to This
Device” at the beginning of the chapter.
References
In addition to this reference manual, the following documents provide additional information on the
operation of the MPC5602P:
IEEE-ISTO 5001™ - 2003 and 2010, The Nexus 5001™ Forum Standard for a Global Embedded
Processor Debug Interface
IEEE 1149.1-2001 standard - IEEE Standard Test Access Port and Boundary-Scan Architecture
Power Architecture Book E V1.0
(http://www.freescale.com/files/32bit/doc/user_guide/BOOK_EUM.pdf)
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Chapter 1
Introduction
1.1 The MPC5602P microcontroller family ..........................................................................................35
1.2 Target applications ..........................................................................................................................36
1.2.1 Application examples .....................................................................................................36
1.2.1.1 Electric power steering .....................................................................................36
1.2.1.2 Airbag ...............................................................................................................37
1.3 Features ...........................................................................................................................................38
1.4 Critical performance parameters .....................................................................................................41
1.5 Chip-level features ..........................................................................................................................41
1.6 Module features ...............................................................................................................................43
1.6.1 High performance e200z0 core processor ......................................................................43
1.6.2 Crossbar switch (XBAR) ................................................................................................43
1.6.3 Enhanced direct memory access (eDMA) ......................................................................44
1.6.4 Flash memory .................................................................................................................44
1.6.5 Static random access memory (SRAM) .........................................................................45
1.6.6 Interrupt controller (INTC) .............................................................................................46
1.6.7 System status and configuration module (SSCM) ..........................................................46
1.6.8 System clocks and clock generation ...............................................................................47
1.6.9 Frequency-modulated phase-locked loop (FMPLL) ......................................................47
1.6.10 Main oscillator ................................................................................................................47
1.6.11 Internal RC oscillator .....................................................................................................47
1.6.12 Periodic interrupt timer (PIT) .........................................................................................48
1.6.13 System timer module (STM) ..........................................................................................48
1.6.14 Software watchdog timer (SWT) ....................................................................................48
1.6.15 Fault collection unit (FCU) ............................................................................................48
1.6.16 System integration unit – Lite (SIUL) ............................................................................49
1.6.17 Boot and censorship .......................................................................................................49
1.6.17.1 Boot assist module (BAM) ..............................................................................49
1.6.18 Error correction status module (ECSM) .........................................................................50
1.6.19 Peripheral bridge (PBRIDGE) ........................................................................................50
1.6.20 Controller area network (FlexCAN) ...............................................................................50
1.6.21 Safety port (FlexCAN) ...................................................................................................51
1.6.22 Serial communication interface module (LINFlex) .......................................................51
1.6.23 Deserial serial peripheral interface (DSPI) .....................................................................52
1.6.24 Pulse width modulator (FlexPWM) ................................................................................53
1.6.25 eTimer .............................................................................................................................54
1.6.26 Analog-to-digital converter (ADC) module ...................................................................54
1.6.27 Cross triggering unit (CTU) ...........................................................................................55
1.6.28 Nexus Development Interface (NDI) .............................................................................56
1.6.29 Cyclic redundancy check (CRC) ....................................................................................56
1.6.30 IEEE 1149.1 JTAG controller .........................................................................................56
1.6.31 On-chip voltage regulator (VREG) ................................................................................57
1.7 Developer environment ...................................................................................................................57
1.8 Package ............................................................................................................................................57
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Chapter 2
MPC5602P Memory Map
Chapter 3
Signal Description
3.1 100-pin LQFP pinout ......................................................................................................................63
3.2 64-pin LQFP pinout ........................................................................................................................64
3.3 Pin description .................................................................................................................................64
3.3.1 Power supply and reference voltage pins .......................................................................64
3.3.2 System pins .....................................................................................................................66
3.3.3 Pin multiplexing .............................................................................................................66
3.4 CTU / ADC / FlexPWM / eTimer connections ..............................................................................75
Chapter 4
Clock Description
4.1 Clock architecture ...........................................................................................................................79
4.2 Available clock domains .................................................................................................................82
4.2.1 FMPLL input reference clock ........................................................................................82
4.2.2 Clock selectors ................................................................................................................82
4.2.2.1 System clock selector 0 for SYS_CLK ............................................................82
4.2.3 Auxiliary Clock Selector 0 .............................................................................................83
4.2.4 Auxiliary Clock Selector 1 .............................................................................................83
4.2.5 Auxiliary Clock Selector 2 .............................................................................................83
4.2.6 Auxiliary clock dividers .................................................................................................83
4.2.7 External clock divider .....................................................................................................83
4.3 Alternate module clock domains .....................................................................................................84
4.3.1 FlexCAN clock domains ................................................................................................84
4.3.2 SWT clock domains .......................................................................................................84
4.3.3 Cross Triggering Unit (CTU) clock domains .................................................................84
4.3.4 Peripherals behind the IPS bus clock sync bridge ..........................................................84
4.3.4.1 FlexPWM clock domain ..................................................................................84
4.3.4.2 eTimer_0 clock domain ....................................................................................84
4.3.4.3 ADC_0 clock domain .......................................................................................85
4.3.4.4 Safety Port clock domains ................................................................................85
4.4 Clock behavior in STOP and HALT mode ......................................................................................85
4.5 System clock functional safety ........................................................................................................85
4.6 IRC 16 MHz internal RC oscillator (RC_CTL) ..............................................................................86
4.7 XOSC external crystal oscillator .....................................................................................................87
4.7.1 Functional description ....................................................................................................87
4.7.2 Register description ........................................................................................................88
4.8 Frequency Modulated Phase Locked Loop (FMPLL) ....................................................................89
4.8.1 Introduction ....................................................................................................................89
4.8.2 Overview ........................................................................................................................89
4.8.3 Features ...........................................................................................................................89
4.8.4 Memory map ..................................................................................................................90
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4.8.5 Register description ........................................................................................................90
4.8.5.1 Control Register (CR) ......................................................................................90
4.8.5.2 Modulation Register (MR) ...............................................................................92
4.8.6 Functional description ....................................................................................................93
4.8.6.1 Normal mode ....................................................................................................93
4.8.6.2 Progressive clock switching .............................................................................93
4.8.6.3 Normal Mode with frequency modulation .......................................................94
4.8.6.4 Powerdown mode .............................................................................................96
4.8.7 Recommendations ..........................................................................................................96
4.9 Clock Monitor Unit (CMU) ............................................................................................................96
4.9.1 Overview ........................................................................................................................96
4.9.2 Main features ..................................................................................................................97
4.9.3 Functional description ....................................................................................................97
4.9.3.1 Crystal clock monitor .......................................................................................97
4.9.3.2 PLL clock monitor ...........................................................................................98
4.9.3.3 System clock monitor .......................................................................................98
4.9.3.4 Frequency meter ...............................................................................................99
4.9.4 Memory map and register description ............................................................................99
4.9.4.1 Control Status Register (CMU_0_CSR) ........................................................100
4.9.4.2 Frequency Display Register (CMU_0_FDR) ................................................101
4.9.4.3 High Frequency Reference Register FMPLL_0 (CMU_0_HFREFR_A) ......101
4.9.4.4 Low Frequency Reference Register FMPLL_0 (CMU_0_LFREFR_A) .......102
4.9.4.5 Interrupt Status Register (CMU_0_ISR) ........................................................102
4.9.4.6 Measurement Duration Register (CMU_0_MDR) ........................................103
Chapter 5
Clock Generation Module (MC_CGM)
5.1 Overview .......................................................................................................................................105
5.2 Features .........................................................................................................................................106
5.3 External Signal Description ..........................................................................................................107
5.4 Memory Map and Register Definition ..........................................................................................107
5.5 Register Descriptions ....................................................................................................................112
5.5.1 Output Clock Enable Register (CGM_OC_EN) ..........................................................112
5.5.2 Output Clock Division Select Register (CGM_OCDS_SC) ........................................113
5.5.3 System Clock Select Status Register (CGM_SC_SS) ..................................................114
5.5.4 System Clock Divider Configuration Register (CGM_SC_DC0) ................................114
5.5.5 Auxiliary Clock 0 Select Control Register (CGM_AC0_SC) ......................................115
5.5.6 Auxiliary Clock 0 Divider Configuration Register (CGM_AC0_DC0) ......................116
5.5.7 Auxiliary Clock 1 Select Control Register (CGM_AC1_SC) ......................................116
5.5.8 Auxiliary Clock 1 Divider Configuration Register (CGM_AC1_DC0) ......................117
5.5.9 Auxiliary Clock 2 Select Control Register (CGM_AC2_SC) ......................................118
5.5.10 Auxiliary Clock 2 Divider Configuration Register (CGM_AC2_DC0) ......................119
5.6 Functional Description ..................................................................................................................119
5.7 System Clock Generation ..............................................................................................................119
5.7.1 System Clock Source Selection ....................................................................................120
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5.7.2 System Clock Disable ...................................................................................................120
5.7.3 System Clock Dividers .................................................................................................120
5.8 Auxiliary Clock Generation ..........................................................................................................120
5.8.1 Auxiliary Clock Source Selection ................................................................................123
5.8.2 Auxiliary Clock Dividers .............................................................................................123
5.9 Dividers Functional Description ...................................................................................................123
5.10 Output Clock Multiplexing ...........................................................................................................124
5.11 Output Clock Division Selection ...................................................................................................124
Chapter 6
Power Control Unit (MC_PCU)
6.1 Introduction ...................................................................................................................................125
6.1.1 Overview ......................................................................................................................125
6.1.2 Features .........................................................................................................................126
6.2 External Signal Description ..........................................................................................................126
6.3 Memory Map and Register Definition ..........................................................................................126
6.3.1 Memory Map ................................................................................................................126
6.3.2 Register Descriptions ....................................................................................................127
6.3.2.1 Power Domain Status Register (PCU_PSTAT) ..............................................127
Chapter 7
Mode Entry Module (MC_ME)
7.1 Introduction ...................................................................................................................................129
7.1.1 Overview ......................................................................................................................129
7.1.2 Features .........................................................................................................................131
7.1.3 Modes of Operation ......................................................................................................131
7.2 External Signal Description ..........................................................................................................132
7.3 Memory Map and Register Definition ..........................................................................................132
7.3.1 Memory Map ................................................................................................................133
7.3.2 Register Description .....................................................................................................140
7.3.2.1 Global Status Register (ME_GS) ...................................................................140
7.3.2.2 Mode Control Register (ME_MCTL) ............................................................142
7.3.2.3 Mode Enable Register (ME_ME) ..................................................................143
7.3.2.4 Interrupt Status Register (ME_IS) .................................................................144
7.3.2.5 Interrupt Mask Register (ME_IM) .................................................................145
7.3.2.6 Invalid Mode Transition Status Register (ME_IMTS) ..................................146
7.3.2.7 Debug Mode Transition Status Register (ME_DMTS) ..................................147
7.3.2.8 RESET Mode Configuration Register (ME_RESET_MC) ...........................150
7.3.2.9 TEST Mode Configuration Register (ME_TEST_MC) .................................150
7.3.2.10 SAFE Mode Configuration Register (ME_SAFE_MC) ................................151
7.3.2.11 DRUN Mode Configuration Register (ME_DRUN_MC) .............................151
7.3.2.12 RUN0…3 Mode Configuration Registers (ME_RUN0…3_MC) .................152
7.3.2.13 HALT0 Mode Configuration Register (ME_HALT0_MC) ...........................152
7.3.2.14 STOP0 Mode Configuration Register (ME_STOP0_MC) ............................153
7.3.2.15 Peripheral Status Register 0 (ME_PS0) .........................................................155
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7.3.2.16 Peripheral Status Register 1 (ME_PS1) .........................................................155
7.3.2.17 Peripheral Status Register 2 (ME_PS2) .........................................................156
7.3.2.18 Run Peripheral Configuration Registers (ME_RUN_PC0…7) .....................156
7.3.2.19 Low-Power Peripheral Configuration Registers (ME_LP_PC0…7) .............157
7.3.2.20 Peripheral Control Registers (ME_PCTL0…143) .........................................158
7.4 Functional Description ..................................................................................................................159
7.4.1 Mode Transition Request ..............................................................................................159
7.4.2 Modes Details ...............................................................................................................160
7.4.2.1 RESET Mode .................................................................................................160
7.4.2.2 DRUN Mode ..................................................................................................161
7.4.2.3 SAFE Mode ....................................................................................................161
7.4.2.4 TEST Mode ....................................................................................................162
7.4.2.5 RUN0…3 Modes ...........................................................................................162
7.4.2.6 HALT0 Mode .................................................................................................163
7.4.2.7 STOP0 Mode ..................................................................................................163
7.4.3 Mode Transition Process ..............................................................................................164
7.4.3.1 Target Mode Request .....................................................................................164
7.4.3.2 Target Mode Configuration Loading .............................................................164
7.4.3.3 Peripheral Clocks Disable ..............................................................................165
7.4.3.4 Processor Low-Power Mode Entry ................................................................166
7.4.3.5 Processor and System Memory Clock Disable ..............................................166
7.4.3.6 Clock Sources Switch-On ..............................................................................166
7.4.3.7 Flash Modules Switch-On ..............................................................................167
7.4.3.8 Pad Outputs-On ..............................................................................................167
7.4.3.9 Peripheral Clocks Enable ...............................................................................167
7.4.3.10 Processor and Memory Clock Enable ............................................................167
7.4.3.11 Processor Low-Power Mode Exit ..................................................................167
7.4.3.12 System Clock Switching ................................................................................167
7.4.3.13 Pad Switch-Off ...............................................................................................168
7.4.3.14 Clock Sources (with no Dependencies) Switch-Off ......................................169
7.4.3.15 Clock Sources (with Dependencies) Switch-Off ...........................................169
7.4.3.16 Flash Switch-Off ............................................................................................169
7.4.3.17 Current Mode Update .....................................................................................169
7.4.4 Protection of Mode Configuration Registers ................................................................172
7.4.5 Mode Transition Interrupts ...........................................................................................172
7.4.5.1 Invalid Mode Configuration Interrupt ............................................................172
7.4.5.2 Invalid Mode Transition Interrupt ..................................................................172
7.4.5.3 SAFE Mode Transition Interrupt ...................................................................174
7.4.5.4 Mode Transition Complete Interrupt .............................................................174
7.4.6 Peripheral Clock Gating ...............................................................................................174
7.4.7 Application Example ....................................................................................................175
Chapter 8
Reset Generation Module (MC_RGM)
8.1 Introduction ...................................................................................................................................177
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8.1.1 Overview ......................................................................................................................177
8.1.2 Features .........................................................................................................................178
8.1.3 Reset Sources ................................................................................................................179
8.2 External Signal Description ..........................................................................................................180
8.3 Memory Map and Register Definition ..........................................................................................180
8.3.1 Register Descriptions ....................................................................................................182
8.3.1.1 Functional Event Status Register (RGM_FES) ..............................................182
8.3.1.2 Destructive Event Status Register (RGM_DES) ............................................184
8.3.1.3 Functional Event Reset Disable Register (RGM_FERD) ..............................185
8.3.1.4 Destructive Event Reset Disable Register (RGM_DERD) ............................186
8.3.1.5 Functional Event Alternate Request Register (RGM_FEAR) .......................187
8.3.1.6 Functional Event Short Sequence Register (RGM_FESS) ............................188
8.3.1.7 Functional Bidirectional Reset Enable Register (RGM_FBRE) ....................190
8.4 Functional Description ..................................................................................................................191
8.4.1 Reset State Machine .....................................................................................................191
8.4.1.1 PHASE0 Phase ...............................................................................................192
8.4.1.2 PHASE1 Phase ...............................................................................................193
8.4.1.3 PHASE2 Phase ...............................................................................................193
8.4.1.4 PHASE3 Phase ...............................................................................................193
8.4.1.5 IDLE Phase ....................................................................................................193
8.4.2 Destructive Resets ........................................................................................................194
8.4.3 External Reset ...............................................................................................................194
8.4.4 Functional Resets ..........................................................................................................195
8.4.5 Alternate Event Generation ..........................................................................................195
8.4.6 Boot Mode Capturing ...................................................................................................196
Chapter 9
Interrupt Controller (INTC)
9.1 Introduction ...................................................................................................................................197
9.2 Features .........................................................................................................................................197
9.3 Block diagram ...............................................................................................................................199
9.4 Modes of operation ........................................................................................................................199
9.4.1 Normal mode ................................................................................................................199
9.4.1.1 Software vector mode ....................................................................................199
9.4.1.2 Hardware vector mode ...................................................................................200
9.4.1.3 Debug mode ...................................................................................................200
9.4.1.4 Stop mode .......................................................................................................200
9.5 Memory map and registers description .........................................................................................201
9.5.1 Module memory map ...................................................................................................201
9.5.2 Registers description ....................................................................................................201
9.5.2.1 INTC Module Configuration Register (INTC_MCR) ...................................202
9.5.2.2 INTC Current Priority Register (INTC_CPR) ...............................................203
9.5.2.3 INTC Interrupt Acknowledge Register(INTC_IACKR) ...............................204
9.5.2.4 INTC End-of-Interrupt Register (INTC_EOIR) ............................................205
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9.5.2.5 INTC Software Set/Clear Interrupt Registers
(INTC_SSCIR0_3–INTC_SSCIR4_7) ................................................................................205
9.5.2.6 INTC Priority Select Registers (INTC_PSR0_3–INTC_PSR220_221) ........206
9.6 Functional description ...................................................................................................................209
9.6.1 Interrupt request sources ...............................................................................................217
9.6.1.1 Peripheral interrupt requests ..........................................................................217
9.6.1.2 Software configurable interrupt requests .......................................................218
9.6.1.3 Unique vector for each interrupt request source ............................................218
9.6.2 Priority management ....................................................................................................218
9.6.2.1 Current priority and preemption ....................................................................218
9.6.2.2 Last-in first-out (LIFO) ..................................................................................219
9.6.3 Handshaking with processor .........................................................................................219
9.6.3.1 Software vector mode handshaking ...............................................................219
9.6.3.2 Hardware vector mode handshaking ..............................................................221
9.7 Initialization/application information ............................................................................................221
9.7.1 Initialization flow .........................................................................................................221
9.7.2 Interrupt exception handler ...........................................................................................222
9.7.2.1 Software vector mode ....................................................................................222
9.7.2.2 Hardware vector mode ...................................................................................223
9.7.3 ISR, RTOS, and task hierarchy .....................................................................................223
9.7.4 Order of execution ........................................................................................................224
9.7.5 Priority ceiling protocol ................................................................................................225
9.7.5.1 Elevating priority ...........................................................................................225
9.7.5.2 Ensuring coherency ........................................................................................225
9.7.6 Selecting priorities according to request rates and deadlines .......................................226
9.7.7 Software configurable interrupt requests ......................................................................226
9.7.7.1 Scheduling a lower priority portion of an ISR ...............................................226
9.7.7.2 Scheduling an ISR on another processor .......................................................227
9.7.8 Lowering priority within an ISR ..................................................................................227
9.7.9 Negating an interrupt request outside of its ISR ..........................................................228
9.7.9.1 Negating an interrupt request as a side effect of an ISR ................................228
9.7.9.2 Negating multiple interrupt requests in one ISR ............................................228
9.7.9.3 Proper setting of interrupt request priority .....................................................228
9.7.10 Examining LIFO contents ............................................................................................228
Chapter 10
System Status and Configuration Module (SSCM)
10.1 Introduction ...................................................................................................................................229
10.1.1 Overview ......................................................................................................................229
10.1.2 Features .........................................................................................................................229
10.1.3 Modes of operation .......................................................................................................230
10.2 Memory map and register description ...........................................................................................230
10.2.1 Memory map ................................................................................................................230
10.2.2 Register description ......................................................................................................230
10.2.2.1 System Status register (STATUS) ..................................................................231
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10.2.2.2 System Memory Configuration register (MEMCONFIG) .............................232
10.2.2.3 Error Configuration (ERROR) register ..........................................................233
10.2.2.4 Debug Status Port (DEBUGPORT) register ..................................................233
10.2.2.5 Password comparison registers ......................................................................236
10.3 Functional description ...................................................................................................................237
10.4 Initialization/application information ............................................................................................237
10.4.1 Reset .............................................................................................................................237
Chapter 11
System Integration Unit Lite (SIUL)
11.1 Introduction ...................................................................................................................................239
11.2 Overview .......................................................................................................................................239
11.3 Features .........................................................................................................................................240
11.3.1 Register protection ........................................................................................................241
11.4 External signal description ............................................................................................................241
11.4.1 Detailed signal descriptions ..........................................................................................241
11.4.1.1 General-purpose I/O pins (GPIO[0:66]) ........................................................241
11.4.1.2 External interrupt request input pins (EIRQ[0:24]) .......................................241
11.5 Memory map and register description ...........................................................................................242
11.5.1 SIUL memory map .......................................................................................................242
11.5.2 Register description ......................................................................................................243
11.5.2.1 MCU ID Register #1 (MIDR1) ......................................................................243
11.5.2.2 MCU ID Register #2 (MIDR2) ......................................................................245
11.5.2.3 Interrupt Status Flag Register (ISR) ...............................................................246
11.5.2.4 Interrupt Request Enable Register (IRER) .....................................................246
11.5.2.5 Interrupt Rising-Edge Event Enable Register (IREER) .................................247
11.5.2.6 Interrupt Falling-Edge Event Enable Register (IFEER) ................................247
11.5.2.7 Interrupt Filter Enable Register (IFER) .........................................................248
11.5.2.8 Pad Configuration Registers (PCR[0:71]) .....................................................248
11.5.2.9 Pad Selection for Multiplexed Inputs registers (PSMI[0_3:32_35]) .............250
11.5.2.10 GPIO Pad Data Output registers 0_3–68_71 (GPDO[0_3:68_71]) ...............254
11.5.2.11 GPIO Pad Data Input registers 0_3–68_71 (GPDI[0_3:68_71]) ...................254
11.5.2.12 Parallel GPIO Pad Data Out register 0–3 (PGPDO[0:3]) ..............................255
11.5.2.13 Parallel GPIO Pad Data In register 0–3 (PGPDI[0:3]) ..................................255
11.5.2.14 Masked Parallel GPIO Pad Data Out register 0–6 (MPGPDO[0:6]) .............256
11.5.2.15 Interrupt Filter Maximum Counter registers 0–24 (IFMC[0:24]) ..................257
11.5.2.16 Interrupt Filter Clock Prescaler Register (IFCPR) .........................................257
11.6 Functional description ...................................................................................................................259
11.6.1 General .........................................................................................................................259
11.6.2 Pad control ....................................................................................................................259
11.6.3 General purpose input and output pads (GPIO) ...........................................................259
11.6.4 External interrupts ........................................................................................................260
11.6.4.1 External interrupt management ......................................................................261
11.7 Pin muxing ....................................................................................................................................261
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Chapter 12
e200z0 and e200z0h Core
12.1 Overview .......................................................................................................................................263
12.2 Features .........................................................................................................................................263
12.2.1 Microarchitecture summary ..........................................................................................264
12.2.1.1 Block diagram ................................................................................................264
12.2.1.2 Instruction unit features .................................................................................266
12.2.1.3 Integer unit features .......................................................................................267
12.2.1.4 Load/Store unit features .................................................................................267
12.2.1.5 e200z0h system bus features ..........................................................................267
12.2.1.6 Nexus features ................................................................................................267
12.3 Core registers and programmers model .......................................................................................268
12.3.1 Unimplemented SPRs and read-only SPRs ..................................................................271
12.4 Instruction summary ......................................................................................................................271
Chapter 13
Peripheral Bridge (PBRIDGE)
13.1 Introduction ...................................................................................................................................273
13.1.1 Block diagram ..............................................................................................................273
13.1.2 Overview ......................................................................................................................273
13.1.3 Modes of operation .......................................................................................................274
13.2 Functional description ...................................................................................................................274
13.2.1 Access support ..............................................................................................................274
13.2.1.1 Peripheral Write Buffering .............................................................................274
13.2.1.2 Read cycles ....................................................................................................274
13.2.1.3 Write cycles ....................................................................................................274
13.2.2 General operation .........................................................................................................274
Chapter 14
Crossbar Switch (XBAR)
14.1 Introduction ...................................................................................................................................275
14.2 Block diagram ...............................................................................................................................275
14.3 Overview .......................................................................................................................................276
14.4 Features .........................................................................................................................................276
14.5 Modes of operation ........................................................................................................................276
14.5.1 Normal mode ................................................................................................................276
14.5.2 Debug mode ..................................................................................................................276
14.6 Functional description ...................................................................................................................277
14.6.1 Overview ......................................................................................................................277
14.6.2 General operation .........................................................................................................277
14.6.3 Master ports ..................................................................................................................278
14.6.4 Slave ports ....................................................................................................................278
14.6.5 Priority assignment .......................................................................................................278
14.6.6 Arbitration ....................................................................................................................278
14.6.6.1 Fixed priority operation .................................................................................279
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Chapter 15
Error Correction Status Module (ECSM)
15.1 Introduction ...................................................................................................................................281
15.2 Overview .......................................................................................................................................281
15.3 Features .........................................................................................................................................281
15.4 Memory map and registers description .........................................................................................281
15.4.1 Memory map ................................................................................................................282
15.4.2 Registers description ....................................................................................................283
15.4.2.1 Processor core type (PCT) register ................................................................283
15.4.2.2 Revision (REV) register .................................................................................283
15.4.2.3 Platform XBAR Master Configuration (PLAMC) .........................................284
15.4.2.4 Platform XBAR Slave Configuration (PLASC) ............................................284
15.4.2.5 IPS Module Configuration (IMC) register .....................................................285
15.4.2.6 Miscellaneous Reset Status Register (MRSR) ...............................................285
15.4.2.7 Miscellaneous Interrupt Register (MIR) ........................................................286
15.4.2.8 Miscellaneous User-Defined Control Register (MUDCR) ............................287
15.4.2.9 ECC registers .................................................................................................287
15.4.2.10 ECC Configuration Register (ECR) ...............................................................288
15.4.2.11 ECC Status Register (ESR) ............................................................................289
15.4.2.12 ECC Error Generation Register (EEGR) .......................................................290
15.4.2.13 Flash ECC Address Register (FEAR) ............................................................292
15.4.2.14 Flash ECC Master Number Register (FEMR) ...............................................293
15.4.2.15 Flash ECC Attributes (FEAT) register ...........................................................293
15.4.2.16 Flash ECC Data Register (FEDR) .................................................................294
15.4.2.17 RAM ECC Address Register (REAR) ...........................................................295
15.4.2.18 RAM ECC Syndrome Register (RESR) ........................................................296
15.4.2.19 RAM ECC Master Number Register (REMR) ..............................................298
15.4.2.20 RAM ECC Attributes (REAT) register ..........................................................298
15.4.2.21 RAM ECC Data Register (REDR) .................................................................299
15.4.3 ECSM_reg_protection ..................................................................................................300
Chapter 16
Internal Static RAM (SRAM)
16.1 Introduction ...................................................................................................................................303
16.2 SRAM operating mode ..................................................................................................................303
16.3 Module memory map ....................................................................................................................303
16.4 Register descriptions .....................................................................................................................303
16.5 SRAM ECC mechanism ................................................................................................................303
16.5.1 Access timing ...............................................................................................................304
16.5.2 Reset effects on SRAM accesses ..................................................................................305
16.6 Functional description ...................................................................................................................305
16.7 Initialization and application information .....................................................................................305
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Chapter 17
Flash Memory
17.1 Introduction ...................................................................................................................................307
17.2 Platform Flash controller ...............................................................................................................307
17.2.1 Introduction ..................................................................................................................307
17.2.1.1 Overview ........................................................................................................308
17.2.1.2 Features ..........................................................................................................308
17.2.2 Modes of operation .......................................................................................................309
17.2.3 External signal descriptions ..........................................................................................309
17.2.4 Memory map and registers description ........................................................................309
17.2.4.1 Memory map ..................................................................................................310
17.2.5 Functional description ..................................................................................................311
17.2.6 Basic interface protocol ................................................................................................312
17.2.7 Access protections ........................................................................................................312
17.2.8 Read cycles — buffer miss ...........................................................................................312
17.2.9 Read cycles — buffer hit ..............................................................................................313
17.2.10 Write cycles ..................................................................................................................313
17.2.11 Error termination ..........................................................................................................313
17.2.12 Access pipelining ..........................................................................................................314
17.2.13 Flash error response operation ......................................................................................314
17.2.14 Bank0 page read buffers and prefetch operation ..........................................................314
17.2.14.1 Instruction/data prefetch triggering ................................................................316
17.2.14.2 Per-master prefetch triggering ........................................................................316
17.2.14.3 Buffer allocation .............................................................................................316
17.2.14.4 Buffer invalidation .........................................................................................316
17.2.15 Bank1 temporary holding register ................................................................................317
17.2.16 Read-While-Write functionality ...................................................................................317
17.2.17 Wait state emulation .....................................................................................................319
17.2.18 Timing diagrams ...........................................................................................................320
17.3 Flash memory ................................................................................................................................327
17.3.1 Introduction ..................................................................................................................327
17.3.2 Main features ................................................................................................................327
17.3.3 Block diagram ..............................................................................................................327
17.3.3.1 Data Flash ......................................................................................................327
17.3.3.2 Code Flash ......................................................................................................328
17.3.4 Functional description ..................................................................................................329
17.3.4.1 Macrocell structure ........................................................................................329
17.3.4.2 Flash module sectorization .............................................................................330
17.3.5 Operating modes ...........................................................................................................333
17.3.5.1 Reset ...............................................................................................................333
17.3.5.2 User mode ......................................................................................................333
17.3.5.3 Low-power mode ...........................................................................................334
17.3.5.4 Power-down mode .........................................................................................335
17.3.6 Registers description ....................................................................................................336
17.3.7 Register map .................................................................................................................337
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17.3.7.1 Module Configuration Register (MCR) .........................................................339
17.3.7.2 Low/Mid Address Space Block Locking register (LML) ..............................344
17.3.7.3 Non-Volatile Low/Mid Address Space Block Locking register (NVLML) ...345
17.3.7.4 Secondary Low/Mid Address Space Block Locking register (SLL) .............346
17.3.7.5 Non-Volatile Secondary Low/Mid Address Space Block Locking register
(NVSLL) .........................................................................................................................347
17.3.7.6 Low/Mid Address Space Block Select register (LMS) ..................................349
17.3.7.7 Address Register (ADR) ................................................................................349
17.3.7.8 User Test 0 register (UT0) ..............................................................................357
17.3.7.9 User Test 1 register (UT1) ..............................................................................359
17.3.7.10 User Test 2 register (UT2) ..............................................................................360
17.3.7.11 User Multiple Input Signature Register 0 (UMISR0) ....................................360
17.3.7.12 User Multiple Input Signature Register 1 (UMISR1) ....................................361
17.3.7.13 User Multiple Input Signature Register 2 (UMISR2) ....................................362
17.3.7.14 User Multiple Input Signature Register 3 (UMISR3) ....................................362
17.3.7.15 User Multiple Input Signature Register 4 (UMISR4) ....................................363
17.3.7.16 Non-Volatile Private Censorship Password 0 register (NVPWD0) ...............364
17.3.7.17 Non-Volatile Private Censorship Password 1 register (NVPWD1) ...............364
17.3.7.18 Non-Volatile System Censoring Information 0 register (NVSCI0) ...............365
17.3.7.19 Non-Volatile System Censoring Information 1 register (NVSCI1) ...............366
17.3.7.20 Non-Volatile User Options register (NVUSRO) ............................................367
17.3.8 Code Flash programming considerations .....................................................................368
17.3.8.1 Modify operation ............................................................................................368
17.3.8.2 Error Correction Code (ECC) ........................................................................376
17.3.8.3 EEPROM emulation ......................................................................................376
17.3.8.4 Protection strategy ..........................................................................................377
Chapter 18
Enhanced Direct Memory Access (eDMA)
18.1 Introduction ...................................................................................................................................381
18.2 Overview .......................................................................................................................................381
18.3 Features .........................................................................................................................................382
18.4 Modes of operation ........................................................................................................................383
18.4.1 Normal mode ................................................................................................................383
18.4.2 Debug mode ..................................................................................................................383
18.5 Memory map and register definition .............................................................................................384
18.5.1 Memory map ................................................................................................................384
18.5.2 Register descriptions ....................................................................................................387
18.5.2.1 eDMA Control Register (EDMA_CR) ..........................................................387
18.5.2.2 eDMA Error Status Register (EDMA_ESR) .................................................388
18.5.2.3 eDMA Enable Request Register (EDMA_ERQRL) ......................................390
18.5.2.4 eDMA Enable Error Interrupt Register (EDMA_EEIRL) .............................391
18.5.2.5 eDMA Set Enable Request Register (EDMA_SERQR) ................................392
18.5.2.6 eDMA Clear Enable Request Register (EDMA_CERQR) ............................392
18.5.2.7 eDMA Set Enable Error Interrupt Register (EDMA_SEEIR) .......................393
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18.5.2.8 eDMA Clear Enable Error Interrupt Register (EDMA_CEEIR) ...................393
18.5.2.9 eDMA Clear Interrupt Request Register (EDMA_CIRQR) ..........................394
18.5.2.10 eDMA Clear Error Register (EDMA_CERR) ...............................................395
18.5.2.11 eDMA Set START Bit Register (EDMA_SSBR) ..........................................395
18.5.2.12 eDMA Clear DONE Status Bit Register (EDMA_CDSBR) .........................396
18.5.2.13 eDMA Interrupt Request Register (EDMA_IRQRL) ....................................396
18.5.2.14 eDMA Error Register (EDMA_ERL) ............................................................397
18.5.2.15 DMA Hardware Request Status (DMAHRSL) ..............................................398
18.5.2.16 eDMA Channel n Priority Registers (EDMA_CPRn) ...................................399
18.5.2.17 Transfer Control Descriptor (TCD) ...............................................................400
18.6 Functional description ...................................................................................................................407
18.6.1 eDMA microarchitecture ..............................................................................................407
18.6.2 eDMA basic data flow ..................................................................................................409
18.6.3 eDMA performance ......................................................................................................411
18.7 Initialization / application information ..........................................................................................414
18.7.1 eDMA initialization ......................................................................................................414
18.7.2 DMA programming errors ............................................................................................416
18.7.3 DMA request assignments ............................................................................................417
18.7.4 DMA arbitration mode considerations .........................................................................417
18.7.4.1 Fixed-channel arbitration ...............................................................................417
18.7.4.2 Fixed-group arbitration, round-robin channel arbitration ..............................417
18.7.5 DMA transfer ................................................................................................................418
18.7.5.1 Single request .................................................................................................418
18.7.5.2 Multiple requests ............................................................................................419
18.7.5.3 Modulo feature ...............................................................................................420
18.7.6 TCD status ....................................................................................................................421
18.7.6.1 Minor loop complete ......................................................................................421
18.7.6.2 Active channel TCD reads .............................................................................422
18.7.6.3 Preemption status ...........................................................................................422
18.7.7 Channel linking ............................................................................................................422
18.7.8 Dynamic programming .................................................................................................423
18.7.8.1 Dynamic channel linking and dynamic scatter/gather ...................................423
Chapter 19
DMA Channel Mux (DMA_MUX)
19.1 Introduction ...................................................................................................................................425
19.1.1 Overview ......................................................................................................................425
19.1.2 Features .........................................................................................................................425
19.1.3 Modes of operation .......................................................................................................426
19.2 External signal description ............................................................................................................426
19.2.1 Overview ......................................................................................................................426
19.3 Memory map and register definition .............................................................................................426
19.3.1 Memory map ................................................................................................................426
19.3.2 Register descriptions ....................................................................................................428
19.3.2.1 Channel Configuration Registers ...................................................................428
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19.4 DMA request mapping ..................................................................................................................429
19.5 Functional description ...................................................................................................................430
19.5.1 DMA channels with periodic triggering capability ......................................................430
19.5.2 DMA channels with no triggering capability ...............................................................433
19.6 Initialization/application information ............................................................................................433
19.6.1 Reset .............................................................................................................................433
19.6.2 Enabling and configuring sources ................................................................................433
Chapter 20
Deserial Serial Peripheral Interface (DSPI)
20.1 Introduction ...................................................................................................................................437
20.2 Block diagram ...............................................................................................................................437
20.3 Overview .......................................................................................................................................438
20.4 Features .........................................................................................................................................438
20.5 Modes of operation ........................................................................................................................439
20.5.1 Master mode .................................................................................................................439
20.5.2 Slave mode ...................................................................................................................439
20.5.3 Module disable mode ...................................................................................................440
20.5.4 Debug mode ..................................................................................................................440
20.6 External signal description ............................................................................................................440
20.6.1 Signal overview ............................................................................................................440
20.6.2 Signal names and descriptions ......................................................................................441
20.6.2.1 Peripheral Chip Select / Slave Select (CS_0) ................................................441
20.6.2.2 Peripheral Chip Selects 1–3 (CS1:3) .............................................................441
20.6.2.3 Peripheral Chip Select 4 (CS4) ......................................................................441
20.6.2.4 Peripheral Chip Select 5/Peripheral Chip Select Strobe (CS_5) ....................441
20.6.2.5 Serial Input (SIN_x) .......................................................................................441
20.6.2.6 Serial Output (SOUT_x) ................................................................................441
20.6.2.7 Serial Clock (SCK_x) .....................................................................................442
20.7 Memory map and registers description .........................................................................................442
20.7.1 Memory map ................................................................................................................442
20.7.2 Registers description ....................................................................................................443
20.7.2.1 DSPI Module Configuration Register (DSPIx_MCR) ...................................443
20.7.2.2 DSPI Transfer Count Register (DSPIx_TCR) ...............................................446
20.7.2.3 DSPI Clock and Transfer Attributes Registers 0–7 (DSPIx_CTARn) ...........447
20.7.2.4 DSPI Status Register (DSPIx_SR) .................................................................453
20.7.2.5 DSPI DMA / Interrupt Request Select and Enable Register
(DSPIx_RSER) ....................................................................................................................455
20.7.2.6 DSPI PUSH TX FIFO Register (DSPIx_PUSHR) ........................................456
20.7.2.7 DSPI POP RX FIFO Register (DSPIx_POPR) ..............................................458
20.7.2.8 DSPI Transmit FIFO Registers 0–4 (DSPIx_TXFRn) ...................................459
20.7.2.9 DSPI Receive FIFO Registers 0–4 (DSPIx_RXFRn) ....................................459
20.8 Functional description ...................................................................................................................460
20.8.1 Modes of operation .......................................................................................................461
20.8.1.1 Master mode ...................................................................................................461
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20.8.1.2 Slave mode .....................................................................................................462
20.8.1.3 Module disable mode .....................................................................................462
20.8.1.4 Debug mode ...................................................................................................462
20.8.2 Start and stop of DSPI transfers ...................................................................................462
20.8.3 Serial Peripheral Interface (SPI) configuration ............................................................463
20.8.3.1 SPI master mode ............................................................................................463
20.8.3.2 SPI slave mode ...............................................................................................464
20.8.3.3 FIFO disable operation ...................................................................................464
20.8.3.4 Transmit First In First Out (TX FIFO) buffering mechanism ........................464
20.8.3.5 Receive First In First Out (RX FIFO) buffering mechanism .........................465
20.8.4 DSPI baud rate and clock delay generation ..................................................................466
20.8.4.1 Baud rate generator ........................................................................................466
20.8.4.2 CS to SCK delay (tCSC) ..................................................................................467
20.8.4.3 After SCK delay (tASC) ..................................................................................467
20.8.4.4 Delay after transfer (tDT) ..............................................................................468
20.8.4.5 Peripheral Chip Select strobe enable (CS5_x) ...............................................468
20.8.5 Transfer formats ...........................................................................................................469
20.8.5.1 Classic SPI transfer format (CPHA = 0) ........................................................470
20.8.5.2 Classic SPI transfer format (CPHA = 1) ........................................................471
20.8.5.3 Modified SPI transfer format (MTFE = 1, CPHA = 0) ..................................472
20.8.5.4 Modified SPI transfer format (MTFE = 1, CPHA = 1) ..................................473
20.8.5.5 Continuous selection format ..........................................................................474
20.8.5.6 Clock polarity switching between DSPI transfers .........................................475
20.8.6 Continuous Serial communications clock ....................................................................476
20.8.7 Interrupts/DMA requests ..............................................................................................478
20.8.7.1 End of queue interrupt request (EOQF) .........................................................478
20.8.7.2 Transmit FIFO fill interrupt or DMA request (TFFF) ...................................478
20.8.7.3 Transfer complete interrupt request (TCF) ....................................................478
20.8.7.4 Transmit FIFO underflow interrupt request (TFUF) .....................................479
20.8.7.5 Receive FIFO drain interrupt or DMA request (RFDF) ................................479
20.8.7.6 Receive FIFO overflow interrupt request (RFOF) .........................................479
20.8.7.7 FIFO overrun request (TFUF) or (RFOF) ......................................................479
20.8.8 Power saving features ...................................................................................................479
20.8.8.1 Module disable mode .....................................................................................479
20.9 Initialization and application information .....................................................................................480
20.9.1 Managing queues ..........................................................................................................480
20.9.2 Baud rate settings .........................................................................................................480
20.9.3 Delay settings ...............................................................................................................482
20.9.4 MPC5602P DSPI compatibility with QSPI of the MPC500 MCUs ............................482
20.9.5 Calculation of FIFO pointer addresses .........................................................................483
20.9.5.1 Address calculation for first-in entry and last-in entry in TX FIFO ..............484
20.9.5.2 Address calculation for first-in entry and last-in entry in RX FIFO ..............484
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Chapter 21
LIN Controller (LINFlex)
21.1 Introduction ...................................................................................................................................487
21.2 Main features .................................................................................................................................487
21.2.1 LIN mode features ........................................................................................................487
21.2.2 UART mode features ....................................................................................................487
21.2.3 Features common to LIN and UART ...........................................................................487
21.3 General description .......................................................................................................................488
21.4 Fractional baud rate generation .....................................................................................................489
21.5 Operating modes ...........................................................................................................................491
21.5.1 Initialization mode ........................................................................................................492
21.5.2 Normal mode ................................................................................................................492
21.5.3 Low power mode (Sleep) .............................................................................................492
21.6 Test modes .....................................................................................................................................492
21.6.1 Loop Back mode ...........................................................................................................492
21.6.2 Self Test mode ..............................................................................................................493
21.7 Memory map and registers description .........................................................................................493
21.7.1 Memory map ................................................................................................................493
21.7.1.1 LIN control register 1 (LINCR1) ...................................................................495
21.7.1.2 LIN interrupt enable register (LINIER) .........................................................498
21.7.1.3 LIN status register (LINSR) ...........................................................................499
21.7.1.4 LIN error status register (LINESR) ...............................................................502
21.7.1.5 UART mode control register (UARTCR) ......................................................503
21.7.1.6 UART mode status register (UARTSR) .........................................................504
21.7.1.7 LIN timeout control status register (LINTCSR) ............................................506
21.7.1.8 LIN output compare register (LINOCR) .......................................................507
21.7.1.9 LIN timeout control register (LINTOCR) ......................................................508
21.7.1.10 LIN fractional baud rate register (LINFBRR) ...............................................508
21.7.1.11 LIN integer baud rate register (LINIBRR) ....................................................509
21.7.1.12 LIN checksum field register (LINCFR) .........................................................510
21.7.1.13 LIN control register 2 (LINCR2) ...................................................................510
21.7.1.14 Buffer identifier register (BIDR) ...................................................................511
21.7.1.15 Buffer data register LSB (BDRL) ..................................................................512
21.7.1.16 Buffer data register MSB (BDRM) ................................................................513
21.7.1.17 Identifier filter enable register (IFER) ...........................................................514
21.7.1.18 Identifier filter match index (IFMI) ...............................................................514
21.7.1.19 Identifier filter mode register (IFMR) ............................................................515
21.7.1.20 Identifier filter control register (IFCR2n) ......................................................516
21.7.1.21 Identifier filter control register (IFCR2n+ 1) ................................................517
21.8 Functional description ...................................................................................................................519
21.8.1 UART mode ..................................................................................................................519
21.8.1.1 Buffer in UART mode ....................................................................................519
21.8.1.2 UART transmitter ...........................................................................................520
21.8.1.3 UART receiver ...............................................................................................520
21.8.1.4 Clock gating ...................................................................................................521
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21.8.2 LIN mode ......................................................................................................................521
21.8.2.1 Master mode ...................................................................................................521
21.8.2.2 Slave mode .....................................................................................................523
21.8.2.3 Slave mode with identifier filtering ...............................................................525
21.8.2.4 Slave mode with automatic resynchronization ..............................................527
21.8.2.5 Clock gating ...................................................................................................529
21.8.3 8-bit timeout counter ....................................................................................................529
21.8.3.1 LIN timeout mode ..........................................................................................529
21.8.3.2 Output compare mode ....................................................................................530
21.8.4 Interrupts .......................................................................................................................531
Chapter 22
FlexCAN
22.1 Introduction ...................................................................................................................................533
22.1.1 Overview ......................................................................................................................533
22.1.2 FlexCAN module features ............................................................................................534
22.1.3 Modes of operation .......................................................................................................535
22.2 External signal description ............................................................................................................536
22.2.1 Overview ......................................................................................................................536
22.2.2 Signal Descriptions .......................................................................................................536
22.2.2.1 RXD ...............................................................................................................536
22.2.2.2 TXD ...............................................................................................................536
22.3 Memory map and registers description .........................................................................................536
22.3.1 FlexCAN memory mapping .........................................................................................536
22.3.2 Message buffer structure ..............................................................................................539
22.3.3 Rx FIFO structure .........................................................................................................542
22.3.4 Registers description ....................................................................................................544
22.3.4.1 Module Configuration Register (MCR) .........................................................544
22.3.4.2 Control Register (CTRL) ...............................................................................548
22.3.4.3 Free Running Timer (TIMER) .......................................................................551
22.3.4.4 Rx Global Mask register (RXGMASK) .........................................................552
22.3.4.5 Rx 14 Mask (RX14MASK) ...........................................................................552
22.3.4.6 Rx 15 Mask (RX15MASK) ...........................................................................553
22.3.4.7 Error Counter Register (ECR) ........................................................................554
22.3.4.8 Error and Status Register (ESR) ....................................................................555
22.3.4.9 Interrupt Masks 1 Register (IMASK1) ..........................................................558
22.3.4.10 Interrupt Flags 1 Register (IFLAG1) .............................................................558
22.3.4.11 Rx Individual Mask Registers (RXIMR0–RXIMR31) ..................................559
22.4 Functional description ...................................................................................................................562
22.4.1 Overview ......................................................................................................................562
22.4.2 Transmit process ...........................................................................................................562
22.4.3 Arbitration process .......................................................................................................563
22.4.4 Receive process ............................................................................................................564
22.4.5 Matching process ..........................................................................................................565
22.4.6 Data coherence .............................................................................................................566
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22.4.6.1 Transmission abort mechanism ......................................................................566
22.4.6.2 Message Buffer deactivation ..........................................................................567
22.4.6.3 Message Buffer lock mechanism ...................................................................568
22.4.7 Rx FIFO ........................................................................................................................569
22.4.8 CAN protocol related features ......................................................................................570
22.4.8.1 Remote frames ...............................................................................................570
22.4.8.2 Overload frames .............................................................................................570
22.4.8.3 Time stamp .....................................................................................................570
22.4.8.4 Protocol timing ...............................................................................................571
22.4.8.5 Arbitration and matching timing ....................................................................573
22.4.9 Modes of operation details ...........................................................................................574
22.4.9.1 Freeze mode ...................................................................................................574
22.4.9.2 Module disable mode .....................................................................................574
22.4.9.3 Stop mode .......................................................................................................575
22.4.10 Interrupts .......................................................................................................................575
22.4.11 Bus interface .................................................................................................................576
22.5 Initialization/application information ............................................................................................576
22.5.1 FlexCAN initialization sequence ..................................................................................576
Chapter 23
Analog-to-Digital Converter (ADC)
23.1 Overview .......................................................................................................................................579
23.1.1 Device-specific features ...............................................................................................579
23.1.2 Device-specific pin configuration features ...................................................................580
23.1.3 Device-specific implementation ...................................................................................580
23.2 Introduction ...................................................................................................................................580
23.3 Functional description ...................................................................................................................581
23.3.1 Analog channel conversion ..........................................................................................581
23.3.1.1 Normal conversion .........................................................................................581
23.3.1.2 Start of normal conversion .............................................................................581
23.3.1.3 Normal conversion operating modes .............................................................582
23.3.1.4 Injected channel conversion ...........................................................................583
23.3.1.5 Abort conversion ............................................................................................584
23.3.2 Analog clock generator and conversion timings ..........................................................584
23.3.3 ADC sampling and conversion timing .........................................................................585
23.3.3.1 ADC_0 ...........................................................................................................585
23.3.4 ADC CTU (Cross Triggering Unit) ..............................................................................587
23.3.4.1 Overview ........................................................................................................587
23.3.4.2 CTU in control mode .....................................................................................587
23.3.5 Programmable analog watchdog ..................................................................................588
23.3.5.1 Introduction ....................................................................................................588
23.3.5.2 Analog watchdog functionality ......................................................................589
23.3.6 DMA functionality .......................................................................................................589
23.3.7 Interrupts .......................................................................................................................589
23.3.8 Power-down mode ........................................................................................................590
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23.3.9 Auto-clock-off mode ....................................................................................................591
23.4 Register descriptions .....................................................................................................................591
23.4.1 Introduction ..................................................................................................................591
23.4.2 Control logic registers ..................................................................................................593
23.4.2.1 Main Configuration Register (MCR) .............................................................593
23.4.2.2 Main Status Register (MSR) ..........................................................................594
23.4.3 Interrupt registers ..........................................................................................................596
23.4.3.1 Interrupt Status Register (ISR) .......................................................................596
23.4.3.2 Interrupt Mask Register (IMR) ......................................................................596
23.4.3.3 Watchdog Threshold Interrupt Status Register (WTISR) ..............................598
23.4.3.4 Watchdog Threshold Interrupt Mask Register (WTIMR) ..............................599
23.4.4 DMA registers ..............................................................................................................600
23.4.4.1 DMA Enable (DMAE) register ......................................................................600
23.4.4.2 DMA Channel Select Register (DMAR[0]) ...................................................601
23.4.5 Threshold registers .......................................................................................................602
23.4.5.1 Introduction ....................................................................................................602
23.4.5.2 Threshold Control Register (TRCx, x = [0..3]) ..............................................602
23.4.5.3 Threshold Register (THRHLR[0:3]) ..............................................................603
23.4.6 Conversion Timing Registers CTR[0] ..........................................................................604
23.4.7 Mask registers ...............................................................................................................604
23.4.7.1 Introduction ....................................................................................................604
23.4.7.2 Normal Conversion Mask Registers (NCMR[0]) ..........................................604
23.4.7.3 Injected Conversion Mask Registers (JCMR[0]) ...........................................606
23.4.8 Delay registers ..............................................................................................................607
23.4.8.1 Power-Down Exit Delay Register (PDEDR) .................................................607
23.4.9 Data registers ................................................................................................................607
23.4.9.1 Introduction ....................................................................................................607
23.4.9.2 Channel Data Registers (CDR[0..15]) ...........................................................607
Chapter 24
Cross Triggering Unit (CTU)
24.1 Introduction ...................................................................................................................................609
24.2 CTU overview ...............................................................................................................................609
24.3 Functional description ...................................................................................................................610
24.3.1 Trigger events features .................................................................................................610
24.3.2 Trigger generator subunit (TGS) ..................................................................................611
24.3.3 TGS in triggered mode .................................................................................................611
24.3.4 TGS in sequential mode ...............................................................................................612
24.3.5 TGS counter ..................................................................................................................613
24.4 Scheduler subunit (SU) .................................................................................................................614
24.4.1 ADC commands list .....................................................................................................616
24.4.2 ADC commands list format ..........................................................................................616
24.4.3 ADC results ..................................................................................................................618
24.5 Reload mechanism ........................................................................................................................618
24.6 Power safety mode ........................................................................................................................620
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24.6.1 MDIS bit .......................................................................................................................620
24.6.2 STOP mode ..................................................................................................................620
24.7 Interrupts and DMA requests ........................................................................................................620
24.7.1 DMA support ................................................................................................................620
24.7.2 CTU faults and errors ...................................................................................................620
24.7.3 CTU interrupt/DMA requests .......................................................................................621
24.8 Memory map .................................................................................................................................623
24.8.1 Trigger Generator Sub-unit Input Selection Register (TGSISR) .................................627
24.8.2 Trigger Generator Sub-unit Control Register (TGSCR) ..............................................629
24.8.3 Trigger x Compare Register (TxCR, x= 0...7) .............................................................630
24.8.4 TGS Counter Compare Register (TGSCCR) ...............................................................630
24.8.5 TGS Counter Reload Register (TGSCRR) ...................................................................631
24.8.6 Commands list control register 1 (CLCR1) ..................................................................631
24.8.7 Commands list control register 2 (CLCR2) ..................................................................632
24.8.8 Trigger handler control register 1 (THCR1) .................................................................632
24.8.9 Trigger handler control register 2 (THCR2) .................................................................634
24.8.10 Commands list register x (x = 1,...,24) (CLRx) ............................................................636
24.8.11 FIFO DMA control register (FDCR) ............................................................................637
24.8.12 FIFO control register (FCR) .........................................................................................638
24.8.13 FIFO threshold register (FTH) .....................................................................................639
24.8.14 FIFO status register (FST) ............................................................................................640
24.8.15 FIFO Right aligned data x (x= 0,...,3) (FRx) ...............................................................641
24.8.16 FIFO signed Left aligned data x (x= 0,...,3) (FLx) ......................................................642
24.8.17 Cross triggering unit error flag register (CTUEFR) .....................................................642
24.8.18 Cross triggering unit interrupt flag register (CTUIFR) ................................................643
24.8.19 Cross triggering unit interrupt/DMA register (CTUIR) ...............................................644
24.8.20 Control ON time register (COTR) ................................................................................645
24.8.21 Cross triggering unit control register (CTUCR) ...........................................................647
24.8.22 Cross triggering unit digital filter (CTUDF) ................................................................648
24.8.23 Cross triggering unit power control register (CTUPCR) .............................................648
Chapter 25
FlexPWM
25.1 Overview .......................................................................................................................................649
25.2 Features .........................................................................................................................................649
25.3 Modes of operation ........................................................................................................................650
25.4 Block diagrams ..............................................................................................................................651
25.4.1 Module level .................................................................................................................651
25.4.2 PWM submodule ..........................................................................................................652
25.5 External signal descriptions ..........................................................................................................653
25.5.1 PWMA[n] and PWMB[n] — external PWM pair ........................................................653
25.5.2 PWMX[n] — auxiliary PWM signal ............................................................................653
25.5.3 FAULT[n] — fault inputs .............................................................................................653
25.5.4 EXT_SYNC — external synchronization signal ..........................................................653
25.5.5 EXT_FORCE — external output force signal ..............................................................653
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25.5.6 OUT_TRIG0[n] and OUT_TRIG1[n] — output triggers ............................................653
25.5.7 EXT_CLK — external clock signal .............................................................................653
25.6 Memory map and registers ............................................................................................................654
25.6.1 FlexPWM module memory map ..................................................................................654
25.6.2 Register descriptions ....................................................................................................657
25.6.3 Submodule registers .....................................................................................................657
25.6.3.1 Counter Register (CNT) .................................................................................657
25.6.3.2 Initial Count Register (INIT) .........................................................................657
25.6.3.3 Control 2 Register (CTRL2) ..........................................................................658
25.6.3.4 Control 1 Register (CTRL1) ..........................................................................660
25.6.3.5 Value register 0 (VAL0) .................................................................................662
25.6.3.6 Value register 1 (VAL1) .................................................................................663
25.6.3.7 Value register 2 (VAL2) .................................................................................663
25.6.3.8 Value register 3 (VAL3) .................................................................................664
25.6.3.9 Value register 4 (VAL4) .................................................................................664
25.6.3.10 Value register 5 (VAL5) .................................................................................665
25.6.3.11 Output Control register (OCTRL) ..................................................................665
25.6.3.12 Status register (STS) ......................................................................................666
25.6.3.13 Interrupt Enable register (INTEN) .................................................................667
25.6.3.14 DMA Enable register (DMAEN) ...................................................................668
25.6.3.15 Output Trigger Control register (TCTRL) .....................................................669
25.6.3.16 Fault Disable Mapping register (DISMAP) ...................................................670
25.6.3.17 Deadtime Count registers (DTCNT0, DTCNT1) ..........................................670
25.6.4 Configuration registers .................................................................................................671
25.6.4.1 Output Enable register (OUTEN) ..................................................................671
25.6.4.2 Mask register (MASK) ...................................................................................672
25.6.4.3 Software Controlled Output Register (SWCOUT) ........................................673
25.6.4.4 Deadtime Source Select Register (DTSRCSEL) ...........................................674
25.6.4.5 Master Control Register (MCTRL) ................................................................676
25.6.5 Fault channel registers ..................................................................................................677
25.6.5.1 Fault Control Register (FCTRL) ....................................................................677
25.6.5.2 Fault Status Register (FSTS) ..........................................................................678
25.6.5.3 Fault Filter Register (FFILT) .........................................................................679
25.6.5.4 Input filter considerations ..............................................................................679
25.7 Functional description ...................................................................................................................681
25.7.1 Center-aligned PWMs ..................................................................................................681
25.7.2 Edge-aligned PWMs .....................................................................................................682
25.7.3 Phase-shifted PWMs ....................................................................................................682
25.7.4 Double switching PWMs ..............................................................................................684
25.7.5 ADC triggering .............................................................................................................685
25.7.6 Synchronous switching of multiple outputs .................................................................687
25.8 Functional details ..........................................................................................................................688
25.8.1 PWM clocking ..............................................................................................................688
25.8.2 Register reload logic .....................................................................................................689
25.8.3 Counter synchronization ...............................................................................................690
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26 Freescale Semiconductor
25.8.4 PWM generation ...........................................................................................................691
25.8.5 Output compare capabilities .........................................................................................692
25.8.6 Force out logic ..............................................................................................................692
25.8.7 Independent or complementary channel operation .......................................................694
25.8.8 Deadtime insertion logic ...............................................................................................695
25.8.9 Top/bottom correction ..................................................................................................696
25.8.10 Manual correction .........................................................................................................698
25.8.11 Output logic ..................................................................................................................699
25.8.12 Fault protection .............................................................................................................700
25.8.13 Fault pin filter ...............................................................................................................701
25.8.14 Automatic fault clearing ...............................................................................................702
25.8.15 Manual fault clearing ....................................................................................................702
25.8.16 Fault testing ..................................................................................................................703
25.9 PWM generator loading ................................................................................................................703
25.9.1 Load enable ..................................................................................................................703
25.9.2 Load frequency .............................................................................................................704
25.9.3 Reload flag ....................................................................................................................705
25.9.4 Reload errors ................................................................................................................705
25.9.5 Initialization ..................................................................................................................705
25.10 Clocks ............................................................................................................................................706
25.11 Interrupts .......................................................................................................................................706
25.12 DMA ..............................................................................................................................................706
Chapter 26
eTimer
26.1 Introduction ...................................................................................................................................709
26.2 Features .........................................................................................................................................709
26.3 Module block diagram ..................................................................................................................711
26.4 Channel block diagram ..................................................................................................................712
26.5 External signal descriptions ..........................................................................................................712
26.5.1 ETC[5:0]—eTimer input/outputs .................................................................................712
26.6 Memory map and registers ............................................................................................................712
26.6.1 Overview ......................................................................................................................712
26.6.2 Timer channel registers ................................................................................................716
26.6.2.1 Compare register 1 (COMP1) ........................................................................716
26.6.2.2 Compare register 2 (COMP2) ........................................................................717
26.6.2.3 Capture register 1 (CAPT1) ...........................................................................717
26.6.2.4 Capture register 2 (CAPT2) ...........................................................................718
26.6.2.5 Load register (LOAD) ....................................................................................718
26.6.2.6 Hold register (HOLD) ....................................................................................719
26.6.2.7 Counter register (CNTR) ...............................................................................719
26.6.2.8 Control register 1 (CTRL1) ............................................................................720
26.6.2.9 Control register 2 (CTRL2) ............................................................................722
26.6.2.10 Control register 3 (CTRL3) ............................................................................724
26.6.2.11 Status register (STS) ......................................................................................725
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26.6.2.12 Interrupt and DMA enable register (INTDMA) ............................................726
26.6.2.13 Comparator Load register 1 (CMPLD1) ........................................................727
26.6.2.14 Comparator Load register 2 (CMPLD2) ........................................................728
26.6.2.15 Compare and Capture Control register (CCCTRL) .......................................728
26.6.2.16 Input Filter Register (FILT) ...........................................................................730
26.6.2.17 Input filter considerations ..............................................................................731
26.6.3 Watchdog timer registers ..............................................................................................731
26.6.3.1 Watchdog Time-Out registers (WDTOL and WDTOH) ................................731
26.6.4 Configuration registers .................................................................................................732
26.6.4.1 Channel Enable register (ENBL) ...................................................................732
26.6.4.2 DMA Request Select registers (DREQ0, DREQ1) ........................................732
26.7 Functional description ...................................................................................................................733
26.7.1 General .........................................................................................................................733
26.7.2 Counting modes ............................................................................................................734
26.7.2.1 STOP mode ....................................................................................................734
26.7.2.2 COUNT mode ................................................................................................734
26.7.2.3 EDGE-COUNT mode ....................................................................................735
26.7.2.4 GATED-COUNT mode ..................................................................................735
26.7.2.5 QUADRATURE-COUNT mode ....................................................................735
26.7.2.6 SIGNED-COUNT mode ................................................................................735
26.7.2.7 TRIGGERED-COUNT mode ........................................................................735
26.7.2.8 ONE-SHOT mode ..........................................................................................736
26.7.2.9 CASCADE-COUNT mode ............................................................................736
26.7.2.10 PULSE-OUTPUT mode ................................................................................737
26.7.2.11 FIXED-FREQUENCY PWM mode ..............................................................737
26.7.2.12 VARIABLE-FREQUENCY PWM mode ......................................................737
26.7.2.13 Usage of compare registers ............................................................................738
26.7.2.14 Usage of Compare Load registers ..................................................................738
26.7.2.15 MODULO COUNTING mode ......................................................................739
26.7.3 Other features ...............................................................................................................739
26.7.3.1 Redundant OFLAG checking .........................................................................739
26.7.3.2 Loopback checking ........................................................................................739
26.7.3.3 Input capture mode .........................................................................................739
26.7.3.4 Master/Slave mode .........................................................................................740
26.7.3.5 Watchdog timer ..............................................................................................740
26.8 Clocks ............................................................................................................................................740
26.9 Interrupts .......................................................................................................................................741
26.10 DMA ..............................................................................................................................................741
Chapter 27
Functional Safety
27.1 Introduction ...................................................................................................................................743
27.2 Register protection module ...........................................................................................................743
27.2.1 Overview ......................................................................................................................743
27.2.2 Features .........................................................................................................................743