SPC5602PEF0VLL6 - Freescale Semiconductor

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 1

Qorivva MPC5602P Microcontroller

Reference Manual

Devices Supported:

MPC5601P

MPC5602P

MPC5602PRM

Rev. 4

28 Feb 2012

MPC5602P Microcontroller Reference Manual, Rev. 4

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MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 3

Preface

Overview

The primary objective of this document is to define the functionality of the MPC5602P family of

microcontrollers for use by software and hardware developers. The MPC5602P family is built on

Power Architecture® technology and integrates technologies that are important for today’s electrical

hydraulic power steering (EHPS), electric power steering (EPS), airbag applications, anti-lock braking

systems (ABS), and motor control applications.

As with any technical documentation, it is the reader’s responsibility to be sure he or she is using the most

recent version of the documentation.

To locate any published errata or updates for this document, visit the Freescale Web site at

http://www.freescale.com/.

Audience

This manual is intended for system software and hardware developers and applications programmers who

want to develop products with the MPC5602P device. It is assumed that the reader understands operating

systems, microprocessor system design, basic principles of software and hardware, and basic details of the

Power Architecture.

Chapter organization and device-specific information

This document includes chapters that describe:

• The device as a whole

• The functionality of the individual modules on the device

In the latter, any device-specific information is presented in the section “Information Specific to This

Device” at the beginning of the chapter.

References

In addition to this reference manual, the following documents provide additional information on the

operation of the MPC5602P:

• IEEE-ISTO 5001™ - 2003 and 2010, The Nexus 5001™ Forum Standard for a Global Embedded

Processor Debug Interface

• IEEE 1149.1-2001 standard - IEEE Standard Test Access Port and Boundary-Scan Architecture

• Power Architecture Book E V1.0

(http://www.freescale.com/files/32bit/doc/user_guide/BOOK_EUM.pdf)

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Chapter 1

Introduction

1.1 The MPC5602P microcontroller family ..........................................................................................35

1.2 Target applications ..........................................................................................................................36

1.2.1 Application examples .....................................................................................................36

1.2.1.1 Electric power steering .....................................................................................36

1.2.1.2 Airbag ...............................................................................................................37

1.3 Features ...........................................................................................................................................38

1.4 Critical performance parameters .....................................................................................................41

1.5 Chip-level features ..........................................................................................................................41

1.6 Module features ...............................................................................................................................43

1.6.1 High performance e200z0 core processor ......................................................................43

1.6.2 Crossbar switch (XBAR) ................................................................................................43

1.6.3 Enhanced direct memory access (eDMA) ......................................................................44

1.6.4 Flash memory .................................................................................................................44

1.6.5 Static random access memory (SRAM) .........................................................................45

1.6.6 Interrupt controller (INTC) .............................................................................................46

1.6.7 System status and configuration module (SSCM) ..........................................................46

1.6.8 System clocks and clock generation ...............................................................................47

1.6.9 Frequency-modulated phase-locked loop (FMPLL) ......................................................47

1.6.10 Main oscillator ................................................................................................................47

1.6.11 Internal RC oscillator .....................................................................................................47

1.6.12 Periodic interrupt timer (PIT) .........................................................................................48

1.6.13 System timer module (STM) ..........................................................................................48

1.6.14 Software watchdog timer (SWT) ....................................................................................48

1.6.15 Fault collection unit (FCU) ............................................................................................48

1.6.16 System integration unit – Lite (SIUL) ............................................................................49

1.6.17 Boot and censorship .......................................................................................................49

1.6.17.1 Boot assist module (BAM) ..............................................................................49

1.6.18 Error correction status module (ECSM) .........................................................................50

1.6.19 Peripheral bridge (PBRIDGE) ........................................................................................50

1.6.20 Controller area network (FlexCAN) ...............................................................................50

1.6.21 Safety port (FlexCAN) ...................................................................................................51

1.6.22 Serial communication interface module (LINFlex) .......................................................51

1.6.23 Deserial serial peripheral interface (DSPI) .....................................................................52

1.6.24 Pulse width modulator (FlexPWM) ................................................................................53

1.6.25 eTimer .............................................................................................................................54

1.6.26 Analog-to-digital converter (ADC) module ...................................................................54

1.6.27 Cross triggering unit (CTU) ...........................................................................................55

1.6.28 Nexus Development Interface (NDI) .............................................................................56

1.6.29 Cyclic redundancy check (CRC) ....................................................................................56

1.6.30 IEEE 1149.1 JTAG controller .........................................................................................56

1.6.31 On-chip voltage regulator (VREG) ................................................................................57

1.7 Developer environment ...................................................................................................................57

1.8 Package ............................................................................................................................................57

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Chapter 2

MPC5602P Memory Map

Chapter 3

Signal Description

3.1 100-pin LQFP pinout ......................................................................................................................63

3.2 64-pin LQFP pinout ........................................................................................................................64

3.3 Pin description .................................................................................................................................64

3.3.1 Power supply and reference voltage pins .......................................................................64

3.3.2 System pins .....................................................................................................................66

3.3.3 Pin multiplexing .............................................................................................................66

3.4 CTU / ADC / FlexPWM / eTimer connections ..............................................................................75

Chapter 4

Clock Description

4.1 Clock architecture ...........................................................................................................................79

4.2 Available clock domains .................................................................................................................82

4.2.1 FMPLL input reference clock ........................................................................................82

4.2.2 Clock selectors ................................................................................................................82

4.2.2.1 System clock selector 0 for SYS_CLK ............................................................82

4.2.3 Auxiliary Clock Selector 0 .............................................................................................83

4.2.4 Auxiliary Clock Selector 1 .............................................................................................83

4.2.5 Auxiliary Clock Selector 2 .............................................................................................83

4.2.6 Auxiliary clock dividers .................................................................................................83

4.2.7 External clock divider .....................................................................................................83

4.3 Alternate module clock domains .....................................................................................................84

4.3.1 FlexCAN clock domains ................................................................................................84

4.3.2 SWT clock domains .......................................................................................................84

4.3.3 Cross Triggering Unit (CTU) clock domains .................................................................84

4.3.4 Peripherals behind the IPS bus clock sync bridge ..........................................................84

4.3.4.1 FlexPWM clock domain ..................................................................................84

4.3.4.2 eTimer_0 clock domain ....................................................................................84

4.3.4.3 ADC_0 clock domain .......................................................................................85

4.3.4.4 Safety Port clock domains ................................................................................85

4.4 Clock behavior in STOP and HALT mode ......................................................................................85

4.5 System clock functional safety ........................................................................................................85

4.6 IRC 16 MHz internal RC oscillator (RC_CTL) ..............................................................................86

4.7 XOSC external crystal oscillator .....................................................................................................87

4.7.1 Functional description ....................................................................................................87

4.7.2 Register description ........................................................................................................88

4.8 Frequency Modulated Phase Locked Loop (FMPLL) ....................................................................89

4.8.1 Introduction ....................................................................................................................89

4.8.2 Overview ........................................................................................................................89

4.8.3 Features ...........................................................................................................................89

4.8.4 Memory map ..................................................................................................................90

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4.8.5 Register description ........................................................................................................90

4.8.5.1 Control Register (CR) ......................................................................................90

4.8.5.2 Modulation Register (MR) ...............................................................................92

4.8.6 Functional description ....................................................................................................93

4.8.6.1 Normal mode ....................................................................................................93

4.8.6.2 Progressive clock switching .............................................................................93

4.8.6.3 Normal Mode with frequency modulation .......................................................94

4.8.6.4 Powerdown mode .............................................................................................96

4.8.7 Recommendations ..........................................................................................................96

4.9 Clock Monitor Unit (CMU) ............................................................................................................96

4.9.1 Overview ........................................................................................................................96

4.9.2 Main features ..................................................................................................................97

4.9.3 Functional description ....................................................................................................97

4.9.3.1 Crystal clock monitor .......................................................................................97

4.9.3.2 PLL clock monitor ...........................................................................................98

4.9.3.3 System clock monitor .......................................................................................98

4.9.3.4 Frequency meter ...............................................................................................99

4.9.4 Memory map and register description ............................................................................99

4.9.4.1 Control Status Register (CMU_0_CSR) ........................................................100

4.9.4.2 Frequency Display Register (CMU_0_FDR) ................................................101

4.9.4.3 High Frequency Reference Register FMPLL_0 (CMU_0_HFREFR_A) ......101

4.9.4.4 Low Frequency Reference Register FMPLL_0 (CMU_0_LFREFR_A) .......102

4.9.4.5 Interrupt Status Register (CMU_0_ISR) ........................................................102

4.9.4.6 Measurement Duration Register (CMU_0_MDR) ........................................103

Chapter 5

Clock Generation Module (MC_CGM)

5.1 Overview .......................................................................................................................................105

5.2 Features .........................................................................................................................................106

5.3 External Signal Description ..........................................................................................................107

5.4 Memory Map and Register Definition ..........................................................................................107

5.5 Register Descriptions ....................................................................................................................112

5.5.1 Output Clock Enable Register (CGM_OC_EN) ..........................................................112

5.5.2 Output Clock Division Select Register (CGM_OCDS_SC) ........................................113

5.5.3 System Clock Select Status Register (CGM_SC_SS) ..................................................114

5.5.4 System Clock Divider Configuration Register (CGM_SC_DC0) ................................114

5.5.5 Auxiliary Clock 0 Select Control Register (CGM_AC0_SC) ......................................115

5.5.6 Auxiliary Clock 0 Divider Configuration Register (CGM_AC0_DC0) ......................116

5.5.7 Auxiliary Clock 1 Select Control Register (CGM_AC1_SC) ......................................116

5.5.8 Auxiliary Clock 1 Divider Configuration Register (CGM_AC1_DC0) ......................117

5.5.9 Auxiliary Clock 2 Select Control Register (CGM_AC2_SC) ......................................118

5.5.10 Auxiliary Clock 2 Divider Configuration Register (CGM_AC2_DC0) ......................119

5.6 Functional Description ..................................................................................................................119

5.7 System Clock Generation ..............................................................................................................119

5.7.1 System Clock Source Selection ....................................................................................120

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5.7.2 System Clock Disable ...................................................................................................120

5.7.3 System Clock Dividers .................................................................................................120

5.8 Auxiliary Clock Generation ..........................................................................................................120

5.8.1 Auxiliary Clock Source Selection ................................................................................123

5.8.2 Auxiliary Clock Dividers .............................................................................................123

5.9 Dividers Functional Description ...................................................................................................123

5.10 Output Clock Multiplexing ...........................................................................................................124

5.11 Output Clock Division Selection ...................................................................................................124

Chapter 6

Power Control Unit (MC_PCU)

6.1 Introduction ...................................................................................................................................125

6.1.1 Overview ......................................................................................................................125

6.1.2 Features .........................................................................................................................126

6.2 External Signal Description ..........................................................................................................126

6.3 Memory Map and Register Definition ..........................................................................................126

6.3.1 Memory Map ................................................................................................................126

6.3.2 Register Descriptions ....................................................................................................127

6.3.2.1 Power Domain Status Register (PCU_PSTAT) ..............................................127

Chapter 7

Mode Entry Module (MC_ME)

7.1 Introduction ...................................................................................................................................129

7.1.1 Overview ......................................................................................................................129

7.1.2 Features .........................................................................................................................131

7.1.3 Modes of Operation ......................................................................................................131

7.2 External Signal Description ..........................................................................................................132

7.3 Memory Map and Register Definition ..........................................................................................132

7.3.1 Memory Map ................................................................................................................133

7.3.2 Register Description .....................................................................................................140

7.3.2.1 Global Status Register (ME_GS) ...................................................................140

7.3.2.2 Mode Control Register (ME_MCTL) ............................................................142

7.3.2.3 Mode Enable Register (ME_ME) ..................................................................143

7.3.2.4 Interrupt Status Register (ME_IS) .................................................................144

7.3.2.5 Interrupt Mask Register (ME_IM) .................................................................145

7.3.2.6 Invalid Mode Transition Status Register (ME_IMTS) ..................................146

7.3.2.7 Debug Mode Transition Status Register (ME_DMTS) ..................................147

7.3.2.8 RESET Mode Configuration Register (ME_RESET_MC) ...........................150

7.3.2.9 TEST Mode Configuration Register (ME_TEST_MC) .................................150

7.3.2.10 SAFE Mode Configuration Register (ME_SAFE_MC) ................................151

7.3.2.11 DRUN Mode Configuration Register (ME_DRUN_MC) .............................151

7.3.2.12 RUN0…3 Mode Configuration Registers (ME_RUN0…3_MC) .................152

7.3.2.13 HALT0 Mode Configuration Register (ME_HALT0_MC) ...........................152

7.3.2.14 STOP0 Mode Configuration Register (ME_STOP0_MC) ............................153

7.3.2.15 Peripheral Status Register 0 (ME_PS0) .........................................................155

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7.3.2.16 Peripheral Status Register 1 (ME_PS1) .........................................................155

7.3.2.17 Peripheral Status Register 2 (ME_PS2) .........................................................156

7.3.2.18 Run Peripheral Configuration Registers (ME_RUN_PC0…7) .....................156

7.3.2.19 Low-Power Peripheral Configuration Registers (ME_LP_PC0…7) .............157

7.3.2.20 Peripheral Control Registers (ME_PCTL0…143) .........................................158

7.4 Functional Description ..................................................................................................................159

7.4.1 Mode Transition Request ..............................................................................................159

7.4.2 Modes Details ...............................................................................................................160

7.4.2.1 RESET Mode .................................................................................................160

7.4.2.2 DRUN Mode ..................................................................................................161

7.4.2.3 SAFE Mode ....................................................................................................161

7.4.2.4 TEST Mode ....................................................................................................162

7.4.2.5 RUN0…3 Modes ...........................................................................................162

7.4.2.6 HALT0 Mode .................................................................................................163

7.4.2.7 STOP0 Mode ..................................................................................................163

7.4.3 Mode Transition Process ..............................................................................................164

7.4.3.1 Target Mode Request .....................................................................................164

7.4.3.2 Target Mode Configuration Loading .............................................................164

7.4.3.3 Peripheral Clocks Disable ..............................................................................165

7.4.3.4 Processor Low-Power Mode Entry ................................................................166

7.4.3.5 Processor and System Memory Clock Disable ..............................................166

7.4.3.6 Clock Sources Switch-On ..............................................................................166

7.4.3.7 Flash Modules Switch-On ..............................................................................167

7.4.3.8 Pad Outputs-On ..............................................................................................167

7.4.3.9 Peripheral Clocks Enable ...............................................................................167

7.4.3.10 Processor and Memory Clock Enable ............................................................167

7.4.3.11 Processor Low-Power Mode Exit ..................................................................167

7.4.3.12 System Clock Switching ................................................................................167

7.4.3.13 Pad Switch-Off ...............................................................................................168

7.4.3.14 Clock Sources (with no Dependencies) Switch-Off ......................................169

7.4.3.15 Clock Sources (with Dependencies) Switch-Off ...........................................169

7.4.3.16 Flash Switch-Off ............................................................................................169

7.4.3.17 Current Mode Update .....................................................................................169

7.4.4 Protection of Mode Configuration Registers ................................................................172

7.4.5 Mode Transition Interrupts ...........................................................................................172

7.4.5.1 Invalid Mode Configuration Interrupt ............................................................172

7.4.5.2 Invalid Mode Transition Interrupt ..................................................................172

7.4.5.3 SAFE Mode Transition Interrupt ...................................................................174

7.4.5.4 Mode Transition Complete Interrupt .............................................................174

7.4.6 Peripheral Clock Gating ...............................................................................................174

7.4.7 Application Example ....................................................................................................175

Chapter 8

Reset Generation Module (MC_RGM)

8.1 Introduction ...................................................................................................................................177

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8.1.1 Overview ......................................................................................................................177

8.1.2 Features .........................................................................................................................178

8.1.3 Reset Sources ................................................................................................................179

8.2 External Signal Description ..........................................................................................................180

8.3 Memory Map and Register Definition ..........................................................................................180

8.3.1 Register Descriptions ....................................................................................................182

8.3.1.1 Functional Event Status Register (RGM_FES) ..............................................182

8.3.1.2 Destructive Event Status Register (RGM_DES) ............................................184

8.3.1.3 Functional Event Reset Disable Register (RGM_FERD) ..............................185

8.3.1.4 Destructive Event Reset Disable Register (RGM_DERD) ............................186

8.3.1.5 Functional Event Alternate Request Register (RGM_FEAR) .......................187

8.3.1.6 Functional Event Short Sequence Register (RGM_FESS) ............................188

8.3.1.7 Functional Bidirectional Reset Enable Register (RGM_FBRE) ....................190

8.4 Functional Description ..................................................................................................................191

8.4.1 Reset State Machine .....................................................................................................191

8.4.1.1 PHASE0 Phase ...............................................................................................192

8.4.1.2 PHASE1 Phase ...............................................................................................193

8.4.1.3 PHASE2 Phase ...............................................................................................193

8.4.1.4 PHASE3 Phase ...............................................................................................193

8.4.1.5 IDLE Phase ....................................................................................................193

8.4.2 Destructive Resets ........................................................................................................194

8.4.3 External Reset ...............................................................................................................194

8.4.4 Functional Resets ..........................................................................................................195

8.4.5 Alternate Event Generation ..........................................................................................195

8.4.6 Boot Mode Capturing ...................................................................................................196

Chapter 9

Interrupt Controller (INTC)

9.1 Introduction ...................................................................................................................................197

9.2 Features .........................................................................................................................................197

9.3 Block diagram ...............................................................................................................................199

9.4 Modes of operation ........................................................................................................................199

9.4.1 Normal mode ................................................................................................................199

9.4.1.1 Software vector mode ....................................................................................199

9.4.1.2 Hardware vector mode ...................................................................................200

9.4.1.3 Debug mode ...................................................................................................200

9.4.1.4 Stop mode .......................................................................................................200

9.5 Memory map and registers description .........................................................................................201

9.5.1 Module memory map ...................................................................................................201

9.5.2 Registers description ....................................................................................................201

9.5.2.1 INTC Module Configuration Register (INTC_MCR) ...................................202

9.5.2.2 INTC Current Priority Register (INTC_CPR) ...............................................203

9.5.2.3 INTC Interrupt Acknowledge Register(INTC_IACKR) ...............................204

9.5.2.4 INTC End-of-Interrupt Register (INTC_EOIR) ............................................205

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9.5.2.5 INTC Software Set/Clear Interrupt Registers

(INTC_SSCIR0_3–INTC_SSCIR4_7) ................................................................................205

9.5.2.6 INTC Priority Select Registers (INTC_PSR0_3–INTC_PSR220_221) ........206

9.6 Functional description ...................................................................................................................209

9.6.1 Interrupt request sources ...............................................................................................217

9.6.1.1 Peripheral interrupt requests ..........................................................................217

9.6.1.2 Software configurable interrupt requests .......................................................218

9.6.1.3 Unique vector for each interrupt request source ............................................218

9.6.2 Priority management ....................................................................................................218

9.6.2.1 Current priority and preemption ....................................................................218

9.6.2.2 Last-in first-out (LIFO) ..................................................................................219

9.6.3 Handshaking with processor .........................................................................................219

9.6.3.1 Software vector mode handshaking ...............................................................219

9.6.3.2 Hardware vector mode handshaking ..............................................................221

9.7 Initialization/application information ............................................................................................221

9.7.1 Initialization flow .........................................................................................................221

9.7.2 Interrupt exception handler ...........................................................................................222

9.7.2.1 Software vector mode ....................................................................................222

9.7.2.2 Hardware vector mode ...................................................................................223

9.7.3 ISR, RTOS, and task hierarchy .....................................................................................223

9.7.4 Order of execution ........................................................................................................224

9.7.5 Priority ceiling protocol ................................................................................................225

9.7.5.1 Elevating priority ...........................................................................................225

9.7.5.2 Ensuring coherency ........................................................................................225

9.7.6 Selecting priorities according to request rates and deadlines .......................................226

9.7.7 Software configurable interrupt requests ......................................................................226

9.7.7.1 Scheduling a lower priority portion of an ISR ...............................................226

9.7.7.2 Scheduling an ISR on another processor .......................................................227

9.7.8 Lowering priority within an ISR ..................................................................................227

9.7.9 Negating an interrupt request outside of its ISR ..........................................................228

9.7.9.1 Negating an interrupt request as a side effect of an ISR ................................228

9.7.9.2 Negating multiple interrupt requests in one ISR ............................................228

9.7.9.3 Proper setting of interrupt request priority .....................................................228

9.7.10 Examining LIFO contents ............................................................................................228

Chapter 10

System Status and Configuration Module (SSCM)

10.1 Introduction ...................................................................................................................................229

10.1.1 Overview ......................................................................................................................229

10.1.2 Features .........................................................................................................................229

10.1.3 Modes of operation .......................................................................................................230

10.2 Memory map and register description ...........................................................................................230

10.2.1 Memory map ................................................................................................................230

10.2.2 Register description ......................................................................................................230

10.2.2.1 System Status register (STATUS) ..................................................................231

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10.2.2.2 System Memory Configuration register (MEMCONFIG) .............................232

10.2.2.3 Error Configuration (ERROR) register ..........................................................233

10.2.2.4 Debug Status Port (DEBUGPORT) register ..................................................233

10.2.2.5 Password comparison registers ......................................................................236

10.3 Functional description ...................................................................................................................237

10.4 Initialization/application information ............................................................................................237

10.4.1 Reset .............................................................................................................................237

Chapter 11

System Integration Unit Lite (SIUL)

11.1 Introduction ...................................................................................................................................239

11.2 Overview .......................................................................................................................................239

11.3 Features .........................................................................................................................................240

11.3.1 Register protection ........................................................................................................241

11.4 External signal description ............................................................................................................241

11.4.1 Detailed signal descriptions ..........................................................................................241

11.4.1.1 General-purpose I/O pins (GPIO[0:66]) ........................................................241

11.4.1.2 External interrupt request input pins (EIRQ[0:24]) .......................................241

11.5 Memory map and register description ...........................................................................................242

11.5.1 SIUL memory map .......................................................................................................242

11.5.2 Register description ......................................................................................................243

11.5.2.1 MCU ID Register #1 (MIDR1) ......................................................................243

11.5.2.2 MCU ID Register #2 (MIDR2) ......................................................................245

11.5.2.3 Interrupt Status Flag Register (ISR) ...............................................................246

11.5.2.4 Interrupt Request Enable Register (IRER) .....................................................246

11.5.2.5 Interrupt Rising-Edge Event Enable Register (IREER) .................................247

11.5.2.6 Interrupt Falling-Edge Event Enable Register (IFEER) ................................247

11.5.2.7 Interrupt Filter Enable Register (IFER) .........................................................248

11.5.2.8 Pad Configuration Registers (PCR[0:71]) .....................................................248

11.5.2.9 Pad Selection for Multiplexed Inputs registers (PSMI[0_3:32_35]) .............250

11.5.2.10 GPIO Pad Data Output registers 0_3–68_71 (GPDO[0_3:68_71]) ...............254

11.5.2.11 GPIO Pad Data Input registers 0_3–68_71 (GPDI[0_3:68_71]) ...................254

11.5.2.12 Parallel GPIO Pad Data Out register 0–3 (PGPDO[0:3]) ..............................255

11.5.2.13 Parallel GPIO Pad Data In register 0–3 (PGPDI[0:3]) ..................................255

11.5.2.14 Masked Parallel GPIO Pad Data Out register 0–6 (MPGPDO[0:6]) .............256

11.5.2.15 Interrupt Filter Maximum Counter registers 0–24 (IFMC[0:24]) ..................257

11.5.2.16 Interrupt Filter Clock Prescaler Register (IFCPR) .........................................257

11.6 Functional description ...................................................................................................................259

11.6.1 General .........................................................................................................................259

11.6.2 Pad control ....................................................................................................................259

11.6.3 General purpose input and output pads (GPIO) ...........................................................259

11.6.4 External interrupts ........................................................................................................260

11.6.4.1 External interrupt management ......................................................................261

11.7 Pin muxing ....................................................................................................................................261

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Chapter 12

e200z0 and e200z0h Core

12.1 Overview .......................................................................................................................................263

12.2 Features .........................................................................................................................................263

12.2.1 Microarchitecture summary ..........................................................................................264

12.2.1.1 Block diagram ................................................................................................264

12.2.1.2 Instruction unit features .................................................................................266

12.2.1.3 Integer unit features .......................................................................................267

12.2.1.4 Load/Store unit features .................................................................................267

12.2.1.5 e200z0h system bus features ..........................................................................267

12.2.1.6 Nexus features ................................................................................................267

12.3 Core registers and programmer’s model .......................................................................................268

12.3.1 Unimplemented SPRs and read-only SPRs ..................................................................271

12.4 Instruction summary ......................................................................................................................271

Chapter 13

Peripheral Bridge (PBRIDGE)

13.1 Introduction ...................................................................................................................................273

13.1.1 Block diagram ..............................................................................................................273

13.1.2 Overview ......................................................................................................................273

13.1.3 Modes of operation .......................................................................................................274

13.2 Functional description ...................................................................................................................274

13.2.1 Access support ..............................................................................................................274

13.2.1.1 Peripheral Write Buffering .............................................................................274

13.2.1.2 Read cycles ....................................................................................................274

13.2.1.3 Write cycles ....................................................................................................274

13.2.2 General operation .........................................................................................................274

Chapter 14

Crossbar Switch (XBAR)

14.1 Introduction ...................................................................................................................................275

14.2 Block diagram ...............................................................................................................................275

14.3 Overview .......................................................................................................................................276

14.4 Features .........................................................................................................................................276

14.5 Modes of operation ........................................................................................................................276

14.5.1 Normal mode ................................................................................................................276

14.5.2 Debug mode ..................................................................................................................276

14.6 Functional description ...................................................................................................................277

14.6.1 Overview ......................................................................................................................277

14.6.2 General operation .........................................................................................................277

14.6.3 Master ports ..................................................................................................................278

14.6.4 Slave ports ....................................................................................................................278

14.6.5 Priority assignment .......................................................................................................278

14.6.6 Arbitration ....................................................................................................................278

14.6.6.1 Fixed priority operation .................................................................................279

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Chapter 15

Error Correction Status Module (ECSM)

15.1 Introduction ...................................................................................................................................281

15.2 Overview .......................................................................................................................................281

15.3 Features .........................................................................................................................................281

15.4 Memory map and registers description .........................................................................................281

15.4.1 Memory map ................................................................................................................282

15.4.2 Registers description ....................................................................................................283

15.4.2.1 Processor core type (PCT) register ................................................................283

15.4.2.2 Revision (REV) register .................................................................................283

15.4.2.3 Platform XBAR Master Configuration (PLAMC) .........................................284

15.4.2.4 Platform XBAR Slave Configuration (PLASC) ............................................284

15.4.2.5 IPS Module Configuration (IMC) register .....................................................285

15.4.2.6 Miscellaneous Reset Status Register (MRSR) ...............................................285

15.4.2.7 Miscellaneous Interrupt Register (MIR) ........................................................286

15.4.2.8 Miscellaneous User-Defined Control Register (MUDCR) ............................287

15.4.2.9 ECC registers .................................................................................................287

15.4.2.10 ECC Configuration Register (ECR) ...............................................................288

15.4.2.11 ECC Status Register (ESR) ............................................................................289

15.4.2.12 ECC Error Generation Register (EEGR) .......................................................290

15.4.2.13 Flash ECC Address Register (FEAR) ............................................................292

15.4.2.14 Flash ECC Master Number Register (FEMR) ...............................................293

15.4.2.15 Flash ECC Attributes (FEAT) register ...........................................................293

15.4.2.16 Flash ECC Data Register (FEDR) .................................................................294

15.4.2.17 RAM ECC Address Register (REAR) ...........................................................295

15.4.2.18 RAM ECC Syndrome Register (RESR) ........................................................296

15.4.2.19 RAM ECC Master Number Register (REMR) ..............................................298

15.4.2.20 RAM ECC Attributes (REAT) register ..........................................................298

15.4.2.21 RAM ECC Data Register (REDR) .................................................................299

15.4.3 ECSM_reg_protection ..................................................................................................300

Chapter 16

Internal Static RAM (SRAM)

16.1 Introduction ...................................................................................................................................303

16.2 SRAM operating mode ..................................................................................................................303

16.3 Module memory map ....................................................................................................................303

16.4 Register descriptions .....................................................................................................................303

16.5 SRAM ECC mechanism ................................................................................................................303

16.5.1 Access timing ...............................................................................................................304

16.5.2 Reset effects on SRAM accesses ..................................................................................305

16.6 Functional description ...................................................................................................................305

16.7 Initialization and application information .....................................................................................305

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Chapter 17

Flash Memory

17.1 Introduction ...................................................................................................................................307

17.2 Platform Flash controller ...............................................................................................................307

17.2.1 Introduction ..................................................................................................................307

17.2.1.1 Overview ........................................................................................................308

17.2.1.2 Features ..........................................................................................................308

17.2.2 Modes of operation .......................................................................................................309

17.2.3 External signal descriptions ..........................................................................................309

17.2.4 Memory map and registers description ........................................................................309

17.2.4.1 Memory map ..................................................................................................310

17.2.5 Functional description ..................................................................................................311

17.2.6 Basic interface protocol ................................................................................................312

17.2.7 Access protections ........................................................................................................312

17.2.8 Read cycles — buffer miss ...........................................................................................312

17.2.9 Read cycles — buffer hit ..............................................................................................313

17.2.10 Write cycles ..................................................................................................................313

17.2.11 Error termination ..........................................................................................................313

17.2.12 Access pipelining ..........................................................................................................314

17.2.13 Flash error response operation ......................................................................................314

17.2.14 Bank0 page read buffers and prefetch operation ..........................................................314

17.2.14.1 Instruction/data prefetch triggering ................................................................316

17.2.14.2 Per-master prefetch triggering ........................................................................316

17.2.14.3 Buffer allocation .............................................................................................316

17.2.14.4 Buffer invalidation .........................................................................................316

17.2.15 Bank1 temporary holding register ................................................................................317

17.2.16 Read-While-Write functionality ...................................................................................317

17.2.17 Wait state emulation .....................................................................................................319

17.2.18 Timing diagrams ...........................................................................................................320

17.3 Flash memory ................................................................................................................................327

17.3.1 Introduction ..................................................................................................................327

17.3.2 Main features ................................................................................................................327

17.3.3 Block diagram ..............................................................................................................327

17.3.3.1 Data Flash ......................................................................................................327

17.3.3.2 Code Flash ......................................................................................................328

17.3.4 Functional description ..................................................................................................329

17.3.4.1 Macrocell structure ........................................................................................329

17.3.4.2 Flash module sectorization .............................................................................330

17.3.5 Operating modes ...........................................................................................................333

17.3.5.1 Reset ...............................................................................................................333

17.3.5.2 User mode ......................................................................................................333

17.3.5.3 Low-power mode ...........................................................................................334

17.3.5.4 Power-down mode .........................................................................................335

17.3.6 Registers description ....................................................................................................336

17.3.7 Register map .................................................................................................................337

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17.3.7.1 Module Configuration Register (MCR) .........................................................339

17.3.7.2 Low/Mid Address Space Block Locking register (LML) ..............................344

17.3.7.3 Non-Volatile Low/Mid Address Space Block Locking register (NVLML) ...345

17.3.7.4 Secondary Low/Mid Address Space Block Locking register (SLL) .............346

17.3.7.5 Non-Volatile Secondary Low/Mid Address Space Block Locking register

(NVSLL) .........................................................................................................................347

17.3.7.6 Low/Mid Address Space Block Select register (LMS) ..................................349

17.3.7.7 Address Register (ADR) ................................................................................349

17.3.7.8 User Test 0 register (UT0) ..............................................................................357

17.3.7.9 User Test 1 register (UT1) ..............................................................................359

17.3.7.10 User Test 2 register (UT2) ..............................................................................360

17.3.7.11 User Multiple Input Signature Register 0 (UMISR0) ....................................360

17.3.7.12 User Multiple Input Signature Register 1 (UMISR1) ....................................361

17.3.7.13 User Multiple Input Signature Register 2 (UMISR2) ....................................362

17.3.7.14 User Multiple Input Signature Register 3 (UMISR3) ....................................362

17.3.7.15 User Multiple Input Signature Register 4 (UMISR4) ....................................363

17.3.7.16 Non-Volatile Private Censorship Password 0 register (NVPWD0) ...............364

17.3.7.17 Non-Volatile Private Censorship Password 1 register (NVPWD1) ...............364

17.3.7.18 Non-Volatile System Censoring Information 0 register (NVSCI0) ...............365

17.3.7.19 Non-Volatile System Censoring Information 1 register (NVSCI1) ...............366

17.3.7.20 Non-Volatile User Options register (NVUSRO) ............................................367

17.3.8 Code Flash programming considerations .....................................................................368

17.3.8.1 Modify operation ............................................................................................368

17.3.8.2 Error Correction Code (ECC) ........................................................................376

17.3.8.3 EEPROM emulation ......................................................................................376

17.3.8.4 Protection strategy ..........................................................................................377

Chapter 18

Enhanced Direct Memory Access (eDMA)

18.1 Introduction ...................................................................................................................................381

18.2 Overview .......................................................................................................................................381

18.3 Features .........................................................................................................................................382

18.4 Modes of operation ........................................................................................................................383

18.4.1 Normal mode ................................................................................................................383

18.4.2 Debug mode ..................................................................................................................383

18.5 Memory map and register definition .............................................................................................384

18.5.1 Memory map ................................................................................................................384

18.5.2 Register descriptions ....................................................................................................387

18.5.2.1 eDMA Control Register (EDMA_CR) ..........................................................387

18.5.2.2 eDMA Error Status Register (EDMA_ESR) .................................................388

18.5.2.3 eDMA Enable Request Register (EDMA_ERQRL) ......................................390

18.5.2.4 eDMA Enable Error Interrupt Register (EDMA_EEIRL) .............................391

18.5.2.5 eDMA Set Enable Request Register (EDMA_SERQR) ................................392

18.5.2.6 eDMA Clear Enable Request Register (EDMA_CERQR) ............................392

18.5.2.7 eDMA Set Enable Error Interrupt Register (EDMA_SEEIR) .......................393

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18.5.2.8 eDMA Clear Enable Error Interrupt Register (EDMA_CEEIR) ...................393

18.5.2.9 eDMA Clear Interrupt Request Register (EDMA_CIRQR) ..........................394

18.5.2.10 eDMA Clear Error Register (EDMA_CERR) ...............................................395

18.5.2.11 eDMA Set START Bit Register (EDMA_SSBR) ..........................................395

18.5.2.12 eDMA Clear DONE Status Bit Register (EDMA_CDSBR) .........................396

18.5.2.13 eDMA Interrupt Request Register (EDMA_IRQRL) ....................................396

18.5.2.14 eDMA Error Register (EDMA_ERL) ............................................................397

18.5.2.15 DMA Hardware Request Status (DMAHRSL) ..............................................398

18.5.2.16 eDMA Channel n Priority Registers (EDMA_CPRn) ...................................399

18.5.2.17 Transfer Control Descriptor (TCD) ...............................................................400

18.6 Functional description ...................................................................................................................407

18.6.1 eDMA microarchitecture ..............................................................................................407

18.6.2 eDMA basic data flow ..................................................................................................409

18.6.3 eDMA performance ......................................................................................................411

18.7 Initialization / application information ..........................................................................................414

18.7.1 eDMA initialization ......................................................................................................414

18.7.2 DMA programming errors ............................................................................................416

18.7.3 DMA request assignments ............................................................................................417

18.7.4 DMA arbitration mode considerations .........................................................................417

18.7.4.1 Fixed-channel arbitration ...............................................................................417

18.7.4.2 Fixed-group arbitration, round-robin channel arbitration ..............................417

18.7.5 DMA transfer ................................................................................................................418

18.7.5.1 Single request .................................................................................................418

18.7.5.2 Multiple requests ............................................................................................419

18.7.5.3 Modulo feature ...............................................................................................420

18.7.6 TCD status ....................................................................................................................421

18.7.6.1 Minor loop complete ......................................................................................421

18.7.6.2 Active channel TCD reads .............................................................................422

18.7.6.3 Preemption status ...........................................................................................422

18.7.7 Channel linking ............................................................................................................422

18.7.8 Dynamic programming .................................................................................................423

18.7.8.1 Dynamic channel linking and dynamic scatter/gather ...................................423

Chapter 19

DMA Channel Mux (DMA_MUX)

19.1 Introduction ...................................................................................................................................425

19.1.1 Overview ......................................................................................................................425

19.1.2 Features .........................................................................................................................425

19.1.3 Modes of operation .......................................................................................................426

19.2 External signal description ............................................................................................................426

19.2.1 Overview ......................................................................................................................426

19.3 Memory map and register definition .............................................................................................426

19.3.1 Memory map ................................................................................................................426

19.3.2 Register descriptions ....................................................................................................428

19.3.2.1 Channel Configuration Registers ...................................................................428

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19.4 DMA request mapping ..................................................................................................................429

19.5 Functional description ...................................................................................................................430

19.5.1 DMA channels with periodic triggering capability ......................................................430

19.5.2 DMA channels with no triggering capability ...............................................................433

19.6 Initialization/application information ............................................................................................433

19.6.1 Reset .............................................................................................................................433

19.6.2 Enabling and configuring sources ................................................................................433

Chapter 20

Deserial Serial Peripheral Interface (DSPI)

20.1 Introduction ...................................................................................................................................437

20.2 Block diagram ...............................................................................................................................437

20.3 Overview .......................................................................................................................................438

20.4 Features .........................................................................................................................................438

20.5 Modes of operation ........................................................................................................................439

20.5.1 Master mode .................................................................................................................439

20.5.2 Slave mode ...................................................................................................................439

20.5.3 Module disable mode ...................................................................................................440

20.5.4 Debug mode ..................................................................................................................440

20.6 External signal description ............................................................................................................440

20.6.1 Signal overview ............................................................................................................440

20.6.2 Signal names and descriptions ......................................................................................441

20.6.2.1 Peripheral Chip Select / Slave Select (CS_0) ................................................441

20.6.2.2 Peripheral Chip Selects 1–3 (CS1:3) .............................................................441

20.6.2.3 Peripheral Chip Select 4 (CS4) ......................................................................441

20.6.2.4 Peripheral Chip Select 5/Peripheral Chip Select Strobe (CS_5) ....................441

20.6.2.5 Serial Input (SIN_x) .......................................................................................441

20.6.2.6 Serial Output (SOUT_x) ................................................................................441

20.6.2.7 Serial Clock (SCK_x) .....................................................................................442

20.7 Memory map and registers description .........................................................................................442

20.7.1 Memory map ................................................................................................................442

20.7.2 Registers description ....................................................................................................443

20.7.2.1 DSPI Module Configuration Register (DSPIx_MCR) ...................................443

20.7.2.2 DSPI Transfer Count Register (DSPIx_TCR) ...............................................446

20.7.2.3 DSPI Clock and Transfer Attributes Registers 0–7 (DSPIx_CTARn) ...........447

20.7.2.4 DSPI Status Register (DSPIx_SR) .................................................................453

20.7.2.5 DSPI DMA / Interrupt Request Select and Enable Register

(DSPIx_RSER) ....................................................................................................................455

20.7.2.6 DSPI PUSH TX FIFO Register (DSPIx_PUSHR) ........................................456

20.7.2.7 DSPI POP RX FIFO Register (DSPIx_POPR) ..............................................458

20.7.2.8 DSPI Transmit FIFO Registers 0–4 (DSPIx_TXFRn) ...................................459

20.7.2.9 DSPI Receive FIFO Registers 0–4 (DSPIx_RXFRn) ....................................459

20.8 Functional description ...................................................................................................................460

20.8.1 Modes of operation .......................................................................................................461

20.8.1.1 Master mode ...................................................................................................461

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20.8.1.2 Slave mode .....................................................................................................462

20.8.1.3 Module disable mode .....................................................................................462

20.8.1.4 Debug mode ...................................................................................................462

20.8.2 Start and stop of DSPI transfers ...................................................................................462

20.8.3 Serial Peripheral Interface (SPI) configuration ............................................................463

20.8.3.1 SPI master mode ............................................................................................463

20.8.3.2 SPI slave mode ...............................................................................................464

20.8.3.3 FIFO disable operation ...................................................................................464

20.8.3.4 Transmit First In First Out (TX FIFO) buffering mechanism ........................464

20.8.3.5 Receive First In First Out (RX FIFO) buffering mechanism .........................465

20.8.4 DSPI baud rate and clock delay generation ..................................................................466

20.8.4.1 Baud rate generator ........................................................................................466

20.8.4.2 CS to SCK delay (tCSC) ..................................................................................467

20.8.4.3 After SCK delay (tASC) ..................................................................................467

20.8.4.4 Delay after transfer (tDT) ..............................................................................468

20.8.4.5 Peripheral Chip Select strobe enable (CS5_x) ...............................................468

20.8.5 Transfer formats ...........................................................................................................469

20.8.5.1 Classic SPI transfer format (CPHA = 0) ........................................................470

20.8.5.2 Classic SPI transfer format (CPHA = 1) ........................................................471

20.8.5.3 Modified SPI transfer format (MTFE = 1, CPHA = 0) ..................................472

20.8.5.4 Modified SPI transfer format (MTFE = 1, CPHA = 1) ..................................473

20.8.5.5 Continuous selection format ..........................................................................474

20.8.5.6 Clock polarity switching between DSPI transfers .........................................475

20.8.6 Continuous Serial communications clock ....................................................................476

20.8.7 Interrupts/DMA requests ..............................................................................................478

20.8.7.1 End of queue interrupt request (EOQF) .........................................................478

20.8.7.2 Transmit FIFO fill interrupt or DMA request (TFFF) ...................................478

20.8.7.3 Transfer complete interrupt request (TCF) ....................................................478

20.8.7.4 Transmit FIFO underflow interrupt request (TFUF) .....................................479

20.8.7.5 Receive FIFO drain interrupt or DMA request (RFDF) ................................479

20.8.7.6 Receive FIFO overflow interrupt request (RFOF) .........................................479

20.8.7.7 FIFO overrun request (TFUF) or (RFOF) ......................................................479

20.8.8 Power saving features ...................................................................................................479

20.8.8.1 Module disable mode .....................................................................................479

20.9 Initialization and application information .....................................................................................480

20.9.1 Managing queues ..........................................................................................................480

20.9.2 Baud rate settings .........................................................................................................480

20.9.3 Delay settings ...............................................................................................................482

20.9.4 MPC5602P DSPI compatibility with QSPI of the MPC500 MCUs ............................482

20.9.5 Calculation of FIFO pointer addresses .........................................................................483

20.9.5.1 Address calculation for first-in entry and last-in entry in TX FIFO ..............484

20.9.5.2 Address calculation for first-in entry and last-in entry in RX FIFO ..............484

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Chapter 21

LIN Controller (LINFlex)

21.1 Introduction ...................................................................................................................................487

21.2 Main features .................................................................................................................................487

21.2.1 LIN mode features ........................................................................................................487

21.2.2 UART mode features ....................................................................................................487

21.2.3 Features common to LIN and UART ...........................................................................487

21.3 General description .......................................................................................................................488

21.4 Fractional baud rate generation .....................................................................................................489

21.5 Operating modes ...........................................................................................................................491

21.5.1 Initialization mode ........................................................................................................492

21.5.2 Normal mode ................................................................................................................492

21.5.3 Low power mode (Sleep) .............................................................................................492

21.6 Test modes .....................................................................................................................................492

21.6.1 Loop Back mode ...........................................................................................................492

21.6.2 Self Test mode ..............................................................................................................493

21.7 Memory map and registers description .........................................................................................493

21.7.1 Memory map ................................................................................................................493

21.7.1.1 LIN control register 1 (LINCR1) ...................................................................495

21.7.1.2 LIN interrupt enable register (LINIER) .........................................................498

21.7.1.3 LIN status register (LINSR) ...........................................................................499

21.7.1.4 LIN error status register (LINESR) ...............................................................502

21.7.1.5 UART mode control register (UARTCR) ......................................................503

21.7.1.6 UART mode status register (UARTSR) .........................................................504

21.7.1.7 LIN timeout control status register (LINTCSR) ............................................506

21.7.1.8 LIN output compare register (LINOCR) .......................................................507

21.7.1.9 LIN timeout control register (LINTOCR) ......................................................508

21.7.1.10 LIN fractional baud rate register (LINFBRR) ...............................................508

21.7.1.11 LIN integer baud rate register (LINIBRR) ....................................................509

21.7.1.12 LIN checksum field register (LINCFR) .........................................................510

21.7.1.13 LIN control register 2 (LINCR2) ...................................................................510

21.7.1.14 Buffer identifier register (BIDR) ...................................................................511

21.7.1.15 Buffer data register LSB (BDRL) ..................................................................512

21.7.1.16 Buffer data register MSB (BDRM) ................................................................513

21.7.1.17 Identifier filter enable register (IFER) ...........................................................514

21.7.1.18 Identifier filter match index (IFMI) ...............................................................514

21.7.1.19 Identifier filter mode register (IFMR) ............................................................515

21.7.1.20 Identifier filter control register (IFCR2n) ......................................................516

21.7.1.21 Identifier filter control register (IFCR2n+ 1) ................................................517

21.8 Functional description ...................................................................................................................519

21.8.1 UART mode ..................................................................................................................519

21.8.1.1 Buffer in UART mode ....................................................................................519

21.8.1.2 UART transmitter ...........................................................................................520

21.8.1.3 UART receiver ...............................................................................................520

21.8.1.4 Clock gating ...................................................................................................521

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21.8.2 LIN mode ......................................................................................................................521

21.8.2.1 Master mode ...................................................................................................521

21.8.2.2 Slave mode .....................................................................................................523

21.8.2.3 Slave mode with identifier filtering ...............................................................525

21.8.2.4 Slave mode with automatic resynchronization ..............................................527

21.8.2.5 Clock gating ...................................................................................................529

21.8.3 8-bit timeout counter ....................................................................................................529

21.8.3.1 LIN timeout mode ..........................................................................................529

21.8.3.2 Output compare mode ....................................................................................530

21.8.4 Interrupts .......................................................................................................................531

Chapter 22

FlexCAN

22.1 Introduction ...................................................................................................................................533

22.1.1 Overview ......................................................................................................................533

22.1.2 FlexCAN module features ............................................................................................534

22.1.3 Modes of operation .......................................................................................................535

22.2 External signal description ............................................................................................................536

22.2.1 Overview ......................................................................................................................536

22.2.2 Signal Descriptions .......................................................................................................536

22.2.2.1 RXD ...............................................................................................................536

22.2.2.2 TXD ...............................................................................................................536

22.3 Memory map and registers description .........................................................................................536

22.3.1 FlexCAN memory mapping .........................................................................................536

22.3.2 Message buffer structure ..............................................................................................539

22.3.3 Rx FIFO structure .........................................................................................................542

22.3.4 Registers description ....................................................................................................544

22.3.4.1 Module Configuration Register (MCR) .........................................................544

22.3.4.2 Control Register (CTRL) ...............................................................................548

22.3.4.3 Free Running Timer (TIMER) .......................................................................551

22.3.4.4 Rx Global Mask register (RXGMASK) .........................................................552

22.3.4.5 Rx 14 Mask (RX14MASK) ...........................................................................552

22.3.4.6 Rx 15 Mask (RX15MASK) ...........................................................................553

22.3.4.7 Error Counter Register (ECR) ........................................................................554

22.3.4.8 Error and Status Register (ESR) ....................................................................555

22.3.4.9 Interrupt Masks 1 Register (IMASK1) ..........................................................558

22.3.4.10 Interrupt Flags 1 Register (IFLAG1) .............................................................558

22.3.4.11 Rx Individual Mask Registers (RXIMR0–RXIMR31) ..................................559

22.4 Functional description ...................................................................................................................562

22.4.1 Overview ......................................................................................................................562

22.4.2 Transmit process ...........................................................................................................562

22.4.3 Arbitration process .......................................................................................................563

22.4.4 Receive process ............................................................................................................564

22.4.5 Matching process ..........................................................................................................565

22.4.6 Data coherence .............................................................................................................566

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22.4.6.1 Transmission abort mechanism ......................................................................566

22.4.6.2 Message Buffer deactivation ..........................................................................567

22.4.6.3 Message Buffer lock mechanism ...................................................................568

22.4.7 Rx FIFO ........................................................................................................................569

22.4.8 CAN protocol related features ......................................................................................570

22.4.8.1 Remote frames ...............................................................................................570

22.4.8.2 Overload frames .............................................................................................570

22.4.8.3 Time stamp .....................................................................................................570

22.4.8.4 Protocol timing ...............................................................................................571

22.4.8.5 Arbitration and matching timing ....................................................................573

22.4.9 Modes of operation details ...........................................................................................574

22.4.9.1 Freeze mode ...................................................................................................574

22.4.9.2 Module disable mode .....................................................................................574

22.4.9.3 Stop mode .......................................................................................................575

22.4.10 Interrupts .......................................................................................................................575

22.4.11 Bus interface .................................................................................................................576

22.5 Initialization/application information ............................................................................................576

22.5.1 FlexCAN initialization sequence ..................................................................................576

Chapter 23

Analog-to-Digital Converter (ADC)

23.1 Overview .......................................................................................................................................579

23.1.1 Device-specific features ...............................................................................................579

23.1.2 Device-specific pin configuration features ...................................................................580

23.1.3 Device-specific implementation ...................................................................................580

23.2 Introduction ...................................................................................................................................580

23.3 Functional description ...................................................................................................................581

23.3.1 Analog channel conversion ..........................................................................................581

23.3.1.1 Normal conversion .........................................................................................581

23.3.1.2 Start of normal conversion .............................................................................581

23.3.1.3 Normal conversion operating modes .............................................................582

23.3.1.4 Injected channel conversion ...........................................................................583

23.3.1.5 Abort conversion ............................................................................................584

23.3.2 Analog clock generator and conversion timings ..........................................................584

23.3.3 ADC sampling and conversion timing .........................................................................585

23.3.3.1 ADC_0 ...........................................................................................................585

23.3.4 ADC CTU (Cross Triggering Unit) ..............................................................................587

23.3.4.1 Overview ........................................................................................................587

23.3.4.2 CTU in control mode .....................................................................................587

23.3.5 Programmable analog watchdog ..................................................................................588

23.3.5.1 Introduction ....................................................................................................588

23.3.5.2 Analog watchdog functionality ......................................................................589

23.3.6 DMA functionality .......................................................................................................589

23.3.7 Interrupts .......................................................................................................................589

23.3.8 Power-down mode ........................................................................................................590

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23.3.9 Auto-clock-off mode ....................................................................................................591

23.4 Register descriptions .....................................................................................................................591

23.4.1 Introduction ..................................................................................................................591

23.4.2 Control logic registers ..................................................................................................593

23.4.2.1 Main Configuration Register (MCR) .............................................................593

23.4.2.2 Main Status Register (MSR) ..........................................................................594

23.4.3 Interrupt registers ..........................................................................................................596

23.4.3.1 Interrupt Status Register (ISR) .......................................................................596

23.4.3.2 Interrupt Mask Register (IMR) ......................................................................596

23.4.3.3 Watchdog Threshold Interrupt Status Register (WTISR) ..............................598

23.4.3.4 Watchdog Threshold Interrupt Mask Register (WTIMR) ..............................599

23.4.4 DMA registers ..............................................................................................................600

23.4.4.1 DMA Enable (DMAE) register ......................................................................600

23.4.4.2 DMA Channel Select Register (DMAR[0]) ...................................................601

23.4.5 Threshold registers .......................................................................................................602

23.4.5.1 Introduction ....................................................................................................602

23.4.5.2 Threshold Control Register (TRCx, x = [0..3]) ..............................................602

23.4.5.3 Threshold Register (THRHLR[0:3]) ..............................................................603

23.4.6 Conversion Timing Registers CTR[0] ..........................................................................604

23.4.7 Mask registers ...............................................................................................................604

23.4.7.1 Introduction ....................................................................................................604

23.4.7.2 Normal Conversion Mask Registers (NCMR[0]) ..........................................604

23.4.7.3 Injected Conversion Mask Registers (JCMR[0]) ...........................................606

23.4.8 Delay registers ..............................................................................................................607

23.4.8.1 Power-Down Exit Delay Register (PDEDR) .................................................607

23.4.9 Data registers ................................................................................................................607

23.4.9.1 Introduction ....................................................................................................607

23.4.9.2 Channel Data Registers (CDR[0..15]) ...........................................................607

Chapter 24

Cross Triggering Unit (CTU)

24.1 Introduction ...................................................................................................................................609

24.2 CTU overview ...............................................................................................................................609

24.3 Functional description ...................................................................................................................610

24.3.1 Trigger events features .................................................................................................610

24.3.2 Trigger generator subunit (TGS) ..................................................................................611

24.3.3 TGS in triggered mode .................................................................................................611

24.3.4 TGS in sequential mode ...............................................................................................612

24.3.5 TGS counter ..................................................................................................................613

24.4 Scheduler subunit (SU) .................................................................................................................614

24.4.1 ADC commands list .....................................................................................................616

24.4.2 ADC commands list format ..........................................................................................616

24.4.3 ADC results ..................................................................................................................618

24.5 Reload mechanism ........................................................................................................................618

24.6 Power safety mode ........................................................................................................................620

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24.6.1 MDIS bit .......................................................................................................................620

24.6.2 STOP mode ..................................................................................................................620

24.7 Interrupts and DMA requests ........................................................................................................620

24.7.1 DMA support ................................................................................................................620

24.7.2 CTU faults and errors ...................................................................................................620

24.7.3 CTU interrupt/DMA requests .......................................................................................621

24.8 Memory map .................................................................................................................................623

24.8.1 Trigger Generator Sub-unit Input Selection Register (TGSISR) .................................627

24.8.2 Trigger Generator Sub-unit Control Register (TGSCR) ..............................................629

24.8.3 Trigger x Compare Register (TxCR, x= 0...7) .............................................................630

24.8.4 TGS Counter Compare Register (TGSCCR) ...............................................................630

24.8.5 TGS Counter Reload Register (TGSCRR) ...................................................................631

24.8.6 Commands list control register 1 (CLCR1) ..................................................................631

24.8.7 Commands list control register 2 (CLCR2) ..................................................................632

24.8.8 Trigger handler control register 1 (THCR1) .................................................................632

24.8.9 Trigger handler control register 2 (THCR2) .................................................................634

24.8.10 Commands list register x (x = 1,...,24) (CLRx) ............................................................636

24.8.11 FIFO DMA control register (FDCR) ............................................................................637

24.8.12 FIFO control register (FCR) .........................................................................................638

24.8.13 FIFO threshold register (FTH) .....................................................................................639

24.8.14 FIFO status register (FST) ............................................................................................640

24.8.15 FIFO Right aligned data x (x= 0,...,3) (FRx) ...............................................................641

24.8.16 FIFO signed Left aligned data x (x= 0,...,3) (FLx) ......................................................642

24.8.17 Cross triggering unit error flag register (CTUEFR) .....................................................642

24.8.18 Cross triggering unit interrupt flag register (CTUIFR) ................................................643

24.8.19 Cross triggering unit interrupt/DMA register (CTUIR) ...............................................644

24.8.20 Control ON time register (COTR) ................................................................................645

24.8.21 Cross triggering unit control register (CTUCR) ...........................................................647

24.8.22 Cross triggering unit digital filter (CTUDF) ................................................................648

24.8.23 Cross triggering unit power control register (CTUPCR) .............................................648

Chapter 25

FlexPWM

25.1 Overview .......................................................................................................................................649

25.2 Features .........................................................................................................................................649

25.3 Modes of operation ........................................................................................................................650

25.4 Block diagrams ..............................................................................................................................651

25.4.1 Module level .................................................................................................................651

25.4.2 PWM submodule ..........................................................................................................652

25.5 External signal descriptions ..........................................................................................................653

25.5.1 PWMA[n] and PWMB[n] — external PWM pair ........................................................653

25.5.2 PWMX[n] — auxiliary PWM signal ............................................................................653

25.5.3 FAULT[n] — fault inputs .............................................................................................653

25.5.4 EXT_SYNC — external synchronization signal ..........................................................653

25.5.5 EXT_FORCE — external output force signal ..............................................................653

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25.5.6 OUT_TRIG0[n] and OUT_TRIG1[n] — output triggers ............................................653

25.5.7 EXT_CLK — external clock signal .............................................................................653

25.6 Memory map and registers ............................................................................................................654

25.6.1 FlexPWM module memory map ..................................................................................654

25.6.2 Register descriptions ....................................................................................................657

25.6.3 Submodule registers .....................................................................................................657

25.6.3.1 Counter Register (CNT) .................................................................................657

25.6.3.2 Initial Count Register (INIT) .........................................................................657

25.6.3.3 Control 2 Register (CTRL2) ..........................................................................658

25.6.3.4 Control 1 Register (CTRL1) ..........................................................................660

25.6.3.5 Value register 0 (VAL0) .................................................................................662

25.6.3.6 Value register 1 (VAL1) .................................................................................663

25.6.3.7 Value register 2 (VAL2) .................................................................................663

25.6.3.8 Value register 3 (VAL3) .................................................................................664

25.6.3.9 Value register 4 (VAL4) .................................................................................664

25.6.3.10 Value register 5 (VAL5) .................................................................................665

25.6.3.11 Output Control register (OCTRL) ..................................................................665

25.6.3.12 Status register (STS) ......................................................................................666

25.6.3.13 Interrupt Enable register (INTEN) .................................................................667

25.6.3.14 DMA Enable register (DMAEN) ...................................................................668

25.6.3.15 Output Trigger Control register (TCTRL) .....................................................669

25.6.3.16 Fault Disable Mapping register (DISMAP) ...................................................670

25.6.3.17 Deadtime Count registers (DTCNT0, DTCNT1) ..........................................670

25.6.4 Configuration registers .................................................................................................671

25.6.4.1 Output Enable register (OUTEN) ..................................................................671

25.6.4.2 Mask register (MASK) ...................................................................................672

25.6.4.3 Software Controlled Output Register (SWCOUT) ........................................673

25.6.4.4 Deadtime Source Select Register (DTSRCSEL) ...........................................674

25.6.4.5 Master Control Register (MCTRL) ................................................................676

25.6.5 Fault channel registers ..................................................................................................677

25.6.5.1 Fault Control Register (FCTRL) ....................................................................677

25.6.5.2 Fault Status Register (FSTS) ..........................................................................678

25.6.5.3 Fault Filter Register (FFILT) .........................................................................679

25.6.5.4 Input filter considerations ..............................................................................679

25.7 Functional description ...................................................................................................................681

25.7.1 Center-aligned PWMs ..................................................................................................681

25.7.2 Edge-aligned PWMs .....................................................................................................682

25.7.3 Phase-shifted PWMs ....................................................................................................682

25.7.4 Double switching PWMs ..............................................................................................684

25.7.5 ADC triggering .............................................................................................................685

25.7.6 Synchronous switching of multiple outputs .................................................................687

25.8 Functional details ..........................................................................................................................688

25.8.1 PWM clocking ..............................................................................................................688

25.8.2 Register reload logic .....................................................................................................689

25.8.3 Counter synchronization ...............................................................................................690

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26 Freescale Semiconductor

25.8.4 PWM generation ...........................................................................................................691

25.8.5 Output compare capabilities .........................................................................................692

25.8.6 Force out logic ..............................................................................................................692

25.8.7 Independent or complementary channel operation .......................................................694

25.8.8 Deadtime insertion logic ...............................................................................................695

25.8.9 Top/bottom correction ..................................................................................................696

25.8.10 Manual correction .........................................................................................................698

25.8.11 Output logic ..................................................................................................................699

25.8.12 Fault protection .............................................................................................................700

25.8.13 Fault pin filter ...............................................................................................................701

25.8.14 Automatic fault clearing ...............................................................................................702

25.8.15 Manual fault clearing ....................................................................................................702

25.8.16 Fault testing ..................................................................................................................703

25.9 PWM generator loading ................................................................................................................703

25.9.1 Load enable ..................................................................................................................703

25.9.2 Load frequency .............................................................................................................704

25.9.3 Reload flag ....................................................................................................................705

25.9.4 Reload errors ................................................................................................................705

25.9.5 Initialization ..................................................................................................................705

25.10 Clocks ............................................................................................................................................706

25.11 Interrupts .......................................................................................................................................706

25.12 DMA ..............................................................................................................................................706

Chapter 26

eTimer

26.1 Introduction ...................................................................................................................................709

26.2 Features .........................................................................................................................................709

26.3 Module block diagram ..................................................................................................................711

26.4 Channel block diagram ..................................................................................................................712

26.5 External signal descriptions ..........................................................................................................712

26.5.1 ETC[5:0]—eTimer input/outputs .................................................................................712

26.6 Memory map and registers ............................................................................................................712

26.6.1 Overview ......................................................................................................................712

26.6.2 Timer channel registers ................................................................................................716

26.6.2.1 Compare register 1 (COMP1) ........................................................................716

26.6.2.2 Compare register 2 (COMP2) ........................................................................717

26.6.2.3 Capture register 1 (CAPT1) ...........................................................................717

26.6.2.4 Capture register 2 (CAPT2) ...........................................................................718

26.6.2.5 Load register (LOAD) ....................................................................................718

26.6.2.6 Hold register (HOLD) ....................................................................................719

26.6.2.7 Counter register (CNTR) ...............................................................................719

26.6.2.8 Control register 1 (CTRL1) ............................................................................720

26.6.2.9 Control register 2 (CTRL2) ............................................................................722

26.6.2.10 Control register 3 (CTRL3) ............................................................................724

26.6.2.11 Status register (STS) ......................................................................................725

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26.6.2.12 Interrupt and DMA enable register (INTDMA) ............................................726

26.6.2.13 Comparator Load register 1 (CMPLD1) ........................................................727

26.6.2.14 Comparator Load register 2 (CMPLD2) ........................................................728

26.6.2.15 Compare and Capture Control register (CCCTRL) .......................................728

26.6.2.16 Input Filter Register (FILT) ...........................................................................730

26.6.2.17 Input filter considerations ..............................................................................731

26.6.3 Watchdog timer registers ..............................................................................................731

26.6.3.1 Watchdog Time-Out registers (WDTOL and WDTOH) ................................731

26.6.4 Configuration registers .................................................................................................732

26.6.4.1 Channel Enable register (ENBL) ...................................................................732

26.6.4.2 DMA Request Select registers (DREQ0, DREQ1) ........................................732

26.7 Functional description ...................................................................................................................733

26.7.1 General .........................................................................................................................733

26.7.2 Counting modes ............................................................................................................734

26.7.2.1 STOP mode ....................................................................................................734

26.7.2.2 COUNT mode ................................................................................................734

26.7.2.3 EDGE-COUNT mode ....................................................................................735

26.7.2.4 GATED-COUNT mode ..................................................................................735

26.7.2.5 QUADRATURE-COUNT mode ....................................................................735

26.7.2.6 SIGNED-COUNT mode ................................................................................735

26.7.2.7 TRIGGERED-COUNT mode ........................................................................735

26.7.2.8 ONE-SHOT mode ..........................................................................................736

26.7.2.9 CASCADE-COUNT mode ............................................................................736

26.7.2.10 PULSE-OUTPUT mode ................................................................................737

26.7.2.11 FIXED-FREQUENCY PWM mode ..............................................................737

26.7.2.12 VARIABLE-FREQUENCY PWM mode ......................................................737

26.7.2.13 Usage of compare registers ............................................................................738

26.7.2.14 Usage of Compare Load registers ..................................................................738

26.7.2.15 MODULO COUNTING mode ......................................................................739

26.7.3 Other features ...............................................................................................................739

26.7.3.1 Redundant OFLAG checking .........................................................................739

26.7.3.2 Loopback checking ........................................................................................739

26.7.3.3 Input capture mode .........................................................................................739

26.7.3.4 Master/Slave mode .........................................................................................740

26.7.3.5 Watchdog timer ..............................................................................................740

26.8 Clocks ............................................................................................................................................740

26.9 Interrupts .......................................................................................................................................741

26.10 DMA ..............................................................................................................................................741

Chapter 27

Functional Safety

27.1 Introduction ...................................................................................................................................743

27.2 Register protection module ...........................................................................................................743

27.2.1 Overview ......................................................................................................................743

27.2.2 Features .........................................................................................................................743

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27.2.3 Modes of operation .......................................................................................................744

27.2.4 External signal description ...........................................................................................744

27.2.5 Memory map and registers description ........................................................................744

27.2.5.1 Register protection memory map ...................................................................745

27.2.5.2 Registers description ......................................................................................746

27.2.6 Functional description ..................................................................................................748

27.2.6.1 General ...........................................................................................................748

27.2.6.2 Change lock settings ......................................................................................748

27.2.6.3 Access errors ..................................................................................................751

27.2.7 Reset .............................................................................................................................752

27.3 Software Watchdog Timer (SWT) .................................................................................................752

27.3.1 Overview ......................................................................................................................752

27.3.2 Features .........................................................................................................................752

27.3.3 Modes of operation .......................................................................................................752

27.3.4 External signal description ...........................................................................................753

27.3.5 SWT memory map and registers description ...............................................................753

27.3.5.1 SWT Control Register (SWT_CR) ................................................................754

27.3.5.2 SWT Interrupt Register (SWT_IR) ................................................................755

27.3.5.3 SWT Time-Out register (SWT_TO) ..............................................................756

27.3.5.4 SWT Window Register (SWT_WN) ..............................................................756

27.3.5.5 SWT Service Register (SWT_SR) .................................................................757

27.3.5.6 SWT Counter Output register (SWT_CO) .....................................................757

27.3.5.7 SWT Service Key Register (SWT_SK) .........................................................758

27.3.6 Functional description ..................................................................................................758

Chapter 28

Fault Collection Unit (FCU)

28.1 Introduction ...................................................................................................................................761

28.1.1 Overview ......................................................................................................................761

28.1.1.1 General description ........................................................................................761

28.1.2 Features .........................................................................................................................764

28.1.3 Modes of operation .......................................................................................................764

28.1.3.1 Normal mode ..................................................................................................764

28.1.3.2 Test mode .......................................................................................................764

28.2 Memory map and register definition .............................................................................................764

28.2.1 Memory map ................................................................................................................765

28.2.2 Register summary .........................................................................................................765

28.2.3 Register descriptions ....................................................................................................767

28.2.3.1 Module Configuration Register (FCU_MCR) ...............................................767

28.2.3.2 Fault Flag Register (FCU_FFR) ....................................................................768

28.2.3.3 Frozen Fault Flag Register (FCU_FFFR) ......................................................770

28.2.3.4 Fake Fault Generation Register (FCU_FFGR) ..............................................771

28.2.3.5 Fault Enable Register (FCU_FER) ................................................................771

28.2.3.6 Key Register (FCU_KR) ................................................................................772

28.2.3.7 Timeout Register (FCU_TR) .........................................................................773

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28.2.3.8 Timeout Enable Register (FCU_TER) ...........................................................773

28.2.3.9 Module State Register (FCU_MSR) ..............................................................774

28.2.3.10 Microcontroller State Register (FCU_MCSR) ...............................................774

28.2.3.11 Frozen MC State Register (FCU_FMCSR) ...................................................776

28.3 Functional description ...................................................................................................................777

28.3.1 State machine ................................................................................................................778

28.3.2 Output generation protocol ...........................................................................................779

28.3.2.1 Dual-rail protocol ...........................................................................................779

28.3.2.2 Time switching protocol ................................................................................780

28.3.2.3 Bi-Stable protocol ..........................................................................................781

Chapter 29

Wakeup Unit (WKPU)

29.1 Overview .......................................................................................................................................783

29.2 Features .........................................................................................................................................783

29.3 External signal description ............................................................................................................783

29.4 Memory map and registers description .........................................................................................783

29.4.1 Memory map ................................................................................................................783

29.4.2 Registers description ....................................................................................................784

29.4.2.1 NMI Status Flag Register (NSR) ...................................................................784

29.4.2.2 NMI Configuration Register (NCR) ..............................................................784

29.5 Functional description ...................................................................................................................785

29.5.1 General .........................................................................................................................785

29.5.2 Non-Maskable Interrupts ..............................................................................................786

29.5.2.1 NMI management ..........................................................................................786

Chapter 30

Periodic Interrupt Timer (PIT)

30.1 Introduction ...................................................................................................................................789

30.1.1 Overview ......................................................................................................................789

30.1.2 Features .........................................................................................................................789

30.2 Signal description ..........................................................................................................................790

30.3 Memory map and registers description .........................................................................................790

30.3.1 Memory map ................................................................................................................790

30.3.2 Registers description ....................................................................................................791

30.3.2.1 PIT Module Control Register (PITMCR) ......................................................791

30.3.2.2 Timer Load Value Register n (LDVALn) .......................................................792

30.3.2.3 Current Timer Value Register n (CVALn) .....................................................792

30.3.2.4 Timer Control Register n (TCTRLn) .............................................................793

30.3.2.5 Timer Flag Register n (TFLGn) .....................................................................794

30.4 Functional description ...................................................................................................................794

30.4.1 General .........................................................................................................................794

30.4.1.1 Timers ............................................................................................................795

30.4.1.2 Debug mode ...................................................................................................796

30.4.2 Interrupts .......................................................................................................................796

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30 Freescale Semiconductor

30.5 Initialization and application information .....................................................................................796

30.5.1 Example configuration .................................................................................................796

Chapter 31

System Timer Module (STM)

31.1 Overview .......................................................................................................................................799

31.2 Features .........................................................................................................................................799

31.3 Modes of operation ........................................................................................................................799

31.4 External signal description ............................................................................................................799

31.5 Memory map and registers description .........................................................................................799

31.5.1 Memory map ................................................................................................................799

31.5.2 Registers description ....................................................................................................800

31.5.2.1 STM Control Register (STM_CR) .................................................................800

31.5.2.2 STM Count Register (STM_CNT) ................................................................801

31.5.2.3 STM Channel Control Register (STM_CCRn) ..............................................802

31.5.2.4 STM Channel Interrupt Register (STM_CIRn) .............................................802

31.5.2.5 STM Channel Compare Register (STM_CMPn) ...........................................803

31.6 Functional description ...................................................................................................................804

Chapter 32

Cyclic Redundancy Check (CRC)

32.1 Introduction ...................................................................................................................................805

32.1.1 Glossary ........................................................................................................................805

32.2 Main features .................................................................................................................................805

32.2.1 Standard features ..........................................................................................................805

32.3 Block diagram ...............................................................................................................................805

32.3.1 IPS bus interface ...........................................................................................................806

32.4 Functional description ...................................................................................................................806

32.5 Memory map and registers description .........................................................................................808

32.5.1 CRC Configuration Register (CRC_CFG) ...................................................................809

32.5.2 CRC Input Register (CRC_INP) ..................................................................................810

32.5.3 CRC Current Status Register (CRC_CSTAT) ..............................................................810

32.5.4 CRC Output Register (CRC_OUTP) ............................................................................811

32.6 Use cases and limitations ..............................................................................................................811

Chapter 33

Boot Assist Module (BAM)

33.1 Overview .......................................................................................................................................817

33.2 Features .........................................................................................................................................817

33.3 Boot modes ....................................................................................................................................817

33.4 Memory map .................................................................................................................................817

33.5 Functional description ...................................................................................................................818

33.5.1 Entering boot modes .....................................................................................................818

33.5.2 MPC5602P boot pins ....................................................................................................819

33.5.3 Reset Configuration Half Word (RCHW) ....................................................................820

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33.5.4 Single chip boot mode ..................................................................................................821

33.5.4.1 Boot and alternate boot ..................................................................................822

33.5.5 Boot through BAM .......................................................................................................822

33.5.5.1 Executing BAM .............................................................................................822

33.5.5.2 BAM software flow .......................................................................................823

33.5.5.3 BAM resources ..............................................................................................824

33.5.5.4 Download and execute the new code .............................................................825

33.5.5.5 Download 64-bit password and password check ...........................................825

33.5.5.6 Download start address, VLE bit and code size .............................................827

33.5.5.7 Download data ...............................................................................................828

33.5.5.8 Execute code ..................................................................................................828

33.5.6 Boot from UART—autobaud disabled .........................................................................828

33.5.6.1 Configuration .................................................................................................828

33.5.6.2 UART boot mode download protocol ............................................................829

33.5.7 Bootstrap with FlexCAN—autobaud disabled .............................................................829

33.5.7.1 Configuration .................................................................................................829

33.6 FlexCAN boot mode download protocol ......................................................................................830

33.6.1 Autobaud feature ..........................................................................................................830

33.6.1.1 Configuration .................................................................................................831

33.6.1.2 Boot from UART with autobaud enabled ......................................................833

33.6.1.3 Boot from FlexCAN with autobaud enabled .................................................837

33.6.2 Interrupt ........................................................................................................................842

33.7 Censorship .....................................................................................................................................842

33.7.0.1 Censorship password registers (NVPWD0 and NVPWD1) ..........................842

33.7.0.2 Nonvolatile System Censorship Control registers (NVSCI0 and NVSCI1) ..843

33.7.0.3 Censorship configuration ...............................................................................843

Chapter 34

Voltage Regulators and Power Supplies

34.1 Voltage regulator ...........................................................................................................................849

34.1.1 High Power or Main Regulator (HPREG) ....................................................................849

34.1.2 Low Voltage Detectors (LVD) and Power On Reset (POR) .........................................849

34.1.3 VREG digital interface .................................................................................................850

34.1.4 Registers Description ....................................................................................................851

34.1.4.1 Voltage Regulator Control Register (VREG_CTL) .......................................851

34.1.4.2 Voltage Regulator Status register (VREG_STATUS) ....................................852

34.2 Power supply strategy ...................................................................................................................852

Chapter 35

IEEE 1149.1 Test Access Port Controller (JTAGC)

35.1 Introduction ...................................................................................................................................855

35.2 Block diagram ...............................................................................................................................855

35.3 Overview .......................................................................................................................................855

35.4 Features .........................................................................................................................................856

35.5 Modes of operation ........................................................................................................................856

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35.5.1 Reset .............................................................................................................................856

35.5.2 IEEE 1149.1-2001 defined test modes .........................................................................856

35.5.2.1 Bypass mode ..................................................................................................857

35.5.2.2 TAP sharing mode ..........................................................................................857

35.6 External signal description ............................................................................................................857

35.7 Memory map and registers description .........................................................................................857

35.7.1 Instruction register ........................................................................................................858

35.7.2 Bypass register ..............................................................................................................858

35.7.3 Device identification register .......................................................................................858

35.7.4 Boundary scan register .................................................................................................859

35.8 Functional description ...................................................................................................................859

35.8.1 JTAGC reset configuration ...........................................................................................859

35.8.2 IEEE 1149.1-2001 (JTAG) Test Access Port (TAP) .....................................................859

35.8.3 TAP controller state machine .......................................................................................860

35.8.3.1 Selecting an IEEE 1149.1-2001 register ........................................................862

35.8.4 JTAGC instructions ......................................................................................................862

35.8.4.1 BYPASS instruction .......................................................................................863

35.8.4.2 ACCESS_AUX_TAP_x instructions .............................................................863

35.8.4.3 CLAMP instruction ........................................................................................863

35.8.4.4 EXTEST — external test instruction .............................................................863

35.8.4.5 HIGHZ instruction .........................................................................................864

35.8.4.6 IDCODE instruction ......................................................................................864

35.8.4.7 SAMPLE instruction ......................................................................................864

35.8.4.8 SAMPLE/PRELOAD instruction ..................................................................864

35.8.5 Boundary scan ..............................................................................................................864

35.9 e200z0 OnCE controller ................................................................................................................865

35.9.1 e200z0 OnCE controller block diagram .......................................................................865

35.9.2 e200z0 OnCE controller functional description ...........................................................865

35.9.2.1 Enabling the TAP controller ...........................................................................865

35.9.3 e200z0 OnCE controller registers description ..............................................................866

35.9.3.1 OnCE Command register (OCMD) ...............................................................866

35.10 Initialization/Application Information ..........................................................................................867

Chapter 36

Nexus Development Interface (NDI)

36.1 Introduction ...................................................................................................................................869

36.2 Information specific to this device ................................................................................................869

36.2.1 Features not supported ..................................................................................................869

36.3 Block diagram ...............................................................................................................................870

36.4 Features .........................................................................................................................................870

36.5 Modes of operation ........................................................................................................................871

36.5.1 Nexus reset ...................................................................................................................871

36.5.2 NDI modes ....................................................................................................................871

36.5.2.1 Censored mode ...............................................................................................871

36.5.2.2 Stop mode .......................................................................................................871

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 33

36.6 External signal description ............................................................................................................871

36.7 Memory map and registers description .........................................................................................872

36.8 Interrupts and Exceptions ..............................................................................................................872

36.9 Debug support overview ...............................................................................................................873

36.9.1 Software Debug Facilities ............................................................................................873

36.9.1.1 Power Architecture technology compatibility ...............................................873

36.9.2 Additional Debug Facilities ..........................................................................................874

36.9.3 Hardware Debug Facilities ...........................................................................................874

36.9.4 Sharing Debug Resources by Software/Hardware .......................................................874

36.9.4.1 Simultaneous Hardware and Software Debug Event Handing ......................875

36.10 Software Debug Events and Exceptions .......................................................................................876

36.10.1 Instruction Address Compare Event .............................................................................877

36.10.2 Data Address Compare Event ......................................................................................878

36.10.2.1 Data Address Compare Event Status Updates ...............................................879

36.10.3 Linked Instruction Address and Data Address Compare Event ...................................881

36.10.4 Trap Debug Event .........................................................................................................881

36.10.5 Branch Taken Debug Event ..........................................................................................881

36.10.6 Instruction Complete Debug Event ..............................................................................881

36.10.7 Interrupt Taken Debug Event .......................................................................................882

36.10.8 Critical Interrupt Taken Debug Event ..........................................................................882

36.10.9 Return Debug Event .....................................................................................................882

36.10.10 Critical Return Debug Event ........................................................................................883

36.10.11 External Debug Event ...................................................................................................883

36.10.12 Unconditional Debug Event .........................................................................................883

36.11 Debug Registers ............................................................................................................................883

36.11.1 Debug Address and Value Registers .............................................................................884

36.11.2 Debug Control and Status Registers .............................................................................885

36.11.2.1 Debug Control Register 0 (DBCR0) ..............................................................885

36.11.2.2 Debug Control Register 1 (DBCR1) ..............................................................887

36.11.2.3 Debug Control Register 2 (DBCR2) ..............................................................890

36.11.2.4 Debug Control Register 4 (DBCR4) ..............................................................894

36.11.2.5 Debug Status Register (DBSR) ......................................................................895

36.11.3 Debug External Resource Control Register (DBERC0) ..............................................897

36.12 External Debug Support ................................................................................................................903

36.12.1 OnCE Introduction .......................................................................................................904

36.12.2 JTAG/OnCE Pins ..........................................................................................................907

36.12.3 OnCE Internal Interface Signals ...................................................................................907

36.12.3.1 CPU Debug Request (dbg_dbgrq) .................................................................907

36.12.3.2 CPU Debug Acknowledge (cpu_dbgack) ......................................................908

36.12.3.3 CPU Address, Attributes ................................................................................908

36.12.3.4 CPU Data .......................................................................................................908

36.12.4 OnCE Interface Signals ................................................................................................908

36.12.4.1 OnCE Enable (jd_en_once) ...........................................................................908

36.12.4.2 OnCE Debug Request/Event (jd_de_b, jd_de_en) ........................................908

36.12.4.3 e200z0h OnCE Debug Output (jd_debug_b) .................................................909

MPC5602P Microcontroller Reference Manual, Rev. 4

34 Freescale Semiconductor

36.12.4.4 e200z0h CPU Clock On Input (jd_mclk_on) .................................................909

36.12.4.5 Watchpoint Events (jd_watchpt[0:5]) ............................................................909

36.12.5 e200z0h OnCE Controller and Serial Interface ............................................................909

36.12.5.1 e200z0h OnCE Status Register ......................................................................910

36.12.5.2 e200z0h OnCE Command Register (OCMD) ...............................................911

36.12.5.3 e200z0h OnCE Control Register (OCR) ........................................................915

36.12.6 Access to Debug Resources ..........................................................................................917

36.12.7 Methods of Entering Debug Mode ...............................................................................919

36.12.7.1 External Debug Request During RESET .......................................................919

36.12.7.2 Debug Request During RESET ......................................................................919

36.12.7.3 Debug Request During Normal Activity .......................................................919

36.12.7.4 Debug Request During Waiting, Halted or Stopped State .............................919

36.12.7.5 Software Request During Normal Activity ....................................................920

36.12.8 CPU Status and Control Scan Chain Register (CPUSCR) ...........................................920

36.12.8.1 Instruction Register (IR) ................................................................................921

36.12.8.2 Control State Register (CTL) .........................................................................922

36.12.8.3 Program Counter Register (PC) .....................................................................925

36.12.8.4 Write-Back Bus Register (WBBRlow, WBBRhigh) ......................................925

36.12.8.5 Machine State Register (MSR) ......................................................................926

36.13 Watchpoint Support .......................................................................................................................926

36.14 Basic Steps for Enabling, Using, and Exiting External Debug Mode ...........................................927

36.15 Functional description ...................................................................................................................929

36.15.1 Enabling Nexus clients for TAP access ........................................................................929

36.15.2 Debug mode control .....................................................................................................929

Chapter 37

Document Revision History

Appendix A

Registers Under Protection

Chapter 1 Introduction

MPC5602P Microcontroller Ref e ren ce Man u al, Rev. 4

Freescale Semiconductor 35

Chapter 1

Introduction

1.1 The MPC5602P microcontroller family

The Qorivva MPC5602P microcontroller, a SafeAssure solution, is built on the Power Architecture®

platform. The Power Architecture based 32-bit microcontrollers represent the latest achievement in

integrated automotive application controllers. This device family integrates the most advanced and

up-to-date motor control design features.

The safety features included in MPC5602P (such us fault collection unit, safety port or flash memory and

SRAM with ECC) support the design of system applications where safety is a requirement.

The MPC5602P addresses low-end chassis applications and implements the Harvard bus interface version

of the e200z0h core.

The e200 processor family is a set of CPU cores that implement low-cost versions of the Power

Architecture Book E architecture. The e200 processors are designed for deeply embedded control

applications that require low cost solutions rather than maximum performance. The e200z0h processor

integrates an integer execution unit, branch control unit, instruction fetch and load/store units, and a

multi-ported register file capable to sustaining three read and two write operations per clock. Most integer

instructions execute in a single clock cycle. Branch tar get prefetching is performed by branch unit to allow

single-cycle branches in some cases. The e200z0h core is a single-issue, 32-bit Power Architecture

technology VLE only design with 32-bit general purpose registers (GPRs). All arithmetic instructions that

execute in the core operate on data in the general purpose registers (GPRs). Instead of the base Power

Architecture instruction set support, the e200z0h core only implements the VLE (variable length

encoding) APU, providing improved code density.

The MPC5602P has a single level of memory hierarchy consisting of 20 KB on-chip SRAM and 320 KB

(256 KB program + 64 KB data) of on-chip flash memory . Both the SRAM and the flash memory can hold

instructions and data.

The timer functions of the MPC5602P are performed by the eTimer Modular Timer System and

FlexPWM. The eTimer module implements enhanced timer features (six channels) including dedicated

motor control quadrature decode functionality and DMA support; the FlexPWM module consists of four

submodules controlling a pair of PWM channels each: three submodules may be used to control the three

phases of a motor and the additional pair to support DC-DC converter width modulation control.

Off-chip communication is performed by a suite of serial protocols including CANs, enhanced SPIs

(DSPI), and SCIs (LINFlex).

The System Integration Unit Lite (SIUL) performs several chip-wide configuration functions. Pad

configuration and general-purpose input/output (GPIO) are controlled from the SIUL. External interrupts

and reset control are also found in the SIUL. The internal multiplexer sub-block (IOMUX) provides

multiplexing of daisy chaining the DSPIs and external interrupt signal.

As the MPC5602P is built on a wider legacy of Power Architecture-based devices, when applicable and

possible, reuse or enhancement of existing IP, design and concepts is adopted.

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MPC5602P Microcontroller Reference Manual, Rev. 4

36 Freescale Semiconductor

1.2 Target applications

The MPC5602P belongs to an expanding range of automotive-focused products designed to address and

target the following chassis and safety market segments:

• Electric hydraulic power steering (EHPS)

• Lower end of electric power steering (EPS)

• Airbag applications

• Anti-lock braking systems (ABS)

• Motor control applications

EHPS and EPS systems typically feature sophisticated and advanced electrical motor control periphery

with special enhancements in the area of pulse width modulation, highly flexible timers, and functional

safety.

1.2.1 Application examples

1.2.1.1 Electric power steering

Figure 1-1 outlines a typical electric power steering application built around the MPC5602P

microcontroller.

Chapter 1 Introduction

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 37

Figure 1-1. Electric power steering application

1.2.1.2 Airbag

Figure 1-2 outlines a typical airbag application built around the MPC5602P microcontroller.

Position Sensor

Gearbox

Sensor

Load

Position Sensor

Physical Layer Torque

Relay

Relay Driver

Signal

Conditioning

Circuitry

Driver

PWM

3-phase Low Voltage Power Stage PMSM

Signal

Conditioning

Circuitry

Driver

Reverse Bat

Protection

Fast ADC

<1 µs, 10-bit Timer

Safety Port

Core

FlexCAN

Faults

Motor

Control

PWM

10 ns res

DSPI

MPC5602P

Vcc

Vanalog

Vref

Vcc

Vanalog

Vref

System

Basis

Chip

Windowed

Watchdog

Hi-speed CAN

Physical Layer CAN

Complex

Hardware

Watchdog

Input

Modules

Output Drivers

(Valves, Pump) Sensors

Safety Relay

U DC Bus

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MPC5602P Microcontroller Reference Manual, Rev. 4

38 Freescale Semiconductor

Figure 1-2. Airbag application

1.3 Features

Table 1-1 provides a summary of different members of the MPC5602P family and their features to enable

a comparison among the family members and an understanding of the range of functionality offered within

this family.

Table 1-1. MPC5602P device comparison

Feature MPC5601P MPC5602P

Code flash memory (with ECC) 192 KB 256 KB

Data flash memory / EE option (with ECC) 64 KB (optional feature)

SRAM (with ECC) 12 KB 20 KB

Processor core 32-bit e200z0h

Instruction set VLE (variable length encoding)

CPU performance 0–64 MHz

FMPLL (frequency-modulated phase-locked loop)

module

INTC (interrupt controller) channels 120

PIT (periodic interrupt timer) 1 (with four 32-bit timers)

eDMA (enhanced direct memory access) channels 16

FlexCAN (controller area network) 11,2 21,2

SPI

Physical

Interface

Physical

Interface

Physical

Interface

Physical

Interface

Satellite I/F

Buckle I/F

VIGN

Safing Unit

Power Supply Control Chain

DSPI

ADC

FlexCAN

LINFlex

DSPI DSPI

X/Y - accel.

CAN Physical

Layer

LIN Physical

Layer

Body network (dashboard)

Occupant detection

4-ch Squib

Driver

VBOOST

Squib 1

Squib 2

Squib 3

Squib 4

Custom

Device

VBOOST

VBUCK

VLOGIC

VIO

MPC5602P

Chapter 1 Introduction

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 39

Figure 1.4 shows a top-level block diagram of the MPC5602P microcontroller.

Safety port Yes (via FlexCAN module) Yes (via second FlexCAN

module)

FCU (fault collection unit) Yes

CTU (cross triggering unit) No Yes

eTimer 1 (16-bit, 6 channels)

FlexPWM (pulse-width modulation) channels No 8

(capture capability not

supported)

Analog-to-digital converter (ADC) 1 (10-bit, 16 channels)

LINFlex 1

(1 × Master/Slave)

(1 × Master/Slave,

1 × Master only)

DSPI (deserial serial peripheral interface) 1 3

CRC (cyclic redundancy check) unit Yes

Junction temperature sensor No

JTAG controller Yes

Nexus port controller (NPC) Yes (Nexus Class 1)

Supply Digital power supply 3.3 V or 5 V single supply with external transistor

Analog power supply 3.3 V or 5 V

Internal RC oscillator 16 MHz

External crystal oscillator 4–40 MHz

Packages 64 LQFP

100 LQFP

Temperature Standard ambient temperature –40 to 125 °C

1Each FlexCAN module has 32 message buffers.

2One FlexCAN module can act as a safety port with a bit rate as high as 8 Mbit/s at 64 MHz.

Table 1-1. MPC5602P device comparison (continued)

Feature MPC5601P MPC5602P

Chapter 1 Introduction

MPC5602P Microcontroller Reference Manual, Rev. 4

40 Freescale Semiconductor

Figure 1-3. MPC5602P block diagram

SRAM

(with ECC)

Slave SlaveSlave

Code Flash

(with ECC)

Data Flash

(with ECC)

PIT

STM

SWT

MC_RGM

MC_CGM

MC_ME

BAM

SIUL

WKPU

CRC

ECSM

e200z0 Core

32-bit

general

purpose

registers

Special

purpose

registers

Integer

execution

unit

Exception

handler

Variable

length

encoded

instructions

Instruction

unit

Load/store

unit

Branch

prediction

unit

JTAG

1.2 V regulator

control

XOSC

16 MHz

RC oscillator

FMPLL_0

(System)

Nexus port

controller

Interrupt

controller

eDMA

16 channels

Master Master

Instruction

32-bit

Master

Data

32-bit

Crossbar switch (XBAR, AMBA 2.0 v6 AHB)

Peripheral bridge

FCU

Legend:

ADC Analog-to-digital converter

BAM Boot assist module

CRC Cyclic redundancy check

CTU Cross triggering unit

DSPI Deserial serial peripheral interface

ECSM Error correction status module

eDMA Enhanced direct memory access

eTimer Enhanced timer

FCU Fault collection unit

Flash Flash memory

FlexCAN Controller area network

FlexPWM Flexible pulse width modulation

FMPLL Frequency-modulated phase-locked loop

INTC Interrupt controller

JTAG JTAG controller

LINFlex Serial communication interface (LIN support)

MC_CGM Clock generation module

MC_ME Mode entry module

MC_PCU Power control unit

MC_RGM Reset generation module

PIT Periodic interrupt timer

SIUL System Integration unit Lite

SRAM Static random-access memory

SSCM System status and configuration module

STM System timer module

SWT Software watchdog timer

WKPU Wakeup unit

XOSC External oscillator

XBAR Crossbar switch

External ballast

Nexus 1

eDMA

16 channels

FlexPWM

CTU

3×

eTimer

DSPI

2×

FlexCAN

LINFlex

Safety port

ADC

(6 ch)

SSCM

(10 bit, 16 ch)

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MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 41

1.4 Critical performance parameters

• Fully static operation, 0–64 MHz

• –40 °C to 150 °C junction temperature

• Low power design

— Less than 450 mW power dissipation

— Halt and STOP mode available for power reduction

— Resuming from Halt/STOP mode can be initiated via external pin

• Fabricated in 90 nm process

• 1.2 V nominal internal logic

• Nexus pins operate at VDDIO (no dedicated power supply)

— Unused pins configurable as GPIO

• 10-bit ADC conversion time < 1 µs

• Internal voltage regulator (VREG) with external ballast transistor enables control with a single

input rail

— 3.0 V–3.6 V or 4.5 V–5.5 V input supply voltage

• Configurable pins

— Selectable slew rate for EMI reduction

— Selectable pull-up, pull-down, or no pull on all pins

— Selectable open drain

— Support for 3.3 V or 5 V I/O levels

1.5 Chip-level features

On-chip modules available within the family include the following features:

• Up to 64 MHz, single issue, 32-bit CPU core complex (e200z0h)

— Compliant with Power Architecture embedded category

— Variable Length Encoding (VLE)

• Memory organization

— Up to 256 KB on-chip code flash memory with ECC and erase/program controller

— Optional: additional 64 (4 × 16) KB on-chip data flash memory with ECC for EEPROM

emulation

— Up to 20 KB on-chip SRAM with ECC

• Fail-safe protection

— Programmable watchdog timer

— Non-maskable interrupt

— Fault collection unit

• Nexus Class 1 interface

• Interrupts and events

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MPC5602P Microcontroller Reference Manual, Rev. 4

42 Freescale Semiconductor

— 16-channel eDMA controller

— 16 priority level controller

— Up to 25 external interrupts

— PIT implements four 32-bit timers

— 120 interrupts are routed via INTC

• General purpose I/Os

— Individually programmable as input, output or special function

— 37 on 64 LQFP

— 64 on 100 LQFP

• 1 general purpose eTimer unit

— 6 timers each with up/down capabilities

— 16-bit resolution, cascadeable counters

— Quadrature decode with rotation direction flag

— Double buffer input capture and output compare

• Communications interfaces

— Up to 2 LINFlex modules (1× Master/Slave, 1× Master only)

— Up to 3 DSPI channels with automatic chip select generation (up to 8/4/4 chip selects)

— 1 FlexCAN interface (2.0B Active) with 32 message buffers

— 1 safety port based on FlexCAN with 32 message buffers and up to 8 Mbit/s at 64 MHz

capability usable as second CAN when not used as safety port

• One 10-bit analog-to-digital converter (ADC)

— Up to 16 input channels (16 ch on 100 LQFP and 12 ch on 64 LQFP)

— Conversion time < 1 µs including sampling time at full precision

— Programmable Cross Triggering Unit (CTU)

— 4 analog watchdogs with interrupt capability

• On-chip CAN/UART bootstrap loader with Boot Assist Module (BAM)

• 1 FlexPWM unit

— 8 complementary or independent outputs with ADC synchronization signals

— Polarity control, reload unit

— Integrated configurable dead time unit and inverter fault input pins

— 16-bit resolution

— Lockable configuration

• Clock generation

— 4–40 MHz main oscillator

— 16 MHz internal RC oscillator

— Software-controlled FMPLL capable of up to 64 MHz

• Voltage supply

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MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 43

— 3.3 V or 5 V supply for I/Os and ADC

— On-chip single supply voltage regulator with external ballast transistor

• Operating temperature ranges: –40 to 125 °C or –40 to 105 °C

1.6 Module features

1.6.1 High performance e200z0 core processor

The e200z0 Power Architecture core provides the following features:

• High performance e200z0 core processor for managing peripherals and interrupts

• Single issue 4-stage pipeline in-order execution 32-bit Power Architecture CPU

• Harvard architecture

• Variable length encoding (VLE), allowing mixed 16- and 32-bit instructions

— Results in smaller code size footprint

— Minimizes impact on performance

• Branch processing acceleration using lookahead instruction buffer

• Load/store unit

— 1-cycle load latency

— Misaligned access support

— No load-to-use pipeline bubbles

• Thirty-two 32-bit general purpose registers (GPRs)

• Separate instruction bus and load/store bus Harvard architecture

• Hardware vectored interrupt support

• Reservation instructions for implementing read-modify-write constructs

• Long cycle time instructions, except for guarded loads, do not increase interrupt latency

• Extensive system development support through Nexus debug port

• Non-maskable interrupt support

1.6.2 Crossbar switch (XBAR)

The XBAR multi-port crossbar switch supports simultaneous connections between three master ports and

three slave ports. The crossbar supports a 32-bit address bus width and a 32-bit data bus width.

The crossbar allows for two concurrent transactions to occur from any master port to any slave port; but

one of those transfers must be an instruction fetch from internal flash memory. If a slave port is

simultaneously requested by more than one master port, arbitration logic will select the higher priority

master and grant it ownership of the slave port. All other masters requesting that slave port will be stalled

until the higher priority master completes its transactions. Requesting masters will be treated with equal

priority and will be granted access a slave port in round-robin fashion, based upon the ID of the last master

to be granted access.

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MPC5602P Microcontroller Reference Manual, Rev. 4

44 Freescale Semiconductor

The crossbar provides the following features:

• 3 master ports:

— e200z0 core complex instruction port

— e200z0 core complex Load/Store Data port

—eDMA

• 3 slave ports:

— Flash memory (Code and Data)

—SRAM

— Peripheral bridge

• 32-bit internal address, 32-bit internal data paths

• Fixed Priority Arbitration based on Port Master

• Temporary dynamic priority elevation of masters

1.6.3 Enhanced direct memory access (eDMA)

The enhanced direct memory access (eDMA) controller is a second-generation module capable of

performing complex data movements via 16 programmable channels, with minimal intervention from the

host processor. The hardware micro architecture includes a DMA engine which performs source and

destination address calculations, and the actual data movement operations, along with an SRAM-based

memory containing the transfer control descriptors (TCD) for the channels.

The eDMA module provides the following features:

• 16 channels support independent 8-, 16- or 32-bit single value or block transfers

• Supports variable-sized queues and circular queues

• Source and destination address registers are independently configured to either post-increment or

to remain constant

• Each transfer is initiated by a peripheral, CPU, or eDMA channel request

• Each eDMA channel can optionally send an interrupt request to the CPU on completion of a single

value or block transfer

• DMA transfers possible between system memories, DSPIs, ADC, FlexPWM, eTimer and CTU

• Programmable DMA channel multiplexer allows assignment of any DMA source to any available

DMA channel with as many as 30 request sources

• eDMA abort operation through software

1.6.4 Flash memory

The MPC5602P provides 320 KB of programmable, non-volatile, flash memory. The non-volatile

memory (NVM) can be used for instruction and/or data storage. The flash memory module is interfaced

to the system bus by a dedicated flash memory controller. It supports a 32-bit data bus width at the system

bus port, and a 128-bit read data interface to flash memory. The module contains four 128-bit wide prefetch

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MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 45

buffers. Prefetch buffer hits allow no-wait responses. Normal flash memory array accesses are registered

and are forwarded to the system bus on the following cycle, incurring two wait-states.

The flash memory module provides the following features:

• As much as 320 KB flash memory

— 6 blocks (32 KB + 2×16 KB + 32 KB + 32 KB + 128 KB) code flash memory

— 4 blocks (16 KB + 16 KB + 16 KB + 16 KB) data flash memory

— Full Read-While-Write (RWW) capability between code flash memory and data flash memory

• Four 128-bit wide prefetch buffers to provide single cycle in-line accesses (prefetch buffers can be

configured to prefetch code or data or both)

• Typical flash memory access time: no wait-state for buffer hits, 2 wait-states for page buffer miss

at 64 MHz

• Hardware managed flash memory writes handled by 32-bit RISC Krypton engine

• Hardware and software configurable read and write access protections on a per-master basis

• Configurable access timing allowing use in a wide range of system frequencies

• Multiple-mapping support and mapping-based block access timing (up to 31 additional cycles)

allowing use for emulation of other memory types

• Software programmable block program/erase restriction control

• Erase of selected block(s)

• Read page sizes

— Code flash memory: 128 bits (4 words)

— Data flash memory: 32 bits (1 word)

• ECC with single-bit correction, double-bit detection for data integrity

— Code flash memory: 64-bit ECC

— Data flash memory: 32-bit ECC

• Embedded hardware program and erase algorithm

• Erase suspend and program abort

• Censorship protection scheme to prevent flash memory content visibility

• Hardware support for EEPROM emulation

1.6.5 Static random access memory (SRAM)

The MPC5602P SRAM module provides up to 20 KB of general-purpose memory.

ECC handling is done on a 32-bit boundary and is completely software compatible with MPC55xx family

devices containing an e200z6 core and 64-bit wide ECC.

The SRAM module provides the following features:

• Supports read/write accesses mapped to the SRAM from any master

• Up to 20 KB general purpose SRAM

• Supports byte (8-bit), half word (16-bit), and word (32-bit) writes for optimal use of memory

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46 Freescale Semiconductor

• Typical SRAM access time: no wait-state for reads and 32-bit writes; 1 wait-state for 8- and 16-bit

writes if back-to-back with a read to same memory block

1.6.6 Interrupt controller (INTC)

The interrupt controller (INTC) provides priority-based preemptive scheduling of interrupt requests,

suitable for statically scheduled hard real-time systems. The INTC handles 128 selectable-priority

interrupt sources.

For high-priority interrupt requests, the time from the assertion of the interrupt request by the peripheral

to the execution of the interrupt service routine (ISR) by the processor has been minimized. The INTC

provides a unique vector for each interrupt request source for quick determination of which ISR has to be

executed. It also provides a wide number of priorities so that lower priority ISRs do not delay the execution

of higher priority ISRs. To allow the appropriate priorities for each source of interrupt request, the priority

of each interrupt request is software configurable.

When multiple tasks share a resource, coherent accesses to that resource need to be supported. The INTC

supports the priority ceiling protocol (PCP) for coherent accesses. By providing a modifiable priority

mask, the priority can be raised temporarily so that all tasks which share the same resource can not preempt

each other.

The INTC provides the following features:

• Unique 9-bit vector for each separate interrupt source

• 8 software triggerable interrupt sources

• 16 priority levels with fixed hardware arbitration within priority levels for each interrupt source

• Ability to modify the ISR or task priority: modifying the priority can be used to implement the

priority ceiling protocol for accessing shared resources.

• 1 external high priority interrupt (NMI) directly accessing the main core and I/O processor (IOP)

critical interrupt mechanism

1.6.7 System status and configuration module (SSCM)

The system status and configuration module (SSCM) provides central device functionality.

The SSCM includes these features:

• System configuration and status

— Memory sizes/status

— Device mode and security status

— Determine boot vector

— Search code flash for bootable sector

— DMA status

• Debug status port enable and selection

• Bus and peripheral abort enable/disable

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MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 47

1.6.8 System clocks and clock generation

The following list summarizes the system clock and clock generation on the MPC5602P:

• Lock detect circuitry continuously monitors lock status

• Loss of clock (LOC) detection for PLL outputs

• Programmable output clock divider (1, 2, 4, 8)

• FlexPWM module and eTimer module running at the same frequency as the e200z0h core

• Internal 16 MHz RC oscillator for rapid start-up and safe mode: supports frequency trimming by

user application

1.6.9 Frequency-modulated phase-locked loop (FMPLL)

The FMPLL allows the user to generate high speed system clocks from a 4–40 MHz input clock. Further,

the FMPLL supports programmable frequency modulation of the system clock. The PLL multiplication

factor, output clock divider ratio are all software configurable.

The FMPLL has the following major features:

• Input clock frequency: 4–40 MHz

• Maximum output frequency: 64 MHz

• Voltage controlled oscillator (VCO)—frequency 256–512 MHz

• Reduced frequency divider (RFD) for reduced frequency operation without forcing the FMPLL to

relock

• Frequency-modulated PLL

— Modulation enabled/disabled through software

— Triangle wave modulation

• Programmable modulation depth (±0.25% to ±4% deviation from center frequency):

programmable modulation frequency dependent on reference frequency

• Self-clocked mode (SCM) operation

1.6.10 Main oscillator

The main oscillator provides these features:

• Input frequency range: 4–40 MHz

• Crystal input mode or oscillator input mode

• PLL reference

1.6.11 Internal RC oscillator

This device has an RC ladder phase-shift oscillator. The architecture uses constant current charging of a

capacitor. The voltage at the capacitor is compared by the stable bandgap reference voltage.

The RC oscillator provides these features:

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MPC5602P Microcontroller Reference Manual, Rev. 4

48 Freescale Semiconductor

• Nominal frequency 16 MHz

• ±5% variation over voltage and temperature after process trim

• Clock output of the RC oscillator serves as system clock source in case loss of lock or loss of clock

is detected by the PLL

• RC oscillator is used as the default system clock during startup

1.6.12 Periodic interrupt timer (PIT)

The PIT module implements these features:

• 4 general-purpose interrupt timers

• 32-bit counter resolution

• Clocked by system clock frequency

• Each channel usable as trigger for a DMA request

1.6.13 System timer module (STM)

The STM implements these features:

• One 32-bit up counter with 8-bit prescaler

• Four 32-bit compare channels

• Independent interrupt source for each channel

• Counter can be stopped in debug mode

1.6.14 Software watchdog timer (SWT)

The SWT has the following features:

• 32-bit time-out register to set the time-out period

• Programmable selection of window mode or regular servicing

• Programmable selection of reset or interrupt on an initial time-out

• Master access protection

• Hard and soft configuration lock bits

• Reset configuration inputs allow timer to be enabled out of reset

1.6.15 Fault collection unit (FCU)

The FCU provides an independent fault reporting mechanism even if the CPU is malfunctioning.

The FCU module has the following features:

• FCU status register reporting the device status

• Continuous monitoring of critical fault signals

• User selection of critical signals from different fault sources inside the device

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• Critical fault events trigger 2 external pins (user selected signal protocol) that can be used

externally to reset the device and/or other circuitry (for example, a safety relay)

• Faults are latched into a register

1.6.16 System integration unit – Lite (SIUL)

The MPC5602P SIUL controls MCU pad configuration, external interrupt, general purpose I/O (GPIO),

and internal peripheral multiplexing.

The pad configuration block controls the static electrical characteristics of I/O pins. The GPIO block

provides uniform and discrete input/output control of the I/O pins of the MCU.

The SIUL provides the following features:

• Centralized general purpose input output (GPIO) control of up to 49 input/output pins and 16

analog input-only pads (package dependent)

• All GPIO pins can be independently configured to support pull-up, pull-down, or no pull

• Reading and writing to GPIO supported both as individual pins and 16-bit wide ports

• All peripheral pins, except ADC channels, can be alternatively configured as both general purpose

input or output pins

• ADC channels support alternative configuration as general purpose inputs

• Direct readback of the pin value is supported on all pins through the SIUL

• Configurable digital input filter that can be applied to some general purpose input pins for noise

elimination

• Up to 4 internal functions can be multiplexed onto 1 pin

1.6.17 Boot and censorship

Different booting modes are available in the MPC5602P: booting from internal flash memory and booting

via a serial link.

The default booting scheme uses the internal flash memory (an internal pull-down resistor is used to select

this mode). Optionally, the user can boot via FlexCAN or LINFlex (using the boot assist module software).

A censorship scheme is provided to protect the content of the flash memory and offer increased security

for the entire device.

A password mechanism is designed to grant the legitimate user access to the non-volatile memory.

1.6.17.1 Boot assist module (BAM)

The BAM is a block of read-only memory that is programmed once and is identical for all MPC560xP

devices that are based on the e200z0h core. The BAM program is executed every time the device is

powered on if the alternate boot mode has been selected by the user.

The BAM provides the following features:

• Serial bootloading via FlexCAN or LINFlex

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• Ability to accept a password via the used serial communication channel to grant the legitimate user

access to the non-volatile memory

1.6.18 Error correction status module (ECSM)

The ECSM provides a myriad of miscellaneous control functions regarding program-visible information

about the platform configuration and revision levels, a reset status register, a software watchdog timer,

wakeup control for exiting sleep modes, and information on platform memory errors reported by

error-correcting codes and/or generic access error information for certain processor cores.

The Error Correction Status Module supports a number of miscellaneous control functions for the

platform. The ECSM includes these features:

• Registers for capturing information on platform memory errors if error-correcting codes (ECC) are

implemented

• For test purposes, optional registers to specify the generation of double-bit memory errors are

enabled on the MPC5602P.

The sources of the ECC errors are:

• Flash memory

•SRAM

1.6.19 Peripheral bridge (PBRIDGE)

The PBRIDGE implements the following features:

• Duplicated periphery

• Master access privilege level per peripheral (per master: read access enable; write access enable)

• Write buffering for peripherals

• Checker applied on PBRIDGE output toward periphery

• Byte endianess swap capability

1.6.20 Controller area network (FlexCAN)

The MPC5602P MCU contains one controller area network (FlexCAN) module. This module is a

communication controller implementing the CAN protocol according to Bosch Specification version 2.0B.

The CAN protocol was designed to be used primarily as a vehicle serial data bus, meeting the specific

requirements of this field: real-time processing, reliable operation in the EMI environment of a vehicle,

cost-effectiveness and required bandwidth. The FlexCAN module contains 32 message buffers.

The FlexCAN module provides the following features:

• Full implementation of the CAN protocol specification, version 2.0B

— Standard data and remote frames

— Extended data and remote frames

— Up to 8-bytes data length

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— Programmable bit rate up to 1 Mbit/s

• 32 message buffers of up to 8-bytes data length

• Each message buffer configurable as Rx or Tx, all supporting standard and extended messages

• Programmable loop-back mode supporting self-test operation

• 3 programmable mask registers

• Programmable transmit-first scheme: lowest ID or lowest buffer number

• Time stamp based on 16-bit free-running timer

• Global network time, synchronized by a specific message

• Maskable interrupts

• Independent of the transmission medium (an external transceiver is assumed)

• High immunity to EMI

• Short latency time due to an arbitration scheme for high-priority messages

• Transmit features

— Supports configuration of multiple mailboxes to form message queues of scalable depth

— Arbitration scheme according to message ID or message buffer number

— Internal arbitration to guarantee no inner or outer priority inversion

— Transmit abort procedure and notification

• Receive features

— Individual programmable filters for each mailbox

— 8 mailboxes configurable as a 6-entry receive FIFO

— 8 programmable acceptance filters for receive FIFO

• Programmable clock source

— System clock

— Direct oscillator clock to avoid PLL jitter

1.6.21 Safety port (FlexCAN)

The MPC5602P MCU has a second CAN controller synthesized to run at high bit rates to be used as a

safety port. The CAN module of the safety port provides the following features:

• Identical to the FlexCAN module

• Bit rate up to 8 Mbit/s at 64 MHz CPU clock using direct connection between CAN modules (no

physical transceiver required)

• 32 message buffers of up to 8-bytes data length

• Can be used as a second independent CAN module

1.6.22 Serial communication interface module (LINFlex)

The LINFlex (local interconnect network flexible) on the MPC5602P features the following:

• Supports LIN Master mode (both instances), LIN Slave mode (only one instance) and UART mode

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• LIN state machine compliant to LIN1.3, 2.0 and 2.1 specifications

• Handles LIN frame transmission and reception without CPU intervention

• LIN features

— Autonomous LIN frame handling

— Message buffer to store Identifier and up to 8 data bytes

— Supports message length of up to 64 bytes

— Detection and flagging of LIN errors (sync field, delimiter, ID parity, bit framing, checksum,

and time-out)

— Classic or extended checksum calculation

— Configurable Break duration of up to 36-bit times

— Programmable baud rate prescalers (13-bit mantissa, 4-bit fractional)

— Diagnostic features: Loop back; Self Test; LIN bus stuck dominant detection

— Interrupt-driven operation with 16 interrupt sources

• LIN slave mode features:

— Autonomous LIN header handling

— Autonomous LIN response handling

— Optional discarding of irrelevant LIN responses using ID filter

• UART mode:

— Full-duplex operation

— Standard non return-to-zero (NRZ) mark/space format

— Data buffers with 4-byte receive, 4-byte transmit

— Configurable word length (8-bit or 9-bit words)

— Error detection and flagging

— Parity, Noise and Framing errors

— Interrupt-driven operation with four interrupt sources

— Separate transmitter and receiver CPU interrupt sources

— 16-bit programmable baud-rate modulus counter and 16-bit fractional

— 2 receiver wake-up methods

1.6.23 Deserial serial peripheral interface (DSPI)

The deserial serial peripheral interface (DSPI) module provides a synchronous serial interface for

communication between the MPC5602P MCU and external devices.

The DSPI modules provide these features:

• Full duplex, synchronous transfers

• Master or slave operation

• Programmable master bit rates

• Programmable clock polarity and phase

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• End-of-transmission interrupt flag

• Programmable transfer baud rate

• Programmable data frames from 4 to 16 bits

• Up to 8 chip select lines available:

— 8 on DSPI_0

— 4 each on DSPI_1 and DSPI_2

• 8 clock and transfer attributes registers

• Chip select strobe available as alternate function on one of the chip select pins for deglitching

• FIFOs for buffering up to 4 transfers on the transmit and receive side

• Queueing operation possible through use of the I/O processor or eDMA

• General purpose I/O functionality on pins when not used for SPI

1.6.24 Pulse width modulator (FlexPWM)

The pulse width modulator module (PWM) contains four PWM submodules each of which is set up to

control a single half-bridge power stage. There are also three fault channels.

This PWM is capable of controlling most motor types: AC induction motors (ACIM), permanent magnet

AC motors (PMAC), both brushless (BLDC) and brush DC motors (BDC), switched (SRM) and variable

reluctance motors (VRM), and stepper motors.

The FlexPWM block implements the following features:

• 16-bit resolution for center, edge-aligned, and asymmetrical PWMs

• Clock frequency same as that used for e200z0h core

• PWM outputs can operate as complementary pairs or independent channels

• Can accept signed numbers for PWM generation

• Independent control of both edges of each PWM output

• Synchronization to external hardware or other PWM supported

• Double buffered PWM registers

— Integral reload rates from 1 to 16

— Half cycle reload capability

• Multiple ADC trigger events can be generated per PWM cycle via hardware

• Write protection for critical registers

• Fault inputs can be assigned to control multiple PWM outputs

• Programmable filters for fault inputs

• Independently programmable PWM output polarity

• Independent top and bottom deadtime insertion

• Each complementary pair can operate with its own PWM frequency and deadtime values

• Individual software-control for each PWM output

• All outputs can be programmed to change simultaneously via a “Force Out” event

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• PWMX pin can optionally output a third PWM signal from each submodule

• Channels not used for PWM generation can be used for buffered output compare functions

• Channels not used for PWM generation can be used for input capture functions

• Enhanced dual-edge capture functionality

• eDMA support with automatic reload

• 2 fault inputs

• Capture capability for PWMA, PWMB, and PWMX channels not supported

1.6.25 eTimer

The MPC5602P includes one eTimer module which provides six 16-bit general purpose up/down

timer/counter units with the following features:

• Clock frequency same as that used for the e200z0h core

• Individual channel capability

— Input capture trigger

— Output compare

— Double buffer (to capture rising edge and falling edge)

— Separate prescaler for each counter

— Selectable clock source

— 0–100% pulse measurement

— Rotation direction flag (quad decoder mode)

• Maximum count rate

— External event counting: max. count rate = peripheral clock/2

— Internal clock counting: max. count rate = peripheral clock

• Counters are:

— Cascadable

— Preloadable

• Programmable count modulo

• Quadrature decode capabilities

• Counters can share available input pins

• Count once or repeatedly

• Pins available as GPIO when timer functionality not in use

1.6.26 Analog-to-digital converter (ADC) module

The ADC module provides the following features:

Analog part:

• 1 on-chip analog-to-digital converter

— 10-bit AD resolution

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— 1 sample and hold unit

— Conversion time, including sampling time, less than 1 µs (at full precision)

— Typical sampling time is 150 ns minimum (at full precision)

— DNL/INL ±1 LSB

— TUE < 1.5 LSB

— Single-ended input signal up to 3.3 V/5.0 V

— 3.3 V/5.0 V input reference voltage

— ADC and its reference can be supplied with a voltage independent from VDDIO

— ADC supply can be equal or higher than VDDIO

— ADC supply and ADC reference are not independent from each other (both internally bonded

to same pad)

— Sample times of 2 (default), 8, 64 or 128 ADC clock cycles

Digital part:

• 16 input channels

• 4 analog watchdogs comparing ADC results against predefined levels (low, high, range) before

results are stored in the appropriate ADC result location

• 2 modes of operation: Motor Control mode or Regular mode

• Regular mode features

— Register based interface with the CPU: control register, status register and 1 result register per

channel

— ADC state machine managing 3 request flows: regular command, hardware injected command

and software injected command

— Selectable priority between software and hardware injected commands

— DMA compatible interface

• CTU-controlled mode features

— Triggered mode only

— 4 independent result queues (1×16 entries, 2×8 entries, 1×4 entries)

— Result alignment circuitry (left justified and right justified)

— 32-bit read mode allows to have channel ID on one of the 16-bit part

— DMA compatible interfaces

1.6.27 Cross triggering unit (CTU)

The cross triggering unit allows automatic generation of ADC conversion requests on user selected

conditions without CPU load during the PWM period and with minimized CPU load for dynamic

configuration.

It implements the following features:

• Double buffered trigger generation unit with up to 8 independent triggers generated from external

triggers

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• Trigger generation unit configurable in sequential mode or in triggered mode

• Each trigger can be appropriately delayed to compensate the delay of external low pass filter

• Double buffered global trigger unit allowing eTimer synchronization and/or ADC command

generation

• Double buffered ADC command list pointers to minimize ADC-trigger unit update

• Double buffered ADC conversion command list with up to 24 ADC commands

• Each trigger capable of generating consecutive commands

• ADC conversion command allows to control ADC channel, single or synchronous sampling,

independent result queue selection

1.6.28 Nexus Development Interface (NDI)

The NDI (Nexus Development Interface) block is compliant with Nexus Class 1 of the IEEE-ISTO

5001-2003 standard. This development support is supplied for MCUs without requiring external address

and data pins for internal visibility. The NDI block is an integration of several individual Nexus blocks that

are selected to provide the development support interface for this device. The NDI block interfaces to the

host processor and internal busses to provide development support as per the IEEE-ISTO 5001-2003

Nexus Class 1 standard. The development support provided includes access to the MCU’s internal memory

map and access to the processor’s internal registers.

The NDI provides the following features:

• Configured via the IEEE 1149.1

• All Nexus port pins operate at VDDIO (no dedicated power supply)

• Nexus Class 1 supports Static debug

1.6.29 Cyclic redundancy check (CRC)

The CRC computing unit is dedicated to the computation of CRC off-loading the CPU. The CRC module

features:

• Support for CRC-16-CCITT (x25 protocol):

—x16 + x12 + x5 + 1

• Support for CRC-32 (Ethernet protocol):

—x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x + 1

• Zero wait states for each write/read operations to the CRC_CFG and CRC_INP registers at the

maximum frequency

1.6.30 IEEE 1149.1 JTAG controller

The JTAG controller (JTAGC) block provides the means to test chip functionality and connectivity while

remaining transparent to system logic when not in test mode. All data input to and output from the JTAGC

block is communicated in serial format. The JTAGC block is compliant with the IEEE standard.

The JTAG controller provides the following features:

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• IEEE test access port (TAP) interface 4 pins (TDI, TMS, TCK, TDO)

• Selectable modes of operation include JTAGC/debug or normal system operation.

• 5-bit instruction register that supports the following IEEE 1149.1-2001 defined instructions:

—BYPASS

—IDCODE

—EXTEST

—SAMPLE

— SAMPLE/PRELOAD

• 5-bit instruction register that supports the additional following public instructions:

— ACCESS_AUX_TAP_NPC

— ACCESS_AUX_TAP_ONCE

• 3 test data registers:

— Bypass register

— Boundary scan register (size parameterized to support a variety of boundary scan chain lengths)

— Device identification register

• TAP controller state machine that controls the operation of the data registers, instruction register

and associated circuitry

1.6.31 On-chip voltage regulator (VREG)

The on-chip voltage regulator module provides the following features:

• Uses external NPN (negative-positive-negative) transistor

• Regulates external 3.3 V/5.0 V down to 1.2 V for the core logic

• Low voltage detection on the internal 1.2 V and I/O voltage 3.3 V

1.7 Developer environment

The MPC5602P MCU tools and third-party developers are similar to those used for the Freescale

MPC5500 product family, offering a widespread, established network of tool and software vendors.

The following development support is available:

• Automotive Evaluation Boards (EVBs) featuring CAN, LIN interfaces, and more

• Compilers

• Debuggers

• JTAG and Nexus interfaces

• Autocode generation tools

• Initialization tools

1.8 Package

MPC5602P family members are offered in the following package types:

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58 Freescale Semiconductor

• 64-pin LQFP, 0.5 mm pitch, 10 mm × 10 mm outline

• 100-pin LQFP, 0.5 mm pitch, 14 mm × 14 mm outline

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Freescale Semiconductor 59

Chapter 2

MPC5602P Memory Map

Table 2-1 shows the memory map for the MPC5602P. All addresses on the MPC5602P, including those

that are reserved, are identified in the table. The addresses represent the physical addresses assigned to

each IP block.

Table 2-1. Memory map

Start address End address Size

(KB) Region name

On-chip memory

0x0000_0000 0x0003_FFFF 256 Code Flash Array 0

0x0004_0000 0x001F_FFFF 1792 Reserved

0x0020_0000 0x0020_3FFF 16 Code Flash Array 0 Shadow Sector

0x0020_4000 0x003F_FFFF 2032 Reserved

0x0040_0000 0x0040_3FFF 16 Code Flash Array 0 Test Sector

0x0040_4000 0x007F_FFFF 4080 Reserved

0x0080_0000 0x0080_FFFF 64 Data Flash Array 0

0x0081_0000 0x00C0_1FFF 4040 Reserved

0x00C0_2000 0x00C0_3FFF 8 Data Flash Array 0 Test Sector

0x00C0_4000 0x00FF_FFFF 4080 Reserved

0x0100_0000 0x1FFF_FFFF 507904 Flash Emulation Mapping

0x2000_0000 0x3FFF_FFFF 524288 Reserved

0x4000_0000 0x4000_4FFF 20 SRAM

0x4000_5000 0xC3F8_0000 1048536 Reserved

On-chip peripherals

0xC3F8_0000 0xC3F8_7FFF 32 Reserved

0xC3F8_8000 0xC3F8_BFFF 16 Code Flash 0 Configuration (CFLASH_0)

0xC3F8_C000 0xC3F8_FFFF 16 Data Flash 0 Configuration (DFLASH_0)

0xC3F9_0000 0xC3F9_3FFF 16 System Integration Unit Lite (SIUL)

0xC3F9_4000 0xC3F9_7FFF 16 WakeUp Unit (WKUP)

0xC3F9_8000 0xC3FD_7FF

256 Reserved

0xC3FD_8000 0xC3FD_BFF

16 System Status and Configuration Module (SSCM)

0xC3FD_C00

0xC3FD_FFF

16 Mode Entry module (ME)

0xC3FE_0000 0xC3FE_3FFF 16 Clock Generation Module (CGM, XOSC, IRC, FMPLL_0, CMU0)

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0xC3FE_4000 0xC3FE_7FFF 16 Reset Generation Module (RGM)

0xC3FE_8000 0xC3FE_BFF

16 Power Control Unit (PCU)1

0xC3FE_C00

0xC3FE_FFF

16 Reserved

0xC3FF_0000 0xC3FF_3FFF 16 Periodic Interrupt Timer (PIT)

0xC3FF_4000 0xC3FF_FFFF 48 Reserved

0xFFE0_0000 0xFFE0_3FFF 16 Analog to Digital Converter 0 (ADC_0)

0xFFE0_4000 0xFFE0_BFFF 32 Reserved

0xFFE0_C000 0xFFE0_FFFF 16 CTU_0

0xFFE1_0000 0xFFE1_7FFF 32 Reserved

0xFFE1_8000 0xFFE1_BFFF 16 eTimer_0

0xFFE1_C000 0xFFE2_3FFF 32 Reserved

0xFFE2_4000 0xFFE2_7FFF 16 FlexPWM_0

0xFFE2_8000 0xFFE3_FFFF 96 Reserved

0xFFE4_0000 0xFFE4_3FFF 16 LINFlex_0

0xFFE4_4000 0xFFE4_7FFF 16 LINFlex_1

0xFFE5_0000 0xFFE6_7FFF 128 Reserved

0xFFE6_8000 0xFFE6_BFFF 16 Cyclic Redundancy Check (CRC)

0xFFE6_C000 0xFFE6_FFFF 16 Fault Collection Unit (FCU)

0xFFE7_0000 0xFFE7_FFFF 64 Reserved

0xFFE8_0000 0xFFEF_FFFF 512 Mirrored (range 0xC3F8_0000 – 0xC3FF_FFFF)

0xFFF0_0000 0xFFF3_7FFF 224 Reserved

0xFFF3_8000 0xFFF3_BFFF 16 Software Watchdog (SWT_0)

0xFFF3_C000 0xFFF3_FFFF 16 System Timer Module (STM_0)

0xFFF4_0000 0xFFF4_3FFF 16 Error Correction Status Module (ECSM)

0xFFF4_4000 0xFFF4_7FFF 16 Enhanced Direct Memory Access Controller (eDMA)

0xFFF4_8000 0xFFF4_BFFF 16 Interrupt Controller (INTC)

0xFFF4_C000 0xFFF8_FFFF 272 Reserved

0xFFF9_0000 0xFFF9_3FFF 16 DSPI_0

0xFFF9_4000 0xFFF9_7FFF 16 DSPI_1

0xFFF9_8000 0xFFF9_BFFF 16 DSPI_2

0xFFF9_C000 0xFFFB_FFFF 144 Reserved

Table 2-1. Memory map (continued)

Start address End address Size

(KB) Region name

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0xFFFC_0000 0xFFFC_3FFF 16 FlexCAN_0 (CAN0)

0xFFFC_4000 0xFFFD_BFF

96 Reserved

0xFFFD_C00

0xFFFD_FFF

16 DMA Multiplexer (DMA_MUX)

0xFFFE_0000 0xFFFE_7FFF 32 Reserved

0xFFFE_8000 0xFFFE_BFF

16 Safety Port (FlexCAN)

0xFFFE_C00

0xFFFF_BFFF 64 Reserved

0xFFFF_C000 0xFFFF_FFFF 16 Boot Assist Module (BAM)

1This address space contains also VREG registers. See Chapter 34, “Voltage Regulators and Power Supplies.”

Table 2-1. Memory map (continued)

Start address End address Size

(KB) Region name

Chapter 2 MPC5602P Memory Map

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62 Freescale Semiconductor

Chapter 3 Signal Description

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Freescale Semiconductor 63

Chapter 3

Signal Description

This chapter describes the signals of the MPC5602P. It includes a table of signal properties and detailed

descriptions of signals.

3.1 100-pin LQFP pinout

Figure 3-1 shows the pinout of the 100-pin LQFP.

Figure 3-1. 100-pin LQFP pinout (top view)

100

NMI

A[6]

D[1]

A[7]

C[4]

A[8]

C[5]

A[5]

C[7]

C[3]

N.C.

VDD_HV_IO1

VSS_HV_IO1

D[9]

VDD_HV_OSC

VSS_HV_OSC

XTAL

EXTAL

RESET

D[8]

D[5]

D[6]

VSS_LV_COR0

VDD_LV_COR0

A[4]

VPP_TEST

D[14]

C[14]

C[13]

D[12]

N.C.

D[13]

VSS_LV_COR1

VDD_LV_COR1

A[3]

VDD_HV_IO2

VSS_HV_IO2

TDO

TCK

TMS

TDI

A[2]

C[12]

C[11]

D[11]

D[10]

A[1]

A[0]

D[7]

E[1]

C[1]

B[7]

C[2]

B[8]

E[2]

N.C.

B[9]

B[10]

B[11]

B[12]

VDD_HV_ADC0

VSS_HV_ADC0

E[7]/D[15]

E[3]/B[13]

E[5]/B[15]

E[4]/B[14]

E[6]/C[0]

N.C.

BCTRL

N.C.

VDD_HV_REG

A[15]

A[14]

C[6]

D[2]

B[6]

A[13]

A[9]

VSS_LV_COR2

VDD_LV_COR2

C[8]

D[4]

D[3]

VSS_HV_IO3

VDD_HV_IO3

D[0]

C[15]

C[9]

A[12]

A[11]

A[10]

B[3]

B[2]

C[10]

B[1]

B[0]

100 LQFP

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64 Freescale Semiconductor

3.2 64-pin LQFP pinout

Figure 3-2. 64-pin LQFP pinout(top view)

3.3 Pin description

The following sections provide signal descriptions and related information about the functionality and

configuration of the MPC5602P devices.

3.3.1 Power supply and reference voltage pins

Table 3-1 lists the power supply and reference voltage for the MPC5602P devices.

NMI

A[6]

A[7]

A[8]

A[5]

VDD_HV_IO1

VSS_HV_IO1

D[9]

VDD_HV_OSC

VSS_HV_OSC

XTAL

EXTAL

RESET

D[8]

VSS_LV_COR0

VDD_LV_COR0

A[4]

VPP_TEST

D[14]]

D[12]

D[13

VSS_LV_COR1

VDD_LV_COR1

A[3]

VDD_HV_IO2

VSS_HV_IO2

TDO

TCK

TMS

TDI

C[12]

C[11]

D[7]

E[1]

C[1]

B[7]

C[2]

B[8]

E[2]

B[9]

B[10]

B[11]

B[12]

VDD_HV_ADC0

VSS_HV_ADC0

E[3]/B[13]

BCTRL

VDD_HV_REG

A[15]

A[14]

B[6]

A[13]

A[9]

VSS_LV_COR2

VDD_LV_COR2

C[8]

VSS_HV_IO3

VDD_HV_IO3

A[12]

A[11]

A[10]

B[2]

B[1]

B[0]

64 LQFP

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MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 65

Table 3-1. Supply pins

Supply Pin

Symbol Description 64-pin 100-pin

VREG control and power supply pins. Pins available on 64-pin and 100-pin packages

BCTRL Voltage regulator external NPN ballast base control pin 31 47

VDD_HV_REG

(3.3 V or 5.0 V)

Voltage regulator supply voltage 32 50

ADC_0 reference and supply voltage. Pins available on 64-pin and 100-pin packages

VDD_HV_ADC01

1Analog supply/ground and high/low reference lines are internally physically separate, but are shorted via a

double-bonding connection on VDD_HV_ADCx/VSS_HV_ADCx pins.

ADC_0 supply and high reference voltage 28 39

VSS_HV_ADC0 ADC_0 ground and low reference voltage 29 40

Power supply pins (3.3 V or 5.0 V). Pins available on 64-pin and 100-pin packages

VDD_HV_IO1 Input/output supply voltage 6 13

VSS_HV_IO1 Input/output ground 7 14

VDD_HV_IO2 Input/output supply voltage and data Flash memory supply voltage 40 63

VSS_HV_IO2 Input/output ground and Flash memory HV ground 39 62

VDD_HV_IO3 Input/output supply voltage and code Flash memory supply voltage 55 87

VSS_HV_IO3 Input/output ground and code Flash memory HV ground 56 88

VDD_HV_OSC Crystal oscillator amplifier supply voltage 9 16

VSS_HV_OSC Crystal oscillator amplifier ground 10 17

Power supply pins (1.2 V). Pins available on 64-pin and 100-pin packages

VDD_LV_COR0 1.2 V supply pins for core logic and PLL. Decoupling capacitor must be

connected between these pins and the nearest VSS_LV_COR pin.

16 25

VSS_LV_COR0 1.2 V supply pins for core logic and PLL. Decoupling capacitor must be

connected between these pins and the nearest VDD_LV_COR pin.

15 24

VDD_LV_COR1 1.2 V supply pins for core logic and data Flash. Decoupling capacitor

must be connected between these pins and the nearest VSS_LV_COR pin.

42 65

VSS_LV_COR1 1.2 V supply pins for core logic and data Flash. Decoupling capacitor

must be connected between these pins and the nearest VDD_LV_COR pin.

43 66

VDD_LV_COR2 1.2 V supply pins for core logic and code Flash. Decoupling capacitor

must be connected between these pins and the nearest VSS_LV_COR pin.

58 92

VSS_LV_COR2 1.2 V supply pins for core logic and code Flash. Decoupling capacitor

must be connected betwee.n these pins and the nearest VDD_LV_COR pin.

59 93

Chapter 3 Signal Description

MPC5602P Microcontroller Reference Manual, Rev. 4

66 Freescale Semiconductor

3.3.2 System pins

Table 3-2 and Table 3-3 contain information on pin functions for the MPC5602P devices. The pins listed

in Table 3-2 are single-function pins. The pins shown in Table 3-3 are multi-function pins, programmable

via their respective pad configuration register (PCR) values.

3.3.3 Pin multiplexing

Table 3-3 defines the pin list and muxing for the MPC5602P devices.

Each row of Table 3-3 shows all the possible ways of configuring each pin, via alternate functions. The

default function assigned to each pin after reset is the ALT0 function.

MPC5602P devices provide three main I/O pad types, depending on the associated functions:

•Slow pads are the most common, providing a compromise between transition time and low

electromagnetic emission.

•Medium pads provide fast enough transition for serial communication channels with controlled

current to reduce electromagnetic emission.

•Fast pads provide maximum speed. They are used for improved NEXUS debugging capability.

Table 3-2. System pins

Symbol Description Direction

Pad speed1

1SRC values refer to the value assigned to the Slew Rate Control bits of the pad configuration register.

SRC = 0 SRC = 1 64-pin 100-pin

Dedicated pins

NMI Non-maskable Interrupt Input only Slow — 1 1

XTAL Analog output of the oscillator amplifier

circuit—needs to be grounded if oscillator is

used in bypass mode

———1118

EXTAL Analog input of the oscillator amplifier circuit,

when the oscillator is not in bypass mode

Analog input for the clock generator when the

oscillator is in bypass mode

———1219

TDI JTAG test data input Input only Slow — 35 58

TMS JTAG state machine control Input only Slow — 36 59

TCK JTAG clock Input only Slow — 37 60

TDO JTAG test data output Output only Slow Fast 38 61

Reset pin

RESET Bidirectional reset with Schmitt trigger

characteristics and noise filter

Bidirectional Medium — 13 20

Test pin

VPP_TEST Pin for testing purpose only. To be tied to ground

in normal operating mode.

———4774

Chapter 3 Signal Description

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 67

Medium and Fast pads can use slow configuration to reduce electromagnetic emission, at the cost of

reducing AC performance. For more information, see “Pad AC Specifications” in the device data sheet.

Table 3-3. Pin muxing

Port

PCR

Alternate

function1,2 Functions Peripheral3I/O

direction4

Pad speed5Pin

SRC = 0 SRC = 1 64-pin 100-pin

Port A (16-bit)

A[0] PCR[0] ALT0

ALT1

ALT2

ALT3

—

GPIO[0]

ETC[0]

SCK

F[0]

EIRQ[0]

SIUL

eTimer_0

DSPI_2

FCU_0

SIUL

I/O

Slow Medium — 51

A[1] PCR[1] ALT0

ALT1

ALT2

ALT3

—

GPIO[1]

ETC[1]

SOUT

F[1]

EIRQ[1]

SIUL

eTimer_0

DSPI_2

FCU_0

SIUL

I/O

Slow Medium — 52

A[2] PCR[2] ALT0

ALT1

ALT2

ALT3

—

GPIO[2]

ETC[2]

—

A[3]

SIN

ABS[0]

EIRQ[2]

SIUL

eTimer_0

—

FlexPWM_0

DSPI_2

MC_RGM

SIUL

I/O

—

Slow Medium — 57

A[3] PCR[3] ALT0

ALT1

ALT2

ALT3

—

GPIO[3]

ETC[3]

CS0

B[3]

ABS[1]

EIRQ[3]

SIUL

eTimer_0

DSPI_2

FlexPWM_0

MC_RGM

SIUL

I/O

Slow Medium 41 64

A[4] PCR[4] ALT0

ALT1

ALT2

ALT3

—

GPIO[4]

—

CS1

ETC[4]

FAB

EIRQ[4]

SIUL

—

DSPI_2

eTimer_0

MC_RGM

SIUL

I/O

—

I/O

Slow Medium 48 75

A[5] PCR[5] ALT0

ALT1

ALT2

ALT3

—

GPIO[5]

CS0

—

CS7

EIRQ[5]

SIUL

DSPI_1

—

DSPI_0

SIUL

I/O

—

Slow Medium 5 8

A[6] PCR[6] ALT0

ALT1

ALT2

ALT3

—

GPIO[6]

SCK

—

EIRQ[6]

SIUL

DSPI_1

—

SIUL

I/O

—

Slow Medium 2 2

Chapter 3 Signal Description

MPC5602P Microcontroller Reference Manual, Rev. 4

68 Freescale Semiconductor

A[7] PCR[7] ALT0

ALT1

ALT2

ALT3

—

GPIO[7]

SOUT

—

EIRQ[7]

SIUL

DSPI_1

—

SIUL

I/O

—

Slow Medium 3 4

A[8] PCR[8] ALT0

ALT1

ALT2

ALT3

—

GPIO[8]

—

SIN

EIRQ[8]

SIUL

—

DSPI_1

SIUL

I/O

—

Slow Medium 4 6

A[9] PCR[9] ALT0

ALT1

ALT2

ALT3

—

GPIO[9]

CS1

—

B[3]

FAULT[0]

SIUL

DSPI_2

—

FlexPWM_0

I/O

—

Slow Medium 60 94

A[10] PCR[10] ALT0

ALT1

ALT2

ALT3

—

GPIO[10]

CS0

B[0]

X[2]

EIRQ[9]

SIUL

DSPI_2

FlexPWM_0

SIUL

I/O

Slow Medium 52 81

A[11] PCR[11] ALT0

ALT1

ALT2

ALT3

—

GPIO[11]

SCK

A[0]

A[2]

EIRQ[10]

SIUL

DSPI_2

FlexPWM_0

SIUL

I/O

Slow Medium 53 82

A[12] PCR[12] ALT0

ALT1

ALT2

ALT3

—

GPIO[12]

SOUT

A[2]

B[2]

EIRQ[11]

SIUL

DSPI_2

FlexPWM_0

SIUL

I/O

Slow Medium 54 83

A[13] PCR[13] ALT0

ALT1

ALT2

ALT3

—

GPIO[13]

—

B[2]

—

SIN

FAULT[0]

EIRQ[12]

SIUL

—

FlexPWM_0

—

DSPI_2

FlexPWM_0

SIUL

I/O

—

Slow Medium 61 95

A[14] PCR[14] ALT0

ALT1

ALT2

ALT3

—

GPIO[14]

TXD

—

EIRQ[13]

SIUL

Safety Port_0

—

SIUL

I/O

—

Slow Medium 63 99

Table 3-3. Pin muxing (continued)

Port

PCR

Alternate

function1,2 Functions Peripheral3I/O

direction4

Pad speed5Pin

SRC = 0 SRC = 1 64-pin 100-pin

Chapter 3 Signal Description

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 69

A[15] PCR[15] ALT0

ALT1

ALT2

ALT3

—

GPIO[15]

—

RXD

EIRQ[14]

SIUL

—

Safety Port_0

SIUL

I/O

—

Slow Medium 64 100

Port B (16-bit)

B[0] PCR[16] ALT0

ALT1

ALT2

ALT3

—

GPIO[16]

TXD

—

DEBUG[0]

EIRQ[15]

SIUL

FlexCAN_0

—

SSCM

SIUL

I/O

—

Slow Medium 49 76

B[1] PCR[17] ALT0

ALT1

ALT2

ALT3

—

GPIO[17]

—

DEBUG[1]

RXD

EIRQ[16]

SIUL

—

SSCM

FlexCAN_0

SIUL

I/O

—

Slow Medium 50 77

B[2] PCR[18] ALT0

ALT1

ALT2

ALT3

—

GPIO[18]

TXD

—

DEBUG[2]

EIRQ[17]

SIUL

LIN_0

—

SSCM

SIUL

I/O

—

Slow Medium 51 79

B[3] PCR[19] ALT0

ALT1

ALT2

ALT3

—

GPIO[19]

—

DEBUG[3]

RXD

SIUL

—

SSCM

LIN_0

I/O

—

Slow Medium — 80

B[6] PCR[22] ALT0

ALT1

ALT2

ALT3

—

GPIO[22]

CLKOUT

CS2

—

EIRQ[18]

SIUL

Control

DSPI_2

—

SIUL

I/O

—

Slow Medium 62 96

B[7] PCR[23] ALT0

ALT1

ALT2

ALT3

—

GPIO[23]

—

AN[0]

RXD

SIUL

—

ADC_0

LIN_0

Input only — — 20 29

B[8] PCR[24] ALT0

ALT1

ALT2

ALT3

—

GPIO[24]

—

AN[1]

ETC[5]

SIUL

—

ADC_0

eTimer_0

Input only — — 22 31

Table 3-3. Pin muxing (continued)

Port

PCR

Alternate

function1,2 Functions Peripheral3I/O

direction4

Pad speed5Pin

SRC = 0 SRC = 1 64-pin 100-pin

Chapter 3 Signal Description

MPC5602P Microcontroller Reference Manual, Rev. 4

70 Freescale Semiconductor

B[9] PCR[25] ALT0

ALT1

ALT2

ALT3

—

GPIO[25]

—

AN[11]

SIUL

—

ADC_0

Input only — — 24 35

B[10] PCR[26] ALT0

ALT1

ALT2

ALT3

—

GPIO[26]

—

AN[12]

SIUL

—

ADC_0

Input only — — 25 36

B[11] PCR[27] ALT0

ALT1

ALT2

ALT3

—

GPIO[27]

—

AN[13]

SIUL

—

ADC_0

Input only — — 26 37

B[12] PCR[28] ALT0

ALT1

ALT2

ALT3

—

GPIO[28]

—

AN[14]

SIUL

—

ADC_0

Input only — — 27 38

B[13] PCR[29] ALT0

ALT1

ALT2

ALT3

—

GPIO[29]

—

AN[6]

emu. AN[0]

RXD

SIUL

—

ADC_0

emu. ADC_16

LIN_1

Input only — — 30 42

B[14] PCR[30] ALT0

ALT1

ALT2

ALT3

—

GPIO[30]

—

AN[7]

emu. AN[1]

ETC[4]

EIRQ[19]

SIUL

—

ADC_0

emu. ADC_16

eTimer_0

SIUL

Input only — — — 44

B[15] PCR[31] ALT0

ALT1

ALT2

ALT3

—

GPIO[31]

—

AN[8]

emu. AN[2]

EIRQ[20]

SIUL

—

ADC_0

emu. ADC_16

SIUL

Input only — — — 43

Table 3-3. Pin muxing (continued)

Port

PCR

Alternate

function1,2 Functions Peripheral3I/O

direction4

Pad speed5Pin

SRC = 0 SRC = 1 64-pin 100-pin

Chapter 3 Signal Description

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 71

Port C (16-bit)

C[0] PCR[32] ALT0

ALT1

ALT2

ALT3

—

GPIO[32]

—

AN[9]

emu. AN[3]

SIUL

—

ADC_0

emu. ADC_16

Input only — — — 45

C[1] PCR[33] ALT0

ALT1

ALT2

ALT3

—

GPIO[33]

—

AN[2]

SIUL

—

ADC_0

Input only — — 19 28

C[2] PCR[34] ALT0

ALT1

ALT2

ALT3

—

GPIO[34]

—

AN[3]

SIUL

—

ADC_0

Input only — — 21 30

C[3] PCR[35] ALT0

ALT1

ALT2

ALT3

—

GPIO[35]

CS1

—

TXD

EIRQ[21]

SIUL

DSPI_0

—

LIN_1

SIUL

I/O

—

Slow Medium — 10

C[4] PCR[36] ALT0

ALT1

ALT2

ALT3

—

GPIO[36]

CS0

X[1]

DEBUG[4]

EIRQ[22]

SIUL

DSPI_0

FlexPWM_0

SSCM

SIUL

I/O

—

Slow Medium — 5

C[5] PCR[37] ALT0

ALT1

ALT2

ALT3

—

GPIO[37]

SCK

—

DEBUG[5]

EIRQ[23]

SIUL

DSPI_0

—

SSCM

SIUL

I/O

—

Slow Medium — 7

C[6] PCR[38] ALT0

ALT1

ALT2

ALT3

—

GPIO[38]

SOUT

B[1]

DEBUG[6]

EIRQ[24]

SIUL

DSPI_0

FlexPWM_0

SSCM

SIUL

I/O

—

Slow Medium — 98

C[7] PCR[39] ALT0

ALT1

ALT2

ALT3

—

GPIO[39]

—

A[1]

DEBUG[7]

SIN

SIUL

—

FlexPWM_0

SSCM

DSPI_0

I/O

—

Slow Medium — 9

Table 3-3. Pin muxing (continued)

Port

PCR

Alternate

function1,2 Functions Peripheral3I/O

direction4

Pad speed5Pin

SRC = 0 SRC = 1 64-pin 100-pin

Chapter 3 Signal Description

MPC5602P Microcontroller Reference Manual, Rev. 4

72 Freescale Semiconductor

C[8] PCR[40] ALT0

ALT1

ALT2

ALT3

GPIO[40]

CS1

—

CS6

SIUL

DSPI_1

—

DSPI_0

I/O

—

Slow Medium 57 91

C[9] PCR[41] ALT0

ALT1

ALT2

ALT3

GPIO[41]

CS3

—

X[3]

SIUL

DSPI_2

—

FlexPWM_0

I/O

—

Slow Medium — 84

C[10

]

PCR[42] ALT0

ALT1

ALT2

ALT3

—

GPIO[42]

CS2

—

A[3]

FAULT[1]

SIUL

DSPI_2

—

FlexPWM_0

I/O

—

Slow Medium — 78

C[11

]

PCR[43] ALT0

ALT1

ALT2

ALT3

GPIO[43]

ETC[4]

CS2

—

SIUL

eTimer_0

DSPI_2

—

I/O

—

Slow Medium 33 55

C[12

]

PCR[44] ALT0

ALT1

ALT2

ALT3

GPIO[44]

ETC[5]

CS3

—

SIUL

eTimer_0

DSPI_2

—

I/O

—

Slow Medium 34 56

C[13

]

PCR[45] ALT0

ALT1

ALT2

ALT3

—

GPIO[45]

—

EXT_IN

EXT_SYNC

SIUL

—

CTU_0

FlexPWM_0

I/O

—

Slow Medium — 71

C[14

]

PCR[46] ALT0

ALT1

ALT2

ALT3

GPIO[46]

—

EXT_TGR

—

SIUL

—

CTU_0

—

I/O

—

Slow Medium — 72

C[15

]

PCR[47] ALT0

ALT1

ALT2

ALT3

—

GPIO[47]

—

A[1]

EXT_IN

EXT_SYNC

SIUL

—

FlexPWM_0

CTU_0

FlexPWM_0

I/O

—

Slow Medium — 85

Port D (16-bit)

D[0] PCR[48] ALT0

ALT1

ALT2

ALT3

GPIO[48]

—

B[1]

SIUL

—

FlexPWM_0

I/O

—

Slow Medium — 86

Table 3-3. Pin muxing (continued)

Port

PCR

Alternate

function1,2 Functions Peripheral3I/O

direction4

Pad speed5Pin

SRC = 0 SRC = 1 64-pin 100-pin

Chapter 3 Signal Description

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 73

D[1] PCR[49] ALT0

ALT1

ALT2

ALT3

GPIO[49]

—

EXT_TRG

SIUL

—

CTU_0

I/O

—

Slow Medium — 3

D[2] PCR[50] ALT0

ALT1

ALT2

ALT3

GPIO[50]

—

X[3]

SIUL

—

FlexPWM_0

I/O

—

Slow Medium — 97

D[3] PCR[51] ALT0

ALT1

ALT2

ALT3

GPIO[51]

—

A[3]

SIUL

—

FlexPWM_0

I/O

—

Slow Medium — 89

D[4] PCR[52] ALT0

ALT1

ALT2

ALT3

GPIO[52]

—

B[3]

SIUL

—

FlexPWM_0

I/O

—

Slow Medium — 90

D[5] PCR[53] ALT0

ALT1

ALT2

ALT3

GPIO[53]

CS3

F[0]

—

SIUL

DSPI_0

FCU_0

—

I/O

—

Slow Medium — 22

D[6] PCR[54] ALT0

ALT1

ALT2

ALT3

—

GPIO[54]

CS2

—

FAULT[1]

SIUL

DSPI_0

—

FlexPWM_0

I/O

—

Slow Medium — 23

D[7] PCR[55] ALT0

ALT1

ALT2

ALT3

GPIO[55]

CS3

F[1]

CS4

SIUL

DSPI_1

FCU_0

DSPI_0

I/O

Slow Medium 17 26

D[8] PCR[56] ALT0

ALT1

ALT2

ALT3

GPIO[56]

CS2

—

CS5

SIUL

DSPI_1

—

DSPI_0

I/O

—

Slow Medium 14 21

D[9] PCR[57] ALT0

ALT1

ALT2

ALT3

GPIO[57]

X[0]

TXD

—

SIUL

FlexPWM_0

LIN_1

—

I/O

—

Slow Medium 8 15

D[10

]

PCR[58] ALT0

ALT1

ALT2

ALT3

GPIO[58]

A[0]

—

SIUL

FlexPWM_0

—

I/O

—

Slow Medium — 53

D[11

]

PCR[59] ALT0

ALT1

ALT2

ALT3

GPIO[59]

B[0]

—

SIUL

FlexPWM_0

—

I/O

—

Slow Medium — 54

Table 3-3. Pin muxing (continued)

Port

PCR

Alternate

function1,2 Functions Peripheral3I/O

direction4

Pad speed5Pin

SRC = 0 SRC = 1 64-pin 100-pin

Chapter 3 Signal Description

MPC5602P Microcontroller Reference Manual, Rev. 4

74 Freescale Semiconductor

D[12

]

PCR[60] ALT0

ALT1

ALT2

ALT3

—

GPIO[60]

X[1]

—

RXD

SIUL

FlexPWM_0

—

LIN_1

I/O

—

Slow Medium 45 70

D[13

]

PCR[61] ALT0

ALT1

ALT2

ALT3

GPIO[61]

A[1]

—

SIUL

FlexPWM_0

—

I/O

—

Slow Medium 44 67

D[14

]

PCR[62] ALT0

ALT1

ALT2

ALT3

GPIO[62]

B[1]

—

SIUL

FlexPWM_0

—

I/O

—

Slow Medium 46 73

D[15

]

PCR[63] ALT0

ALT1

ALT2

ALT3

—

GPIO[63]

—

AN[10]

emu. AN[4]

SIUL

—

ADC_0

emu. ADC_16

Input only — — — 41

Port E (16-bit)

E[1] PCR[65] ALT0

ALT1

ALT2

ALT3

—

GPIO[65]

—

AN[4]

SIUL

—

ADC_0

Input only — — 18 27

E[2] PCR[66] ALT0

ALT1

ALT2

ALT3

—

GPIO[66]

—

AN[5]

SIUL

—

ADC_0

Input only — — 23 32

E[3] PCR[67] ALT0

ALT1

ALT2

ALT3

—

GPIO[67]

—

AN[6]

SIUL

—

ADC_0

Input only — — 30 42

E[4] PCR[68] ALT0

ALT1

ALT2

ALT3

—

GPIO[68]

—

AN[7]

SIUL

—

ADC_0

Input only — — — 44

E[5] PCR[69] ALT0

ALT1

ALT2

ALT3

—

GPIO[69]

—

AN[8]

SIUL

—

ADC_0

Input only — — — 43

Table 3-3. Pin muxing (continued)

Port

PCR

Alternate

function1,2 Functions Peripheral3I/O

direction4

Pad speed5Pin

SRC = 0 SRC = 1 64-pin 100-pin

Chapter 3 Signal Description

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 75

3.4 CTU / ADC / FlexPWM / eTimer connections

Figure 3-3 shows the interconnections between the CTU, ADC, FlexPWM, and eTimer.

E[6] PCR[70] ALT0

ALT1

ALT2

ALT3

—

GPIO[70]

—

AN[9]

SIUL

—

ADC_0

Input only — — — 45

E[7] PCR[71] ALT0

ALT1

ALT2

ALT3

—

GPIO[71]

—

AN[10]

SIUL

—

ADC_0

Input only — — — 41

1ALT0 is the primary (default) function for each port after reset.

2Alternate functions are chosen by setting the values of the PCR.PA bitfields inside the SIU module.

PCR.PA = 00 ALT0; PCR.PA = 01 ALT1; PCR.PA = 10 ALT2; PCR.PA = 11 ALT3. This is intended to

select the output functions; to use one of the input functions, the PCR.IBE bit must be written to ‘1’, regardless of

the values selected in the PCR.PA bitfields. For this reason, the value corresponding to an input only function is

reported as “—”.

3Module included on the MCU.

4Multiple inputs are routed to all respective modules internally. The input of some modules must be configured by

setting the values of the PSMIO.PADSELx bitfields inside the SIUL module.

5Programmable via the SRC (Slew Rate Control) bits in the respective Pad Configuration Register.

6ADC0.AN emulates ADC1.AN. This feature is used to provide software compatibility between MPC5602P and

MPC5604P. Refer to ADC chapter of reference manual for more details.

Table 3-3. Pin muxing (continued)

Port

PCR

Alternate

function1,2 Functions Peripheral3I/O

direction4

Pad speed5Pin

SRC = 0 SRC = 1 64-pin 100-pin

Chapter 3 Signal Description

MPC5602P Microcontroller Reference Manual, Rev. 4

76 Freescale Semiconductor

Figure 3-3. CTU / ADC / FlexPWM / eTimer connections

Table 3-4. CTU / ADC / FlexPWM / eTimer connections

Source module

(Signal)

Target module

(Signal) Comment

PWM (Master Reload) CTU (PWM Reload) From PWM sub-module 0

PWM (OUT_TRIG0_0) CTU (PWM_ODD_0) OUT_TRIG0 sub-module 0

PWM (OUT_TRIG1_0) CTU (PWM_EVEN_0) OUT_TRIG1 sub-module 0

PWM (PWMX0) CTU (PWM_REAL_0) —

PWM (OUT_TRIG0_1) CTU (PWM_ODD_1) OUT_TRIG0 sub-module 1

PWM (OUT_TRIG1_1) CTU (PWM_EVEN_1) OUT_TRIG1 sub-module 1

PWM (PWMX1) CTU (PWM_REAL_1) —

PWM (OUT_TRIG0_2) CTU (PWM_ODD_2) OUT_TRIG0 sub-module 2

PWM (OUT_TRIG1_2) CTU (PWM_EVEN_2) OUT_TRIG1 sub-module 2

PWM (PWMX2) CTU (PWM_REAL_2) —

PWM (OUT_TRIG0_3) CTU (PWM_ODD_3) OUT_TRIG0 sub-module 3

PWM (OUT_TRIG1_3) CTU (PWM_EVEN_3) OUT_TRIG1 sub-module 3

PWM (PWMX3) CTU (PWM_REAL_3) —

External pins

PWMA0

PWMB0

PWMA1

PWMB1

PWMA2

PWMB2

PWMA3

PWMB3

Master reload

FAULT0

FAULT1

OUT_TRIG0_0

OUT_TRIG0_1

OUT_TRIG0_2

OUT_TRIG0_3

OUT_TRIG1_0

OUT_TRIG1_1

OUT_TRIG1_2

OUT_TRIG1_3

PWMX0

PWMX1

PWMX2

PWMX3

FlexPWM

EXT_FORCE

CLOCK

EXT_SYNC

PWM_REL

PWM_ODD_0

PWM_ODD_1

PWM_ODD_2

PWM_ODD_3

PWM_EVEN_0

PWM_EVEN_1

PWM_EVEN_2

TRIGGER_0

RPWM_0

RPWM_1

ADC_CMD_0

NEXT_CMD_0

FIFO_0

TRIGGER_1

ADC_CMD_1

NEXT_CMD_1

FIFO_1

EXT_IN

EXT_TRG

CTU

PWM_EVEN_3

RPWM_2

RPWM_3

ETMR0_IN

ETIMER0_TRG

ETIMER1_TRG

AUX_0

AUX_1

AUX_2

eTimer0 External pins

DSPI1

SCK

ADC0

(ipp_ind_injection_trg)

External pins

CTU/ADC

IP Interface

External pins

Chapter 3 Signal Description

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 77

PWM (PWMA0) SIU lite —

PWM (PWMB0) SIU lite —

PWM (PWMX1) SIU lite —

PWM (PWMA1) SIU lite —

PWM (PWMB1) SIU lite —

PWM (PWMX2) SIU lite —

PWM (PWMA2) SIU lite —

PWM (PWMB2) SIU lite —

PWM (PWMX3) SIU lite —

PWM (PWMA3) SIU lite —

PWM (PWMB3) SIU lite —

PWM (PWMX3) SIU lite —

eTimer_0 (T1) PWM (EXT_FORCE) —

eTimer_0 (T2) CTU (ETMR0_IN) —

eTimer_0 (T5) ADC_0 ADC injected conversion request signal (for non CTU mode of

operation)

CTU (ETIMER0_TRG) eTimer_0 (AUX_0) —

CTU (ETIMER1_TRG) eTimer_0 (AUX_1) —

CTU (TRIGGER_0) ADC_0 (through

CTU/ADC IP Interface)

—

CTU (TRIGGER_1) Virtual ADC_1 (through

CTU/ADC IP Interface)

—

CTU (ADC_CMD_0) ADC_0 (through

CTU/ADC IP Interface)

16-bit signal

CTU (ADC_CMD_1) Virtual ADC_1 (through

CTU/ADC IP Interface)

16-bit signal

CTU (EXT_TGR) SIU lite —

ADC_0 (EOC) CTU (NEXT_CMD_0) End Of Conversion should be used as next command request

signal

Virtual ADC_1 (EOC) CTU (NEXT_CMD_1)

(through CTU/ADC IP

Interface)

End Of Conversion should be used as next command request

signal

ADC_0 CTU (FIFO_0) 18-bit signal

Virtual ADC_1 CTU (FIFO_1) (through

CTU/ADC IP Interface)

18-bit signal

SIU lite CTU (EXT_IN) The same GPIO pin as used for CTU (EXT_IN) and the PWM

(EXT_SYNC)

Table 3-4. CTU / ADC / FlexPWM / eTimer connections (continued)

Source module

(Signal)

Target module

(Signal) Comment

Chapter 3 Signal Description

MPC5602P Microcontroller Reference Manual, Rev. 4

78 Freescale Semiconductor

SIU lite PWM (EXT_SYNC) The same GPIO pin as used for CTU (EXT_IN) and the PWM

(EXT_SYNC)

SIU lite PWM (FAULT0) —

SIU lite PWM (FAULT1) —

DSPI_1 (SCK) eTimer_0 (AUX_2) —

Table 3-4. CTU / ADC / FlexPWM / eTimer connections (continued)

Source module

(Signal)

Target module

(Signal) Comment

Chapter 4 Clock Description

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 79

Chapter 4

Clock Description

This chapter describes the clock architectural implementation for MPC5602P.

The following clock related modules are implemented on the MPC5602P:

• Clock, Reset, and Mode Handling

— Clock Generation Module (CGM) (see Chapter 5, “Clock Generation Module (MC_CGM))

— Reset Generation Module (RGM) (see Chapter 8, “Reset Generation Module (MC_RGM))

— Mode Entry Module (ME) (see Chapter 7, “Mode Entry Module (MC_ME))

• High Frequency Oscillator (XOSC) (see Section 4.7, “XOSC external crystal oscillator)

• High Frequency RC Oscillator (IRC) (see Section 4.6, “IRC 16 MHz internal RC oscillator

(RC_CTL))

• FMPLL (FMPLL_0) (see Section 4.8, “Frequency Modulated Phase Locked Loop (FMPLL))

• CMU (CMU_0) (see Section 4.9, “Clock Monitor Unit (CMU))

• Periodic Interrupt Timer (PIT) (see Chapter 30, “Periodic Interrupt Timer (PIT))

• System Timer Module (STM_0) (see Chapter 31, “System Timer Module (STM))

• Software Watchdog Timer (SWT_0) (see Section 27.3, “Software Watchdog Timer (SWT))

4.1 Clock architecture

The system and peripheral clocks are generated from three sources:

• IRC—internal RC oscillator clock

• XOSC—oscillator clock

• FMPLL_0 clock output

The clock architecture is shown in Figure 4-1, Figure 4-2, and Figure 4-3.

The frequencies shown in Figure 4-1 represent only one possible setting.

NOTE

MC_PLL_CLK and SP_PLL_CLK are SYS_CLK.

Chapter 4 Clock Description

MPC5602P Microcontroller Reference Manual, Rev. 4

80 Freescale Semiconductor

Figure 4-1. MPC5602P system clock generation

PHI_PCS

PHI

FMPLL_0

64 MHz

CMU_0

1, 2, 3, ... 16

Clock Out Divider

MC_PLL Divider

CMU_PLL Divider

SP_PLL Divider

[0]

[2]

[4]

[5]

[8]

AUX Clock Selector 0

AUX Clock Selector 1

[0]

[2]

[4]

[5]

[8]

System Clock Selector 0

RC Oscillator

(IRC)

Oscillator

(XOSC40)

N.C.

IRC_CLK

16 MHz

SYS_CLK

64 MHz—50%

IRC_CLK

16 MHz

XOSC_CLK

8 MHz—50%

Clockout

30/32 MHz

1, 2, 4, 8

Clock Out Selector

[0]

[1]

[2]

[3]

1, 2, 3, ... 16

[0]

[2]

[4]

[5]

[8]

AUX Clock Selector 2

XOSC_CLK

8 MHz—50%

FMPLL_0_PCS_CLK

FMPLL_0_CLK

NOTE: FlexRay protocol clock does not support IRC as a clock source.

FMPLL_0_CLK

XOSC_CLK

IRC_CLK

FMPLL_0_PCS_CLK—64 MHz, 50%

FMPLL_0_CLK—64 MHz, 50%

SYS_CLK = System Clock

N.C.

50%

Chapter 4 Clock Description

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 81

Figure 4-2. MPC5602P system clock distribution Part A

SafetyPort

Protocol Clock

Module Clock

XOSC_CLK

SP_CLK

eTimer_0

FlexPWM

ADC_0

Module Clock

DMA Support

CTU

SYS_CLK

MC_CLK

DSPI_0

DSPI_1

DSPI_2

CTU Trigger Output

CTU Sync Event Input

Legend:

BIU

IPS @ SYS_CLK

BIU

MC_CLK

Module Clock

BIU

MC_CLK

Module Clock

BIU

MC_CLK

Protocol Clock

Module Clock

BIU

Module Clock

BIU

SYS_CLK

Module Clock

BIU

SYS_CLK

Module Clock

BIU

SYS_CLK

SP_CLK

IPS @ MC_CLK

IPS @ SP_CLK

NOTE: MC_CLK and SP_CLK are SYS_CLK

Chapter 4 Clock Description

MPC5602P Microcontroller Reference Manual, Rev. 4

82 Freescale Semiconductor

Figure 4-3. MPC5602P system clock distribution Part B

4.2 Available clock domains

This section describes the various clock domains available on MPC5602P.

4.2.1 FMPLL input reference clock

The input reference clock for FMPLL_0 is always the external crystal oscillator clock (XOSC).

4.2.2 Clock selectors

4.2.2.1 System clock selector 0 for SYS_CLK

The system clock selector 0 selects the clock source for the system clock (SYS_CLK) from clock signals:

SYS_CLK

IRCOSC_CLK

SYS_CLK

IRCOSC_CLK

XOSC_CLK

SYS_CLK

IPS

SYS_CLK

IPS

SYS_CLK

LINFlex_0

Module clock

BIU

LINFlex_1

Module clock

BIU

DMA Mux

Module clock

BIU

eDMA2

Module clock

BIU

INTC

Module clock

BIU

SWT

Module clock

Protocol clock

BIU

FlexCAN

Module clock

Protocol clock

BIU

FCU

Module clock

Protocol clock

BIU

STM

Module clock

BIU

ECSM

Module clock

BIU

SIUL

Module clock

BIU

SSCM

Module clock

BIU

WKPU

Module clock

BIU

PIT/RTI

Module clock

BIU

Data Flash 0

Code Flash 0

MC Unit

Module clock

BIU

CGM

RGM

PCU

PMU

FMPLL_0

CQM_0

IRCOSC

XOSC

SYS_CLK

Platform Flash Controller

Module clock

BIU

Chapter 4 Clock Description

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 83

• Internal RC oscillator clock (IRC)

• Progressive output clock of FMPLL_0

• Directly from the oscillator clock (XOSC)

Its behavior is configured via software through ME_x_MC register of the ME module.

When the standard boot from internal flash is selected via the boot configuration pins, the clock source for

the system clock (SYS_CLK) after reset (DRUN mode) is the internal RC oscillator (IRC).

4.2.3 Auxiliary Clock Selector 0

There is no Auxiliary Clock present on MPC5602P device, but to maintain the software compatibility,

corresponding register in MC_CGM (CGM_AC0_SC) has been implemented through which user can

select any clock source from the given auxiliary clock sources. As there is no auxiliary clock, all the

auxiliary clock sources have been tied to ‘0’.

4.2.4 Auxiliary Clock Selector 1

There is no Auxiliary Clock present on MPC5602P device, but to maintain the software compatibility,

corresponding register in MC_CGM (CGM_AC1_SC) has been implemented through which user can

select any clock source from the given auxiliary clock sources. As there is no auxiliary clock, all the

auxiliary clock sources have been tied to ‘0’.

4.2.5 Auxiliary Clock Selector 2

There is no Auxiliary Clock present on MPC5602P device, but to maintain the software compatibility,

corresponding register in MC_CGM (CGM_AC2_SC) has been implemented through which user can

select any clock source from the given auxiliary clock sources. As there is no auxiliary clock, all the

auxiliary clock sources have been tied to ‘0’.

4.2.6 Auxiliary clock dividers

As there is no auxiliary clock present on MPC5602P, there is no point in having the auxiliary clock

dividers. To maintain the software compatibility, one divider corresponding to every auxiliary clock has

been implemented. Corresponding registers have been implemented in MC_CGM which can be accessed

by user but have no impact in device. These registers are CGM_AC0_DC0, CGM_AC1_DC0, and

CGM_AC2_DC0

4.2.7 External clock divider

The output clock divider provides a nominal 50% duty cycle clock and allows the selected output clock

source to be divided with these divide options:

• ÷ 1, ÷ 2, ÷ 4, ÷ 8

Chapter 4 Clock Description

MPC5602P Microcontroller Reference Manual, Rev. 4

84 Freescale Semiconductor

4.3 Alternate module clock domains

This section lists the different clock domains for each module. If not otherwise noted, all modules on the

MPC5602P device are clocked on the SYS_CLK.

4.3.1 FlexCAN clock domains

The FlexCAN modules have two distinct software controlled clock domains. One of the clock domains is

always derived from the system clock. This clock domain includes the message buffer logic. The source

for the second clock domain can be either the system clock (SYS_CLK) or a direct feed from the oscillator

pin XOSC_CLK. The logic in the second clock domain controls the CAN interface pins. The CLK_SRC

bit in the FlexCAN CTRL register selects between the system clock and the oscillator clock as the clock

source for the second domain. Selecting the oscillator as the clock source ensures very low jitter on the

CAN bus. System software can gate both clocks by writing to the MDIS bit in the FlexCAN MCR.

Figure 22-1 shows the two clock domains in the FlexCAN modules.

Refer to Chapter 22, “FlexCAN for more information on the FlexCAN modules.

4.3.2 SWT clock domains

The SWT module has two distinct clock domains. The first clock domain (Module Clock) is always

supplied from the SYS_CLK. This clock domain includes the register interface.

The source for the second clock domain (Protocol Clock) is always the IRC generated by the internal RC

oscillator.

4.3.3 Cross Triggering Unit (CTU) clock domains

The CTU module has two distinct clock domains. The first clock domain (Module Clock) is supplied from

the SYS_CLK. This clock domain includes the Command Buffer logic.

The source for the second clock domain (Protocol Clock) is the MC_PLL_CLK. The logic in the Protocol

Clock domain controls the CTU interface pins to the eTimer module and the ADC module.

4.3.4 Peripherals behind the IPS bus clock sync bridge

4.3.4.1 FlexPWM clock domain

The FlexPWM module has only one clock domain. The FlexPWM module is clocked from the

MC_PLL_CLK. Therefore, it is placed behind the IPS bus clock sync bridge.

4.3.4.2 eTimer_0 clock domain

The eTimer_0 module has only one clock domain. The eTimer_0 module is clocked from the

MC_PLL_CLK. Therefore, it is placed behind the IPS bus clock sync bridge.

Chapter 4 Clock Description

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 85

4.3.4.3 ADC_0 clock domain

The ADC_0 module has only one clock domain. The ADC_0 module is clocked from the MC_PLL_CLK.

Therefore, it is placed behind the IPS bus clock sync bridge.

4.3.4.4 Safety Port clock domains

The Safety Port module has two distinct software-controlled clock domains. The first clock domain

(Module Clock) is always supplied from the SP_PLL_CLK. The source for the second clock domain

(Protocol Clock) can either be the SP_PLL_CLK or the XOSC_CLK.

The user must ensure that the frequency of the first clock domain (Module Clock) clocked from the

MC_PLL_CLK is always the same or greater than the clock selected for the second clock domain

(Protocol Clock).

4.4 Clock behavior in STOP and HALT mode

In this section the term “resume” is used to describe the transition from STOP and HALT mode back to a

RUN mode.

The MPC5602P supports the STOP and the HALT modes. These two modes allow to put the device into

a power saving mode with the configuration options defined in the ME module.

The following constraints are applied on MPC5602P to guarantee that in all modes of operation a resume

from STOP or HALT mode is always possible without the need to reset:

• STOP and HALT mode:

— SIUL clock is not gateable

— SIUL filter for external interrupt capable pins is always clocked with IRC

— Resume via interrupt that can be generated by any peripheral that clock is not gated

— Resume via NMI pin is always possible if once enabled after reset (no software configuration

that could block resume afterwards)

• STOP mode:

— IRC can NOT be switched off

— The System Clock Selector 0 is switched to the IRC and therefore the SYS_CLK is feed by the

IRC signal

— Resume via external interrupt pin is always possible (if not masked)

• HALT mode:

— The output of the System Clock Selector 0 can only be switched to a running clock input

— Resume via external interrupt pin is always possible (if not masked) and IRC is not switched off

4.5 System clock functional safety

This section shows the MPC5602P modules used to detect clock failures:

Chapter 4 Clock Description

MPC5602P Microcontroller Reference Manual, Rev. 4

86 Freescale Semiconductor

• The Clock Monitoring Unit (CMU_0) monitors the clock frequency of the FMPLL_0 and the

XOSC signal against the IRC and provides clock out of range information about the monitored

clock signals.

• FMPLL_0 provides a signal that indicates a loss of lock. Each loss of lock signal is sent to the CGM

module.

Upon the detection of one of the above mentioned failures, the MPC5602P device either asserts a reset,

generates an interrupt, or sends the device into the SAFE state.

The reaction to each of the clock failures and system parameters (like active clocks and SYS_CLK clock

source) that become active in SAFE state are under software control and can be configured in the ME

module.

4.6 IRC 16 MHz internal RC oscillator (RC_CTL)

The IRC output frequency can be trimmed using RCTRIM bits. After a power-on reset, the IRC is trimmed

using a factory test value stored in test flash memory. However, after a power-on reset the test flash

memory value is not visible at RC_CTL[RCTRIM], and this field shows a value of zero. Therefore, be

aware that the RC_CTL[RCTRIM] field does not reflect the current trim value until you have written to

it. Pay particular attention to this feature when you initiate a read-modify-write operation on RC_CTL,

because a RCTRIM value of zero may be unintentionally written back and this may alter the IRC

frequency. In this case, you should calibrate the IRC using the CMU.

In this oscillator, two's complement trimming method is implemented. So the trimming code increases

from -32 to 31. As the trimming code increases, the internal time constant increases and frequency reduces.

Please refer to device datasheet for average frequency variation of the trimming step.

Address:

0xC3FE_0060

(Base + 0x0000)

Access: Supervisor read/write; User read-only

0123456789101112131415

R0000000000 RCTRIM[5:0]

Reset0000000000000000

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

R0000000000000000

Reset0000000000000000

Figure 4-4. RC Control register (RC_CTL)

Table 4-1. RC_CTL field descriptions

Field Description

RCTRIM[5:0] Main RC trimming bits

Chapter 4 Clock Description

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 87

4.7 XOSC external crystal oscillator

The external crystal oscillator (XOSC) operates in the range of 4 MHz to 40 MHz. The XOSC digital

interface contains the control and status registers accessible for the external crystal oscillator.

Main features are:

• Oscillator clock available interrupt

• Oscillator bypass mode

4.7.1 Functional description

The crystal oscillator circuit includes an internal oscillator driver and an external crystal circuitry. The

XOSC provides an output clock to the PLL or it is used as a reference clock to specific modules depending

on system needs.

The crystal oscillator can be controlled by the ME:

• Control by ME module. The OSCON bit of the ME_xxx_MCRs controls the powerdown of

oscillator based on the current device mode while S_OSC of ME_GS register provides the

oscillator clock available status.

After system reset, the oscillator is put to power down state and software has to switch on when required.

Whenever the crystal oscillator is switched on from off state, OSCCNT counter starts and when it reaches

the value EOCV[7:0] × 512, oscillator clock is made available to the system. Also an interrupt pending bit

I_OSC of OSC_CTL register is set. An interrupt will be generated if the interrupt mask bit M_OSC is set.

The oscillator circuit can be bypassed by setting OSC_CTL[OSCBYP]. This bit can only be set by the

software. System reset is needed to reset this bit. In this bypass mode, the output clock has the same

polarity as external clock applied on EXTAL pin and the oscillator status is forced to ‘1’. The bypass

configuration is independent of the powerdown mode of the oscillator.

Table 4-2 shows the truth table of different configurations of oscillator.

Table 4-2. Crystal oscillator truth table

ENABLE BYP XTALIN EXTAL CK_OSCM XOSC Mode

0 0 No crystal,

High Z

No crystal,

High Z

0 Power down, IDDQ

x 1 x Ext clock EXTAL Bypass, XOSC disabled

1 0 Crystal Crystal EXTAL Normal, XOSC enabled

Chapter 4 Clock Description

MPC5602P Microcontroller Reference Manual, Rev. 4

88 Freescale Semiconductor

4.7.2 Register description

Table 4-3. OSC_CTL memory map

Offset from

OSC_CTL_BASE

(0xC3FE_0000)

Access

Reset value Location

0x0000 OSC_CTL—Oscillator control register R/W 0x0080_0000 on page 88

0x0004–0x000F Reserved

Address:

0xC3FE_0000

(Base + 0x0000)

Access: Supervisor read/write; User read-only

0123456789101112131415

ROSC

BYP

0000000EOCV[7:0]

Reset0000000010000000

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

RM_

OSC

0000000I_

OSC 0000000

Ww1c

Reset0000000000000000

Figure 4-5. Crystal Oscillator Control register (OSC_CTL)

Table 4-4. OSC_CTL field descriptions

Field Description

OSCBYP Crystal Oscillator bypass

This bit specifies whether the oscillator should be bypassed or not. Software can only set this bit.

System reset is needed to reset this bit.

0: Oscillator output is used as root clock.

1: EXTAL is used as root clock.

EOCV[7:0] End of Count Value

These bits specify the end of count value to be used for comparison by the oscillator stabilization

counter OSCCNT after reset or whenever it is switched on from the off state. This counting period

ensures that external oscillator clock signal is stable before it can be selected by the system. When

oscillator counter reaches the value EOCV[7:0]*512, oscillator available interrupt request is generated.

The reset value of this field depends on the device specification. The OSCCNT counter will be kept

under reset if oscillator bypass mode is selected.

M_OSC Crystal oscillator clock interrupt mask

0: Crystal oscillator clock interrupt masked

1: Crystal oscillator clock interrupt enabled

I_OSC Crystal oscillator clock interrupt

This bit is set by hardware when OSCCNT counter reaches the count value EOCV[7:0]*512. It is

cleared by software by writing 1.

0: No oscillator clock interrupt occurred

1: Oscillator clock interrupt pending

Chapter 4 Clock Description

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 89

4.8 Frequency Modulated Phase Locked Loop (FMPLL)

4.8.1 Introduction

This section describes the features and functions of the FMPLL module implemented in MPC5602P.

4.8.2 Overview

The FMPLL enables the generation of high speed system clocks from a common 4–40 MHz input clock.

Further, the FMPLL supports programmable frequency modulation of the system clock. The PLL

multiplication factor and output clock divider ratio are all software configurable.

The FMPLL block diagram is shown in Figure 4-6.

Figure 4-6. FMPLL block diagram

4.8.3 Features

The FMPLL has the following major features:

• Input clock frequency 4–40 MHz

• Voltage controlled oscillator (VCO) range from 256 MHz to 512 MHz

• Reduced frequency divider (RFD) for reduced frequency operation without forcing the FMPLL to

relock

• Frequency modulated PLL

— Modulation enabled/disabled through software

— Triangle wave modulation

• Programmable modulation depth

— ±0.25% to ±4% deviation from center spread frequency

— –0.5% to +8% deviation from down spread frequency

— Programmable modulation frequency dependent on reference frequency

• Self-clocked mode (SCM) operation

• 4 available modes

— Normal mode

— Progressive clock switching

BUFFER

Charge

Pump

Low Pass

Filter

VCO

IDF

DIV2

Loop

Division

Factor

XOSC

Output

PHI

(LDF)

CR[NDIV]

Division

Factor

(ODF)

CR[ODF]

DIV4

Chapter 4 Clock Description

MPC5602P Microcontroller Reference Manual, Rev. 4

90 Freescale Semiconductor

— Normal Mode with SSCG

— Powerdown mode

4.8.4 Memory map

Table 4-5 shows the memory map locations. Addresses are given as offsets of the module base address.

4.8.5 Register description

The PLL operation is controlled by two registers. Those registers can only be written in supervisor mode.

4.8.5.1 Control Register (CR)

Table 4-5. FMPLL memory map

Offset from

ME_CGM_BASE

FMPLL_0: 0xC3FE_00A0

1FMPLL_x are mapped through the ME_CGM Register Slot

Access

Reset value Location

0x0000 CR—Control Register R/W 0x0080_0000 on page 90

0x0004 MR—Modulation register R/W 0x0080_0000 on page 92

0x0004–0x000F Reserved

Address:

Base + 0x0000

FMPLL_0 = 0xC3FE_00A0

Access: Supervisor read/write

User read-only

0123456789101112131415

R 0 0 IDF[3:0] ODF[1:0] 0NDIV[6:0]

Reset0000010101000000

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

0000000

en_pll

_sw

unlock

_once

0 i_lock

s_lock pll_fail

_mask

pll_fai

l_flag 1

Ww1c w1c

Reset0000000000000001

Figure 4-7. Control Register (CR)

Chapter 4 Clock Description

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 91

Table 4-6. CR field descriptions

Field Description

IDF[3:0] Input Division Factor

The value of this field sets the PLL input division factor.

0000: Divide by 1

0001: Divide by 2

0010: Divide by 3

0011: Divide by 4

0100: Divide by 5

0101: Divide by 6

0110: Divide by 7

0111: Divide by 8

1000: Divide by 9

1001: Divide by 10

1010: Divide by 11

1011: Divide by 12

1100: Divide by 13

1101: Divide by 14

1110: Divide by 15

1111: Clock Inhibit

ODF[1:0] Output Division Factor

The value of this field sets the PLL output division factor.

00: Divide by 2

01: Divide by 4

10: Divide by 8

11: Divide by 16

NDIV[6:0] Loop Division Factor

The value of this field sets the PLL loop division factor.

0000000–0011111: Reserved

0100000: Divide by 32

0100001: Divide by 33

0100010: Divide by 34

...

1011111: Divide by 95

1100000: Divide by 96

1100001–1111111: Reserved

en_pll_sw This bit is used to enable progressive clock switching. After the PLL locks, the PLL output initially

is divided by 8, and then progressively decreases until it reaches divide-by-1.

Note: The PLL output should not be used if a non-changing clock is needed, such as for serial

communications, until the division has finished.

0: Progressive clock switching disabled

1: Progressive clock switching enabled

unlock_once This bit is a sticky indication of PLL loss of lock condition. Unlock_once is set when the PLL loses

lock. Whenever the PLL reacquires lock, unlock_once remains set. unlock_once is cleared after a

POR event.

i_lock This bit is set by hardware whenever there is a lock/unlock event.It is cleared by software, writing 1.

s_lock This bit indicates whether the PLL has acquired lock.

0: PLL unlocked

1: PLL locked

Chapter 4 Clock Description

MPC5602P Microcontroller Reference Manual, Rev. 4

92 Freescale Semiconductor

4.8.5.2 Modulation Register (MR)

pll_fail_mask This bit masks the pll_fail output.

0: pll_fail not masked

1: pll_fail masked

pll_fail_flag This bit is asynchronously set by hardware whenever a loss of lock event occurs while PLL is

switched on. It is cleared by software, writing 1.

Address:

Base + 0x0004 Access: Supervisor read/write

User read-only

0123456789101112131415

STRB

_BYPA

0SPRD

_SEL

MOD_PERIOD

Reset0000000000000000

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

RFM_

EN INC_STEP

Reset0000000000000000

Figure 4-8. Modulation Register (MR)

Table 4-7. MR field descriptions

Field Description

STRB_BYPASS Strobe bypass

The STRB_BYPASS signal bypasses the STRB signal used inside the PLL to latch the correct

values for control bits (INC_STEP, MOD_PERIOD and SPRD_SEL).

0: STRB latches the PLL modulation control bits.

1: STRB is bypassed. In this case, the control bits need to be static. The control bits must be

changed only when PLL is in power down mode.

SPRD_SEL Spread type selection

The SPRD_SEL bit selects the spread type in Frequency Modulation mode.

0: Center spread

1: Down spread

MOD_PERIOD Modulation period

The MOD_PERIOD field is the binary equivalent of the value modperiod derived from following

formula:

where:

fref: represents the frequency of the feedback divider

fmod: represents the modulation frequency

Table 4-6. CR field descriptions (continued)

Field Description

modperiod fref

mod



--------------------

Chapter 4 Clock Description

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 93

4.8.6 Functional description

4.8.6.1 Normal mode

In Normal mode, the PLL inputs are driven by the Control Register (CR). This means that when the PLL

is locked, the PLL output clock (PHI) is derived from the reference clock (XOSC) through this

relationship:

Eqn. 4-1

where the value of idf (Input Division Factor), ldf (Loop Division Factor), and odf (Output Division Factor)

are set in the CR as shown in Table 4-6. idf and odf are specified in the IDF and ODF bitfields, respectively;

ldf is specified in the NDIV bitfield.

4.8.6.2 Progressive clock switching

Progressive clock switching allows to switch system clock to PLL output clock stepping through different

division factors. This means that the current consumption gradually increases and, in turn, voltage

regulator response is improved.

This feature can be enabled by programming bit en_pll_sw in the CR. Then, when the PLL is selected as

the system clock, the output clock progressively increases its frequency as shown in Table 4-8.

FM_EN Frequency modulation enable

The FM_EN bit enables the frequency modulation.

0: Frequency Modulation disabled

1: Frequency Modulation enabled

INC_STEP Increment step

The INC_STEP field is the binary equivalent of the value incstep derived from following formula:

where:

md: represents the peak modulation depth in percentage

(Center spread — pk-pk = ±md, Downspread — pk-pk = –2 × md)

MDF: represents the nominal value of loop divider (NDIV in PLL Control Register).

Table 4-8. Progressive clock switching on pll_select rising edge

Number of PLL output clock cycles ck_pll_div frequency (PLL output frequency)

8 (ck_pll_out frequency) 8

16 (ck_pll_out frequency) 4

32 (ck_pll_out frequency) 2

Table 4-7. MR field descriptions (continued)

Field Description

incstep round 215 1–mdMDF

100 5MODPERIOD

---------------------------------------------------------------





phi xosc ldf

idf odf

-----------------------

Chapter 4 Clock Description

MPC5602P Microcontroller Reference Manual, Rev. 4

94 Freescale Semiconductor

Figure 4-9. Progressive clock switching scheme

4.8.6.3 Normal Mode with frequency modulation

The FMPLL default mode is without frequency modulation enabled. When frequency modulation is

enabled, however, two parameters must be set to generate the desired level of modulation: the PERIOD,

and the STEP. The modulation waveform is always a triangle wave and its shape is not programmable.

Frequency modulation is activated as follows:

1. Configure the FM modulation characteristics: MOD_PERIOD, INC_STEP.

2. Enable the FM modulation by programming bit SSCG_EN of the MR to ‘1’. FM modulated mode

can be enabled only when PLL is in lock state.

There are two ways to latch these values inside the FMPLL, depending on the value of bit STRB_BYPASS

in the MR.

If STRB_BYPASS is low, the modulation parameters are latched in the PLL only when the strobe signal

goes high. The strobe signal is automatically generated in the FMPLL when the modulation is enabled

(SSCG_EN goes high) if the PLL is locked (s_lock = 1) or when the modulation has been enabled

(SSCG_EN = 1) and PLL enters in lock state (s_lock goes high).

If STRB_BYPASS is high, the strobe signal is bypassed. In this case, control bits (MOD_PERIOD[12:0],

INC_STEP[14:0], SPREAD_CONTROL) must be changed only when the PLL is in power down mode.

The modulation depth in % is

Eqn. 4-2

NOTE

The user must ensure that the product of INCSTEP and MODPERIOD is

less than (215 –1).

The following values show the input setting for one possible configuration of the PLL:

• PLL input frequency: 4 MHz

• Loop divider (LDF): 64

• Input divider (IDF): 1

• VCO frequency = 4 MHz × 64 = 256 MHz

onward (ck_pll_out frequency)

Table 4-8. Progressive clock switching on pll_select rising edge (continued)

Number of PLL output clock cycles ck_pll_div frequency (PLL output frequency)

Division factors

ck_pll_out ck_pll_div

of 8, 4, 2, or 1

ModulationDepth 100 5INCSTEPxMODPERIOD

215 1–MDF

---------------------------------------------------------------------------------------------





Chapter 4 Clock Description

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 95

• PLL output frequency = 256 MHz/ODF

• Spread: Center spread (SPREAD_CONTROL = 0)

• Modulation frequency = 24 kHz

• Modulation depth = ±2.0% (4% pk-pk)

Using the formulae for MODPERIOD and INCSTEP:

MODPERIOD = Round [(4e06) / (4 × 24e03)] = Round [41.66] = 42 Eqn. 4-3

INCSTEP = Round [((215 – 1) × 2 × 64) / (100 × 5 × 42)] = Round [199.722] = 200 Eqn. 4-4

MODPERIOD × INCSTEP = 42 × 200 = 8400 (which is less than 215)Eqn. 4-5

md(quantized)% = ((42*200*100*5) / ((2^15-1)*64) = 2.00278% (peak) Eqn. 4-6

Error in modulation depth = 2.00278 - 2.0 = 0.00278% Eqn. 4-7

If we choose MODPERIOD = 41,

INCSTEP = Round [((215 – 1) × 2 × 64) / (100 × 5 × 41)] = Round [204.878] = 205 Eqn. 4-8

MODPERIOD × INCSTEP = 41 × 205 = 8405 (which is less than 215)Eqn. 4-9

md(quantized)% = ((41 × 205 × 100 × 5) / ((215 – 1) × 64) = 2.00397% (peak) Eqn. 4-10

Error in modulation depth = 2.00397 – 2.0 = 0.00397% Eqn. 4-11

The above calculations show that the quantization error in the modulation depth depends on the flooring

and rounding of MODPERIOD and INCSTEP. For this reason, the MODPERIOD and INCSTEP should

be judiciously rounded/floored to minimize the quantization error in the modulation depth.

Figure 4-10. Frequency modulation depth spreads

Time

Frequency

Center Spread

Down Spread

2× md

Tmod 2Tmod

Chapter 4 Clock Description

MPC5602P Microcontroller Reference Manual, Rev. 4

96 Freescale Semiconductor

4.8.6.4 Powerdown mode

To reduce consumption, the FMPLL can be switched off when not required by programming the registers

ME_x_MC on the ME module.

4.8.7 Recommendations

To avoid any unpredictable behavior of the PLL clock, it is recommended to follow these guidelines:

• The PLL VCO frequency should reside in the range 256 MHz to 512 MHz. Care is required when

programming the multiplication and division factors to respect this requirement.

• The user must change the multiplication, division factors only when the PLL output clock is not

selected as system clock. MOD_PERIOD, INC_STEP, SPREAD_SEL bits should be modified

before activating the FM modulated mode. Then strobe has to be generated to enable the new

settings. If STRB_BYP is set to ‘1’ then MOD_PERIOD, INC_STEP and SPREAD_SEL can be

modified only when PLL is in power down mode.

• Use progressive clock switching.

4.9 Clock Monitor Unit (CMU)

4.9.1 Overview

The Clock Monitor Unit (CMU) serves three purposes:

• PLL clock monitoring: detects if PLL leaves an upper or lower frequency boundary

• XOSC clock monitoring: monitor the XOSC clock, which must be greater than the IRCOSC clock

divided by a division factor given by CMU_CSR[RCDIV]

• Frequency meter: measure the frequency of the IRCOSC clock versus the reference XOSC clock

frequency

When mismatch occurs in the CMU either with the PLL monitor or the XOSC monitor, the CMU notifies

the RGM, ME and the FCU (Fault Collection Unit) modules. The default behavior is such that a reset

occurs and a status bit is set in the RGM. The user also has the option to change the behavior of the action

by disabling the reset and selecting an alternate action. The alternate action can be either entering safe

mode or generating an interrupt.

Table 4-9. CMU module summary

Module Monitored clocks

CMU_0 • XOSC integrity supervisor

• FMPLL_0 integrity supervisor

• IRCOSC frequency meter

Chapter 4 Clock Description

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 97

Figure 4-11. MPC5602PCMU

4.9.2 Main features

• RC oscillator frequency measurement

• External oscillator clock monitoring with respect to CK_IRC/n clock

• PLL clock frequency monitoring with respect to CK_IRC/4 clock

• Event generation for various failures detected inside monitoring unit

4.9.3 Functional description

The clock and frequency names referenced in this block are defined as follows:

• CK_XOSC: clock coming from the external crystal oscillator

• CK_IRC: clock coming from the low frequency internal RC oscillator

• CK_PLL: clock coming from the PLL

•f

XOSC: frequency of external crystal oscillator clock

•f

RC: frequency of low frequency internal RC oscillator

•f

PLL: frequency of FMPLL clock

4.9.3.1 Crystal clock monitor

If fXOSC is smaller than fRC divided by 2RCDIV bits of CMU_0_CSR and the CK_XOSC is ‘ON’ and stable

as signaled by the ME, then:

• An event pending bit OLRI in CMU_0_ISR is set

• A failure event OLR is signaled to the RGM and FCU, which in turn can generate either an

interrupt, a reset, or a SAFE mode request.

IRC_CLK

XOSC_CLK

FMPLL_0

16 MHz

4 to 40 MHz

64 MHz

CK 0 (reference)

CK XOSC

CK PLL

XOSC valid (on AND stable) / off

CMU_0

FLL

OLR

FMPLL_0 valid (on AND locked) / off

FCU

FMPLL_0 freq.

out of range

Loss of crystal

Clock

Control

Logic

Chapter 4 Clock Description

MPC5602P Microcontroller Reference Manual, Rev. 4

98 Freescale Semiconductor

4.9.3.2 PLL clock monitor

The PLL clock CK_PLL frequency can be monitored by programming bit CME_0 of the CMU_0_CSR to

‘1’. The CK_PLL monitor starts as soon as bit CME_0 is set. This monitor can be disabled at any time by

writing bit CME_0 to ‘0’.

If the CK_PLL frequency (fPLL) is greater than a reference value determined by bits HFREF[11:0] of the

CMU_HFREFR and the CK_PLL is ‘ON’ and the PLL locked as signaled by the ME then:

• An event pending bit FHHI_0 in the CMU_0_ISR is set.

• A failure event FHH is signaled to the RGM and FCU, which in turn can generate either an

interrupt, a reset, or a SAFE mode request.

If fPLL is less than a reference clock frequency (fRC/4) and the CK_PLL is ‘ON’ and the PLL locked as

signaled by the ME, then:

• An event pending bit FLCI_0 in the CMU_0_ISR is set.

• A failure event FLC is signaled to the RGM and FCU, which in turn can generate either an

interrupt, a reset, or a SAFE mode request.

If fPLL is less than a reference value determined by bits LFREF[11:0] of the CMU_LFREFR and the

CK_PLL is ‘ON’ and the PLL locked as signaled by the ME, then:

• An event pending bit FLLI_0 in the CMU_0_ISR is set.

• A failure event FLL is signaled to the RGM and FCU, which in turn can generate either an

interrupt, a reset, or a SAFE mode request.

NOTE

It is possible for either the XOSC or PLL monitors to produce a false event

when the XOSC or PLL frequency is too close to RC/2RCDIV frequency due

to an accuracy limitation of the compare circuitry.

4.9.3.3 System clock monitor

The system clock is monitored by CMU_1. The FSYS_CLK frequency can be monitored by programming

CMU_1_CSR[CME] = 1. SYS_CLK monitoring starts as soon as CMU_1_CSR[CME] = 1. This

monitor can be disabled at any time by writing CME bit to 0.

If FSYS_CLK is greater than a reference value determined by the CMU_1_HFREFR_A[HFREF_A] bits and

the system clock is enabled, then:

• CMU_1_ISR[FHHI] is set

• A failure event is signaled to the MC_RGM and FCU, which in turn can generate a ‘functional'

reset, a SAFE mode request, or an interrupt

If FSYS_CLK is less than a reference clock frequency (FIRCOSC_CLK4) and the system clock is enabled,

then:

• CMU_1_ISR[FLCI] is set

• A failure event FLC is signaled to the MC_RGM and Fault Collection Unit, which in turn can

generate a ‘functional' reset, a SAFE mode request, or an interrupt

Chapter 4 Clock Description

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 99

If FSYS_CLK is less than a reference value determined by the CMU_1_LFREFR_A[LFREF_A] bits and

the system clock is enabled, then:

• CMU_1_ISR[FLLI] is set

• A failure event is signaled to the MC_RGM and FCU, which in turn can generate a ‘functional’

reset, a SAFE mode request, or an interrupt

NOTE

The system clock monitor may produce a false event when FSYS_CLK is less

than 2FIRCOSC_CLK/2CMU_1_CSR[RCDIV] due to an accuracy limitation of

the compare circuitry.

4.9.3.4 Frequency meter

The frequency meter calibrates the internal RC oscillator (CK_IRC) using a known frequency.

NOTE

This value can then be stored into the flash so that application software can

reuse it later on.

The reference clock will be always the XOSC. A simple frequency meter returns a draft value of CK_IRC.

The measure starts when bit SFM (Start Frequency Measure) in the CMU_CSR is set to ‘1’. The

measurement duration is given by the CMU_MDR in numbers of IRC clock cycles with a width of 20 bits.

Bit SFM is reset to ‘0’ by hardware once the frequency measurement is done and the count is loaded in the

CMU_FDR. The frequency fRC can be derived from the value loaded in the CMU_FDR as follows:

fRC = (fOSC × MD) / n Eqn. 4-12

where n is the value in the CMU_FDR and MD is the value in the CMU_MDR.

4.9.4 Memory map and register description

Table 4-10 shows the memory map of the CMU.

Table 4-10. CMU memory map

Offset from

CMU_BASE

(0xC3FE_0100)

Access

Reset value Location

0x0000 Control Status Register (CMU_0_CSR) R/W 0x0000_0006 on page 100

0x0004 Frequency Display Register (CMU_0_FDISP) R 0x0000_0000 on page 101

0x0008 High Frequency Reference Register FMPLL_0

(CMU_0_HFREFR_A)

R/W 0x0000_0FFF on page 101

0x000C Low Frequency Reference Register FMPLL_0

(CMU_0_LFREFR_A)

R/W 0x0000_0000 on page 102

0x0010 Interrupt Status Register (CMU_0_ISR) R/W 0x0000_0000 on page 102

0x0014 Reserved

Chapter 4 Clock Description

MPC5602P Microcontroller Reference Manual, Rev. 4

100 Freescale Semiconductor

4.9.4.1 Control Status Register (CMU_0_CSR)

0x0018 Measurement Duration Register (CMU_0_MDR) R/W 0x0000_0000 on page 103

0x001C–0x3FFF Reserved

Address:

Base + 0x0000 Access: User read/write

0123456789101112131415

R00000000SFM 0000000

Reset0000000000000000

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

R0000000000000

RCDIV[1:0] CME

Reset0000000000000000

Figure 4-12. Control Status Register (CMU_0_CSR)

Table 4-11. CMU_0_CSR field descriptions

Field Description

SFM Start frequency measure

The software can only set this bit to start a clock frequency measure. It is reset by hardware when the

measure is ready in the CMU_FDR.

0: Frequency measurement completed or not yet started

1: Frequency measurement not completed

RCDIV[1:0] RC clock division factor

These bits specify the RC clock division factor. The output clock is CK_IRC divided by the factor 2RCDIV

This output clock is compared with CK_XOSC for crystal clock monitor feature.The clock division

coding is as follows.

00: Clock divided by 1 (no division)

01: Clock divided by 2

10: Clock divided by 4

11: Clock divided by 8

CME_0 FMPLL_0 clock monitor enable

0: FMPLL_0 monitor disabled

1: FMPLL_0 monitor enabled

Table 4-10. CMU memory map (continued)

Offset from

CMU_BASE

(0xC3FE_0100)

Access

Reset value Location

Chapter 4 Clock Description

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 101

4.9.4.2 Frequency Display Register (CMU_0_FDR)

4.9.4.3 High Frequency Reference Register FMPLL_0 (CMU_0_HFREFR_A)

Address:

Base + 0x0004 Access: User read-only

0123456789101112131415

R000000000000 FD[19:16]

Reset0000000000000000

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

RFD[15:0]

Reset0000000000000000

Figure 4-13. Frequency Display Register (CMU_0_FDR)

Table 4-12. CMU_0_FDR field descriptions

Field Description

FD[19:0] Measured frequency bits

This register displays the measured frequency fRC with respect to fOSC. The measured value is given

by the following formula: fRC = (f

OSC × MD) / n, where n is the value in CMU_FDR.

Address:

Base + 0x0008 Access: User read/write

0123456789101112131415

R0000000000000000

Reset0000000000000000

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

R0000 HFREF[11:0]

Reset0000111111111111

Figure 4-14. High Frequency Reference register FMPLL_0 (CMU_0_HFREFR_A)

Table 4-13. CMU_0_HFREFR_A field descriptions

Field Description

HFREF_A High Frequency reference value

These bits determine the high reference value for the FMPLL_0 clock. The reference value is given by:

(HFREF_A[11:0]/16) × (fRC/4).

Chapter 4 Clock Description

MPC5602P Microcontroller Reference Manual, Rev. 4

102 Freescale Semiconductor

4.9.4.4 Low Frequency Reference Register FMPLL_0 (CMU_0_LFREFR_A)

4.9.4.5 Interrupt Status Register (CMU_0_ISR)

Address:

Base + 0x000C Access: User read/write

0123456789101112131415

R0000000000000000

Reset0000000000000000

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

R0000 LFREF[11:0]

Reset0000000000000000

Figure 4-15. Low Frequency Reference Register FMPLL_0 (CMU_0_LFREFR_A)

Table 4-14. CMU_0_LFREFR_A fields descriptions

Field Description

LFREF_A Low Frequency reference value

These bits determine the low reference value for the FMPLL_0. The reference value is given by:

(LFREF_A[11:0]/16) * (fRC/4).

Address:

Base + 0x0010 Access: User read/write

0123456789101112131415

R0000000000000000

Reset0000000000000000

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

R000000000000

FLCI

FHHI

FLLI

_0 OLRI

Ww1c w1c w1c w1c

Reset0000000000000000

Figure 4-16. Interrupt Status Register (CMU_0_ISR)

Table 4-15. CMU_0_ISR field descriptions

Field Description

FLCI_0 FMPLL_0 Clock frequency less than reference clock interrupt

This bit is set by hardware when CK_FMPLL_0 frequency becomes lower than reference clock

frequency (fRC/4) value and CK_FMPLL_0 is ‘ON’ and the PLL locked as signaled by the ME. It can be

cleared by software by writing 1.

0: No FLC event

1: FLC event pending

Chapter 4 Clock Description

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 103

4.9.4.6 Measurement Duration Register (CMU_0_MDR)

FHHI_0 FMPLL_0 Clock frequency higher than high reference interrupt

This bit is set by hardware when CK_FMPLL_ 0 frequency becomes higher than HFREF_A value and

CK_FMPLL_0 is ‘ON’ and the PLL locked as signaled by the ME. It can be cleared by software by

writing 1.

0: No FHH event

1: FHH event pending

FLLI_0 FMPLL_0 Clock frequency less than low reference event

This bit is set by hardware when CK_FMPLL_0 frequency becomes lower than LFREF_A value and

CK_FMPLL_0 is ‘ON’ and the PLL locked as signaled by the ME. It can be cleared by software by

writing 1.

0: No FLL event

1: FLL event pending

OLRI Oscillator frequency less than RC frequency event

This bit is set by hardware when the frequency of CK_XOSC is less than CK_IRC/2RCDIV frequency and

CK_XOSC is ‘ON’ and stable as signaled by the ME. It can be cleared by software by writing 1.

0: No OLR event

1: OLR event pending

Address:

Base + 0x0018 Access: User read/write

0123456789101112131415

R000000000000 MD[19:16]

Reset0000000000000000

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

RMD[15:0]

Reset0000000000000000

Figure 4-17. Measurement Duration Register (CMU_0_MDR)

Table 4-16. CMU_0_MDR field descriptions

Field Description

MD[19:0] Measurement duration bits

This register displays the measured duration in term of IRC clock cycles. This value is loaded in the

frequency meter downcounter. When SFM bit is set to ‘1’, downcounter starts counting.

Table 4-15. CMU_0_ISR field descriptions (continued)

Field Description

Chapter 4 Clock Description

MPC5602P Microcontroller Reference Manual, Rev. 4

104 Freescale Semiconductor

Chapter 5 Clock Generation Module (MC_CGM)

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 105

Chapter 5

Clock Generation Module (MC_CGM)

5.1 Overview

The clock generation module (MC_CGM) generates reference clocks for all the SoC blocks. The

MC_CGM selects one of the system clock sources to supply the system clock. The MC_ME controls the

system clock selection (see the MC_ME chapter for more details). Peripheral clock selection is controlled

by MC_CGM control registers. A set of MC_CGM registers controls the clock dividers which are used for

divided system and peripheral clock generation. The memory spaces of system and peripheral clock

sources which have addressable memory spaces are accessed through the MC_CGM memory space. The

MC_CGM also selects and generates an output clock.

Figure 5-1 depicts the MC_CGM Block Diagram.

Chapter 5 Clock Generation Module (MC_CGM)

MPC5602P Microcontroller Reference Manual, Rev. 4

106 Freescale Semiconductor

5.2 Features

The MC_CGM includes the following features:

• generates system and peripheral clocks

• selects and enables/disables the system clock supply from system clock sources according to

MC_ME control

• contains a set of registers to control clock dividers for divided clock generation

Output Clock

Selector/Divider

Registers

Platform Interface

core

MC_CGM

Figure 5-1. MC_CGMBlock Diagram

MC_ME

Auxiliary Clock

Selector/Divider

System Clock

Multiplexer/Divider

XOSC0

PLL0

16 MHz_IRC

Mapped Modules Interface

mapped

peripherals

PA D [ 2 2 ]

MC_RGM

Chapter 5 Clock Generation Module (MC_CGM)

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 107

• contains a set of registers to control peripheral clock selection

• supports multiple clock sources and maps their address spaces to its memory map

• generates an output clock

• guarantees glitch-less clock transitions when changing the system clock selection

• supports 8, 16 and 32-bit wide read/write accesses

5.3 External Signal Description

The MC_CGM delivers an output clock to the PAD[22] pin for off-chip use and/or observation.

5.4 Memory Map and Register Definition

NOTE

Any access to unused registers as well as write accesses to read-only

registers will not change register content, and cause a transfer error.

Table 5-1. MC_CGM Register Description

Address Name Description Size

Access

Location

User Supervisor Test

0xC3FE

_0370

CGM_OC_EN Output Clock Enable word read read/write read/write on page 112

0xC3FE

_0374

CGM_OCDS_SC Output Clock Division

Select

byte read read/write read/write on page 113

0xC3FE

_0378

CGM_SC_SS System Clock Select

Status

byte read read read on page 114

0xC3FE

_037C

CGM_SC_DC0 System Clock Divider

Configuration 0

byte read read/write read/write on page 114

0xC3FE

_0380

CGM_AC0_SC Aux Clock 0 Select

Control

word read read/write read/write on page 115

0xC3FE

_0384

CGM_AC0_DC0 Aux Clock 0 Divider

Configuration 0

byte read read/write read/write on page 116

0xC3FE

_0388

CGM_AC1_SC Aux Clock 1 Select

Control

word read read/write read/write on page 116

0xC3FE

_038C

CGM_AC1_DC0 Aux Clock 1 Divider

Configuration 0

byte read read/write read/write on page 117

0xC3FE

_0390

CGM_AC2_SC Aux Clock 2 Select

Control

word read read/write read/write on page 118

0xC3FE

_0394

CGM_AC2_DC0 Aux Clock 2 Divider

Configuration 0

byte read read/write read/write on page 119

Chapter 5 Clock Generation Module (MC_CGM)

MPC5602P Microcontroller Reference Manual, Rev. 4

108 Freescale Semiconductor

Table 5-2. MC_CGM Memory Map

0xC3FE

_0000

…

0xC3FE

_001C

XOSC registers

0xC3FE

_0020

…

0xC3FE

_003C

reserved

0xC3FE

_0040

…

0xC3FE

_005C

reserved

0xC3FE

_0060

…

0xC3FE

_007C

IRCOSC registers

0xC3FE

_0080

…

0xC3FE

_009C

reserved

0xC3FE

_00A0

…

0xC3FE

_00BC

PLL0 registers

0xC3FE

_00C0

…

0xC3FE

_00DC

reserved

0xC3FE

_00E0

…

0xC3FE

_00FC

reserved

0xC3FE

_0100

…

0xC3FE

_011C

CMU0 registers

Chapter 5 Clock Generation Module (MC_CGM)

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 109

0xC3FE

_0120

…

0xC3FE

_013C

reserved

0xC3FE

_0140

…

0xC3FE

_015C

reserved

0xC3FE

_0160

…

0xC3FE

_017C

reserved

0xC3FE

_0180

…

0xC3FE

_019C

reserved

0xC3FE

_01A0

…

0xC3FE

_01BC

reserved

0xC3FE

_01C0

…

0xC3FE

_01DC

reserved

0xC3FE

_01E0

…

0xC3FE

_01FC

reserved

0xC3FE

_0200

…

0xC3FE

_021C

reserved

0xC3FE

_0220

…

0xC3FE

_023C

reserved

Table 5-2. MC_CGM Memory Map (continued)

Chapter 5 Clock Generation Module (MC_CGM)

MPC5602P Microcontroller Reference Manual, Rev. 4

110 Freescale Semiconductor

0xC3FE

_0240

…

0xC3FE

_025C

reserved

0xC3FE

_0260

…

0xC3FD

_C27C

reserved

0xC3FE

_0280

…

0xC3FE

_029C

reserved

0xC3FE

_02A0

…

0xC3FE

_02BC

reserved

0xC3FE

_02C0

…

0xC3FE

_02DC

reserved

0xC3FE

_02E0

…

0xC3FE

_02FC

reserved

0xC3FE

_0300

…

0xC3FE

_031C

reserved

0xC3FE

_0320

…

0xC3FE

_033C

reserved

0xC3FE

_0340

…

0xC3FE

_035C

reserved

Table 5-2. MC_CGM Memory Map (continued)

Chapter 5 Clock Generation Module (MC_CGM)

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 111

0xC3FE

_0360

…

0xC3FE

_036C

reserved

0xC3FE

_0370

CGM_OC_ENR0000000000000000

R000000000000000

0xC3FE

_0374

CGM_OCDS_

R0 0

SELDIV SELCTL

00000000

R0000000000000000

0xC3FE

_0378

CGM_SC_SSR0000 SELSTAT 00000000

R0000000000000000

0xC3FE

_037C

CGM_SC_DC

DE0

000

DIV0

00000000

R0000000000000000

0xC3FE

_0380

CGM_AC0_S

R0000

SELCTL

00000000

R0000000000000000

0xC3FE

_0384

CGM_AC0_D

DE0

000

DIV0

00000000

R0000000000000000

0xC3FE

_0388

CGM_AC1_S

R0000

SELCTL

00000000

R0000000000000000

Table 5-2. MC_CGM Memory Map (continued)

Chapter 5 Clock Generation Module (MC_CGM)

MPC5602P Microcontroller Reference Manual, Rev. 4

112 Freescale Semiconductor

5.5 Register Descriptions

All registers may be accessed as 32-bit words, 16-bit half-words, or 8-bit bytes. The bytes are ordered

according to big endian. For example, the CGM_OC_EN register may be accessed as a word at address

0xC3FE_0370, as a half-word at address 0xC3FE_0372, or as a byte at address 0xC3FE_0373.

5.5.1 Output Clock Enable Register (CGM_OC_EN)

This register is used to enable and disable the output clock.

0xC3FE

_038C

CGM_AC1_D

DE0

000

DIV0

00000000

R0000000000000000

0xC3FE

_0390

CGM_AC2_S

R0000

SELCTL

00000000

R0000000000000000

0xC3FE

_0394

CGM_AC2_D

DE0

000

DIV0

00000000

R0000000000000000

0xC3FE

_0398

…

0xC3FE

_3FFC

reserved

Address 0xC3FE_0370 Access: User read, Supervisor read/write, Test read/write

R0000000000000000

Reset0000000000000000

R000000000000000

Reset0000000000000000

Figure 5-2. Output Clock Enable Register (CGM_OC_EN)

Table 5-2. MC_CGM Memory Map (continued)

Chapter 5 Clock Generation Module (MC_CGM)

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 113

5.5.2 Output Clock Division Select Register (CGM_OCDS_SC)

This register is used to select the current output clock source and by which factor it is divided before being

delivered at the output clock.

Table 5-3. Output Clock Enable Register (CGM_OC_EN) Field Descriptions

Field Description

EN Output Clock Enable control

0 Output Clock is disabled

1 Output Clock is enabled

Address 0xC3FE_0374 Access: User read, Supervisor read/write, Test read/write

R0 0 SELDIV SELCTL 00000000

Reset0000000000000000

R0000000000000000

Reset0000000000000000

Figure 5-3. Output Clock Division Select Register (CGM_OCDS_SC)

Table 5-4. Output Clock Division Select Register (CGM_OCDS_SC) Field Descriptions

Field Description

SELDIV Output Clock Division Select

00 output selected Output Clock without division

01 output selected Output Clock divided by 2

10 output selected Output Clock divided by 4

11 output selected Output Clock divided by 8

SELCTL Output Clock Source Selection Control — This value selects the current source for the output clock.

0000 16 MHz int. RC osc.

0001 4 MHz crystal osc.

0010 system PLL

0011 reserved

0100 reserved

0101 reserved

0110 reserved

0111 reserved

1000 reserved

1001 reserved

1010 reserved

1011 reserved

1100 reserved

1101 reserved

1110 reserved

1111 reserved

Chapter 5 Clock Generation Module (MC_CGM)

MPC5602P Microcontroller Reference Manual, Rev. 4

114 Freescale Semiconductor

5.5.3 System Clock Select Status Register (CGM_SC_SS)

This register provides the current system clock source selection.

5.5.4 System Clock Divider Configuration Register (CGM_SC_DC0)

This register controls the system clock divider.

Address 0xC3FE_0378 Access: User read, Supervisor read, Test read

R0000 SELSTAT 00000000

Reset0000000000000000

R0000000000000000

Reset0000000000000000

Figure 5-4. System Clock Select Status Register (CGM_SC_SS)

Table 5-5. System Clock Select Status Register (CGM_SC_SS) Field Descriptions

Field Description

SELSTAT System Clock Source Selection Status — This value indicates the current source for the system clock.

0000 16 MHz int. RC osc.

0001 reserved

0010 4 MHz crystal osc.

0011 reserved

0100 system PLL

0101 reserved

0110 reserved

0111 reserved

1000 reserved

1001 reserved

1010 reserved

1011 reserved

1100 reserved

1101 reserved

1110 reserved

1111 system clock is disabled

Address 0xC3FE_037C Access: User read, Supervisor read/write, Test read/write

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RDE0 000 DIV0 00000000

Reset1000000000000000

1514131211109876543210

R0000000000000000

Reset0000000000000000

Figure 5-5. System Clock Divider Configuration Register (CGM_SC_DC0)

Chapter 5 Clock Generation Module (MC_CGM)

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 115

5.5.5 Auxiliary Clock 0 Select Control Register (CGM_AC0_SC)

This register is used to select the current clock source for the following clocks:

• undivided: (unused)

• divided by auxiliary clock 0 divider 0: (unused)

See Figure 5-15 for details.

Table 5-6. System Clock Divider Configuration Register (CGM_SC_DC0) Field Descriptions

Field Description

DE0 Divider 0 Enable

0 Disable system clock divider 0

1 Enable system clock divider 0

DIV0 Divider 0 Division Value — The resultant divided system clock 0 will have a period DIV0 + 1 times that

of the system clock. If the DE0 is set to ‘0’ (Divider 0 is disabled), any write access to the DIV0 field is

ignored and the divided system clock 0 remains disabled.

Address 0xC3FE_0380 Access: User read, Supervisor read/write, Test read/write

R0000 SELCTL 00000000

Reset0000000000000000

R0000000000000000

Reset0000000000000000

Figure 5-6. Auxiliary Clock 0 Select Control Register (CGM_AC0_SC)

Table 5-7. Auxiliary Clock 0 Select Control Register (CGM_AC0_SC) Field Descriptions

Field Description

SELCTL Auxiliary Clock 0 Source Selection Control — This value selects the current source for auxiliary clock

0000 (no clock)

0001 reserved

0010 (no clock)

0011 reserved

0100 (no clock)

0101 (no clock)

0110 reserved

0111 reserved

1000 (no clock)

1001 reserved

1010 reserved

1011 reserved

1100 reserved

1101 reserved

1110 reserved

1111 reserved

Chapter 5 Clock Generation Module (MC_CGM)

MPC5602P Microcontroller Reference Manual, Rev. 4

116 Freescale Semiconductor

5.5.6 Auxiliary Clock 0 Divider Configuration Register (CGM_AC0_DC0)

This register controls the auxiliary clock 0 divider.

5.5.7 Auxiliary Clock 1 Select Control Register (CGM_AC1_SC)

This register is used to select the current clock source for the following clocks:

• undivided: (unused)

• divided by auxiliary clock 1 divider 0: (unused)

Address 0xC3FE_0384 Access: User read, Supervisor read/write, Test read/write

RDE0 000 DIV0 00000000

Reset1000000000000000

R0000000000000000

Reset0000000000000000

Figure 5-7. Auxiliary Clock 0 Divider Configuration Register (CGM_AC0_DC0)

Table 5-8. Auxiliary Clock 0 Divider Configuration Register (CGM_AC0_DC0) Field Descriptions

Field Description

DE0 Divider 0 Enable

0 Disable auxiliary clock 0 divider 0

1 Enable auxiliary clock 0 divider 0

DIV0 Divider 0 Division Value — The resultant (unused) will have a period DIV0 + 1 times that of auxiliary

clock 0. If the DE0 is set to 0 (Divider 0 is disabled), any write access to the DIV0 field is ignored and the

(unused) remains disabled.

Address 0xC3FE_0388 Access: User read, Supervisor read/write, Test read/write

R0000 SELCTL 00000000

Reset0000000000000000

R0000000000000000

Reset0000000000000000

Figure 5-8. Auxiliary Clock 1 Select Control Register (CGM_AC1_SC)

Chapter 5 Clock Generation Module (MC_CGM)

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 117

5.5.8 Auxiliary Clock 1 Divider Configuration Register (CGM_AC1_DC0)

This register controls the auxiliary clock 1 divider.

Table 5-9. Auxiliary Clock 1 Select Control Register (CGM_AC1_SC) Field Descriptions

Field Description

SELCTL Auxiliary Clock 1 Source Selection Control — This value selects the current source for auxiliary clock

0000 (no clock)

0001 reserved

0010 reserved

0011 reserved

0100 reserved

0101 reserved

0110 reserved

0111 reserved

1000 reserved

1001 reserved

1010 reserved

1011 reserved

1100 reserved

1101 reserved

1110 reserved

1111 reserved

Address 0xC3FE_038C Access: User read, Supervisor read/write, Test read/write

RDE0 000 DIV0 00000000

Reset1000000000000000

R0000000000000000

Reset0000000000000000

Figure 5-9. Auxiliary Clock 1 Divider Configuration Register (CGM_AC1_DC0)

Table 5-10. Auxiliary Clock 1 Divider Configuration Register (CGM_AC1_DC0) Field Descriptions

Field Description

DE0 Divider 0 Enable

0 Disable auxiliary clock 1 divider 0

1 Enable auxiliary clock 1 divider 0

DIV0 Divider 0 Division Value — The resultant (unused) will have a period DIV0 + 1 times that of auxiliary

clock 1. If the DE0 is set to 0 (Divider 0 is disabled), any write access to the DIV0 field is ignored and the

(unused) remains disabled.

Chapter 5 Clock Generation Module (MC_CGM)

MPC5602P Microcontroller Reference Manual, Rev. 4

118 Freescale Semiconductor

5.5.9 Auxiliary Clock 2 Select Control Register (CGM_AC2_SC)

This register is used to select the current clock source for the following clocks:

• undivided: (unused)

• divided by auxiliary clock 2 divider 0: (unused)

See Figure 5-13 for details.

Address 0xC3FE_0390 Access: User read, Supervisor read/write, Test read/write

R0000 SELCTL 00000000

Reset0000000000000000

R0000000000000000

Reset0000000000000000

Figure 5-10. Auxiliary Clock 2 Select Control Register (CGM_AC2_SC)

Table 5-11. Auxiliary Clock 2 Select Control Register (CGM_AC2_SC) Field Descriptions

Field Description

SELCTL Auxiliary Clock 2 Source Selection Control — This value selects the current source for auxiliary clock

0000 (no clock)

0001 reserved

0010 (no clock)

0011 reserved

0100 (no clock)

0101 (no clock)

0110 reserved

0111 reserved

1000 (no clock)

1001 reserved

1010 reserved

1011 reserved

1100 reserved

1101 reserved

1110 reserved

1111 reserved

Chapter 5 Clock Generation Module (MC_CGM)

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 119

5.5.10 Auxiliary Clock 2 Divider Configuration Register (CGM_AC2_DC0)

This register controls the auxiliary clock 2 divider.

5.6 Functional Description

5.7 System Clock Generation

Figure 5-12 shows the block diagram of the system clock generation logic. The MC_ME provides the

system clock select and switch mask (see MC_ME chapter for more details), and the MC_RGM provides

the safe clock request (see MC_RGM chapter for more details). The safe clock request forces the selector

to select the 16 MHz int. RC osc. as the system clock and to ignore the system clock select.

Address 0xC3FE_0394 Access: User read, Supervisor read/write, Test read/write

RDE0 000 DIV0 00000000

Reset1000000000000000

R0000000000000000

Reset0000000000000000

Figure 5-11. Auxiliary Clock 2 Divider Configuration Register (CGM_AC2_DC0)

Table 5-12. Auxiliary Clock 2 Divider Configuration Register (CGM_AC2_DC0) Field Descriptions

Field Description

DE0 Divider 0 Enable

0 Disable auxiliary clock 2 divider 0

1 Enable auxiliary clock 2 divider 0

DIV0 Divider 0 Division Value — The resultant (unused) will have a period DIV0 + 1 times that of auxiliary

clock 2. If the DE0 is set to 0 (Divider 0 is disabled), any write access to the DIV0 field is ignored and the

(unused) remains disabled.

Chapter 5 Clock Generation Module (MC_CGM)

MPC5602P Microcontroller Reference Manual, Rev. 4

120 Freescale Semiconductor

Figure 5-12. MC_CGM System Clock Generation Overview

5.7.1 System Clock Source Selection

During normal operation, the system clock selection is controlled

• on a SAFE mode or reset event, by the MC_RGM

• otherwise, by the MC_ME

5.7.2 System Clock Disable

During the TEST mode, the system clock can be disabled by the MC_ME.

5.7.3 System Clock Dividers

The MC_CGM generates the divided system clock 0 - controlled by the CGM_SC_DC0 register.

5.8 Auxiliary Clock Generation

Figure 5-13 shows the block diagram of the auxiliary clock generation logic. See Section 5.5.5, “Auxiliary

Clock 0 Select Control Register (CGM_AC0_SC), Section 5.5.7, “Auxiliary Clock 1 Select Control

(CGM_AC2_SC) for auxiliary clock selection control.

4 MHz crystal osc. 2

system PLL 4

system clock

’0’

CGM_SC_SS Register

MC_RGM SAFE mode request

ME_<current mode>

_MC.SYSCLK

CGM_SC_DC0 Register

clock divider divided system clock 0

system clock is disabled if

ME_<current mode>_MC.SYSCLK = “1111”

“0000” 1

16 MHz int. RC osc. 0

Chapter 5 Clock Generation Module (MC_CGM)

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 121

Figure 5-13. MC_CGM Auxiliary Clock 0 Generation Overview

CGM_AC0_DC0 Register

clock divider (unused)

(unused)

(no clock) 2

(no clock) 4

(no clock) 5

(no clock) 8

CGM_AC0_SC Register

(no clock) 0

Chapter 5 Clock Generation Module (MC_CGM)

MPC5602P Microcontroller Reference Manual, Rev. 4

122 Freescale Semiconductor

Figure 5-14. MC_CGM Auxiliary Clock 1 Generation Overview

CGM_AC1_DC0 Register

clock divider (unused)

(unused)

CGM_AC1_SC Register

(no clock) 0

Chapter 5 Clock Generation Module (MC_CGM)

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 123

Figure 5-15. MC_CGM Auxiliary Clock 2 Generation Overview

5.8.1 Auxiliary Clock Source Selection

During normal operation, the auxiliary clock selection is done via the CGM_AC0…2_SC registers. If

software selects an ‘unavailable’ source, the old selection remains, and the register content does not

change.

5.8.2 Auxiliary Clock Dividers

The MC_CGM generates the following derived clocks:

• (unused) - controlled by the CGM_AC0_DC0 register

• (unused) - controlled by the CGM_AC1_DC0 register

• (unused) - controlled by the CGM_AC2_DC0 register

5.9 Dividers Functional Description

Dividers are used for the generation of divided system and peripheral clocks. The MC_CGM has the

following control registers for built-in dividers:

•Section 5.5.4, “System Clock Divider Configuration Register (CGM_SC_DC0)

•Section 5.5.6, “Auxiliary Clock 0 Divider Configuration Register (CGM_AC0_DC0)

•Section 5.5.8, “Auxiliary Clock 1 Divider Configuration Register (CGM_AC1_DC0)

•Section 5.5.10, “Auxiliary Clock 2 Divider Configuration Register (CGM_AC2_DC0)

CGM_AC2_DC0 Register

clock divider (unused)

(unused)

(no clock) 2

(no clock) 4

(no clock) 5

(no clock) 8

CGM_AC2_SC Register

(no clock) 0

Chapter 5 Clock Generation Module (MC_CGM)

MPC5602P Microcontroller Reference Manual, Rev. 4

124 Freescale Semiconductor

The reset value of all counters is ‘1’. If a divider has its DE bit in the respective configuration register set

to ‘0’ (the divider is disabled), any value in its DIVn field is ignored.

5.10 Output Clock Multiplexing

The MC_CGM contains a multiplexing function for a number of clock sources which can then be used as

output clock sources. The selection is done via the CGM_OCDS_SC register.

5.11 Output Clock Division Selection

Figure 5-16. MC_CGM Output Clock Multiplexer and PAD[22] Generation

The MC_CGM provides the following output signals for the output clock generation:

• PAD[22] (see Figure 5-16). This signal is generated by using one of the 3-stage ripple counter

outputs or the selected signal without division. The non-divided signal is not guaranteed to be 50%

duty cycle by the MC_CGM.

the MC_CGM also has an output clock enable register (see Section 5.5.1, “Output Clock Enable Register

(CGM_OC_EN)) which contains the output clock enable/disable control bit.

CGM_OCDS_SC.SELCTL CGM_OCDS_SC.SELDIV

16 MHz int. RC osc. 0

4 MHz crystal osc. 1

system PLL 2

reserved 3

PAD[22]

’0’

CGM_OC_EN Register

Chapter 6 Power Control Unit (MC_PCU)

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 125

Chapter 6

Power Control Unit (MC_PCU)

6.1 Introduction

6.1.1 Overview

The power control unit (MC_PCU) acts as a bridge for mapping the PMU peripheral to the MC_PCU

address space.

Figure 6-1 depicts the MC_PCU block diagram.

Registers

Platform Interface

MC_PCU

Figure 6-1. MC_PCU Block Diagram

Mapped Module Interface

mapped

peripheral

core

Chapter 6 Power Control Unit (MC_PCU)

MPC5602P Microcontroller Reference Manual, Rev. 4

126 Freescale Semiconductor

6.1.2 Features

The MC_PCU includes the following features:

• maps the PMU registers to the MC_PCU address space

6.2 External Signal Description

The MC_PCU has no connections to any external pins.

6.3 Memory Map and Register Definition

6.3.1 Memory Map

NOTE

Any access to unused registers as well as write accesses to read-only

registers will:

• not change register content

• cause a transfer error

Table 6-1. MC_PCU Register Description

Address Name Description Size

Access

Location

User Supervisor Test

0xC3FE

_8040

PCU_PSTAT Power Domain Status

word read read read on page 127

Table 6-2. MC_PCU Memory Map

0xC3FE

_80004

…

0xC3FE

_803C

reserved

0xC3FE

_8040

PCU_PSTAT R0000000000000000

R000000000000000

PD0

0x044

…

0x07C

reserved

Chapter 6 Power Control Unit (MC_PCU)

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 127

6.3.2 Register Descriptions

All registers may be accessed as 32-bit words, 16-bit half-words, or 8-bit bytes. The bytes are ordered

according to big endian. For example, the PD0 field of the PCU_PSTAT register may be accessed as a

word at address 0xC3FE_8040, as a half-word at address 0xC3FE_8042, or as a byte at address

0xC3FE_8043.

6.3.2.1 Power Domain Status Register (PCU_PSTAT)

This register reflects the power status of all available power domains.

0xC3FE

_8080

…

0xC3FE

_80FC

PMU registers

0xC3FE

_8100

…

0xC3FE

_BFFC

reserved

Address 0xC3FE_8040 Access: User read, Supervisor read, Test read

R0000000000000000

Reset0000000000000000

R000000000000000

PD0

Reset0000000000000001

Figure 6-2. Power Domain Status Register (PCU_PSTAT)

Table 6-3. Power Domain Status Register (PCU_PSTAT) Field Descriptions

Field Description

PDnPower status for power domain #n

0 Power domain is inoperable

1 Power domain is operable

Table 6-2. MC_PCU Memory Map (continued)

Chapter 6 Power Control Unit (MC_PCU)

MPC5602P Microcontroller Reference Manual, Rev. 4

128 Freescale Semiconductor

Chapter 7 Mode Entry Module (MC_ME)

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor 129

Chapter 7

Mode Entry Module (MC_ME)

7.1 Introduction

7.1.1 Overview

The MC_ME controls the SoC mode and mode transition sequences in all functional states. It also contains

configuration, control and status registers accessible for the application.

Figure 7-1 depicts the MC_ME Block Diagram.

Chapter 7 Mode Entry Module (MC_ME)

MPC5602P Microcontroller Reference Manual, Rev. 4

130 Freescale Semiconductor

Registers

Platform Interface

core

MC_ME

Figure 7-1. MC_ME Block Diagram

MC_RGM

XOSC0

PLL0

16 MHz_IRC

MC_CGM

peripherals

Flashes

VREG

Device

Mode

State

Machine

WKPU