LMP7312 www.ti.com SNOSB32B - MARCH 2010 - REVISED MARCH 2013 LMP7312 Precision SPI-Programmable AFE with Differential/Single-Ended Input/Output Check for Samples: LMP7312 FEATURES DESCRIPTION 1 * * * 2 * * * * * * * * * * + - Typical Values, TA = 25C, V =5V, V =0V. Gain Bandwidth 1 MHz Input Voltage Range (G= 0.096 V/V) -15V to +15V Core Op-Amp Input Offset Voltage 100 V (Max) Supply Current 2 mA (Max) Gain (Attenuation Mode) 0.096 V/V, 0.192 V/V0.384 V/V, 0.768 V/V Gain (Amplification Mode) 1 V/V, 2 V/V Gain Error 0.035% (Max) Core Op-Amp PSRR 90 dB (Min) CMRR 80 dB (min) Adjustable Output Common Mode 1V to 4V Temperature Range -40 to 125C Package 14-Pin SOIC APPLICATIONS * * * * * * Signal Conditioning AFE - 10V; 5V; 0-5V; 0-10V; 0-20mA; 4-20mA Data Acquisition Systems Motor Control Instrument and Process Control Remote Sensing Programmable Automation Control The LMP7312 is a digitally programmable variable gain amplifier/attenuator. Its wide input voltage range and superior precision make it a prime choice for applications requiring high accuracy such as data acquisition systems for IO modules in programmable logic control (PLC). The LMP7312 provides a differential output to maximize dynamic range and signal to noise ratio, thereby reducing the overall system error. It can also be configured to handle single ended input data converters by means of the VOCM pin (see Application Section for details). The inputs of LMP7312 can be configured in attenuation mode to handle large input signals of up to +/- 15V, as well as in amplification mode to handle current loops of 0-20mA and 4-20mA.The LMP7312 is equipped with a null switch to evaluate the offset of the internal amplifier. A ensured 0.035% maximum gain error (for all gains) and a maximum gain drift of 5ppm over the extended industrial temperature range (-40 to 125C) make the LMP7312 very attractive for high precision systems even under harsh conditions. A low input offset voltage of 100V and low voltage noise of 3Vpp give the LMP7312 a superior performance. The LMP7312 is fully specified from 40 to 125C and is available in SOIC-14 package. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2010-2013, Texas Instruments Incorporated LMP7312 SNOSB32B - MARCH 2010 - REVISED MARCH 2013 www.ti.com Typical Application + V VIO SCK CS SDI SDO Sensor -VIN -IN R1N RFP R2N VREF +VOUT + V ADC - + - Driver SPI Controller RS ADC +IN IS 4-20 mA +VIN + -VOUT/VR R2P R1P V VCM + RF 100 k: N VOCM 100 k: - V - V + LMPTM is a trademark of Texas Instruments Corporation. 2 Submit Documentation Feedback Copyright (c) 2010-2013, Texas Instruments Incorporated Product Folder Links: LMP7312 LMP7312 www.ti.com SNOSB32B - MARCH 2010 - REVISED MARCH 2013 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings ESD Rating (1) (2) (3) Human Body Model 2000V Machine Body Model 150V Charge device Model 1000V Analog Supply Voltage (VS = V+ - V-) 6V DigitaI Supply Voltage (VDIO=VIO-V-) 6V - Attenuation pins -VIN, +VIN referred to V 17.5V Amplification pins -IN, +IN referred to V- 10V Voltage at all other pins referred to V- 6V Storage Temperature Range For soldering specification: -65C to 150C http://www.ti.com/lit/SNOA549 Junction Temperature (1) 150C Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but for which specific performance is not ensured. For ensured specifications and the test conditions, see Electrical Characteristics. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of JEDEC). Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC). (2) (3) Operating Ratings (1) Analog Supply Voltage (VS = V+ - V-), V-=0V 4.5V to 5.5V Digital Supply Voltage (VDIO = VIO- V-), V-=0V 2.7V to 5.5V Attenuation pins -VIN, +VIN referred to V- -15V to 15V - Amplification pins -IN, +IN referred to V Temperature Range -2.35V to 7.35V (2) Package Thermal Resistance -40C to 125C (2) SOIC-14 (1) (2) 145C/W Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but for which specific performance is not ensured. For ensured specifications and the test conditions, see Electrical Characteristics. The maximum power dissipation is a function of TJ(max), JA. The maximum allowable power dissipation at any ambient temperature is: PD(max) = (TJ(max) - TA)/ JA. All numbers apply for packages soldered directly onto a PC Board. 5V Electrical Characteristics (1) Unless otherwise specified, all limits ensured for TA = 25C, V+ = 5V, VIO = 5V, V- = 0V, G = 0.192 V/V, VCM_ATT=(+VIN+(VIN))/2, VCM_AMP=(+IN+(-IN))/2. Differential output configuration. SE = Single Ended Output, DE = Differential Output.Boldface limits apply at the temperature extremes. Symbol VOS (1) (2) (3) Parameter Core op-amp Input Offset Voltage Conditions Min (2) Typ (3) Max (2) Nulling Switch Mode, DE, VOCM = 1V; Nulling switch Mode, SE, -VOUT/VR = 1V -100 -250 100 250 Nulling Switch Mode, DE, VOCM = 4V; Nulling Switch Mode, SE, -VOUT/VR = 4V -100 -250 100 250 Units V Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No ensured specification of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ > TA. All limits are specified by testing, design, or statistical analysis. Typical values represent the most likely parametric norm at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped production material. Submit Documentation Feedback Copyright (c) 2010-2013, Texas Instruments Incorporated Product Folder Links: LMP7312 3 LMP7312 SNOSB32B - MARCH 2010 - REVISED MARCH 2013 www.ti.com 5V Electrical Characteristics (1) (continued) Unless otherwise specified, all limits ensured for TA = 25C, V+ = 5V, VIO = 5V, V- = 0V, G = 0.192 V/V, VCM_ATT=(+VIN+(VIN))/2, VCM_AMP=(+IN+(-IN))/2. Differential output configuration. SE = Single Ended Output, DE = Differential Output.Boldface limits apply at the temperature extremes. Symbol TCVOS Parameter Conditions Core op-amp Input Offset Voltage (4) Max 3 Nulling Switch Mode, DE, VOCM = 4V; Nulling Switch Mode, SE, -VOUT/VR = 4V -3 1.5 3 SE / DE Core op-amp Voltage Noise Density RTI, Nulling Switch Mode, f = 10 kHz Core op-amp Peak to Peak Voltage Noise RTI, Nulling Switch Mode, f= 0.1Hz to 10Hz IVA Analog Supply Current +VIN = -VIN = VOCM IVIO Digital Supply Current Without any load connected to SDO pin RIN_CM CM Input Resistance G= 0.192 V/V -0.035 -0.045 -5 (2) Units V/C 0.035 0.045 % 5 ppm/C 1 7.25 nV/Hz 3 VPP 2 mA 120 A 62.08 G= 1 V/V Differential Input Resistance (3) 1.5 Gain Drift RIN_DIFF Typ -3 All gains, RL = 10 k, CL = 50pF, SE / DE en (2) Nulling Switch Mode, DE, VOCM = 1V; Nulling Switch Mode, SE, -VOUT/VR = 1V Gain Error Av Min k 40 G= 0.192 V/V 248.3 G= 1 V/V k 160 G= 0.096V/V, -15V < VCM_ATT < 15V, SE / DE G= 0.192V/V, -11.4V < VCM_ATT < 15V, SE / DE G= 0.384V/V, -6V < VCM_ATT < 11V, SE / DE DC Common Mode Rejection Ratio CMRR G= 0.768V/V, -3V < VCM_ATT < 8V, SE / DE 80 77 dB 90 dB G= 1V/V, -2.3V < VCM_AMP < 7.3V, SE / DE G= 2V/V, -1.15V < VCM_AMP < 6.15V, SE / DE. PSRR Core op-amp DC Nulling Switch Mode, 4.5V <V+ <5.5V Power Supply Rejection Ratio VOCM_OS VOCM Output Offset VOUT IOUT GBW (4) (5) 4 (5) VOCM = 2.5 V -20 20 V -0.2 Positive Output Voltage RL = 10 k, CL = 50 pF, Swing +VIN= 15V, -VIN= -15V Negative Output Voltage Swing RL = 10 k, CL = 50 pF, +VIN= -15V, -VIN= 15V Short circuit current +VIN= -VIN = 2.5V, +VOUT, -VOUT/VR connected individually to either V+ or V- Current limitation Internal current limiter Bandwidth mV + V V-+0.2 10 mA 55 Attenuation Mode, G = 0.096 V/V, RL =10 k, CL = 50 pF 1.2 Attenuation Mode, G = 0.192 V/V, RL = 10 k, CL = 50 pF 1.0 Attenuation Mode, G = 0.384 V/V, RL = 10 k, CL = 50 pF 560 Attenuation Mode, G = 0.768 V/V, RL = 10 k, CL = 50 pF 310 Amplification Mode, G = 1 V/V, RL = 10 k, CL = 50 pF 530 Amplification Mode, G = 2 V/V, RL = 10 k, CL = 50 pF 280 MHz kHz kHz Offset voltage temperature drift is determined by dividing the change in VOS at the temperature extremes by the total temperature change. VOCM_OS is the difference between the Output Common mode voltage (+VOUT+(-VOUT/VR))/2 and the Voltage on the VOCM pin. Submit Documentation Feedback Copyright (c) 2010-2013, Texas Instruments Incorporated Product Folder Links: LMP7312 LMP7312 www.ti.com SNOSB32B - MARCH 2010 - REVISED MARCH 2013 5V Electrical Characteristics (1) (continued) Unless otherwise specified, all limits ensured for TA = 25C, V+ = 5V, VIO = 5V, V- = 0V, G = 0.192 V/V, VCM_ATT=(+VIN+(VIN))/2, VCM_AMP=(+IN+(-IN))/2. Differential output configuration. SE = Single Ended Output, DE = Differential Output.Boldface limits apply at the temperature extremes. Symbol Parameter Conditions SR Slew Rate RL = 10 k, CL = 50 pF THD+N Total Harmonic Distorsion + Noise Vout = 4.096 Vpp, f = 1KHz, RL = 10 k (6) Min (2) Typ (3) 1.4 (6) Max (2) Units V/sec 0.0026 % The number specified is the average of rising and falling slew rates and is measured at 90% to 10%. Submit Documentation Feedback Copyright (c) 2010-2013, Texas Instruments Incorporated Product Folder Links: LMP7312 5 LMP7312 SNOSB32B - MARCH 2010 - REVISED MARCH 2013 www.ti.com Electrical Characteristics (Serial Interface) (1) Unless otherwise specified. All limits ensured for TA = 25C, V+ = 5V, V- = 0V, 2.7V < VIO < 5.5V Symbol Parameter Conditions VIL Input Logic Low Threshold VIH Input Logic High Threshold (SDO pin) VOL Output logic Low Threshold (SDO pin) VOH Min (2) Typ (3) Max (2) 0.8 2 Output logic High Threshold 0.2 ISDO= 2mA 0.4 VIO-0.2 ISDO= 2mA VIO-0.6 V V ISDO= 100A ISDO= 100A Units V V High Period, SCK (4) 100 ns t2 Low Period, SCK (4) 100 ns t3 Set Up Time, CS to SCK (4) 50 ns t4 Set Up Time, SDI to SCK (4) 30 ns t5 Hold Time, SCK to SDI (4) 10 t6 Prop. Delay, SCK to SDO (4) t7 Hold Time, SCK Transition to CS Rising Edge (4) t8 CS Inactive (4) 100 t9 Hold Time, SCK Transition to CS Falling Edge (4) 10 tR/tF Signal Rise and Fall Times (4) t1 (1) (2) (3) (4) ns 60 50 1.5 ns ns ns ns 5 ns Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No ensured specification of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ > TA. All limits are specified by testing, design, or statistical analysis. Typical values represent the most likely parametric norm at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped production material. Load for these tests is shown in Test Circuit Diagram. TEST CIRCUIT DIAGRAM IOL 100 PA VIO/2 TO SDO PIN CL 20 pF IOH 100 PA 6 Submit Documentation Feedback Copyright (c) 2010-2013, Texas Instruments Incorporated Product Folder Links: LMP7312 LMP7312 www.ti.com SNOSB32B - MARCH 2010 - REVISED MARCH 2013 Timing Diagram SCK t9 t1 t2 t3 t7 CS t4 t8 t5 DN SDI DN4 DN1 t6 SDO OLD DN OLD DN3 OLD DN4 Connection Diagram SDI 1 14 SCK +IN 2 13 V -IN 3 12 VOCM +VIN 4 11 -VOUT/VR -VIN 5 10 +VOUT CS 6 9 V SDO 7 8 VIO LMP7312 + Figure 1. 14-Pin SOIC-Top View PIN DESCRIPTIONS Pin Name Description 1 SDI SPI data IN 2 +IN Non-inverting input of Amplification pair 3 -IN Inverting input of Amplification pair 4 +VIN Non-inverting input of Attenuation pair 5 -VIN Inverting input of Attenuation pair 6 CS SPI chip select 7 SDO SPI data OUT 8 VIO SPI supply voltage 9 V+ Positive supply voltage 10 +VOUT Non-inverting output 11 -VOUT/VR Inverting output in differential output mode, reference input in single-ended operation mode 12 VOCM Output common mode voltage in DE 13 V- Negative supply voltage, reference for both Analog and Digital supplies 14 SCK SPI Clock Submit Documentation Feedback Copyright (c) 2010-2013, Texas Instruments Incorporated Product Folder Links: LMP7312 7 LMP7312 SNOSB32B - MARCH 2010 - REVISED MARCH 2013 www.ti.com Typical Performance Characteristics Unless otherwise specified, TA = 25C, V+ = 5V, VIO = 5V, V- = 0V, VCM_ATT=(+VIN+(-VIN))/2, VCM_AMP=(+IN+(-IN))/2. RL = 10k, CL =50pF, Differential output configuration. Offset Voltage distribution (PMOS) Offset Voltage distribution (NMOS) Figure 2. Figure 3. TCVOS distribution (PMOS) TCVOS distribution (NMOS) RELATIVE FREQUENCY (%) 15 Nulling Switch Mode VOCM = 1V 12 9 6 3 0 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 TCVOS (eV/C) Figure 4. Figure 5. Noise vs. Frequency (Core op-amp) 0.1Hz to 10Hz Noise (Core op-amp) 500 nV/DIV NOISE (nV/iHz) 100 10 1 10 100 1k 10k 100k 1M 1s/DIV FREQUENCY (Hz) Figure 6. 8 Figure 7. Submit Documentation Feedback Copyright (c) 2010-2013, Texas Instruments Incorporated Product Folder Links: LMP7312 LMP7312 www.ti.com SNOSB32B - MARCH 2010 - REVISED MARCH 2013 Typical Performance Characteristics (continued) Unless otherwise specified, TA = 25C, V+ = 5V, VIO = 5V, V- = 0V, VCM_ATT=(+VIN+(-VIN))/2, VCM_AMP=(+IN+(-IN))/2. RL = 10k, CL =50pF, Differential output configuration. Gain vs. Frequency (Attenuation Mode) Gain vs. Frequency (Amplification Mode) 9 0 Gain 2V/V 9 6 Gain 0.768V/V 6 33 GAIN (dB) GAIN (dB) -5 -10 Gain 0.384V/V -15 Gain 1V/V 0 0 Gain 0.192V/V -3 -3 -6 -20 Gain 0.096V/V -25 100 -6 1k 10k 100k 1M 10M 100 1k FREQUENCY (Hz) CMRR vs. Frequency (Attenuation Mode) CMRR vs. Frequency (Amplification Mode) 100 100 Gain 2V/V 90 90 CMRR (dB) Gain 0.384V/V 90 CMRR (dB) 1M Figure 9. Gain 0.768V/V 70 100k Figure 8. 100 80 10k FREQUENCY (Hz) Gain 0.192V/V Gain 0.096V/V Gain 1V/V 8080 70 70 60 60 50 60 VOCM = 4V 50 10 100 1k 10k 100k VOCM = 4V 50 10 1M 100 1k 10k 100k 1M FREQUENCY (Hz) FREQUENCY (Hz) Figure 10. Figure 11. PSRR (Core op-amp) Vos vs. Input Common Mode Voltage 110 15 10 100 NULLING SWITCH MODE 5 VOUT (PV) PSRR (dB) 90 80 70 0 -5 -10 -15 60 50 10 -20 100 1k 10k 100k 1M -25 1.0 1.0 2.0 2.5 3.0 3.5 4.0 VOCM (V) FREQUENCY (Hz) Figure 12. Figure 13. Submit Documentation Feedback Copyright (c) 2010-2013, Texas Instruments Incorporated Product Folder Links: LMP7312 9 LMP7312 SNOSB32B - MARCH 2010 - REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) Unless otherwise specified, TA = 25C, V+ = 5V, VIO = 5V, V- = 0V, VCM_ATT=(+VIN+(-VIN))/2, VCM_AMP=(+IN+(-IN))/2. RL = 10k, CL =50pF, Differential output configuration. Small signal step (Attenuation Mode) Small signal step (Amplification Mode) VCM_ATT = 2.5V VCM_AMP = 2.5V Gain 0.768V/V Gain 0.384V/V Input Gain 2V/V Gain 0.192V/V 200 mV/DIV 100 mV/DIV 20 mV/DIV 200 mV/DIV Input Gain 1V/V Gain 0.096V/V 5 Ps/DIV 5 Ps/DIV Figure 14. Figure 15. Large signal step (Attenuation Mode) Large signal step (Amplification Mode) VCM_ATT = 2.5V Input 5V/DIV 2V/DIV 2V/DIV Gain 2V/V 10V/DIV Gain 0.384V/V VCM_AMP = 2.5V Input Gain 0.768V/V Gain 1V/V Gain 0.192V/V Gain 0.096V/V 5 Ps/DIV 5 Ps/DIV Figure 16. Figure 17. Settling time - Rise (Attenuation Mode) Settling time - Rise (Amplification Mode) VCM_ATT = 2.5V VCM_AMP = 2.5V Input Gain 0.192V/V Gain 0.096V/V Gain 1V/V 100 mV/DIV Gain 2V/V 50 mV/DIV Input 100 mV/DIV 20 mV/DIV Gain 0.384V/V Gain 0.768V/V 500 ns/DIV 500 ns/DIV Figure 18. 10 Figure 19. Submit Documentation Feedback Copyright (c) 2010-2013, Texas Instruments Incorporated Product Folder Links: LMP7312 LMP7312 www.ti.com SNOSB32B - MARCH 2010 - REVISED MARCH 2013 Typical Performance Characteristics (continued) Unless otherwise specified, TA = 25C, V+ = 5V, VIO = 5V, V- = 0V, VCM_ATT=(+VIN+(-VIN))/2, VCM_AMP=(+IN+(-IN))/2. RL = 10k, CL =50pF, Differential output configuration. Settling time - Fall (Attenuation Mode) VCM_ATT = 2.5V 55 mV/DIV Gain 0.384V/V Gain 2V/V 100 mV/DIV 20 mV/DIV Gain 0.768V/V VCM_AMP = 2.5V Input 100 mV/DIV Input Settling time - Fall (Amplification Mode) Gain 0.096V/V Gain 1V/V Gain 0.192V/V 500 ns/DIV 500 ns/DIV Figure 20. Figure 21. Gain change (Attenuation Mode) Gain change (Amplification Mode) CS Gain 1V/V 1V/DIV 1V/DIV 2V/DIV Gain 0.096V/V 2V/DIV CS Gain 0.768V/V Gain 2V/V 10 Ps/DIV Figure 23. THD + N (Attenuation Mode) THD + N (Amplification Mode) 1 Differential Input VCM_AMP = 2.5V +VOUT -(-VOUT) = 4.096 Vpp +VOUT -(-VOUT) = 4.096 Vpp Gain 0.384V/V 0.1 Gain 0.192V/V 0.01 Differential Input 1 VCM_ATT = 2.5V THD + N (%) THD + N (%) 10 Ps/DIV Figure 22. 0.1 Gain 2V/V 0.01 Gain 0.768V/V 0.001 0.001 10 Gain 1V/V Gain 0.096V/V 100 1k 10k 100k 10 100 1k 10k 100k FREQUENCY (Hz) FREQUENCY (Hz) Figure 24. Figure 25. Submit Documentation Feedback Copyright (c) 2010-2013, Texas Instruments Incorporated Product Folder Links: LMP7312 11 LMP7312 SNOSB32B - MARCH 2010 - REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) Unless otherwise specified, TA = 25C, V+ = 5V, VIO = 5V, V- = 0V, VCM_ATT=(+VIN+(-VIN))/2, VCM_AMP=(+IN+(-IN))/2. RL = 10k, CL =50pF, Differential output configuration. IVA vs. VA IVIO vs. VIO Voltage 1.35 75 125C 67 1.27 IVIO (eA) IVA (mA) 1.31 25C 1.23 59 125C -40C 51 25C -40C 1.19 1.15 4.5 43 4.7 4.9 5.1 5.3 35 2.7 5.5 3.3 3.8 Short Circuit Current +VOUT vs. Temperature Short Circuit Current -VOUT vs. Temperature 30.0 30.0 Source 10.0 -10.0 Sink Source 10.0 -10.0 Sink -30.0 -30.0 -7 26 59 92 -50.0 -40 125 -7 TEMPERATURE (C) 59 92 125 Figure 28. Figure 29. Output voltage swing +VOUT vs. Output current Output voltage swing -VOUT vs. Output current 5.0 -40C SINK VIN+ = -15V VIN- = +15V 4.0 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 26 TEMPERATURE (C) 5.0 25C 3.0 125C 125C 2.0 25C SOURCE VIN+ = +15V VIN- = -15V 1.0 -40C SINK VIN+ = +15V VIN- = -15V 4.0 25C 3.0 125C 125C 2.0 25C SOURCE VIN+ = -15V VIN- = +15V 1.0 -40C -40C -20 -10 0 10 20 0 -30 30 -20 -10 0 10 20 30 OUTPUT CURRENT (mA) OUTPUT CURRENT (mA) Figure 30. 12 5.5 Figure 27. 50.0 0 -30 4.9 Figure 26. 50.0 -50.0 -40 4.4 VIO (V) IOUT (mA) IOUT (mA) VA (V) Figure 31. Submit Documentation Feedback Copyright (c) 2010-2013, Texas Instruments Incorporated Product Folder Links: LMP7312 LMP7312 www.ti.com SNOSB32B - MARCH 2010 - REVISED MARCH 2013 Typical Performance Characteristics (continued) Unless otherwise specified, TA = 25C, V+ = 5V, VIO = 5V, V- = 0V, VCM_ATT=(+VIN+(-VIN))/2, VCM_AMP=(+IN+(-IN))/2. RL = 10k, CL =50pF, Differential output configuration. SDO sink current vs. SDO Voltage 20.0 20.0 20.0 20.0 VIO = 2.7V 16.0 16.0 ISDO (mA) ISDO (mA) 16.0 16.0 12.0 12.0 8.0 8.0 VIO = 5.5V 12.0 12.0 VIO = 5.5V 8.0 8.0 4.0 VIO = 2.7V 4.0 4.0 4.0 0 0 SDO source current vs. SDO Voltage 0 0 0.3 0.6 0.9 1.2 1.5 VSDO (V) 0 1.0 2.0 3.0 4.0 5.0 6.0 VSDO (V) Figure 32. Figure 33. Submit Documentation Feedback Copyright (c) 2010-2013, Texas Instruments Incorporated Product Folder Links: LMP7312 13 LMP7312 SNOSB32B - MARCH 2010 - REVISED MARCH 2013 www.ti.com APPLICATION SECTION GENERAL DESCRIPTION The LMP7312 is a single supply programmable gain difference amplifier with two input pairs: Attenuation pair (VIN, +VIN) and Amplification pair (-IN, +IN). The output can be configured in both single-ended and differential modes with the output common mode voltage set by the user. The input selection, the gains and the mode of operation of the LMP7312 are controlled through a 4- wire SPI interface (SCK, CS, SDI, SDO). These features combined make the LMP7312 a very easy interface between the analog high voltage industrial buses and the low voltage digital converters. OUTPUT MODE CONFIGURATION The LMP7312 is able to work in both single ended and differential output mode. The selection of the mode is made through the VOCM (output common mode voltage) pin. Differential Output This mode of operation is enabled when the output common mode voltage pin (VOCM) is connected to a voltage higher than 1V, for instance the common mode voltage supplied by an ADC, (Figure 34) or a voltage reference. If the VOCM pin is floating an internal voltage divider biases it at the half supply voltage. In this configuration the output signals are set on the VOCM voltage level. Single-Ended Output This mode of operation is enabled when the VOCM pin is tied to a voltage less than 0.5 V, for example to ground. In this mode of operation the LMP7312 behaves as a difference amplifier, where the +VOUT pin is the singleended output while the -VOUT /VR is the reference voltage. 1. In the case of bipolar input signal the non inverting output will be connected to an external reference through a buffer (Figure 35). 2. In the case of unipolar input signal the non inverting output will be connected to ground (Figure 36). In both cases the inverting output pin is configured as an input pin. V VIO SCK CS SDI SDO + SPI Controller R1N -VIN RFP R2N -IN - +IN + VREF +VOUT + V ADC ADC -VOUT/VR R2P +VIN R1P V VCM + RF 100 k: N VOCM 100 k: V - V + Figure 34. Differential ADC Interfacing with VCM provided by the ADC 14 Submit Documentation Feedback Copyright (c) 2010-2013, Texas Instruments Incorporated Product Folder Links: LMP7312 LMP7312 www.ti.com SNOSB32B - MARCH 2010 - REVISED MARCH 2013 V + VIO SCK CS SDI SDO -VIN SPI Controller R1N RFP R2N -IN - +IN + VAC + +VOUT VREF ADC -VOUT/VR R2P VDC V ADC +VIN + - V + R1P 100 k: RFN VOCM + 100 k: V - VAC >0 , VAC <0 Where VAC = -VIN (+VIN) V - Figure 35. Bipolar Input Signal to Single-Ended ADC Interface + V VIO SCK CS SDI SDO -VIN SPI Controller R1N R2N RFP -IN - +IN + VAC ADC -VOUT/VR R2P VDC + V ADC +VOUT + + - +VIN V R1P RF 100 k: N VOCM 100 k: - V VAC > 0 Where VAC = -VIN (+VIN) - V Figure 36. Unipolar Input Signal to Single-Ended ADC Interface Submit Documentation Feedback Copyright (c) 2010-2013, Texas Instruments Incorporated Product Folder Links: LMP7312 15 LMP7312 SNOSB32B - MARCH 2010 - REVISED MARCH 2013 www.ti.com INPUT VOLTAGE RANGE The LMP7312 has an internal OpAmp with rail-to-rail input voltage range capability. The requirement to stay within the V-and V+ rail at the OpAmp input translates in an Input Voltage Range specification as explained in this application section. Differential Output Considering a single positive supply (V-= GND, V+ = VS) the Input Common mode voltage, VCM_ATT = (+VIN + (VIN))/2 for the Attenuation inputs and VCM_AMP = (+IIN + (-IIN))/2 for the Amplification inputs, has to stay between the MIN and MAX values determined by these formulas: CMMAX = VS + 1/KV*(VS - VOCM) CMMIN = -1/KV*VOCM KV is a function of the Gain according to the table below: Gain 0.096 V/V 0.192 V/V 0.384 V/V 0.768 V/V 1 V/V 2 V/V KV 0.12 0.218 0.414 0.806 1.065 2.096 Regardless to the values derived by the formula, the voltage on each input pin must never exceed the specified Absolute Maximum Ratings. Below are some typical values: Table 1. Differential Input, Differential Output, VS= 5V, VOCM = 2.5V VCM_ATT (1) VCM_AMP Gain Min Max 0.096 V/V -15 V (1) +15 V (1) Min Max 0.192 V/V -11.5 V +15 V 0.384 V/V -6 V +11 V 0.768 V/V 1 V/V -3.1 V +8.1 V -2.3 V +7.3 V 2 V/V -1.2 V +6.2 V Limited by the operating ratings on input pins In the case of a single ended input referred to ground (-VIN = GND, -IN = GND) the table below summarizes the voltage range allowed on the +VIN and +IIN inputs. Table 2. Single Ended Input, Differential Output, VS= 5V, VOCM = 2.5V, -VIN = GND, -IIN = GND +VIN Gain (1) (2) 16 Min (1) +IN Max +15 V Min Max (1) 0.096 V/V -15 V 0.192 V/V -15 V (1) +15 V (1) 0.384 V/V -12 V (2) +12 V (2) 0.768 V/V -6 V (2) +6 V (2) 1 V/V -4.6 V (2) +4.6 V (2) 2 V/V (2) +2.3 V (2) -2.3 V Limited by the operating ratings on input pins. Limited by the output voltage swing (0.2V to VS-0.2V on both + VOUT and -VOUT) Submit Documentation Feedback Copyright (c) 2010-2013, Texas Instruments Incorporated Product Folder Links: LMP7312 LMP7312 www.ti.com SNOSB32B - MARCH 2010 - REVISED MARCH 2013 Single Ended Output In this mode the LMP7312 behaves as a Difference Amplifier, with -VOUT/VR being the reference output voltage when a zero volt differential input signal is applied. The voltages at the OpAmp inputs are determined by +VIN and -VOUT/VR voltages. The voltage range of +VIN and +IIN inputs is as follows: VMAX = VS + 1/ KV * (VS - (-VOUT/VR)) VMIN = -1/KV * (-VOUT/VR) Regardless of the values derived by the formula, the voltage on each input pin must never exceed the specified Absolute Maximum Ratings. Below are some typical values: Table 3. Differential Input, Single Ended Output, VS = 5V, VOCM = GND, and -VOUT/VR = 2.5V +VIN Gain Min Max 1 V/V -2.3 V +7.3 V 2 V/V -1.2 V +6.2 V 0.096 V/V (1) +IIN Min -15 V Max (1) +15 V (1) 0.192 V/V -11.5 V (1) 0.384 V/V -6 V +11 V 0.768 V/V -3.1 V +8.1 V +15 V Limited by the operating ratings on input pins In the case of a single ended input referred to ground (-VIN = GND, -IN = GND) this table summarize the voltage ranges allowed on the +VIN and +IIN inputs. Table 4. Single Ended Input, Single Ended Output, VS = 5V, VOCM = GND, -VOUT/VR = 2.5V, -VIN = GND, -IIN = GND +VIN Gain +IIN Min (1) 0.096 V/V -15 V 0.192 V/V -11.5 V (2) 0.384 V/V -6 V 0.768 V/V -3 V** Max +15 V Min Max (1) +12 V (2) +6 V (2) +3 V (2) 1 V/V -2.3 V (2) +2.3 V (2) 2 V/V (2) +1.1 V (2) (1) (2) -1.1 V Limited by the operating ratings on input pins. Limited by the output voltage swing (0.2V to VS-0.2V on +VOUT ) SERIAL INTERFACE CONTROL OPERATION The serial interface control of the LMP7312 can be supplied with a voltage between 2.7V and 5.5V through the VIO pin for compatibility with different logic families present in the market. The LMP7312 Attenuation, Amplification, Null switch and HiZ modes are controlled by a register. Data to be written into the control register is first loaded into the LMP7312 via the serial interface. The serial interface employs a 5-bit shift register. Data is loaded through the serial data input, SDI. Data passing through the shift register is obtained through the serial data output, SDO. The serial clock, SCK controls the serial loading process. All five data bits are required to correctly program the device. The falling edge of CS enables the shift register to receive data. The SCK signal must be high during the falling edge of CS. Each data bit is clocked into the shift register on the rising edge of SCK. Data is transferred from the shift register to the holding register on the rising edge of CS. Operation is shown in the Timing Diagram. Submit Documentation Feedback Copyright (c) 2010-2013, Texas Instruments Incorporated Product Folder Links: LMP7312 17 LMP7312 SNOSB32B - MARCH 2010 - REVISED MARCH 2013 www.ti.com SPI Registers MSB Gain_1 LSB Gain_0 EN_CL Null_SW Hi_Z Gain_0, Gain_1 bit:Gain Values Different gains are available in Attenuation Mode or Amplification Mode according to the following Gain Table. Gain_1 Gain_0 EN_CL Gain Value (V/V) 0 0 0 0.096 0 1 0 0.192 1 0 0 0.384 1 1 0 0.768 1 0 1 1 1 1 1 2 EN_CL bit:Enable Amplification Mode This register selects which input pair is processed. EN_CL Mode 0 Attenuation Mode Description 1 Amplification Mode VIN inputs are processed through the 104.16k input resistors IN inputs are processed through the 40k input resistors NULL_SW bit: Input Offset Nulling Switch Mode This register selects a mode in which the amplifier is not processing any input but it is configured in unity gain to allow system level amplifier offset calibration. The Nulling Switch mode is available in both single ended and fully differential output mode. The LMP7312 in Nulling Switch and fully differential mode has he following configuration. 18 NULL_SW Mode Description 0 Normal Operation Mode VIN and IN inputs are processed depending on EN_CL register setting. 1 Nulling Switch Mode Enables to evaluate the offset of the internal amplifier for system level calibration Submit Documentation Feedback Copyright (c) 2010-2013, Texas Instruments Incorporated Product Folder Links: LMP7312 LMP7312 www.ti.com SNOSB32B - MARCH 2010 - REVISED MARCH 2013 VIO + V R1N -VIN R2 N RFP -IN +IN - +VOUT + -VOUT/VR R2 P +VIN V + RF R1 P N 100 k: VOCM 100 k: - V - V Figure 37. LMP7312 in Nulling Switch Mode In this condition at the Output pins is possible to measure the input voltage offset of the op-amp: Output Mode Differential Single-Ended +VOUT -VOUT/VR VCM_out+VOS/2 VCM_out -VOS/2 VR+VOS VR Hi_Z bit:High Impedance In this mode both outputs +VOUT and -VOUT/VR of the LMP7312 are in tri-state Figure 38. HI_Z Mode 0 Normal Operation Mode Description 1 High Impedance Mode The LMP7312 is configured according to value of the other 4 bits of the register. The LMP7312 output is in high impedance Submit Documentation Feedback Copyright (c) 2010-2013, Texas Instruments Incorporated Product Folder Links: LMP7312 19 LMP7312 SNOSB32B - MARCH 2010 - REVISED MARCH 2013 www.ti.com + VIO V R1N -VIN RFP R2 N -IN +IN - +VOUT + -VOUT/VR R2 P +VIN V + R1 P RF N 100 k: VOCM 100 k: - V - V Figure 38. LMP7312 in High Impedance Mode In each case the SPI registers require 5 bits. The table below is a summary of all allowed configurations. MSB LSB Gain_1 Gain_0 EN_CL Null_SW Hi_Z Gain Value (V/V) Mode of Operation 0 0 0 0 0 0.096 Attenuation Mode 0 1 0 0 0 0.192 Attenuation Mode 1 0 0 0 0 0.384 Attenuation Mode 1 1 0 0 0 0.768 Attenuation Mode 1 0 1 0 0 1 Amplification Mode 1 1 1 0 0 2 Amplification Mode x x x x 1 - High Impedance Output x x x 1 0 1 Null Switch Mode Daisy Chain The LMP7312 supports daisy chaining of the serial data stream between multiple chips. To use this feature serial data is clocked into the first chip SDI pin, and the next chip SDI pin is connected to the SDO pin of the first chip. Both chips may share a chip select signal, or the second chip can be enabled separately. When the chip select pin goes low on both chips and 5 bits have been clocked into the first chip the next 5 clock cycle begins moving new configuration data into the second chip. With a full 10 clock cycles both chips have valid data and the chip select pin of both chips should be brought high to prevent the data from overshooting. 20 Submit Documentation Feedback Copyright (c) 2010-2013, Texas Instruments Incorporated Product Folder Links: LMP7312 LMP7312 www.ti.com SNOSB32B - MARCH 2010 - REVISED MARCH 2013 CS CS CS LMP7312 LMP7312 eController MOSI SDI SDO SDO SDI SCK SCK SCK MISO Figure 39. Daisy Chain Shared 4-wire SPI with ADC The LMP7312 is a good choice when interfacing to differential analog to digital converters ADC141S626 and ADC161S626 of PowerWise(R) Family. Its SPI interface has been designed to enable sharing CSB with the ADC. LMP7312 register access happens only when CSB is asserted low while SCK is high. However, the ADC starts conversion under any of the following conditions: 1. CSB goes low while SCK is high 2. CSB goes low while SCK is low 3. CSB and SCK both going low Therefore, if a system uses timing condition #2 above, LMP7312 and ADC1x1S626 can share CSB and SCK as shown in Figure 40. The only side-effect would be that writing to LMP7312 triggers an ADC conversion, but then the result can be ignored. At other times, the LMP7312 is not affected by the CSB assertions used to initiate normal ADC conversions. CS CS CS LMP7312 ADC1x1S626 eController MOSI SDI SDO SCK SCK SCK MISO Figure 40. 4-wire SPI with ADC interface LMP7312 IN 4-20mA CURRENT LOOP APPLICATION The 4-20mA current loop shown in Figure 41 is a common method of transmitting sensor information in many industrial process-monitoring applications. Transmitting sensor information via a current loop is particularly useful when the information has to be sent to a remote location over long distances (1000 feet, or more). The loop's operation is straightforward: a sensor's output voltage is first converted to a proportional current, with 4mA normally representing the sensor's zero-level output, and 20mA representing the sensor's full-scale output. Then, a receiver at the remote end converts the 4-20mA current back into a voltage which in turn can be further processed by a computer or display module. A typical 4-20mA current-loop circuit is made up of four individual elements: a sensor/transducer; a voltage-to-current converter (commonly referred to as a transmitter and/or signal conditioner); a loop power supply; and a receiver/monitor. In loop powered applications, all four elements Submit Documentation Feedback Copyright (c) 2010-2013, Texas Instruments Incorporated Product Folder Links: LMP7312 21 LMP7312 SNOSB32B - MARCH 2010 - REVISED MARCH 2013 www.ti.com are connected in a closed, series circuit, loop configuration (Figure 41). Sensors provide an output voltage whose value represents the physical parameter being measured. The transmitter amplifies and conditions the sensor's output, and then converts this voltage to a proportional 4-20mA dc-current that circulates within the closed series-loop. The loop power-supply generally provides all operating power to the transmitter and receiver, and any other loop components that require a well-regulated dc voltage. In loop-powered applications, the power supply's internal elements also furnish a path for closing the series loop. The receiver/monitor, normally a subsection of a panel meter or data acquisition system, converts the 4-20mA current back into a voltage which can be further processed and/or displayed. The high DC performance of the LMP7312 makes this difference amplifier an ideal choice for use in current loop AFE receiver. The LMP7312 has a low input offset voltage and low input offset voltage drift when configured in amplification mode. In the circuit shown in Figure 41 the LMP7312 is in amplification mode with a gain of 2V/V and differential output in order to well match the input stage of the ADC141S626 (SAR ADC with differential input). The shunt resistor is 100ohm in order to have a max voltage drop of 2V when 20mA flows in the loop. The first order filter between the LMP7312 and the ADC141S626 reduces the noise bandwidth and allows handling input signal up to 2kHz. That frequency has been calculated taking in account the roll off of the filter and ensuring a gain error less than 1LSB of the ADC141S626. In order to utilize the maximum number of bits of the ADC141S626 in this configuration, a 4.1V reference voltage is used. With this system, the current of the 4-20mA loop is accurately gained to the full scale of the ADC and then digitized for further processing. +5V + 0.1 PF 10 PF + VIO V +5V -VIN + +VOUT - SENSOR T R A N S M I T T E R 100: - -IN + 1.1k: VA + I_LOOP -VOUT/VR V +VIN 0.1 PF VOCM V +5V LM4132-4.1 + + 4.7 PF 4.7 PF 100 k: - REF 0.1 PF 100 k: 10 PF 1.1k: Fs = 70 kS/s + 0.1 PF ADC141S626 680 pF +IN VIO - AMPLIFICATION MODE G = 2 V/V V Figure 41. LMP7312 in 4-20mA Current Loop application LAYOUT CONSIDERATIONS Power supply bypassing In order to preserve the gain accuracy of the LMP7312, power supply stability requires particular attention. The LMP7312 ensures minimum PSRR of 90dB (or 31.62 V/V). However, the dynamic range, the gain accuracy and the inherent low-noise of the amplifier can be compromised by introducing and amplifying power supply noise. To decouple the LMP7312 from supply line AC noise, a 0.1 F ceramic capacitor should be located on the supply line, close to the LMP7312. Adding a 10 F tantalum capacitor in parallel with the 0.1 F ceramic capacitor will reduce the noise introduced to the LMP7312 even further by providing an AC path to ground for most frequency ranges. 22 Submit Documentation Feedback Copyright (c) 2010-2013, Texas Instruments Incorporated Product Folder Links: LMP7312 LMP7312 www.ti.com SNOSB32B - MARCH 2010 - REVISED MARCH 2013 APPENDIX Offset Voltage and Offset Voltage Drift calculation Listed in the table below are the calculated values for Offset Voltage and Offset Voltage Drift based on the max specifications of these parameters for the core op-amp (for all gain configurations). Parameter Unit Value Gain V/V 0.096 0.192 0.384 0.768 1 2 Total Offset Input Referred (MAX) V 1141 620 360 230 200 150 Total Offset Output Referred (MAX) V 109 119 138 176 200 300 TCVOS Input Referred @ 25C (MAX) V/C 32.3 18.6 10.8 6.9 6 4.5 TCVOS Output Referred @ 25C (MAX) V/C 3.3 3.6 4.1 5.3 6 9 Noise calculation Listed in the table below are the calculated values for Voltage Noise based on the spectral density of the core op-amp at 10kHz (for all gain configurations). Parameter Unit Gain Value V/V 0.096 0.192 0.384 0.768 1 2 Total Noise Referred to Input nV/Hz 211 150 112 89 53 46 Total Noise Referred to Output nV/Hz 20 29 43 68 53 92 Input resistance calculation The common mode input resistance is the resistance seen from node "A" when V1 = V2 = 0 and a common mode voltage VCM is applied to both inputs of the LMP7312. The differential input resistance is the resistance seen from the nodes "B" and "C" when VCM=0 and a differential voltage V1 = V2 = V/2 is applied to the inputs of the LMP7312. B + A + - + - AV1 - AV2 + AVCM C Figure 42. Circuit for Input Resistance calculation Mode of Operation Unit Attenuation Mode Gains 0.096 0.192 0.384 Common Mode Resistance k 57.08 62.08 72.08 92.08 Differential Resistance k 228.30 248.30 288.30 368.30 1 2 Common Mode Resistance k 40.0 60.0 Differential Resistance k 160.0 240.0 Amplification Mode 0.768 Submit Documentation Feedback Copyright (c) 2010-2013, Texas Instruments Incorporated Product Folder Links: LMP7312 23 LMP7312 SNOSB32B - MARCH 2010 - REVISED MARCH 2013 www.ti.com REVISION HISTORY Changes from Revision A (March 2013) to Revision B * 24 Page Changed layout of National Data Sheet to TI format .......................................................................................................... 23 Submit Documentation Feedback Copyright (c) 2010-2013, Texas Instruments Incorporated Product Folder Links: LMP7312 PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (C) Top-Side Markings (3) (4) LMP7312MA/NOPB ACTIVE SOIC D 14 55 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LMP7312 MA LMP7312MAX/NOPB ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LMP7312 MA (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. 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Addendum-Page 1 Samples PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device LMP7312MAX/NOPB Package Package Pins Type Drawing SOIC D 14 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 16.4 Pack Materials-Page 1 6.5 B0 (mm) K0 (mm) P1 (mm) 9.35 2.3 8.0 W Pin1 (mm) Quadrant 16.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMP7312MAX/NOPB SOIC D 14 2500 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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