20 V, 300 mA, Low Noise, CMOS LDO ADP7102 Data Sheet FEATURES TYPICAL APPLICATION CIRCUITS VIN = 8V CIN + 1F R1 100k ON OFF R2 100k VIN VOUT SENSE VOUT = 5V + COUT 1F RPG 100k EN/ UVLO PG PG 09506-001 GND Figure 1. ADP7102 with Fixed Output Voltage, 5 V VIN = 8V ON OFF CIN + 1F R3 100k R4 100k VIN VOUT ADJ EN/ UVLO PG R1 40.2k R2 13k VOUT = 5V + COUT 1F RPG 100k PG GND 09506-002 Input voltage range: 3.3 V to 20 V Maximum output current: 300 mA Low noise: 15 V rms for fixed output versions PSRR performance of 60 dB at 10 kHz, VOUT = 3.3 V Reverse current protection Low dropout voltage: 200 mV at 300 mA load Initial accuracy: 0.8% Accuracy over line, load, and temperature: -2%, +1% Low quiescent current (VIN = 5 V), IGND = 750 A with 300 mA load Low shutdown current: 40 A at VIN = 12 V Stable with small 1 F ceramic output capacitor 7 fixed output voltage options: 1.5 V, 1.8 V, 2.5 V, 3 V, 3.3 V, 5 V, and 9 V Adjustable output from 1.22 V to VIN - VDO Foldback current limit and thermal overload protection User programmable precision UVLO/enable Power-good indicator 8-lead LFCSP and 8-lead SOIC packages Figure 2. ADP7102 with Adjustable Output Voltage, 5 V APPLICATIONS Regulation to noise sensitive applications: ADC, DAC circuits, precision amplifiers, high frequency oscillators, clocks, and phase-locked loops Communications and infrastructure Medical and healthcare Industrial and instrumentation GENERAL DESCRIPTION The ADP7102 is a CMOS, low dropout linear regulator that operates from 3.3 V to 20 V and provides up to 300 mA of output current. This high input voltage LDO is ideal for regulation of high performance analog and mixed signal circuits operating from 19 V to 1.22 V rails. Using an advanced proprietary architecture, it provides high power supply rejection, low noise, and achieves excellent line and load transient response with just a small 1 F ceramic output capacitor. The ADP7102 is available in seven fixed output voltage options and an adjustable version, which allows output voltages that range from 1.22 V to VIN - VDO via an external feedback divider. Rev. E The ADP7102 output noise voltage is 15 V rms and is independent of the output voltage. A digital power-good output allows power system monitors to check the health of the output voltage. A user programmable precision undervoltage lockout function facilitates sequencing of multiple power supplies. The ADP7102 is available in 8-lead, 3 mm x 3 mm LFCSP and 8-lead SOIC packages. The LFCSP offers a very compact solution and also provides excellent thermal performance for applications requiring up to 300 mA of output current in a small, low profile footprint. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 (c)2011-2015 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADP7102 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation ...................................................................... 17 Applications ....................................................................................... 1 Applications Information .............................................................. 18 Typical Application Circuits............................................................ 1 Capacitor Selection .................................................................... 18 General Description ......................................................................... 1 Programable Undervoltage Lockout (UVLO)........................... 19 Revision History ............................................................................... 2 Power-Good Feature .................................................................. 20 Specifications..................................................................................... 3 Noise Reduction of the Adjustable ADP7102............................ 20 Input and Output Capacitor, Recommended Specifications .. 4 Current Limit and Thermal Overload Protection ................. 21 Absolute Maximum Ratings............................................................ 5 Thermal Considerations............................................................ 21 Thermal Data ................................................................................ 5 Printed Circuit Board Layout Considerations ............................ 24 ESD Caution .................................................................................. 5 Outline Dimensions ....................................................................... 25 Pin Configurations and Function Descriptions ........................... 6 Ordering Guide .......................................................................... 26 Typical Performance Characteristics ............................................. 7 REVISION HISTORY 9/15--Rev. D to Rev. E Changes to Figure 60 ...................................................................... 17 5/14--Rev. C to Rev. D Changed UVLO Threshold Rising Typ Parameter from 1.23 V to 1.22 V; Table 1 ............................................................................... 4 Changes to Power Good Section .................................................. 20 Updated Outline Dimensions ....................................................... 26 8/13--Rev. B to Rev. C Changes to Table 3 ............................................................................ 5 2/13--Rev. A to Rev. B Changes to Noise Reduction of the Adjustable ADP7102 Section .............................................................................................. 20 11/11--Rev. 0 to Rev. A Changes to Figure 50 ...................................................................... 14 10/11--Revision 0: Initial Version Rev. E | Page 2 of 28 Data Sheet ADP7102 SPECIFICATIONS VIN = (VOUT + 1 V) or 3.3 V (whichever is greater), EN = VIN, IOUT = 10 mA, CIN = COUT = 1 F, TA = 25C, unless otherwise noted. Table 1. Parameter INPUT VOLTAGE RANGE OPERATING SUPPLY CURRENT Symbol VIN IGND SHUTDOWN CURRENT IGND-SD INPUT REVERSE CURRENT IREV-INPUT OUTPUT VOLTAGE ACCURACY Fixed Output Voltage Accuracy Adjustable Output Voltage Accuracy IOUT = 100 A, VIN = 10 V IOUT = 100 A, VIN = 10 V, TJ = -40C to +125C IOUT = 10 mA, VIN = 10 V IOUT = 10 mA, VIN = 10 V, TJ = -40C to +125C IOUT = 150 mA, VIN = 10 V IOUT = 150 mA, VIN = 10 V, TJ = -40C to +125C IOUT = 300 mA, VIN = 10 V IOUT = 300 mA, VIN = 10 V, TJ = -40C to +125C EN = GND, VIN = 12 V EN = GND, VIN = 12 V, TJ = -40C to +125C EN = GND, VIN = 0 V, VOUT = 20 V EN = GND, VIN = 0 V, VOUT = 20 V, TJ = -40C to +125C Typ Max 20 5 Unit V A A A A A A A A A A A A 400 900 450 1050 650 1250 750 1400 40 75 0.3 IOUT = 10 mA -0.8 +0.8 % -2 +1 % VADJ 1 mA < IOUT < 300 mA, VIN = (VOUT + 1 V) to 20 V, TJ = -40C to +125C IOUT = 10 mA 1.23 V 1 mA < IOUT < 300 mA, VIN = (VOUT + 1 V) to 20 V, TJ = -40C to +125C VIN = (VOUT + 1 V) to 20 V, TJ = -40C to +125C IOUT = 1 mA to 300 mA IOUT = 1 mA to 300 mA, TJ = -40C to +125C 1 mA < IOUT < 300 mA, VIN = (VOUT + 1 V) to 20 V, ADJ connected to VOUT 1 mA < IOUT < 300 mA, VIN = (VOUT + 1 V) to 20 V, SENSE connected to VOUT, VOUT = 1.5 V IOUT = 10 mA IOUT = 10 mA, TJ = -40C to +125C IOUT = 150 mA IOUT = 150 mA, TJ = -40C to +125C IOUT = 300 mA IOUT = 300 mA, TJ = -40C to +125C VOUT = 5 V 1.196 1.232 V +0.015 10 %/V %/A %/A nA 1 A VOUT/VIN VOUT/IOUT ADJ INPUT BIAS CURRENT ADJI-BIAS SENSE INPUT BIAS CURRENT SENSEI-BIAS DROPOUT VOLTAGE2 VDROPOUT START-UP TIME CURRENT-LIMIT THRESHOLD4 PG OUTPUT LOGIC LEVEL PG Output Logic High PG Output Logic Low PG OUTPUT THRESHOLD Output Voltage Falling Output Voltage Rising Min 3.3 VOUT LINE REGULATION LOAD REGULATION1 3 Test Conditions/Comments tSTART-UP ILIMIT PGHIGH PGLOW 1.21 -0.015 0.2 1.0 20 750 mV mV mV mV mV mV s mA 0.4 V V 40 100 175 200 325 450 IOH < 1 A IOL < 2 mA 1.22 800 575 1.0 PGFALL PGRISE -9.2 -6.5 Rev. E | Page 3 of 28 % % ADP7102 Parameter THERMAL SHUTDOWN Thermal Shutdown Threshold Thermal Shutdown Hysteresis PROGRAMMABLE EN/UVLO UVLO Threshold rising UVLO Threshold falling UVLO Hysteresis Current Enable Pulldown Current INPUT VOLTAGE Start Threshold Shutdown Threshold Hysteresis OUTPUT NOISE POWER SUPPLY REJECTION RATIO Data Sheet Symbol Test Conditions/Comments TSSD TJ rising Min TSSD-HYS UVLORISE UVLOFALL UVLOHYS I EN-IN 3.3 V V IN 20 V, T J = -40C to +125C 3.3 V V IN 20 V, T J = -40C to +125C, 10 k in series with enable pin VEN > 1.25 V, TJ = -40C to +125C EN = VIN VSTART VSHUTDOWN TJ = -40C to +125C TJ = -40C to +125C OUTNOISE 10 Hz to 100 kHz, VIN = 5.5 V, VOUT = 1.8 V 10 Hz to 100 kHz, VIN = 6.3 V, VOUT = 3.3 V 10 Hz to 100 kHz, VIN = 8 V, VOUT = 5 V 10 Hz to 100 kHz, VIN = 12 V, VOUT = 9 V 10 Hz to 100 kHz, VIN = 5.5 V, VOUT = 1.5 V, adjustable mode 10 Hz to 100 kHz, VIN = 12 V, VOUT = 5 V, adjustable mode 10 Hz to 100 kHz, VIN = 18 V, VOUT = 15 V, adjustable mode 100 kHz, VIN = 4.3 V, VOUT = 3.3 V PSRR Typ Max Unit 150 C 15 C 1.18 1.22 1.13 1.28 V V 7.5 9.8 500 12 A nA 3.2 250 15 15 15 15 18 V V mV V rms V rms V rms V rms V rms 30 V rms 65 V rms 50 dB 50 60 60 50 60 60 60 80 80 dB dB dB dB dB dB dB dB dB 2.45 100 kHz, VIN = 6 V, VOUT = 5 V 10 kHz, VIN = 4.3 V, VOUT = 3.3 V 10 kHz, VIN = 6 V, VOUT = 5 V 100 kHz, VIN = 3.3 V, VOUT = 1.8 V, adjustable mode 100 kHz, VIN = 6 V, VOUT = 5 V, adjustable mode 100 kHz, VIN = 16 V, VOUT = 15 V, adjustable mode 10 kHz, VIN = 3.3 V, VOUT = 1.8 V, adjustable mode 10 kHz, VIN = 6 V, VOUT = 5 V, adjustable mode 10 kHz, VIN = 16 V, VOUT = 15 V, adjustable mode 1 Based on an end point calculation using 1 mA and 300 mA loads. See Figure 6 for typical load regulation performance for loads less than 1 mA. Dropout voltage is defined as the input to output voltage differential when the input voltage is set to the nominal output voltage. This applies only for output voltages above 3.0 V. 3 Start-up time is defined as the time between the rising edge of EN to VOUT being at 90% of its nominal value. 4 Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 5.0 V output voltage is defined as the current that causes the output voltage to drop to 90% of 5.0 V, or 4.5 V. 2 INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS Table 2. Parameter Minimum Input and Output Capacitance1 Capacitor ESR 1 Symbol CMIN RESR Test Conditions/Comments TA = -40C to +125C TA = -40C to +125C Min 0.7 0.001 Typ Max 0.2 Unit F The minimum input and output capacitance should be greater than 0.7 F over the full range of operating conditions. The full range of operating conditions in the application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended; Y5V and Z5U capacitors are not recommended for use with any LDO. Rev. E | Page 4 of 28 Data Sheet ADP7102 ABSOLUTE MAXIMUM RATINGS Table 3. Parameter VIN to GND VOUT to GND EN/UVLO to GND PG to GND SENSE/ADJ to GND Storage Temperature Range Operating Junction Temperature Range Soldering Conditions Rating -0.3 V to +22 V -0.3 V to +20 V -0.3 V to VIN -0.3 V to VIN -0.3 V to VOUT -65C to +150C -40C to +125C JEDEC J-STD-020 Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. THERMAL DATA Absolute maximum ratings apply individually only, not in combination. The ADP7102 can be damaged when the junction temperature limit is exceeded. Monitoring ambient temperature does not guarantee that TJ is within the specified temperature limits. In applications with high power dissipation and poor thermal resistance, the maximum ambient temperature may have to be derated. In applications with moderate power dissipation and low printed circuit board (PCB) thermal resistance, the maximum ambient temperature can exceed the maximum limit as long as the junction temperature is within specification limits. The junction temperature (TJ) of the device is dependent on the ambient temperature (TA), the power dissipation of the device (PD), and the junction to ambient thermal resistance of the package (JA). Maximum junction temperature (TJ) is calculated from the ambient temperature (TA) and power dissipation (PD) using the formula In applications where high maximum power dissipation exists, close attention to thermal board design is required. The value of JA may vary, depending on PCB material, layout, and environmental conditions. The specified values of JA are based on a 4-layer, 4 in. x 3 in. circuit board. See JESD51-7 and JESD51-9 for detailed information on the board construction. For additional information, see the AN-617 Application Note, MicroCSP Wafer Level Chip Scale Package. JB is the junction to board thermal characterization parameter with units of C/W. The package's JB is based on modeling and calculation using a 4-layer board. The JESD51-12, Guidelines for Reporting and Using Electronic Package Thermal Information, states that thermal characterization parameters are not the same as thermal resistances. JB measures the component power flowing through multiple thermal paths rather than a single path as in thermal resistance, JB. Therefore, JB thermal paths include convection from the top of the package as well as radiation from the package, factors that make JB more useful in real-world applications. Maximum junction temperature (TJ) is calculated from the board temperature (TB) and power dissipation (PD) using the formula TJ = TB + (PD x JB) See JESD51-8 and JESD51-12 for more detailed information about JB. Thermal Resistance JA and JB are specified for the worst case conditions, that is, a device soldered in a circuit board for surface-mount packages. JC is a parameter for surface-mount packages with top mounted heat sinks. JC is presented here for reference only. Table 4. Thermal Resistance Package Type 8-Lead LFCSP 8-Lead SOIC ESD CAUTION TJ = TA + (PD x JA) Junction to ambient thermal resistance (JA) of the package is based on modeling and calculation using a 4-layer board. The junction to ambient thermal resistance is highly dependent on the application and board layout. Rev. E | Page 5 of 28 JA 40.1 48.5 JC 27.1 58.4 JB 17.2 31.3 Unit C/W C/W ADP7102 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TOP VIEW (Not to Scale) NC 4 VOUT 1 7 PG SENSE/ADJ 2 5 EN/UVLO NOTES 1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN. 2. IT IS HIGHLY RECOMMENDED THAT THE EXPOSED PAD ON THE BOTTOM OF THE PACKAGE BE CONNECTED TO THE GROUND PLANE ON THE BOARD. 8 ADP7102 VIN PG TOP VIEW GND 3 (Not to Scale) 6 GND NC 4 5 EN/UVLO 6 GND 7 NOTES 1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN. 2. IT IS HIGHLY RECOMMENDED THAT THE EXPOSED PAD ON THE BOTTOM OF THE PACKAGE BE CONNECTED TO THE GROUND PLANE ON THE BOARD. 09506-003 GND 3 8 VIN ADP7102 09506-104 VOUT 1 SENSE/ADJ 2 Figure 4. Narrow Body SOIC Package Figure 3. LFCSP Package Table 5. Pin Function Descriptions Pin No. 1 2 Mnemonic VOUT SENSE/ADJ 3 4 5 GND NC EN/UVLO 6 7 GND PG 8 VIN EPAD Description Regulated Output Voltage. Bypass VOUT to GND with a 1 F or greater capacitor. Sense (SENSE). Measures the actual output voltage at the load and feeds it to the error amplifier. Connect SENSE as close as possible to the load to minimize the effect of IR drop between the regulator output and the load. This function applies to fixed voltages only. Adjust Input (ADJ). An external resistor divider sets the output voltage. This function applies to adjustable voltages only. Ground. Do Not Connect to this Pin. Enable Input (EN). Drive EN high to turn on the regulator; drive EN low to turn off the regulator. For automatic startup, connect EN to VIN. Programmable Undervoltage Lockout (UVLO). When the programmable UVLO function is used, the upper and lower thresholds are determined by the programming resistors. Ground. Power Good. This open-drain output requires an external pull-up resistor to VIN or VOUT. If the device is in shutdown, current limit, thermal shutdown, or falls below 90% of the nominal output voltage, PG immediately transitions low. If the power-good function is not used, the pin may be left open or connected to ground. Regulator Input Supply. Bypass VIN to GND with a 1 F or greater capacitor. Exposed Pad. Exposed paddle on the bottom of the package. The EPAD enhances thermal performance and is electrically connected to GND inside the package. It is highly recommended that the EPAD be connected to the ground plane on the board. Rev. E | Page 6 of 28 Data Sheet ADP7102 TYPICAL PERFORMANCE CHARACTERISTICS VIN = 5 V, VOUT = 3.3 V, IOUT = 1 mA, CIN = COUT = 1 F, TA = 25C, unless otherwise noted. 3.35 LOAD = 100A LOAD = 1mA LOAD = 10mA LOAD = 100mA LOAD = 300mA 800 700 GROUND CURRENT (A) 3.33 VOUT (V) 900 LOAD = 100A LOAD = 1mA LOAD = 10mA LOAD = 100mA LOAD = 300mA 3.31 3.29 600 500 400 300 200 3.27 100 -5C 25C 85C 125C 0 TJ (C) -40C -5C 25C 85C 125C 09506-007 -40C 09506-004 3.25 TJ (C) Figure 8. Ground Current vs. Junction Temperature Figure 5. Output Voltage vs. Junction Temperature 700 3.35 600 GROUND CURRENT (A) VOUT (V) 3.33 3.31 3.29 500 400 300 200 3.27 10 100 1000 ILOAD (mA) 0 0.1 900 1000 20 LOAD = 100A LOAD = 1mA LOAD = 10mA LOAD = 100mA LOAD = 300mA 800 GROUND CURRENT (A) 700 3.31 3.29 600 500 400 300 200 3.27 100 3.25 4 6 8 10 12 14 16 VIN (V) 18 20 09506-006 VOUT (V) 100 Figure 9. Ground Current vs. Load Current LOAD = 100A LOAD = 1mA LOAD = 10mA LOAD = 100mA LOAD = 300mA 3.33 10 ILOAD (mA) Figure 6. Output Voltage vs. Load Current 3.35 1 09506-008 1 09506-005 3.25 0.1 09506-009 100 0 4 6 8 10 12 14 16 18 VIN (V) Figure 10. Ground Current vs. Input Voltage Figure 7. Output Voltage vs. Input Voltage Rev. E | Page 7 of 28 ADP7102 100 80 60 40 1000 -25 0 25 50 75 100 125 TEMPERATURE (C) 140 5.02 120 5.01 VOUT (V) 5.03 100 80 40 4.97 20 4.96 1000 ILOAD (mA) 3.50 3.60 3.70 4.99 4.98 100 3.40 5.00 60 10 3.30 LOAD = 100A LOAD = 1mA LOAD = 10mA LOAD = 100mA LOAD = 300mA 5.04 4.95 09506-011 -40C -5C 25C 85C 125C TJ (C) Figure 12. Dropout Voltage vs. Load Current Figure 15. Output Voltage vs. Junction Temperature, VOUT = 5 V 3.35 5.05 3.30 5.04 5.03 3.25 5.02 VOUT (V) 3.20 3.15 3.10 3.05 5.01 5.00 4.99 4.98 3.00 3.20 3.30 3.40 3.50 3.60 3.70 VIN (V) 4.96 09506-012 2.95 2.90 3.10 4.97 LOAD = 100A LOAD = 1mA LOAD = 10mA LOAD = 100mA LOAD = 300mA 4.95 0.1 1 10 100 ILOAD (mA) Figure 16. Output Voltage vs. Load Current, VOUT = 5 V Figure 13. Output Voltage vs. Input Voltage (in Dropout) Rev. E | Page 8 of 28 1000 09506-015 DROPOUT (mV) 5.05 VOUT = 3.3V TA = 25C 1 3.20 Figure 14. Ground Current vs. Input Voltage (in Dropout) 160 0 LOAD = 5mA LOAD = 10mA LOAD = 100mA LOAD = 200mA LOAD = 300mA VIN (V) Figure 11. Shutdown Current vs. Temperature at Various Input Voltages VOUT (V) 400 0 3.10 09506-010 0 -50 180 600 200 20 200 800 09506-013 120 1200 GROUND CURRENT (A) 140 SHUTDOWN CURRENT (A) 1400 3.3V 4.0V 6.0V 8.0V 12.0V 20.0V 09506-014 160 Data Sheet Data Sheet 900 LOAD = 100A LOAD = 1mA LOAD = 10mA LOAD = 100mA LOAD = 300mA 5.04 700 GROUND CURRENT (A) 5.03 5.01 5.00 4.99 4.98 600 500 400 300 4.97 200 4.96 100 8 10 12 14 16 18 20 VIN (V) 0 09506-016 6 6 180 16 18 20 140 700 600 120 500 400 100 80 60 300 40 200 -40C -5C 25C 85C 125C TJ (C) 09506-118 0 0 1 10 100 09506-017 20 100 1000 ILOAD (mA) Figure 18. Ground Current vs. Junction Temperature, VOUT = 5 V Figure 21. Dropout Voltage vs. Load Current, VOUT = 5 V 700 5.05 600 5.00 4.95 500 4.90 VOUT (V) 400 300 4.85 4.80 200 4.75 100 LOAD = 5mA LOAD = 10mA LOAD = 100mA LOAD = 200mA LOAD = 300mA 4.70 0 0.1 1 10 100 ILOAD (mA) 1000 09506-119 GROUND CURRENT (A) 14 VOUT = 5V TA = 25C 160 DROPOUT (mV) GROUND CURRENT (A) 800 12 Figure 20. Ground Current vs. Input Voltage, VOUT = 5 V LOAD = 100A LOAD = 1mA LOAD = 10mA LOAD = 100mA LOAD = 300mA 900 10 VIN (V) Figure 17. Output Voltage vs. Input Voltage, VOUT = 5 V 1000 8 4.65 4.8 4.9 5.0 5.1 VIN (V) 5.2 5.3 5.4 09506-018 VOUT (V) 5.02 4.95 LOAD = 100A LOAD = 1mA LOAD = 10mA LOAD = 100mA LOAD = 300mA 800 09506-120 5.05 ADP7102 Figure 22. Output Voltage vs. Input Voltage (in Dropout), VOUT = 5 V Figure 19. Ground Current vs. Load Current, VOUT = 5 V Rev. E | Page 9 of 28 ADP7102 Data Sheet 1.85 2500 1.83 VOUT (V) 1500 1000 1.81 1.79 500 -500 4.80 1.77 LOAD = 5mA LOAD = 10mA LOAD = 100mA LOAD = 200mA LOAD = 300mA 4.90 5.00 1.75 5.10 5.20 5.30 5.40 VIN (V) 900 800 700 GROUND CURRENT (A) VOUT (V) 6 8 10 12 14 16 18 20 Figure 26. Output Voltage vs. Input Voltage, VOUT = 1.8 V LOAD = 100A LOAD = 1mA LOAD = 10mA LOAD = 100mA LOAD = 300mA 1.83 4 VIN (V) Figure 23. Ground Current vs. Input Voltage (in Dropout), VOUT = 5 V 1.85 2 09506-022 0 09506-019 GROUND CURRENT (A) 2000 LOAD = 100A LOAD = 1mA LOAD = 10mA LOAD = 100mA LOAD = 300mA 1.81 1.79 LOAD = 100A LOAD = 1mA LOAD = 10mA LOAD = 100mA LOAD = 300mA 600 500 400 300 200 1.77 -40C -5C 25C 85C 125C TJ (C) 09506-020 0 1.75 -40C -5C 25C 85C 125C TJ (C) Figure 24. Output Voltage vs. Junction Temperature, VOUT = 1.8 V Figure 27. Ground Current vs. Junction Temperature, VOUT = 1.8 V 1.85 700 09506-023 100 600 GROUND CURRENT (A) 1.81 1.79 500 400 300 200 1.77 1.75 0.1 1 10 100 1000 ILOAD (mA) Figure 25. Output Voltage vs. Load Current, VOUT = 1.8 V 0 0.1 1 10 100 1000 ILOAD (mA) Figure 28. Ground Current vs. Load Current, VOUT = 1.8 V Rev. E | Page 10 of 28 09506-128 100 09506-021 VOUT (V) 1.83 Data Sheet 1200 5.08 LOAD = 100A LOAD = 1mA LOAD = 10mA LOAD = 100mA LOAD = 300mA 1000 GROUND CURRENT (A) ADP7102 LOAD = 100A LOAD = 1mA LOAD = 10mA LOAD = 100mA LOAD = 300mA 5.07 5.06 5.05 VOUT (V) 800 600 400 5.04 5.03 5.02 5.01 5.00 200 2 4 6 8 10 12 14 16 18 20 VIN (V) 09506-129 4.98 0 5.06 LOAD = 100A LOAD = 1mA LOAD = 10mA LOAD = 100mA LOAD = 300mA 2.0 5.05 VOUT (V) 10 12 14 16 18 20 Figure 32. Output Voltage vs. Input Voltage, VOUT = 5 V, Adjustable IOUT SHUTDOWN CURRENT (A) 5.07 8 VIN (V) Figure 29. Ground Current vs. Input Voltage, VOUT = 1.8 V 5.08 6 09506-026 4.99 5.04 5.03 5.02 5.01 5.00 1.5 3.3V 4V 5V 6V 8V 10V 12V 15V 18V 20V 1.0 0.5 -40C -5C 25C 85C 125C TJ (C) Figure 30. Output Voltage vs. Junction Temperature, VOUT = 5 V, Adjustable 0 5.07 -10 5.06 -20 5.05 -30 5.04 -40 5.02 5.01 20 40 60 80 100 120 140 LOAD = 300mA LOAD = 100mA LOAD = 10mA LOAD = 1mA -50 -60 -70 5.00 -80 4.99 1 10 100 1000 ILOAD (mA) -100 10 100 1k 10k 100k 1M 10M FREQUENCY (Hz) Figure 34. Power Supply Rejection Ratio vs. Frequency, VOUT = 1.8 V, VIN = 3.3 V Figure 31. Output Voltage vs. Load Current, VOUT = 5 V, Adjustable Rev. E | Page 11 of 28 09506-027 -90 09506-025 4.98 0.1 0 Figure 33. Reverse Input Current vs. Temperature, VIN = 0 V, Different Voltages on VOUT 5.08 5.03 -20 TEMPERATURE (C) PSRR (dB) VOUT (V) 0 -40 09506-024 4.98 09506-053 4.99 ADP7102 -20 -30 -40 -40 -50 -60 -80 -80 -90 -90 10 100 1k 10k 100k 1M 10M Figure 35. Power Supply Rejection Ratio vs. Frequency, VOUT = 3.3 V, VIN = 4.8 V 0 -10 -20 -100 10 0 LOAD = 300mA LOAD = 100mA LOAD = 10mA LOAD = 1mA -10 -20 -40 -40 PSRR (dB) -30 -50 -60 -70 -80 -90 -90 -100 -100 10 10k 100k 1M 10M FREQUENCY (Hz) Figure 36. Power Supply Rejection Ratio vs. Frequency, VOUT = 3.3 V, VIN = 4.3 V 0 -10 -20 0 LOAD = 300mA LOAD = 100mA LOAD = 10mA LOAD = 1mA -10 -20 -40 PSRR (dB) -40 -50 -60 -80 -80 -90 -90 100k 1M 10M FREQUENCY (Hz) Figure 37. Power Supply Rejection Ratio vs. Frequency, VOUT = 3.3 V, VIN = 3.8 V -100 10 09506-030 10k 100 1k 10k 100k 1M 10M LOAD = 1mA LOAD = 10mA LOAD = 100mA LOAD = 300mA -60 -70 1k LOAD = 1mA LOAD = 10mA LOAD = 100mA LOAD = 300mA -50 -70 100 10M Figure 39. Power Supply Rejection Ratio vs. Frequency, VOUT = 5 V, VIN = 6 V -30 10 1M FREQUENCY (Hz) -30 -100 100k -60 -80 1k 10k -50 -70 100 1k Figure 38. Power Supply Rejection Ratio vs. Frequency, VOUT = 5 V, VIN = 6.5 V -30 10 100 FREQUENCY (Hz) 09506-029 PSRR (dB) -60 -70 FREQUENCY (Hz) PSRR (dB) -50 -70 -100 LOAD = 1mA LOAD = 10mA LOAD = 100mA LOAD = 300mA 09506-031 PSRR (dB) -30 09506-028 PSRR (dB) -20 -10 09506-032 -10 0 LOAD = 300mA LOAD = 100mA LOAD = 10mA LOAD = 1mA 100 1k 10k 100k FREQUENCY (Hz) 1M 10M 09506-033 0 Data Sheet Figure 40. Power Supply Rejection Ratio vs. Frequency, VOUT = 5 V, VIN = 5.5 V Rev. E | Page 12 of 28 Data Sheet -20 -30 -40 -40 -50 -60 -70 -80 -80 -90 -90 -100 10 -100 10 100 1k 10k 100k 1M 10M Figure 41. Power Supply Rejection Ratio vs. Frequency, VOUT = 5 V, VIN = 5.3 V 0 -10 -20 0 -20 -30 -40 -40 PSRR (dB) -30 -80 -80 -90 -90 -100 10 -100 10k 100k 1M 10M FREQUENCY (Hz) Figure 42. Power Supply Rejection Ratio vs. Frequency, VOUT = 5 V, VIN = 5.2 V 0 -10 -20 0 -40 PSRR (dB) -30 -70 -80 -90 -90 FREQUENCY (Hz) 1M 10M -100 09506-036 100k Figure 43. Power Supply Rejection Ratio vs. Frequency, VOUT = 5 V, VIN = 6 V, Adjustable 1.00 1.25 1.50 -60 -80 10k 0.75 -50 -70 1k 0.50 LOAD = 1mA LOAD = 10mA LOAD = 100mA LOAD = 300mA -20 -40 100 0.25 Figure 45. Power Supply Rejection Ratio vs. Headroom Voltage, 100 Hz, VOUT = 5 V -30 -100 10 0 -10 -60 10M HEADROOM VOLTAGE (V) LOAD = 1mA LOAD = 10mA LOAD = 100mA LOAD = 300mA -50 1M -60 -70 1k 100k -50 -70 100 10k LOAD = 1mA LOAD = 10mA LOAD = 100mA LOAD = 300mA -10 -60 1k Figure 44. Power Supply Rejection Ratio vs. Frequency, VOUT = 5 V, VIN = 6 V, Adjustable with Noise Reduction Circuit LOAD = 1mA LOAD = 10mA LOAD = 100mA LOAD = 300mA -50 100 FREQUENCY (Hz) 09506-035 PSRR (dB) -60 -70 FREQUENCY (Hz) PSRR (dB) -50 09506-037 PSRR (dB) -30 09506-034 PSRR (dB) -20 LOAD = 1mA LOAD = 10mA LOAD = 100mA LOAD = 300mA -10 09506-038 -10 0 LOAD = 1mA LOAD = 10mA LOAD = 100mA LOAD = 300mA 0 0.25 0.50 0.75 1.00 HEADROOM VOLTAGE 1.25 1.50 09506-039 0 ADP7102 Figure 46. Power Supply Rejection Ratio vs. Headroom Voltage, 1 kHz, VOUT = 5 V Rev. E | Page 13 of 28 ADP7102 Data Sheet 0 10 LOAD = 1mA LOAD = 10mA LOAD = 100mA LOAD = 300mA -10 -20 1 -40 V/Hz PSRR (dB) -30 3.3V 5V 5V ADJ 5V ADJ NR -50 -60 0.1 -70 -80 0.25 0.50 0.75 1.00 1.25 1.50 HEADROOM VOLTAGE (V) 0.01 10 09506-040 0 -20 10k 100k Figure 50. Output Noise Spectral Density, ILOAD = 10 mA, COUT = 1 F LOAD = 1mA LOAD = 10mA LOAD = 100mA LOAD = 300mA -10 1k FREQUENCY (Hz) Figure 47. Power Supply Rejection Ratio vs. Headroom Voltage, 10 kHz, VOUT = 5 V 0 100 09506-043 -90 -100 LOAD CURRENT PSRR (dB) -30 1 -40 -50 -60 2 OUTPUT VOLTAGE -70 -80 0 0.25 0.50 0.75 1.00 1.25 1.50 HEADROOM VOLTAGE (V) Figure 48. Power Supply Rejection Ratio vs. Headroom Voltage, 100 kHz, VOUT = 5 V CH1 200mA BW CH2 50mV B W M 20s T 10.4% A CH1 76mA 09506-044 -100 09506-041 -90 Figure 51. Load Transient Response, CIN, COUT = 1 F, ILOAD = 1 mA to 300 mA, VOUT = 1.8 V, VIN = 5 V 30 LOAD CURRENT 25 15 2 OUTPUT VOLTAGE 3.3V 1.8V 5V 5VADJ 5VADJ NR 5 0 0.00001 0.0001 0.001 0.01 0.1 1 LOAD CURRENT (A) Figure 49. Output Noise vs. Load Current and Output Voltage, COUT = 1 F CH1 200mA BW CH2 50mV B W M 20s T 10.2% A CH1 168mA 09506-045 10 09506-042 NOISE (V rms) 1 20 Figure 52. Load Transient Response, CIN, COUT = 1 F, ILOAD = 1 mA to 300 mA, VOUT = 3.3 V, VIN = 5 V Rev. E | Page 14 of 28 Data Sheet ADP7102 INPUT VOLTAGE LOAD CURRENT 1 OUTPUT VOLTAGE 2 OUTPUT VOLTAGE 2 B W M 20s T 10.2% A CH1 216mA CH1 1V B W B W M 4s T 9.8% A CH4 1.56V Figure 55. Line Transient Response, CIN, COUT = 1 F, ILOAD = 300 mA, VOUT = 3.3 V Figure 53. Load Transient Response, CIN, COUT = 1 F, ILOAD = 1 mA to 300 mA, VOUT = 5 V, VIN = 7 V INPUT VOLTAGE INPUT VOLTAGE OUTPUT VOLTAGE 2 CH2 10mV 09506-048 CH1 200mA BW CH2 50mV 09506-046 1 OUTPUT VOLTAGE 2 B W CH2 10mV B W M 4s T 9.8% A CH4 1.56V 1 09506-047 CH1 1V Figure 54. Line Transient Response, CIN, COUT = 1 F, ILOAD = 300 mA, VOUT = 1.8 V CH1 1V B W CH2 10mV B W M 4s T 9.8% A CH4 1.56V 09506-049 1 Figure 56. Line Transient Response, CIN, COUT = 1 F, ILOAD = 300 mA, VOUT = 5 V Rev. E | Page 15 of 28 ADP7102 Data Sheet INPUT VOLTAGE INPUT VOLTAGE OUTPUT VOLTAGE 2 OUTPUT VOLTAGE 2 B W CH2 10mV B W M 4s T 9.8% A CH4 1.56V 1 09506-050 CH1 1V CH1 1V Figure 57. Line Transient Response, CIN, COUT = 1 F, ILOAD = 1 mA, VOUT = 1.8 V OUTPUT VOLTAGE B W CH2 10mV B W M 4s T 9.8% A CH4 1.56V 09506-051 1 CH1 1V CH2 10mV B W M 4s T 9.8% A CH4 1.56V Figure 59. Line Transient Response, CIN, COUT = 1 F, ILOAD = 1 mA, VOUT = 5 V INPUT VOLTAGE 2 B W 09506-052 1 Figure 58. Line Transient Response, CIN, COUT = 1 F, ILOAD = 1 mA, VOUT = 3.3 V Rev. E | Page 16 of 28 Data Sheet ADP7102 THEORY OF OPERATION The ADP7102 is a low quiescent current, low dropout linear regulator that operates from 3.3 V to 20 V and provides up to 300 mA of output current. Drawing a low 750 A of quiescent current (typical) at full load makes the ADP7102 ideal for battery operated portable equipment. Typical shutdown current consumption is 40 A at room temperature. Optimized for use with small 1 F ceramic capacitors, the ADP7102 provides excellent transient performance. The ADP7102 is available in seven fixed output voltage options, ranging from 1.8 V to 9 V, and in an adjustable version with an output voltage that can be set to any voltage between 1.22 V and 19 V by an external voltage divider. The output voltage can be set according to the following equation: VOUT = 1.22 V(1 + R1/R2) VOUT VREG GND 10A EN/ UVLO SHORT-CIRCUIT, THERMAL PROTECT PGOOD VIN = 8V PG SHUTDOWN SENSE OFF CIN + 1F R3 ON 100k R4 100k Figure 60. Fixed Output Voltage Internal Block Diagram VIN EN/ UVLO 10A SHORT-CIRCUIT, THERMAL PROTECT PGOOD PG SHUTDOWN SENSE 1.22V REFERENCE EN/ UVLO R2 13k PG + COUT 1F VOUT = 5V RPG 100k PG The value of R2 must be less than 200 k to minimize errors in the output voltage caused by the ADJ pin input current. For example, when R1 and R2 each equal 200 k, the output voltage is 2.44 V. The output voltage error introduced by the ADJ pin input current is 2 mV or 0.08%, assuming a typical ADJ pin input current of 10 nA at 25C. VOUT VREG R1 40.2k Figure 62. Typical Adjustable Output Voltage Application Schematic 09506-056 GND VOUT ADJ GND 09506-055 REFERENCE VIN 09506-057 VIN If the feedback voltage is higher than the reference voltage, the gate of the PMOS device is pulled higher, allowing less current to pass and decreasing the output voltage. Figure 61. Adjustable Output Voltage Internal Block Diagram Internally, the ADP7102 consists of a reference, an error amplifier, a feedback voltage divider, and a PMOS pass transistor. Output current is delivered via the PMOS pass device, which is controlled by the error amplifier. The error amplifier compares the reference voltage with the feedback voltage from the output and amplifies the difference. If the feedback voltage is lower than the reference voltage, the gate of the PMOS device is pulled lower, allowing more current to pass and increasing the output voltage. The ADP7102 uses the EN/UVLO pin to enable and disable the VOUT pin under normal operating conditions. When EN/UVLO is high, VOUT turns on; when EN is low, VOUT turns off. For automatic startup, EN/UVLO can be tied to VIN. The ADP7102 incorporates reverse current protections circuitry that prevents current flow backwards through the pass element when the output voltage is greater than the input voltage. A comparator senses the difference between the input and output voltages. When the difference between the input voltage and output voltage exceeds 55 mV, the body of the PFET is switched to VOUT and turned off or opened. In other words, the gate is connected to VOUT. Rev. E | Page 17 of 28 ADP7102 Data Sheet APPLICATIONS INFORMATION Output Capacitor The ADP7102 is designed for operation with small, space-saving ceramic capacitors but functions with most commonly used capacitors as long as care is taken with regard to the effective series resistance (ESR) value. The ESR of the output capacitor affects the stability of the LDO control loop. A minimum of 1 F capacitance with an ESR of 0.2 or less is recommended to ensure the stability of the ADP7102. Transient response to changes in load current is also affected by output capacitance. Using a larger value of output capacitance improves the transient response of the ADP7102 to large changes in load current. Figure 63 shows the transient responses for an output capacitance value of 1 F. LOAD CURRENT Figure 64 depicts the capacitance vs. voltage bias characteristic of an 0402, 1 F, 10 V, X5R capacitor. The voltage stability of a capacitor is strongly influenced by the capacitor size and voltage rating. In general, a capacitor in a larger package or higher voltage rating exhibits better stability. The temperature variation of the X5R dielectric is ~ 15% over the -40C to +85C temperature range and is not a function of package or voltage rating. 1.2 1.0 CAPACITANCE (F) CAPACITOR SELECTION 0.8 0.6 0.4 0.2 0 0 2 4 6 8 VOLTAGE (V) 2 OUTPUT VOLTAGE 10 09506-059 1 Figure 64. Capacitance vs. Voltage Characteristic CH1 200mA BW CH2 50mV B W M 20s T 10.4% A CH1 76mA 09506-058 Use Equation 1 to determine the worst case capacitance accounting for capacitor variation over temperature, component tolerance, and voltage. CEFF = CBIAS x (1 - TEMPCO) x (1 - TOL) Figure 63. Output Transient Response, VOUT = 1.8 V, COUT = 1 F Input Bypass Capacitor Connecting a 1 F capacitor from VIN to GND reduces the circuit sensitivity to PCB layout, especially when long input traces or high source impedance are encountered. If greater than 1 F of output capacitance is required, the input capacitor should be increased to match it. Input and Output Capacitor Properties (1) where: CBIAS is the effective capacitance at the operating voltage. TEMPCO is the worst case capacitor temperature coefficient. TOL is the worst case component tolerance. In this example, the worst case temperature coefficient (TEMPCO) over -40C to +85C is assumed to be 15% for an X5R dielectric. The tolerance of the capacitor (TOL) is assumed to be 10%, and CBIAS is 0.94 F at 1.8 V, as shown in Figure 64. Substituting these values in Equation 1 yields Any good quality ceramic capacitors can be used with the ADP7102, as long as they meet the minimum capacitance and maximum ESR requirements. Ceramic capacitors are manufactured with a variety of dielectrics, each with different behavior over temperature and applied voltage. Capacitors must have a dielectric adequate to ensure the minimum capacitance over the necessary temperature range and dc bias conditions. X5R or X7R dielectrics with a voltage rating of 6.3 V to 50 V are recommended. Y5V and Z5U dielectrics are not recommended, due to their poor temperature and dc bias characteristics. CEFF = 0.94 F x (1 - 0.15) x (1 - 0.1) = 0.719 F Therefore, the capacitor chosen in this example meets the minimum capacitance requirement of the LDO over temperature and tolerance at the chosen output voltage. To guarantee the performance of the ADP7102, it is imperative that the effects of dc bias, temperature, and tolerances on the behavior of the capacitors be evaluated for each application. Rev. E | Page 18 of 28 Data Sheet ADP7102 PROGRAMABLE UNDERVOLTAGE LOCKOUT (UVLO) VIN = 8V OFF R1 ON 100k R2 100k VIN VOUT SENSE EN/ UVLO VOUT = 5V + COUT 1F RPG 100k PG PG GND Figure 66. Typical EN Pin Voltage Divider 2.0 Figure 65 shows the typical hysteresis of the EN/UVLO pin. This prevents on/off oscillations that can occur due to noise on the EN pin as it passes through the threshold points. 1.8 1.6 1.4 The ADP7102 uses an internal soft start to limit the inrush current when the output is enabled. The start-up time for the 3.3 V option is approximately 580 s from the time the EN active threshold is crossed to when the output reaches 90% of its final value. As shown in Figure 67, the start-up time is dependent on the output voltage setting. 1.2 VOUT, EN RISE VOUT, EN FALL 1.0 0.8 0.6 0.4 6 1.25 1.50 1.75 2.00 2.25 2.50 2.75 3.00 09506-060 0.2 0 1.00 CIN + 1F 09506-061 The ADP7102 uses the EN/UVLO pin to enable and disable the VOUT pin under normal operating conditions. As shown in Figure 65, when a rising voltage on EN crosses the upper threshold, VOUT turns on. When a falling voltage on EN/UVLO crosses the lower threshold, VOUT turns off. The hysteresis of the EN/UVLO threshold is determined by the Thevenin equivalent resistance in series with the EN/ UVLO pin. 5V 5 Figure 65. Typical VOUT Response to EN Pin Operation 4 R1 = VHYS/10 A 3.3V 3 ENABLE 2 1 0 0 500 1000 1500 TIME (s) R2 = 1.22 V x R1/(VIN - 1.22 V) Figure 67. Typical Start-Up Behavior where: VIN is the desired turn on voltage. VHYS is the desired EN/UVLO hysteresis level. Hysteresis can also be achieved by connecting a resistor in series with EN/UVLO pin. For the example shown in Figure 66, the enable threshold is 2.44 V with a hysteresis of 1 V. Rev. E | Page 19 of 28 2000 09506-062 VOUT (V) The upper and lower thresholds are user programmable and can be set using two resistors. When the EN/UVLO pin voltage is below 1.22 V, the LDO is disabled. When the EN/UVLO pin voltage transitions above 1.22 V, the LDO is enabled and 10 A hysteresis current is sourced out of the pin raising the voltage, thus providing threshold hysteresis. Typically, two external resistors program the minimum operational voltage for the LDO. The resistance values, R1 and R2 can be determined from: ADP7102 Data Sheet POWER-GOOD FEATURE NOISE REDUCTION OF THE ADJUSTABLE ADP7102 The ADP7102 provides a power-good pin (PG) to indicate the status of the output. This open-drain output requires an external pull-up resistor to VOUT. If the device is in shutdown mode, current-limit mode, or thermal shutdown, or if it falls below 90% of the nominal output voltage, the power-good pin (PG) immediately transitions low. During soft start, the rising threshold of the power-good signal is 93.5% of the nominal output voltage. The ultralow output noise of the fixed output ADP7102 is achieved by keeping the LDO error amplifier in unity gain and setting the reference voltage equal to the output voltage. This architecture does not work for an adjustable output voltage LDO. The adjustable output ADP7102 uses the more conventional architecture where the reference voltage is fixed and the error amplifier gain is a function of the output voltage. The disadvantage of the conventional LDO architecture is that the output voltage noise is proportional to the output voltage. Power-good accuracy is 93.5% of the nominal regulator output voltage when this voltage is rising, with a 90% trip point when this voltage is falling. Regulator input voltage brownouts or glitches trigger power no good signals if VOUT falls below 90%. A normal power-down causes the power-good signal to go low when VOUT drops below 90%. Figure 68 and Figure 69 show the typical power-good rising and falling threshold over temperature. 6 5 PG -40C PG -5C PG +25C PG +85C PG +125C PG (V) 4 The adjustable LDO circuit may be modified slightly to reduce the output voltage noise to levels close to that of the fixed output ADP7102. The circuit shown in Figure 70 adds two additional components to the output voltage setting resistor divider. CNR and RNR are added in parallel with RFB1 to reduce the ac gain of the error amplifier. RNR is chosen to be equal to RFB2; this limits the ac gain of the error amplifier to approximately 6 dB. The actual gain is the parallel combination of RNR and RFB1, divided by RFB2. This ensures that the error amplifier always operates at greater than unity gain. CNR is chosen by setting the reactance of CNR equal to RFB1 - RNR at a frequency between 50 Hz and 100 Hz. This sets the frequency where the ac gain of the error amplifier is 3 dB down from its dc gain. VIN = 8V CIN + 1F VIN ADJ 3 ON OFF 2 100k VOUT RFB2 13k EN/ UVLO 100k GND 0 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 5.0 VOUT (V) 09506-063 1 Figure 68. Typical Power-Good Threshold vs. Temperature, VOUT Rising 6 5 PG -40C PG -5C PG +25C PG +85C PG +125C PG (V) + CNR 100nF RNR 13k VOUT = 5V + COUT 1F 100k PG PG Figure 70. Noise Reduction Modification to Adjustable LDO The noise of the adjustable LDO can be found by using the following formula, assuming the noise of a fixed output LDO is approximately 15 V. 1 / 13 k 15 V 1 1 / 13 k 1 / 40.2 k 4 Based on the component values shown in Figure 70, the ADP7102 has the following characteristics: 3 2 4.3 4.4 4.5 4.6 VOUT (V) 4.7 4.8 4.9 5.0 09506-064 1 0 4.2 RFB1 40.2k Figure 69. Typical Power-Good Threshold vs. Temperature, VOUT Falling Rev. E | Page 20 of 28 DC gain of 4.09 (12.2 dB) 3 dB roll off frequency of 59 Hz High frequency ac gain of 1.76 (4.89 dB) Noise reduction factor of 1.33 (2.59 dB) RMS noise of the adjustable LDO without noise reduction of 27.8 V rms RMS noise of the adjustable LDO with noise reduction (assuming 15 V rms for fixed voltage option) of 19.95 V rms 09506-065 The open-drain output is held low when the ADP7102 has sufficient input voltage to turn on the internal PG transistor. The PG transistor is terminated via a pull-up resistor to VOUT or VIN. Data Sheet ADP7102 CURRENT LIMIT AND THERMAL OVERLOAD PROTECTION The ADP7102 is protected against damage due to excessive power dissipation by current and thermal overload protection circuits. The ADP7102 is designed to current limit when the output load reaches 400 mA (typical). When the output load exceeds 400 mA, the output voltage is reduced to maintain a constant current limit. Thermal overload protection is included, which limits the junction temperature to a maximum of 150C (typical). Under extreme conditions (that is, high ambient temperature and/or high power dissipation) when the junction temperature starts to rise above 150C, the output is turned off, reducing the output current to zero. When the junction temperature drops below 135C, the output is turned on again, and output current is restored to its operating value. Consider the case where a hard short from VOUT to ground occurs. At first, the ADP7102 current limits, so that only 400 mA is conducted into the short. If self heating of the junction is great enough to cause its temperature to rise above 150C, thermal shutdown activates, turning off the output and reducing the output current to zero. As the junction temperature cools and drops below 135C, the output turns on and conducts 400 mA into the short, again causing the junction temperature to rise above 150C. This thermal oscillation between 135C and 150C causes a current oscillation between 400 mA and 0 mA that continues as long as the short remains at the output. Current and thermal limit protections are intended to protect the device against accidental overload conditions. For reliable operation, device power dissipation must be externally limited so the junction temperature does not exceed 125C. THERMAL CONSIDERATIONS In applications with low input to output voltage differential, the ADP7102 does not dissipate much heat. However, in applications with high ambient temperature and/or high input voltage, the heat dissipated in the package may become large enough that it causes the junction temperature of the die to exceed the maximum junction temperature of 125C. When the junction temperature exceeds 150C, the converter enters thermal shutdown. It recovers only after the junction temperature has decreased below 135C to prevent any permanent damage. Therefore, thermal analysis for the chosen application is very important to guarantee reliable performance over all conditions. The junction temperature of the die is the sum of the ambient temperature of the environment and the temperature rise of the package due to the power dissipation, as shown in Equation 2. To guarantee reliable operation, the junction temperature of the ADP7102 must not exceed 125C. To ensure that the junction temperature stays below this maximum value, the user must be aware of the parameters that contribute to junction temperature changes. These parameters include ambient temperature, power dissipation in the power device, and thermal resistances between the junction and ambient air (JA). The JA number is dependent on the package assembly compounds that are used and the amount of copper used to solder the package GND pins to the PCB. Table 6 shows typical JA values of the 8-lead SOIC and 8-lead LFCSP packages for various PCB copper sizes. Table 7 shows the typical JB values of the 8-lead SOIC and 8-lead LFCSP. Table 6. Typical JA Values Copper Size (mm2) 251 100 500 1000 6400 1 LFCSP 165.1 125.8 68.1 56.4 42.1 JA (C/W) SOIC 167.8 111 65.9 56.1 45.8 Device soldered to minimum size pin traces. Table 7. Typical JB Values Model LFCSP SOIC JB (C/W) 15.1 31.3 The junction temperature of the ADP7102 is calculated from the following equation: TJ = TA + (PD x JA) (2) where: TA is the ambient temperature. PD is the power dissipation in the die, given by PD = [(VIN - VOUT) x ILOAD] + (VIN x IGND) (3) where: ILOAD is the load current. IGND is the ground current. VIN and VOUT are input and output voltages, respectively. Power dissipation due to ground current is quite small and can be ignored. Therefore, the junction temperature equation simplifies to the following: TJ = TA + {[(VIN - VOUT) x ILOAD] x JA} (4) As shown in Equation 4, for a given ambient temperature, input to output voltage differential, and continuous load current, there exists a minimum copper size requirement for the PCB to ensure that the junction temperature does not rise above 125C. Figure 71 to Figure 78 show junction temperature calculations for different ambient temperatures, power dissipation, and areas of PCB copper. Rev. E | Page 21 of 28 Data Sheet 145 135 135 125 125 115 105 95 85 75 65 55 6400mm 2 500mm 2 25mm 2 TJ MAX 45 35 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 TOTAL POWER DISSIPATION (W) 85 75 65 55 6400mm 2 500mm 2 25mm 2 TJ MAX 45 35 25 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 Figure 74. SOIC, TA = 25C 140 130 130 JUNCTION TEMPERATURE (C) 140 120 110 100 90 80 70 6400mm 2 500mm 2 25mm 2 TJ MAX 60 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 TOTAL POWER DISSIPATION (W) 120 100 110 90 80 70 6400mm 2 500mm 2 25mm 2 TJ MAX 60 50 09506-067 JUNCTION TEMPERATURE (C) Figure 71. LFCSP, TA = 25C 50 0 0.2 0.4 135 JUNCTION TEMPERATURE (C) 135 125 115 105 95 85 6400mm 2 500mm 2 25mm 2 TJ MAX 75 0.2 0.3 0.4 0.5 0.6 0.7 TOTAL POWER DISSIPATION (W) 1.0 1.2 1.4 1.6 1.8 0.8 0.9 1.0 125 115 105 95 85 6400mm 2 500mm 2 25mm 2 TJ MAX 75 09506-068 JUNCTION TEMPERATURE (C) 145 0.1 0.8 Figure 75. SOIC, TA = 50C 145 0 0.6 TOTAL POWER DISSIPATION (W) Figure 72. LFCSP, TA = 50C 65 1.8 2.0 2.2 2.4 TOTAL POWER DISSIPATION (W) 09506-070 0 95 65 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 TOTAL POWER DISSIPATION (W) Figure 76. SOIC, TA = 85C Figure 73. LFCSP, TA = 85C Rev. E | Page 22 of 28 0.8 0.9 1.0 09506-071 25 115 105 09506-069 JUNCTION TEMPERATURE (C) 145 09506-066 JUNCTION TEMPERATURE (C) ADP7102 Data Sheet ADP7102 (5) The typical value of JB is 15.1C/W for the 8-lead LFCSP package and 31.3C/W for the 8-lead SOIC package. 140 120 100 80 60 40 TB = 25C TB = 50C TB = 65C TB = 85C TJ MAX 20 0 100 0.5 1.0 1.5 2.0 Figure 78. SOIC 80 60 40 TB = 25C TB = 50C TB = 65C TB = 85C TJ MAX 20 0 0 2.5 TOTAL POWER DISSIPATION (W) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 TOTAL POWER DISSIPATION (W) 09506-072 JUNCTION TEMPERATURE (TJ) 120 Figure 77. LFCSP Rev. E | Page 23 of 28 3.0 3.5 09506-073 TJ = TB + (PD x JB) 140 JUNCTION TEMPERATURE (TJ) In the case where the board temperature is known, use the thermal characterization parameter, JB, to estimate the junction temperature rise (see Figure 77 and Figure 78). Maximum junction temperature (TJ) is calculated from the board temperature (TB) and power dissipation (PD) using the following formula: ADP7102 Data Sheet PRINTED CIRCUIT BOARD LAYOUT CONSIDERATIONS Heat dissipation from the package can be improved by increasing the amount of copper attached to the pins of the ADP7102. However, as listed in Table 6, a point of diminishing returns is eventually reached, beyond which an increase in the copper size does not yield significant heat dissipation benefits. 09506-075 Place the input capacitor as close as possible to the VIN and GND pins. Place the output capacitor as close as possible to the VOUT and GND pins. Use of 0805 or 0603 size capacitors and resistors achieves the smallest possible footprint solution on boards where area is limited. 09506-074 Figure 80. Example SOIC PCB Layout Figure 79. Example LFCSP PCB Layout Rev. E | Page 24 of 28 Data Sheet ADP7102 OUTLINE DIMENSIONS 2.48 2.38 2.23 3.10 3.00 SQ 2.90 8 5 EXPOSED PAD INDEX AREA 4 TOP VIEW SEATING PLANE 0.30 0.25 0.18 0.20 MIN PIN 1 INDICATOR (R 0.2) 1 BOTTOM VIEW 0.80 MAX 0.55 NOM 0.80 0.75 0.70 1.74 1.64 1.49 0.50 BSC 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 02-05-2013-B 0.50 0.40 0.30 COMPLIANT TO JEDEC STANDARDS MO-229-WEED-4 Figure 81. 8-Lead Lead Frame Chip Scale Package [LFCSP_WD] 3 mm x 3 mm Body, Very Very Thin, Dual Lead (CP-8-5) Dimensions shown in millimeters 5.00 4.90 4.80 3.098 0.356 5 1 4 6.20 6.00 5.80 4.00 3.90 3.80 2.41 0.457 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. BOTTOM VIEW 1.27 BSC 3.81 REF TOP VIEW 1.65 1.25 1.75 1.35 SEATING PLANE 0.51 0.31 0.50 0.25 0.10 MAX 0.05 NOM COPLANARITY 0.10 8 0 45 0.25 0.17 1.04 REF 1.27 0.40 COMPLIANT TO JEDEC STANDARDS MS-012-A A Figure 82. 8-Lead Standard Small Outline Package, with Exposed Pad [SOIC_N_EP] Narrow Body (RD-8-2) Dimensions shown in millimeters Rev. E | Page 25 of 28 06-03-2011-B 8 ADP7102 Data Sheet ORDERING GUIDE Model1 ADP7102ACPZ-R7 ADP7102ACPZ-1.5-R7 ADP7102ACPZ-1.8-R7 ADP7102ACPZ-2.5-R7 ADP7102ACPZ-3.0-R7 ADP7102ACPZ-3.3-R7 ADP7102ACPZ-5.0-R7 ADP7102ACPZ-9.0-R7 ADP7102ARDZ-R7 ADP7102ARDZ-1.5-R7 ADP7102ARDZ-1.8-R7 ADP7102ARDZ-2.5-R7 ADP7102ARDZ-3.0-R7 ADP7102ARDZ-3.3-R7 ADP7102ARDZ-5.0-R7 ADP7102ARDZ-9.0-R7 ADP7102CP-EVALZ ADP7102RD-EVALZ ADP7102CPZ-REDYKIT ADP7102RDZ-REDYKIT Temperature Range -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C Output Voltage (V)2, 3 Adjustable 1.5 1.8 2.5 3.0 3.3 5 9 Adjustable 1.5 1.8 2.5 3.0 3.3 5 9 3.3 3.3 Package Description 8-Lead LFCSP_WD 8-Lead LFCSP_WD 8-Lead LFCSP_WD 8-Lead LFCSP_WD 8-Lead LFCSP_WD 8-Lead LFCSP_WD 8-Lead LFCSP_WD 8-Lead LFCSP_WD 8-Lead SOIC_N_EP 8-Lead SOIC_N_EP 8-Lead SOIC_N_EP 8-Lead SOIC_N_EP 8-Lead SOIC_N_EP 8-Lead SOIC_N_EP 8-Lead SOIC_N_EP 8-Lead SOIC_N_EP LFCSP Evaluation Board SOIC Evaluation Board LFCSP REDYKIT SOIC REDYKIT 1 Z = RoHS Compliant Part. For additional voltage options, contact a local Analog Devices, Inc., sales or distribution representative. 3 The ADP7102CP-EVALZ and ADP7102RD-EVALZ evaluation boards are preconfigured with a 3.3 V ADP7102 2 Rev. E | Page 26 of 28 Package Option CP-8-5 CP-8-5 CP-8-5 CP-8-5 CP-8-5 CP-8-5 CP-8-5 CP-8-5 RD-8-2 RD-8-2 RD-8-2 RD-8-2 RD-8-2 RD-8-2 RD-8-2 RD-8-2 Branding LHO LJV LJW LJZ LKO LK1 LK2 LLC Data Sheet ADP7102 NOTES Rev. E | Page 27 of 28 ADP7102 Data Sheet NOTES (c)2011-2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09506-0-9/15(E) Rev. E | Page 28 of 28