SMSC LAN8710A/LAN8710Ai Revision 1.4 (08-23-12)
DATASHEET
Datasheet
PRODUCT FEATURES
LAN8710A/LAN8710Ai
Small Footprint MII/RMII 10/100 Ethernet
Transceiver with HP Auto-MDIX and
flexPWR® Technology
Highlights
Single-Chip Ethernet Physical Layer Transceiver
(PHY)
Comprehensive flexPWR® Technology
— Flexible Power Management Architecture
— LVCMOS Variable I/O voltage range: +1.6V to +3.6V
— Integrated 1.2V regulator with disable feature
HP Auto-MDIX support
Small footprint 32-pin QFN lead-free RoHS complia nt
package (5 x 5 x 0.9mm height)
Target Applications
Set-Top Boxes
Networked Printers and Servers
Test Instrumentation
LAN on Motherboard
Embedded Telecom Applications
Video Record/Playback Systems
Cable Modems/Routers
DSL Modems/Routers
Digital Video Recorders
IP and Video Phones
Wireless Access Points
Digital Televisions
Digital Media Adaptors/Servers
Gaming Consoles
POE Applications (Refer to SMSC Application Note 17.18)
Key Benefits
High-Performance 10/100 Ethernet Transceiver
— Compliant with IEEE802.3/802.3u (Fast Ethernet)
— Compliant with ISO 802-3/IEEE 802.3 (10BASE-T)
— Loop-back modes
— Auto-negotiation
— Automatic polarity detection and correction
— Link status change wake-up detection
— Vendor specific register functions
— Supports both MII and the reduced pin count RMII
interfaces
Power and I/Os
— Various low power modes
— Integrated power-on reset circuit
— Two status LED outputs
— Latch-Up Performance Exceeds 150mA per EIA/JESD
78, Class II
— May be used with a single 3.3V supply
Additional Features
— Ability to use a low cost 25Mhz crystal for reduced BOM
Packaging
— 32-pin QFN (5x5 mm) Lead-Free RoHS Compliant
package with MII and RMII
Environmental
— Extended commercial temperature range
(0°C to +85°C)
— Industrial temperature range version available
(-40°C to +85°C)
Order Numbers:
LAN8710Ai-EZK for 32-pin QFN lead-free RoHS compliant package (-40 to +85°C temp)
LAN8710Ai-EZK-TR for 32-pin QFN lead-free RoHS compliant package (-40 to +85°C temp)
LAN8710A-EZC for 32-pin QFN lead-free RoHS compliant package (0 to +85°C temp)
LAN8710A-EZC-TR for 32-pin QFN lead-free RoHS compliant package (0 to +85°C temp)
TR indicates tape & reel option. Reel size is 4,000.
This product meets the halogen maximum concentration values per IEC61249-2-21
For RoHS compliance and environmental information, please visit www.smsc.com/rohs
Please contact your SMSC sales representative for additional documentation related to this product
such as application notes, anomaly sheets, and design guidelines.
Small Footprint MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX and flexPWR® Technology
Datasheet
Revision 1.4 (08-23-12) 2 SMSC LAN8710A/LAN8710Ai
DATASHEET
Copyright © 2012 SMSC or its subsidiaries. All rights reserved.
Circuit diagrams and other informa tion relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete information sufficient for
construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC
reserves the right to make changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest specifications
before placing your product order. The provision of this information does not convey to the purchaser of the described semiconductor devices any licenses under any patent
rights or other intellectual property rights of SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated
version of SMSC's standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors
known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request. SMSC products are not
designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property
damage. Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of
this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC’s website at http://www.smsc.com. SMSC is a registered
trademark of Standard Microsystems Corporation (“SMSC”). Product names and company names are the trademarks of their respective holders.
The Microchip name and logo, and the Microchip logo are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.
SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE, TITLE, A ND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND ALL WARRANTIES ARISING FROM ANY COURSE
OF DEALING OR USAGE OF TRADE. IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL
DAMAGES; OR FOR LOST DATA, PROFITS , SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT;
TORT; NEGLIGENCE OF SMSC OR OTHERS ; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD
TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHE THER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES .
Small Footprint MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX and flexPWR® Technology
Datasheet
SMSC LAN8710A/LAN8710Ai 3 Revision 1.4 (08-23-12)
DATASHEET
Table of Contents
Chapter 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.1 General Terms and Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.2 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Chapter 2 Pin Description and Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1 Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.2 Buffer Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Chapter 3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.1 Transceiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.1.1 100BASE-TX Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.1.2 100BASE-TX Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.1.3 10BASE-T Transmit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.1.4 10BASE-T Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.2 Auto-negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.2.1 Parallel Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.2.2 Restarting Auto-negotiation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.2.3 Disabling Auto-negotiation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.2.4 Half vs. Full Duplex . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.3 HP Auto-MDIX Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.4 MAC Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.4.1 MII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.4.2 RMII. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.4.3 MII vs. RMII Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.5 Serial Management Interface (SMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.6 Interrupt Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.6.1 Primary Interrupt System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.6.2 Alternate Interrupt System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.7 Configuration Straps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.7.1 PHYAD[2:0]: PHY Address Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.7.2 MODE[2:0]: Mode Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.7.3 RMIISEL: MII/RMII Mode Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.7.4 REGOFF: Internal +1.2V Regulator Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.7.5 nINTSEL: nINT/TXER/TXD4 Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.8 Miscellaneous Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.8.1 LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.8.2 Variable Voltage I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.8.3 Power-Down Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.8.4 Isolate Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.8.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.8.6 Carrier Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.8.7 Collision Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.8.8 Link Integrity Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.8.9 Loopback Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.9 Application Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.9.1 Simplified System Level Application Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.9.2 Power Supply Diagram (1.2V Supplied by Internal Regulator) . . . . . . . . . . . . . . . . . . . . 46
3.9.3 Power Supply Diagram (1.2V Supplied by External Source). . . . . . . . . . . . . . . . . . . . . . 47
3.9.4 Twisted-Pair Interface Diagram (Single Power Supply). . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.9.5 Twisted-Pair Interface Diagram (Dual Power Supplies) . . . . . . . . . . . . . . . . . . . . . . . . . 49
Small Footprint MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX and flexPWR® Technology
Datasheet
Revision 1.4 (08-23-12) 4 SMSC LAN8710A/LAN8710Ai
DATASHEET
Chapter 4 Register Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.1 Register Nomenclature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.2 Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4.2.1 Basic Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
4.2.2 Basic Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
4.2.3 PHY Identifier 1 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
4.2.4 PHY Identifier 2 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
4.2.5 Auto Negotiation Advertisement Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
4.2.6 Auto Negotiation Link Partner Ability Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
4.2.7 Auto Negotiation Expansion Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
4.2.8 Mode Control/Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
4.2.9 Special Modes Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
4.2.10 Symbol Error Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
4.2.11 Special Control/Status Indications Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
4.2.12 Interrupt Source Flag Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
4.2.13 Interrupt Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
4.2.14 PHY Special Control/Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Chapter 5 Operational Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
5.1 Absolute Maximum Ratings*. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
5.2 Operating Conditions**. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
5.3 Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
5.4 DC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
5.5 AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
5.5.1 Equivalent Test Load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
5.5.2 Power Sequence Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
5.5.3 Power-On nRST & Configuration Strap Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
5.5.4 MII Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
5.5.5 RMII Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
5.5.6 SMI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
5.6 Clock Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Chapter 6 Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Chapter 7 Datasheet Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Small Footprint MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX and flexPWR® Technology
Datasheet
SMSC LAN8710A/LAN8710Ai 5 Revision 1.4 (08-23-12)
DATASHEET
List of Figures
Figure 1.1 System Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 1.2 Architectural Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 2.1 32-QFN Pin Assignments (TOP VIEW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 3.1 100BASE-TX Transmit Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 3.2 100BASE-TX Receive Data Path. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 3.3 Relationship Between Received Data and Specific MII Signals . . . . . . . . . . . . . . . . . . . . . . 24
Figure 3.4 Direct Cable Connection vs. Cross-over Cable Connection . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 3.5 MDIO Timing and Frame Structure - READ Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 3.6 MDIO Timing and Frame Structure - WRITE Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 3.7 LED1/REGOFF Polarity Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 3.8 LED2/nINTSEL Polarity Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 3.9 Near-end Loopback Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 3.10 Far Loopback Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 3.11 Connector Loopback Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 3.12 Simplified System Level Application Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 3.13 Power Supply Diagram (1.2V Supplied by Internal Regulator) . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 3.14 Power Supply Diagram (1.2V Supplied by External Source). . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 3.15 Twisted-Pair Interface Diagram (Single Power Supply). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 3.16 Twisted-Pair Interface Diagram (Dual Power Supplies). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 5.1 Output Equivalent Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 5.2 Power Sequence Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 5.3 Power-On nRST & Configuration Strap Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 5.4 MII Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 5.5 MII Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 5.6 RMII Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 5.7 SMI Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 6.1 32-QFN Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 6.2 Recommended PCB Land Pattern. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 6.3 Taping Dimensions and Part Or ientation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 6.4 Reel Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 6.5 Tape Length and Part Quantity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Small Footprint MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX and flexPWR® Technology
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Revision 1.4 (08-23-12) 6 SMSC LAN8710A/LAN8710Ai
DATASHEET
List of Tables
Table 2.1 MII/RMII Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 2.2 LED Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 2.3 Serial Management Interface (SMI) Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 2.4 Ethernet Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 2.5 Miscellaneous Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 2.6 Analog Reference Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 2.7 Power Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 2.8 32-QFN Package Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 2.9 Buffer Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 3.1 4B/5B Code Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 3.2 MII/RMII Signal Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 3.3 Interrupt Management Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 3.4 Alternative Interrupt System Management Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 3.5 Pin Names for Address Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 3.6 MODE[2:0] Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 3.7 Pin Names for Mode Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 4.1 Register Bit Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 4.2 SMI Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 5.1 Device Only Current Consumption and Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 5.2 Non-Variable I/O Buffer Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 5.3 Variable I/O Buffer Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 5.4 100BASE-TX Transceiver Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 5.5 10BASE-T Transceiver Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 5.6 Power Sequence Timing Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 5.7 Power-On nRST & Con figuration Strap Timing Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 5.8 MII Receive Timing Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 5.9 MII Transmit Timing Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 5.10 RMII Timing Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 5.11 RMII CLKIN (REF_CLK) Timing Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 5.12 SMI Timing Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 5.13 Crystal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 6.1 32-QFN Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table 7.1 Customer Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Small Footprint MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX and flexPWR® Technology
Datasheet
SMSC LAN8710A/LAN8710Ai 7 Revision 1.4 (08-23-12)
DATASHEET
Chapter 1 Introduction
1.1 General Terms and Conventions
The following is list of the general terms used throughout this document:
1.2 General Description
The LAN8710A/LAN8710Ai is a low-power 10BASE-T/100BASE-TX physical layer (PHY) transceiver
with variable I/O voltage that is compliant with the IEEE 802.3-2005 standards.
The LAN8710A/LAN8710Ai supports communication with an Ethernet MAC via a standard MII (IEEE
802.3u)/RMII interface. It contains a full-duplex 10-BASE-T/100BASE-TX transceiver and supports
10Mbps (10BASE-T) and 100Mbps (100BASE-TX) operation. The LAN8710A/LAN8710Ai implements
auto-negotiation to automatically determine the be st possible spe ed and duplex mode of operati on. HP
Auto-MDIX support allows the use of direct connect or cross-over LAN cables.
The LAN8710A/LAN8710Ai supports both IEEE 802.3-2005 compliant and vendor-specific register
functions. However, no register access is required for operation. The initial configuration may be
selected via the configuration pins as described in Section 3.7, "Configuration Straps," on page 36.
Register-selectable configuration options may be used to further define the functionality of the
transceiver.
Per IEEE 802.3-2005 standards, all digital interface pins are tolerant to 3.6V. The device can be
configured to operate on a single 3.3V supply utilizing an integrated 3. 3V to 1.2V linear regulator. The
linear regulator may be optionally disabled, allowing usage of a high efficiency external regulator for
lower system power dissipation.
The LAN8710A/LAN8710 Ai is available in both ext ended commercial and industrial temperatu re range
versions. A typical system application is shown in Figure 1.1.
BYTE 8-bits
FIFO First In First Out buffer; often used for elasticity buffer
MAC Media Access Controller
MII Media Independent Interface
RMIITM Reduced Media Independent InterfaceTM
N/A Not Applicable
XIndicates that a logic state is “don’t care” or undefined.
RESERVED Refers to a reserved bit field or address. Unless otherwise
noted, reserved bits must always be zero for write
operations. Unless otherwise noted, values are not
guaranteed when reading reserved bits. Unless otherwise
noted, do not read or write to reserved addresses.
SMI Serial Management Interface
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Figure 1.1 System Block Diagram
Figure 1.2 Architectural Overview
LAN8710A/
LAN8710Ai
10/100
Ethernet
MAC
MII/
RMII
Mode LED
Transformer
Crystal or
Clock
Oscillator
MDI RJ45
RMII/MII Logic
Interrupt
Generator
LEDs
PLL
Receiver
DSP System:
Clock
Data Recovery
Equalizer
Squeltch
& Filters
Analog-to-
Digital
10M RX
Logic
100M RX
Logic
100M PLL
10M PLL
Transmitter
10M
Transmitter
100M
Transmitter
10M TX
Logic
100M TX
Logic
Central Bias
PHY Address
Latches
LAN8710A/LAN8710Ai
RBIAS
LED1
nINT
XTAL2
XTAL1/CLKIN
LED2
Management
Control
Mode Control
Reset Control
MDIX
Control
HP Auto-MDIX
RXP/RXN
TXP/TXN
TXD[0:3]
TXEN
TXER
TXCLK
RXD[0:3]
RXDV
RXER
RXCLK
CRS
COL/CRS_DV
MDC
MDIO
Auto-
Negotiation
RMIISEL
nRST
MODE[0:2]
SMI
PHYAD[0:2]
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SMSC LAN8710A/LAN8710Ai 9 Revision 1.4 (08-23-12)
DATASHEET
Chapter 2 Pin Description and Configuration
Note: When a lower case “n” is used at the beginning of the signal name, it indicates that the signal
is active low. For example, nRST indicates that the reset signal is active low.
Note: The buffer type for each signal is indicated in the BUFFER TYPE column. A description of the
buffer types is provided in Section 2.2.
Figure 2.1 32-QFN Pin Assignments (TOP VIEW)
VSS
NOTE: Exposed pad (VSS) on bottom of package must be connected to ground
SMSC
LAN8710A/LAN8710Ai
32 PIN QFN
(TOP VIEW)
MDIO
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
24
23
22
21
20
19
18
17
32
31
30
29
28
27
26
25
RXD3/PHYAD2
RXCLK/PHYAD1
VDDCR
XTAL1/CLKIN
XTAL2
LED1/REGOFF
LED2/nINTSEL
VDD2A TXD2
TXD1
TXD0
TXEN
TXCLK
nRST
nINT/TXER/TXD4
MDC
TXD3
RXDV
VDD1A
TXN
TXP
RXN
RXP
RBIAS
COL/CRS_DV/MODE2
CRS
RXER/RXD4/PHYAD0
VDDIO
RXD0/MODE0
RXD1/MODE1
RXD2/RMIISEL
Small Footprint MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX and flexPWR® Technology
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DATASHEET
Table 2.1 MII/RMII Signals
NUM PINS NAME SYMBOL BUFFER
TYPE DESCRIPTION
1Transmit
Data 0 TXD0 VIS The MAC transmits data to the transceiver using
this signal in all modes.
1Transmit
Data 1 TXD1 VIS The MAC transmits data to the transceiver using
this signal in all modes.
1
Transmit
Data 2
(MII Mode)
TXD2 VIS The MAC transmits data to the transceiver using
this signal in MII Mode.
Note: This signal must be grounded in RMII
Mode.
1
Transmit
Data 3
(MII Mode)
TXD3 VIS The MAC transmits data to the transceiver using
this signal in MII Mode.
Note: This signal must be grounded in RMII
Mode.
1
Interrupt
Output nINT VO8 Active low interrupt output. Place an external
resistor pull-up to VDDIO.
Note: Refer to Section 3.6, "Interrupt
Management," on page 34 for additional
details on device interrupts.
Note: Refer to Section 3.8.1.2, "nINTSEL and
LED2 Polarity Selection," on page 39 for
details on how the nINTSEL
configuration strap is used to determine
the function of this pin.
Transmit
Error
(MII Mode)
TXER VIS
(PU) When driven high, the 4B/5B encode process
substitutes the Transmit Error code-group (/H/)
for the encoded data word. This input is ignored
in the 10BASE-T mode of operation.
Transmit
Data 4
(MII Mode)
TXD4 VIS
(PU) In Symbol Interface (5B Decoding) mode, this
signal becomes the MII Transmit Data 4 line (the
MSB of the 5-bit symbol code-group).
Note: This signal is not used in RMII Mode.
1Transmit
Enable TXEN VIS
(PD) Indicates that valid transmission data is present
on TXD[3:0]. In RMII Mode, only TXD[1:0]
provide valid data.
1
Transmit
Clock
(MII Mode)
TXCLK VO8 Used to latch data from the MAC into the
transceiver.
MII (100BASE-TX): 25MHz
MII (10BASE-T): 2.5MHz
Note: This signal is not used in RMII Mode.
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DATASHEET
1
Receive
Data 0 RXD0 VO8 Bit 0 of the 4 (2 in RMII Mode) data bits that are
sent by the transceiver on the receive path.
PHY
Operating
Mode 0
Configuration
Strap
MODE0 VIS
(PU) Combined with MODE1 and MODE2, this
configuration strap sets the default PHY mode.
See Note 2.1 for more information on
configuration straps.
Note: Refer to Section 3.7.2, "MODE[2:0]:
Mode Configuration," on page 36 for
additional details.
1
Receive
Data 1 RXD1 VO8 Bit 1 of the 4 (2 in RMII Mode) data bits that are
sent by the transceiver on the receive path.
PHY
Operating
Mode 1
Configuration
Strap
MODE1 VIS
(PU) Combined with MODE0 and MODE2, this
configuration strap sets the default PHY mode.
See Note 2.1 for more information on
configuration straps.
Note: Refer to Section 3.7.2, "MODE[2:0]:
Mode Configuration," on page 36 for
additional details.
1
Receive
Data 2
(MII Mode)
RXD2 VO8 Bit 2 of the 4 (in MII Mode) data bits that are sent
by the transceiver on the receive path.
Note: This signal is not used in RMII Mode.
MII/RMII
Mode Select
Configuration
Strap
RMIISEL VIS
(PD) This configuration strap selects the MII or RMII
mode of operation. When strapped low to VSS,
MII Mode is selected. When strapped high to
VDDIO RMII Mode is selected.
See Note 2.1 for more information on
configuration straps.
Note: Refer to Section 3.7.3, "RMIISEL:
MII/RMII Mode Configuration," on
page 37 for additional details.
1
Receive
Data 3
(MII Mode)
RXD3 VO8 Bit 3 of the 4 (in MII Mode) data bits that are sent
by the transceiver on the receive path.
Note: This signal is not used in RMII Mode.
PHY Address
2
Configuration
Strap
PHYAD2 VIS
(PD) Combined with PHYAD0 and PHYAD1, this
configuration strap sets the transceiver’s SMI
address.
See Note 2.1 for more information on
configuration straps.
Note: Refer to Section 3.7.1, "PHYAD[2:0]:
PHY Address Configuration," on
page 36 for additional information.
Table 2.1 MII/RMII Signals (continued)
NUM PINS NAME SYMBOL BUFFER
TYPE DESCRIPTION
Small Footprint MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX and flexPWR® Technology
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DATASHEET
1
Receive Error RXER VO8 This signal is asserted to indicate that an error
was detected somewhere in the frame presently
being transferred from the transceiver.
Note: This signal is optional in RMII Mode.
Receive
Data 4
(MII Mode)
RXD4 VO8 In Symbol Interface (5B Decoding) mode, this
signal is the MII Receive Da ta 4 signal, the MSB
of the received 5-bit symbol code-group.
Note: Unless configured to the Symbol
Interface mode, this pin functions as
RXER.
PHY Address
0
Configuration
Strap
PHYAD0 VIS
(PD) Combined with PHYAD1 and PHYAD2, this
configuration strap sets the transceiver’s SMI
address.
See Note 2.1 for more information on
configuration straps.
Note: Refer to Section 3.7.1, "PHYAD[2:0]:
PHY Address Configuration," on
page 36 for additional information.
1
Receive
Clock
(MII Mode)
RXCLK VO8 In MII mode, this pin is the receive clock output.
MII (100BASE-TX): 25MHz
MII (10BASE-T): 2.5MHz
PHY Address
1
Configuration
Strap
PHYAD1 VIS
(PD) Combined with PHYAD0 and PHYAD2, this
configuration strap sets the transceiver’s SMI
address.
See Note 2.1 for more information on
configuration straps.
Note: Refer to Section 3.7.1, "PHYAD[2:0]:
PHY Address Configuration," on
page 36 for additional information.
1Receive Data
Valid RXDV VO8 Indicates that recovered and decoded data is
available on the RXD pins.
Table 2.1 MII/RMII Signals (continued)
NUM PINS NAME SYMBOL BUFFER
TYPE DESCRIPTION
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SMSC LAN8710A/LAN8710Ai 13 Revision 1.4 (08-23-12)
DATASHEET
Note 2.1 Configuration strap values are latched on power-on reset and system reset. Configuration
straps are identified by an underlined symbol name. Signals that function as configuration
straps must be augmented with an external resistor when connected to a load. Refer to
Section 3.7, "Configuration Straps," on page 36 for additional information.
1
Carrier Sense
/ Receive
Data Valid
(RMII Mode)
CRS_DV VO8 This signal is asserted to indicate the receive
medium is non-idle in RMII Mode. When a
10BASE-T packet is received, CRS_DV is
asserted, but RXD[1:0] is held low until the SFD
byte (10101011) is received.
Note: Per the RMII standard, transmitted data
is not looped back onto the receive data
pins in 10BASE-T half-duplex mode.
Collision
Detect
(MII Mode)
COL VO8 This signal is asserted to indicate detection of a
collision condition in MII Mode.
PHY
Operating
Mode 2
Configuration
Strap
MODE2 VIS
(PU) Combined with MODE0 and MODE1, this
configuration strap sets the default PHY mode.
See Note 2.1 for more information on
configuration straps.
Note: Refer to Section 3.7.2, "MODE[2:0]:
Mode Configuration," on page 36 for
additional details.
1Carrier Sense
(MII Mode) CRS VO8
(PD) This signal indicates detection of a carrier in MII
Mode.
Table 2.2 LED Pins
NUM PINS NAME SYMBOL BUFFER
TYPE DESCRIPTION
1
LED 1 LED1 O12 Link activity LED Indication. This pin is driven
active when a valid link is detected and blinks
when activity is detected.
Note: Refer to Section 3.8.1, "LEDs," on
page 39 for additional LED information.
Regulator Off
Configuration
Strap
REGOFF IS
(PD) This configuration strap is used to disable the
internal 1.2V regulator. When the regulator is
disabled, external 1.2V must be supplied to
VDDCR.
When REGOFF is pulled high to VDD2A with
an external resistor, the internal regulator is
disabled.
When REGOFF is floating or pulled low, the
internal regulator is enabled (default).
See Note 2.2 for more information on
configuration straps.
Note: Refer to Section 3.7.4, "REGOFF:
Internal +1.2V Regulator Configuration,"
on page 38 for additional details.
Table 2.1 MII/RMII Signals (continued)
NUM PINS NAME SYMBOL BUFFER
TYPE DESCRIPTION
Small Footprint MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX and flexPWR® Technology
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DATASHEET
Note 2.2 Configuration strap values are latched on power-on reset and system reset. Configuration
straps are identified by an underlined symbol name. Signals that function as configuration
straps must be augmented with an external resistor when connected to a load. Refer to
Section 3.7, "Configuration Straps," on page 36 for additional information.
1
LED 2 LED2 O12 Link Speed LED Indication. This pin is driven
active when the operating speed is 100Mbps. It
is inactive when the operating speed is 10Mbps
or during line isolation.
Note: Refer to Section 3.8.1, "LEDs," on
page 39 for additional LED information.
nINT/TXER/
TXD4
Function
Select
Configuration
Strap
nINTSEL IS
(PU) This configuration strap selects the mode of the
nINT/TXER/TXD4 pin.
When nINTSEL is floated or pulled to VDD2A,
nINT is selected for operation on the
nINT/TXER/TXD4 pin (default).
When nINTSEL is pulled low to VSS,
TXER/TXD4 is selected for operation on the
nINT/TXER/TXD4 pin.
See Note 2.2 for more information on
configuration straps.
Note: Refer to See Section 3.8.1.2, "nINTSEL
and LED2 Polarity Selection," on
page 39 for additional information.
Table 2.3 Serial Manag ement Interface (SMI) Pins
NUM PINS NAME SYMBOL BUFFER
TYPE DESCRIPTION
1SMI Data
Input/Output MDIO VIS/
VOD8 Serial Management Interface data input/output
1 SMI Clock MDC VIS Serial Management Interface clock
Table 2.4 Ethernet Pins
NUM PINS NAME SYMBOL BUFFER
TYPE DESCRIPTION
1Ethernet
TX/RX
Positive
Channel 1
TXP AIO Transmit/Receive Positive Channel 1
1Ethernet
TX/RX
Negative
Channel 1
TXN AIO Transmit/Receive Negative Channel 1
Table 2.2 LED Pins (continued)
NUM PINS NAME SYMBOL BUFFER
TYPE DESCRIPTION
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DATASHEET
1Ethernet
TX/RX
Positive
Channel 2
RXP AIO Transmit/Receive Positive Channel 2
1Ethernet
TX/RX
Negative
Channel 2
RXN AIO Transmit/Receive Negative Channel 2
Table 2.5 Miscellaneous Pins
NUM PINS NAME SYMBOL BUFFER
TYPE DESCRIPTION
1
External
Crystal
Input
XTAL1 ICLK External crystal input
External
Clock Input CLKIN ICLK Single-ended clock oscillator input.
Note: When using a single ended clock
oscillator, XTAL2 should be left
unconnected.
1External
Crystal
Output
XTAL2 OCLK External crystal output
1External
Reset nRST VIS
(PU) System reset. This signal is active low.
Table 2.6 Analog Reference Pins
NUM PINS NAME SYMBOL BUFFER
TYPE DESCRIPTION
1
External 1%
Bias Resistor
Input
RBIAS AI This pin requires connection of a 12.1k ohm (1%)
resistor to ground.
Refer to the LAN8710A/LAN8710Ai reference
schematic for connection information.
Note: The nominal voltage is 1.2V and the
resistor will dissipate approximately
1mW of power.
Table 2.4 Ethernet Pins (continued)
NUM PINS NAME SYMBOL BUFFER
TYPE DESCRIPTION
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Table 2.7 Power Pins
NUM PINS NAME SYMBOL BUFFER
TYPE DESCRIPTION
1+1.6V to
+3.6V
Variable I/O
Power
VDDIO P +1.6V to +3.6V variable I/O power
Refer to the LAN8710A/LAN8710Ai reference
schematic for connection information.
1
+1.2V Digital
Core Power
Supply
VDDCR P Supplied by the on-chip regulator unless
configured for regulator off mode via the
REGOFF configuration strap.
Refer to the LAN8710A/LAN8710Ai reference
schematic for connection information.
Note: 1 uF and 470 pF decouplin g capacitors
in parallel to ground should be used on
this pin.
1+3.3V
Channel 1
Analog Port
Power
VDD1A P +3.3V Analog Port Power to Channel 1
Refer to the LAN8710A/LAN8710Ai reference
schematic for connection information.
1
+3.3V
Channel 2
Analog Port
Power
VDD2A P +3.3V Analog Port Power to Channel 2 and the
internal regulator.
Refer to the LAN8710A/LAN8710Ai reference
schematic for connection information.
1Ground VSS P Common ground. This exposed pad must be
connected to the ground plane with a via array.
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2.1 Pin Assignments
Table 2.8 32-QFN Package Pin Assignments
PIN NUM PIN NAME PIN NUM PIN NAME
1 VDD2A 17 MDC
2 LED2/nINTSEL 18 nINT/TXER/TXD4
3LED1/REGOFF
19 nRST
4XTAL220 TXCLK
5 XTAL1/CLKIN 21 TXEN
6 VDDCR 22 TXD0
7 RXCLK/PHYAD1 23 TXD1
8 RXD3/PHYAD2 24 TXD2
9 RXD2/RMIISEL 25 TXD3
10 RXD1/MODE1 26 RXDV
11 RXD0/MODE0 27 VDD1A
12 VDDIO 28 TXN
13 RXER/RXD4/PHYAD0 29 TXP
14 CRS 30 RXN
15 COL/CRS_DV/MODE2 31 RXP
16 MDIO 32 RBIAS
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2.2 Buffer Types
Note: The digital signals are not 5V tolerant. Refer to Section 5.1, "Absolute Maximum Ratings*," on
page 66 for additional buffer information.
Note 2.3 Sink and source capabilities are dependant on the VDDIO voltage. Refer to Section 5.1,
"Absolute Maximum Ratings*," on page 66 for additional information.
Table 2.9 Buffer Types
BUFFER TYPE DESCRIPTION
IS Schmitt-triggered input
O12 Output with 12mA sink and 12mA source
VIS Variable voltage Schmitt-triggered input
VO8 Variable voltage output with 8mA sink and 8mA source
VOD8 Variable voltage open-drain output with 8mA sink
PU 50uA (typical) internal pull-up. Unless otherwise noted in the pin description, internal pull-
ups are always enabled.
Note: Internal pull-up resistors prevent unconnecte d inputs from floating. Do not rely on
internal resistors to drive signals external to the device. When connected to a load
that must be pulled high, an external resistor must be added.
PD 50uA (typical) internal pull-down. Unless otherwise noted in the pin description, internal
pull-downs are always enabled.
Note: Internal pull-down resistors prevent unconne cted inputs from floating. Do not rely
on internal resistors to drive signals ex ternal to the device. When connected to a
load that must be pulled low, an external resistor must be added.
AI Analog input
AIO Analog bi-directional
ICLK Crystal oscillator input pin
OCLK Crystal oscillator output pin
P Power pin
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Chapter 3 Functional Description
This chapter provides functiona l descriptions of the various device features. These features have been
categorized into the following sections:
Transceiver
Auto-negotiation
HP Auto-MDIX Support
MAC Interface
Serial Management Interface (SMI)
Interrupt Management
Configuration Straps
Miscellaneous Functions
Application Diagrams
3.1 Transceiver
3.1.1 100BASE-TX Transmit
The 100BASE-TX transmit data path is shown in Figure 3.1. Each major block is explained in the
following subsections.
3.1.1.1 100BASE-TX Transmit Data Across the MII/RMII Interface
For MII, the MAC controller drives the transmit data onto the TXD bus and asserts TXEN to indicate
valid data. The data is latched by the transceiver’s MII block on the rising edge of TXCLK. The data
is in the form of 4-bit wide 25MHz data.
Figure 3.1 100BASE-TX Transmit Data Path
MAC
Tx
Driver
MLT-3
Converter
NRZI
Converter
4B/5B
Encoder
CAT-5RJ45
25MHz by
5 bits
NRZI
MLT-3MLT-3
MLT-3
Scrambler
and PISO
MII/RMII 25MHz
by 4 bits
Ext Ref_CLK (for RMII only)
PLL
MII 25 Mhz by 4 bits
or
RMII 50Mhz by 2 bits
MLT-3
Magnetics
125 Mbps Serial
TX_CLK
(for MII only)
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For RMII, the MAC controller drive s the transmit data onto the TXD bus and asserts TXEN to indicate
valid data. The data is latched by the transceiver’s RMII block on the rising edge of REF_CLK. The
data is in the form of 2-bit wide 50MHz data.
3.1.1.2 4B/5B Encoding
The transmit data passes from the MII/RMII block to the 4B/5B encoder. This block encodes the data
from 4-bit nibbles to 5-bit symbols (known as “code-groups”) according to Table 3.1. Each 4-bit data-
nibble is mapped to 16 of the 32 possible co de-groups. The remaining 16 code-groups are either used
for control information or are not valid.
The first 16 code-groups are referred to by the hexadecimal values of their corre sponding data nibbles,
0 through F. The remaining code-groups are given letter designations with slashes on either side. For
example, an IDLE code-group is /I/, a transmit error code-group is /H/, etc.
Table 3.1 4B/5B Code Table
CODE
GROUP SYM RECEIVER
INTERPRETATION TRANSMITTER
INTERPRETATION
11110 0 0 0000 DATA 0 0000 DATA
01001 1 1 0001 1 0001
10100 2 2 0010 2 0010
10101 3 3 0011 3 0011
01010 4 4 0100 4 0100
01011 5 5 0101 5 0101
01110 6 6 0110 6 0110
01111 7 7 0111 7 0111
10010 8 8 1000 8 1000
10011 9 9 1001 9 1001
10110 A A 1010 A 1010
10111 B B 1011 B 1011
11010 C C 1100 C 1100
11011 D D 1101 D 1101
11100 E E 1110 E 1110
11101 F F 1111 F 1111
11111 I IDLE Sent after /T/R until TXEN
1100 0 J First nibble of SSD, translated to “0101”
following IDLE, else RXER Sent for rising TXEN
10001 K Second nibble of SSD, translated to
“0101” following J, else RXER Sent for rising TXEN
0110 1 T First nibble of ESD, causes de-assertion
of CRS if followed by /R/, else assertion
of RXER
Sent for falling TXEN
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3.1.1.3 Scrambling
Repeated data patterns (especially the IDLE code-group) can have power spectral den sities with large
narrow-band peaks. Scrambling the data helps eliminate these peaks and spread the signal power
more uniformly over the entire channel bandwidth. This uniform spectral density is required by FCC
regulations to prevent excessive EMI from being radiated by the physical wiring.
The seed for the scrambler is generated from the transceiver address, PHYAD, ensuring that in
multiple-transceiver applications, such as repeaters or switches, each transceiver will have its own
scrambler sequence.
The scrambler also performs the Parallel In Serial Out conversion (PISO) of the data.
3.1.1.4 NRZI and MLT-3 Encoding
The scrambler block passes the 5-bit wide parallel data to the NRZI converter where it becomes a
serial 125MHz NRZI data stream. The NRZI is encoded to MLT-3. MLT-3 is a tri-level code where a
change in the logic level represents a code bit “1” and the logic output remaining at the same level
represents a code bit “0”.
3.1.1.5 100M Transmit Driver
The MLT3 data is then passed to the analog transmitter, which drives the differential MLT-3 signal, on
outputs TXP and TXN, to the twisted pair media across a 1:1 ratio isolation transformer. The 10BASE-
T and 100BASE-TX signals pass through the same transformer so that common “magnetics” can be
used for both. The transmitter drives into the 100Ω impedance of the CAT-5 cable. Cable termination
and impedance matching require external components.
00111 R Second nibble of ESD, causes
deassertion of CRS if following /T/, else
assertion of RXER
Sent for falling TXEN
00100 H Transmit Error Symbol Sent for rising TXER
00110 V INVALID, RXER if during RXDV INVALID
11001 V INVALID, RXER if during RXDV INVALID
00000 V INVALID, RXER if during RXDV INVALID
00001 V INVALID, RXER if during RXDV INVALID
00010 V INVALID, RXER if during RXDV INVALID
00011 V INVALID, RXER if during RXDV INVALID
00101 V INVALID, RXER if during RXDV INVALID
01000 V INVALID, RXER if during RXDV INVALID
01100 V INVALID, RXER if during RXDV INVALID
10000 V INVALID, RXER if during RXDV INVALID
Table 3.1 4B/5B Code Table (continued)
CODE
GROUP SYM RECEIVER
INTERPRETATION TRANSMITTER
INTERPRETATION
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3.1.1.6 100M Phase Lock Loop (PLL)
The 100M PLL locks onto refe rence clock and gene rate s the 125MHz cl ock used to drive the 12 5 MHz
logic and the 100BASE-TX transmitter.
3.1.2 100BASE-TX Receive
The 100BASE-TX receive data path is shown in Figure 3.2. Each major block is explained in the
following subsections.
3.1.2.1 100M Receive Input
The MLT-3 from the cable is fed into the transceiver (on inputs RXP and RXN) via a 1:1 ratio
transformer. The ADC samples the incoming differential sig nal at a rate of 125M samples per se cond.
Using a 64-level quanitizer, it generates 6 digital bits to represent each sample. The DSP adjusts the
gain of the ADC according to the observed signal levels such that the full dynamic range of the ADC
can be used.
3.1.2.2 Equalizer, Baseline Wander Correction and Clock and Data Recovery
The 6 bits from the ADC are fed into the DSP block. The equalizer in the DSP section compensates
for phase and amplitud e distortion caused by the physical channel consisting of magnetics, connectors,
and CAT- 5 cable. The equalizer can restore the signal for any good-quality CAT-5 cable between 1m
and 150m.
If the DC content of the signal is such that the low-frequen cy components fall below the low frequency
pole of the isolation transformer, then the droop characteristics of the transformer will become
significant and Baseline Wander (BLW) on the received signal will result. To prevent corruption of the
received data, the transceiver corrects for BLW and can receive the ANSI X3.263-1995 FDDI TP-PMD
defined “killer packet” with no bit errors.
Figure 3.2 100BASE-TX Receive Data Path
MAC
A/D
Converter
MLT-3
Converter
NRZI
Converter
4B/5B
Decoder
Magnetics CAT-5RJ45
PLL
MII 25Mhz by 4 bits
or
RMII 50Mhz by 2 bits
RX_CLK
(for MII only)
25MHz by
5 bits
NRZI
MLT-3MLT-3 MLT-3
6 bit Data
Descrambler
and SIPO
125 Mbps Serial
DSP: Timing
recovery, Equalizer
and BLW Correction
MLT-3
MII/RMII 25MHz
by 4 bits
Ext Ref_CLK (for RMII only)
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The 100M PLL generates multiple phases of the 125MHz clock. A multiplexer, controll ed by the timing
unit of the DSP, selects the optimum phase for sampling the data. This is used as the received
recovered clock. This clock is used to extract the serial data from the received signal.
3.1.2.3 NRZI and MLT-3 Decoding
The DSP generates the MLT-3 recovered levels that are fed to th e MLT-3 converter. The MLT-3 is th en
converted to an NRZI data stream.
3.1.2.4 Descrambling
The descrambler performs an inverse function to the scrambler in the transmitter and also performs
the Serial In Parallel Out (SIPO) conversion of the data.
During reception of IDLE (/I/) symbols. the descrambler synchronizes its descrambler key to the
incoming stream. Once synchronization is achieved, the descrambler locks on this key and is able to
descramble incoming data.
Special logic in the descrambler ensures synchronization with the remote transceiver by searching for
IDLE symbols within a window of 4000 bytes (40us). This win dow ensures tha t a maximum packet size
of 1514 bytes, allowed by the IEEE 802.3 standard, can be received with no interference. If no IDLE-
symbols are detected with in this time-period, receive ope ration is aborted and the descrambler re-starts
the synchronization process.
3.1.2.5 Alignment
The de-scrambled signal is then aligned into 5-bit code-groups by recognizing the /J/K/ Start-of-Stream
Delimiter (SSD) pair at the start of a packet. Once the code-word alignment is determined, it is stored
and utilized until the next start of frame.
3.1.2.6 5B/4B Decoding
The 5-bit code-groups are translated into 4-bit data nibbles according to the 4B/5B table. The
translated data is presented on the RXD[3:0] signal lines. The SSD, /J/K/, is translated to “0101 0101”
as the first 2 nibbles o f the MAC preamble. Recepti on of the SSD causes the transceiver to assert the
receive data valid signal, indicati ng that valid data is available on the RXD bus. Succe ssive valid code-
groups are translated to data nibbles. Recep tion of either the End of Stream Delimiter (ESD) consisting
of the /T/R/ symbols, or at least two /I/ symbols causes the transceiver to de-assert the carrier sense
and receive data valid signals.
Note: These symbols are not translated into data.
3.1.2.7 Receive Data Valid Signal
The Receive Data Valid signal (RXDV) indicates that recovered and decoded nibbles are being
presented on the RXD[3:0] outputs synchronous to RXCLK. RXDV becomes active after the /J/K/
delimiter has been recognized and RXD is aligned to nibble boundaries. It remains active until either
the /T/R/ delimiter is recognized or link test indicates failure or SIGDET becomes false.
RXDV is asserted when the first nibble of translated /J/K/ is ready for transfer over the Media
Independent Interface (MII mode).
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Figure 3.3 Relationship Between Received Data and Specific MII Signals
3.1.2.8 Receiver Errors
During a frame, unexpected co de-groups are considered receive errors. Expected code groups are the
DATA set (0 through F), and the /T/R/ (ESD) symbol pair. When a receive error occurs, the RXER
signal is asserted and arbitrary data is driven onto the RXD[3:0] lines. Should an error be detected
during the time that the /J/K/ delimiter is being decoded (bad SSD error), RXER is asserted true and
the value ‘1110’ is driven onto the RXD[3:0] lines. Note that the Valid Data signal is not yet asserted
when the bad SSD error occurs.
3.1.2.9 100M Receive Data Across the MII/RMII Interface
In MII mode, the 4-bit data nibbles are sent to the MII block. These data nibbles are clocked to the
controller at a rate of 25MHz. The controller samples the data on the rising edge of RXCLK. To ensure
that the setup and hold requirements are met, the nibbles are clocked out of the transceiver on the
falling edge of RXCLK. RXCLK is the 25MHz output clock for the MII bus. It is recovered from the
received data to clock the RXD bus. If there is no received signal, it is derived from the system
reference clock (XTAL1/CLKIN).
When tracking the received data, RXCLK has a maximum jitter of 0.8ns (provided that the jitter of the
input clock, XTAL1/CLKIN, is below 100ps).
In RMII mode, the 2-bit data nibbles are sent to the RMII block. These data nibbles are clocked to the
controller at a rate of 50MHz. The controller samples the data on the rising edge of XTAL1/CLKIN
(REF_CLK). To ensure that the setup and hold requirements are met, the nibbles are clocked out of
the transceiver on the falling edge of XTAL1/CLKIN (REF_CLK).
3.1.3 10BASE-T Transmit
Data to be transmitted comes from the MAC layer controller. The 10BASE-T transmitter receives 4-bit
nibbles from the MII at a rate of 2.5MHz and converts them to a 10Mbps serial data stream. The data
stream is then Manchester-encoded and sent to the analog transmitter, which drives a signal onto the
twisted pair via the external magnetics.
The 10M transmitter uses the following blocks:
MII (digital)
TX 10M (digital)
10M Transmitter (analog)
10M PLL (analog)
3.1.3.1 10M Transmit Data Across the MII/RMII Interface
The MAC controller drives the transmit data onto the TXD b us. For MII, when the controller has driven
TXEN high to indicate valid data, the data is latched by the MII block on the rising edge of TXCLK.
The data is in the form of 4-bit wide 2.5MHz data. For RMII, TXD[1:0] shall transition synchronously
with respect to REF_CLK. When TXEN is asserted, TXD[1:0] are accepted for transmission by the
device. TXD[1:0] shall be “00” to indi cate idle when T XEN is deasserted. Values of TXD[1:0] other than
“00” when TXEN is deasserted are reserved for out-of-band signalling (to be defined). Values other
5D5 data data data data
RXD
RX_DV
RX_CLK
5D5data data data data
CLEAR-TEXT 5JK
555
TR
Idle
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than “00” on TXD[1:0] while TXEN is deasse rted shall be ignored by the device.TXD[1:0] shall provide
valid data for each REF_CLK period while TXEN is asserted.
In order to comply with legacy 10BASE-T MAC/Controllers, in half-duplex mode the transceiver loops
back the transmitted data, on the receive path. This does not confuse the MAC/Controller since the
COL signal is not asse rted during this time. The tr ansceiver also supports the SQE (Heartbeat) signal.
See Section 3.8.7, "Collision Detect," on page 42, for more details.
3.1.3.2 Manchester Encoding
The 4-bit wide data is sent to the 10M TX block. The nibbles are converted to a 10Mbps serial NRZI
data stream. The 10M PLL locks onto the external clock or internal oscillator and produces a 20MHz
clock. This is used to Manchester encode the NRZ data stream. When no data is being transmitted
(TXEN is low), the 10M T X block outputs Normal Link Pulses (NLPs) to maintain communications with
the remote link partner.
3.1.3.3 10M Transmit Drivers
The Manchester encoded data is sent to the analog transmitter where it is shaped and filtered before
being driven out as a differential signal across the TXP and TXN outputs.
3.1.4 10BASE-T Receive
The 10BASE-T receiver gets the Manchester- encoded an alog signa l from the cable vi a the magneti cs.
It recovers the receive clock from the signal and uses this clock to recover the NRZI da ta stream. This
10M serial data is converted to 4-bit data nibbles which are passed to the controller via MII at a rate
of 2.5MHz.
This 10M receiver uses the following blocks:
Filter and SQUELCH (analog)
10M PLL (analog)
RX 10M (digital)
MII (digital)
3.1.4.1 10M Receive Input and Squelch
The Manchester signal from the cable is fed in to t he transceiver (on inp uts RXP and RXN) via 1:1 ratio
magnetics. It is first filtered to reduce any out-of-band noise. It then passes through a SQUELCH
circuit. The SQUELCH is a set of amplitude and timing comparators that normally reject differential
voltage levels below 300mV and detect and recognize differential voltages above 585mV.
3.1.4.2 Manchester Decoding
The output of the SQUELCH goes to the 10M RX block where it is validated as Manchester encoded
data. The polarity of the signal is also checked. If the polarity is reversed (local RXP is connected to
RXN of the remote partner and vice versa), the condition is identified and corrected. The reversed
condition is indi cated by the XPOL bit of the Special Control /Status Indications Register. The 1 0M PLL
is locked onto the received Manchester signal, from which the 20MHz cock is generated. Using this
clock, the Manchester encoded data is extracted and converted to a 10MHz NRZI data stream. It is
then converted from serial to 4-bit wide parallel data.
The 10M RX block also detects valid 10Base-T IDLE signals - Normal Link Pul ses (NLPs) - to maintain
the link.
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3.1.4.3 10M Receive Data Across the MII/RMII Interface
For MII, the 4-bit data nibbles are sent to the MII block. In MII mode, these data nibbles are valid on
the rising edge of the 2.5 MHz RXCLK.
For RMII, the 2-bit data nibbles a re sent to the RMII block. In RMII mode, these data nibbles are valid
on the rising edge of the RMII REF_CLK.
3.1.4.4 Jabber Detection
Jabber is a condition in which a station transmits for a period of time longer than the maximum
permissible packet length, usually due to a fault condition, which results in holding the TXEN input for
a long period. Special logic is used to detect the jabber state and abort the transmission to the line
within 45ms. Once TXEN is deasserted, the logic resets the jabber condition.
As shown in Section 4.2.2, "Basic Status Register," on page 53, the Jabber Detect bit indicates that a
jabber condition was detected.
3.2 Auto-negotiation
The purpose of the auto-negotiation function is to automatically configure the transceiver to the
optimum link parameters based on the capabilities of its link partner. Auto-negotiation is a mechanism
for exchanging configuration information between two link-partners and automatically selecting the
highest performance mode of operation supported by both sides. Auto-negotiation is fully defined in
clause 28 of the IEEE 802.3 specification.
Once auto-negotiation has completed, information about the resolved link can be passed back to the
controller via the Serial Management Interface (SMI). The results of the negotiation process are
reflected in the Speed Ind ication bits of the PHY Special Control/Status Register, as well as i n the Auto
Negotiation Link Partner Ability Register. The auto-negotiation protocol is a purely physical layer
activity and proceeds independently of the MAC controller.
The advertised capabilities of the transceiver are stored in the Auto Negotiation Advertisement
Register. The default advertised by the transceiver is determined by user-defined on-chip signal
options.
The following blocks are activated during an Auto-negotiation session:
Auto-negotiation (digital)
100M ADC (analog)
100M PLL (analog)
100M equalizer/BLW/clock recovery (DSP)
10M SQUELCH (analog)
10M PLL (analog)
10M Transmitter (analog)
When enabled, auto-negotiation is started by the occurrence of one of the following events:
Hardware reset
Software reset
Power-down reset
Link status down
Setting the Restart Auto-Negotiate bit of the Basic Control Register
On detection of one of these events, the transceiver begins auto-negotiation by transmitting bursts of
Fast Link Pulses (FLP), which are bursts of link pulses from the 10M transmitter. They are shaped as
Normal Link Pulses and can pass uncorrupted down CAT-3 or CAT-5 cable. A Fast Link Pulse Burst
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consists of up to 33 pulses. The 17 odd-numbered pulses, which are always present, frame the FLP
burst. The 16 even-numbered pulses, which may be present or absent, contain the data word being
transmitted. Presence of a data pulse represents a “1”, while absence represents a “0”.
The data transmitted by an FLP burst i s known as a “Link Code Word.” These are defined fully in IEEE
802.3 clause 28. In summary, the transceiver advertise s 802.3 compliance in its selector field (the first
5 bits of the Link Code Word). It advertises its technology ability according to the bits set in the Auto
Negotiation Advertisement Register.
There are 4 possible matches of the technology abilities. In the order of priority these are:
100M Full Duplex (Highest Priority)
100M Half Duplex
10M Full Duplex
10M Half Duplex (Lowest Priority)
If the full capabilities of the transceiver are advertised (100M, Full Duplex), and if the link partner is
capable of 10M and 100M, then auto-negotiation selects 100M as the highest performance mode. If
the link partner is capable of half and full duplex modes, then auto-negotiation selects full duplex as
the highest performance operation.
Once a capability match has been determined, th e link code words are repeated w ith the acknowledge
bit set. Any difference in the main con tent of the lin k code words at thi s time w ill cause auto-n egotia tion
to re-start. Auto-negotiation will also re-start if not all of the required FLP bursts are received.
The capabilities advertised during auto-negotiation by the transceiver are initially determined by the
logic levels latched on the MODE[2:0] configuration straps after reset completes. These configuration
straps can also be used to disable auto-negotiation on power-up. Refer to Section 3.7.2, "MODE[2:0]:
Mode Configuration," on page 36 for additional information.
Writing the bits 8 through 5 of the Auto Negotiation Advertisement Register allows software control of
the capabilities advertised by the transceiver. Writing the Auto Negotiation Advertisement Register
does not automatically re-start auto-negotiation. The Restart Auto-Negotiate bit of the Basic Control
Register must be set before the new abilities will be ad vertised. Auto-negotiation can also be disabled
via software by clearing the Auto-Negotiation Enable bit of the Basic Control Register.
Note: The device does not support “Next Page” capability.
3.2.1 Parallel Detection
If the LAN8710A/LAN8710Ai is connected to a device lacking the ability to auto-negotiate (i.e. no FLPs
are detected), it is able to determine the speed of the link based on either 100M MLT-3 symbols or
10M Normal Link Pulses. In this case the link is presumed to be half duplex per the IEEE standard.
This ability is known as “Parallel Detection.” This feature ensures interoperability with legacy link
partners. If a link is formed via parallel detectio n, then the Link Pa rtner Auto-Negotiation Able bit of the
Auto Negotiation Expansion Register is cle ared to indicate that the Link Partner is not capable of auto-
negotiation. The controller has access to this information via the management interface. If a fault
occurs during parallel detection, the Parallel Detection Fault bit of Link Partner Auto-Negotiation Able
is set.
Auto Negotiation Link Partner Abil ity Register is used to sto re the link partner ability information, which
is coded in the received FLPs. If the link partner is not auto-negotiation capable, then the Auto
Negotiation Link Partner Ability Register is updated after completion of parallel detection to reflect the
speed capability of the link partner.
3.2.2 Restarting Auto-negotiation
Auto-negotiation can be restarted at any time by setting the Restart Auto-Negotiate bit of the Basic
Control Register. Auto-negotiation will also restart if the link is broken at any time. A broken link is
caused by signal loss. This may occur because of a cable break, or because of an interruption in the
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signal transmitted by the link partner. Auto-negotiation resumes in an attempt to determine the new
link configuration.
If the management entity re-starts auto-negotiation by setting the Restart Auto-Negotiate bit of the
Basic Control Register, the LAN8710A/LAN8710Ai will respond by stopping all transmission/receiving
operations. Once the break_link_timer is completed in the Auto-negotiation state-machine
(approximately 1200ms), auto-negotiation will re-start. In this case, the link partner will have also
dropped the link due to lack of a received signal, so it too will resume auto-negotiation.
3.2.3 Disabling Auto-negotiation
Auto-negotiation can be disabled by setting the Auto-Negotiation Enable bit of the Basic Control
Register to zero. The device will then force its speed of operatio n to reflect the information in the Basic
Control Register (Speed Select bit and Duplex Mode bit). These bits should be ignored when auto-
negotiation is enabled.
3.2.4 Half vs. Full Duplex
Half duplex operation relies on the CSMA/CD (Carrier Sense Multiple Access / Collision Detect)
protocol to handle network traffic and collisions. In th is mode, the carrier sense signal, CRS, responds
to both transmit and receive activity. If data is received while the transceiver is transmitting, a collision
results.
In full duplex mode, the transceiver is able to transmit and receive data simultaneously. In this mode,
CRS responds only to receive activity. The CSMA/CD protocol does not apply and collision detection
is disabled.
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3.3 HP Auto-MDIX Support
HP Auto-MDIX facilitates the use of CAT-3 (10BASE-T) or CAT-5 (100BASE-T) media UTP
interconnect cable without consideration of interface wiring scheme. If a user plugs in either a direct
connect LAN cable, or a cross-over patch cable, as shown in Figure 3.4, the device’s Auto-MDIX
transceiver is capable of configuring the TXP/TXN a nd RXP/RXN pins for correct transceiver op eration.
The internal logic of the device detects the TX and RX pins of the connecting device. Since the RX
and TX line pairs are interchangeable, special PCB design considerati ons are ne eded to acco mmodate
the symmetrical magnetics and termination of an Auto-MDIX design.
The Auto-MDIX function can be disabled via the AMDIXCTRL bit in the Special Control/Status
Indications Register.
Figure 3.4 Direct Cable Connection vs. Cross-over Cable Connection
1
2
3
4
5
6
7
8
TXP
TXN
RXP
Not Used
Not Used
RXN
Not Used
Not Used
1
2
3
4
5
6
7
8
TXP
TXN
RXP
Not Used
Not Used
RXN
Not Used
Not Used
Direct Connect Cable
RJ-45 8-pin straight-through
for 10BASE-T/100BASE-TX
signaling
1
2
3
4
5
6
7
8
TXP
TXN
RXP
Not Used
Not Used
RXN
Not Used
Not Used
1
2
3
4
5
6
7
8
TXP
TXN
RXP
Not Used
Not Used
RXN
Not Used
Not Used
Cross-O ver Cable
RJ-45 8-pin cross-over for
10BASE-T/100BASE-TX
signaling
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3.4 MAC Interface
The MII/RMII block is responsible for communication with the MAC controller. Special sets of hand-
shake signals are used to indicate that valid received/transmitted data is present on the 4 bit
receive/transmit bus.
The device must be configured in MII or RMII mode. This is done by specific pin strapping
configurations. Refer to Section 3.4.3, "MII vs. RMII Configuration," on page 31 for information on pin
strapping and how the pins are mapped differently.
3.4.1 MII
The MII includes 16 interface signals:
transmit data - TXD[3:0]
transmit strobe - TXEN
transmit clock - TXCLK
transmit error - TXER/TXD4
receive data - RXD[3:0]
receive strobe - RXDV
receive clock - RXCLK
receive error - RXER/RXD4/PHYAD0
collision indication - COL
carrier sense - CRS
In MII mode, on the transmit path, the transceiver drives the transmit clock, TXCLK, to the controller.
The controller synchronizes the transmit data to the rising edge of TXCLK. The controll er drives TXEN
high to indicate val id transmit data. The controller drives TXER high when a transmit error is detected.
On the receive path, the transceiver drives both the receive data, RXD[3:0], and the RXCLK signal.
The controller clocks in the receive data on the rising edge of RXCLK when the transceiver drives
RXDV high. The transceiver drives RXER high when a receive error is detected.
3.4.2 RMII
The device supports the low pin count Reduced Media Independent Interface (RMII) intended for use
between Ethernet transceivers and switch ASICs. Under IEEE 802.3, an MII comprised of 16 pins for
data and control is defined. In devices incorporating many MACs or transceiver interfaces such as
switches, the number of pins can add significant cost as the port counts increase. RMII reduces this
pin count while retaining a management interface (MDIO/MDC) that is identical to MII.
The RMII interface has the following characteristics:
It is capable of supporting 10Mbps and 100Mbps data rates
A single clock reference is used for both transmit and receive
It provides independent 2-bit (di-bit) wide transmit and receive data paths
It uses LVCMOS signal levels, compatible with common digital CMOS ASIC processes
The RMII includes the following interface signals (1 optional):
transmit data - TXD[1:0]
transmit strobe - TXEN
receive data - RXD[1:0]
receive error - RXER (Optional)
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carrier sense - CRS_DV
Reference Clock - (RMII references usually define this signal as REF_CLK)
3.4.2.1 CRS_DV - Carrier Sense/Receive Data Valid
The CRS_DV is asserted by the device when the receive medium is non-idle. CRS_DV is asserted
asynchronously on detection of carrier due to the criteria relevant to the operating mode. In 10BASE-
T mode when squelch is passed, or in 100BASE-X mod e when 2 non-contiguous zeroes i n 10 bits are
detected, the carrier is said to be detected.
Loss of carrier shall result in the deassertion o f CRS_DV synchronous to the cycle of REF_CLK which
presents the first di-bit of a nibble onto RXD[1:0] (i.e. CRS_DV is deasserted only on nibble
boundaries). If the device has additional bits to be presented on RXD[1:0] following the initial
deassertion of CRS_DV, then the device shall assert CRS_DV on cycles of REF_CLK which present
the second di-bit of each nibble and de-assert CRS _DV on cycles of REF_CLK which present the fi rst
di-bit of a nibble. The resu lt is, starting on nibble boundaries, CRS_DV toggles at 25 MH z in 100Mbps
mode and 2.5 MHz in 10Mbps mode when CRS ends before RXDV (i.e. the FIFO still has bits to
transfer when the carrier event ends). Therefore, the MAC can accurately recover RXDV and CRS.
During a false carrier event, CRS_D V shal l remain asse rted for the dura tion of carrier activity. The data
on RXD[1:0] is considered valid once CRS_DV is asserted. However, since the assertion of CRS_DV
is asynchronous relative to REF_CLK, the data on RXD[1:0] shall be “00” until proper receive signal
decoding takes place.
3.4.2.2 Reference Clock (REF_CLK)
The RMII REF_CLK is a continuous clock that provides the timing reference for CRS_DV, RXD[1:0],
TXEN, TXD[1:0] and RXER. The device uses REF_CLK as the network clock such that no buffering
is required on the transmit data path. However, on the receive data path, the receiver recovers the
clock from the incoming data stream, and the device uses elasticity buffering to accommodate for
differences between the recovered clock and the local REF_CLK.
3.4.3 MII vs. RMII Configuration
The device must be configured to support the MII or RMII bus for connectivity to the MAC. This
configuration is done via the RMIISEL configuration strap. MII or RMII mode selection is configured
based on the strapping of the RMIISEL configuration strap as described in Section 3.7.3, "RMIISEL:
MII/RMII Mode Configuration," on page 37.
Most of the MII and RMII pins are multiplexed. Table 3.2, "MII/RMII Signal Mapping" describes the
relationship of the related device pins to the MII and RMII mode signal names.
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Note 3.1 In RMII mode, this pin needs to tied to VSS.
Note 3.2 The RXER signal is optional on the RMII bus. This signal is required by the transceiver,
but it is optional for the MAC. The MAC can choose to ignore or not use this signal.
Table 3.2 MII/RMII Signal Mapping
PIN NAME MII MODE RMII MODE
TXD0 TXD0 TXD0
TXD1 TXD1 TXD1
TXEN TXEN TXEN
RXER/
RXD4/PHYAD0 RXER RXER
Note 3.2
COL/CRS_DV/MODE2 COL CRS_DV
RXD0/MODE0 RXD0 RXD0
RXD1/MODE1 RXD1 RXD1
TXD2 TXD2 Note 3.1
TXD3 TXD3 Note 3.1
nINT/TXER/TXD4 TXER/
TXD4
CRS CRS
RXDV RXDV
RXD2/RMIISEL RXD2
RXD3/PHYAD2 RXD3
TXCLK TXCLK
RXCLK/PHYAD1 RXCLK
XTAL1/CLKIN XTAL1/CLKIN REF_CLK
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3.5 Serial Management Interface (SMI)
The Serial Management Interface is used to control the device and obtain its status. This interface
supports registers 0 through 6 as required by Clause 22 of the 802.3 standard, as well as “vendor-
specific” registers 16 to 31 allowed by the specification. Non-sup ported registers (such as 7 to 15) will
be read as hexadecimal “FFFF”. Device registers are detailed in Chapter 4, "Register Descriptions,"
on page 50.
At the system level, SMI provides 2 signals: MDIO and MDC. The MDC signal is an aperiodic clock
provided by the station management controller (SMC). MDIO is a bi-directional data SMI input/output
signal that receives serial data (commands) from the controller SMC and sends serial data (status) to
the SMC. The minimum time between edges of the MDC is 160 ns. There is no maximum time
between edges. The minimum cycle time (time between two consecutive rising or two consecutive
falling edges) is 400 ns. These modest timing requirements allow this interface to be easily driven by
the I/O port of a microcontroller.
The data on the MDIO line is latched on the rising edge of the MDC. The frame structure and timing
of the data is shown in Figure 3.5 and Figure 3.6. The timing relationships of the MDIO signals are
further described in Section 5.5.6, "SMI Timing," on page 76.
Figure 3.5 MDIO Timing and Frame Structure - READ Cycle
Figure 3.6 MDIO Timing and Frame Structure - WRITE Cycle
MDC
MDIO
Read Cycle
...
32 1's 0110A4A3A2A1A0R4R3R2R1R0 D1
...
D15 D14 D0
Preamble Start of
Frame OP
Code PHY Address Register Address Turn
Around Data
Data From Phy
Data To Phy
MDC
MDIO ...
32 1's 0 1 10 A4A3A2A1A0R4R3R2R1R0
Write Cycle
D15 D14 D1 D0
...
DataPreamble Start of
Frame OP
Code PHY Address Register Address Turn
Around
Data To Phy
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3.6 Interrupt Management
The device management interface supports an interrupt capability that is not a part of the IEEE 802.3
specification. This interrupt capability generates an active low asynchronous interrupt signal on the
nINT output whenever certain events are detected as setup by the Interrupt Mask Register.
The device’s interrupt system provides two modes, a Primary Interrupt mode and an Alternative
interrupt mode. Both systems will assert the nINT pin low when the corresponding mask bit is set.
These modes differ only in how they de-assert the nINT interrupt output. These modes are detailed in
the following subsections.
Note: The Primary interrupt mode is the default interrupt mode after a power-up or hard reset. The
Alternative interrupt mode requires setup after a power-up or hard reset.
3.6.1 Primary Interrupt System
The Primary interrupt system is the default interrupt mode (ALTINT bit of the Mode Control/Status
Register is “0”). The Primary interrupt system is always selected after power-up or hard reset. In this
mode, to set an interrupt, set the corresponding mask bit in the Interrupt Mask Regi ster (see Table 3.3).
Then when the event to assert nINT is true, the nINT output will be asserted. When the corresponding
event to deassert nINT is true, then the nINT will be de-asserted.
Note 3.3 If the mask bit is enabled and nINT has been de-asserted while ENERGYON is still high,
nINT will assert for 256 ms, approximately one second after ENERGYON goes low when
the Cable is unplugged. To prevent an unexpected assertion of nINT, the ENERGYON
interrupt mask should always be cleared as part of the ENERGYON interrupt service
routine.
Table 3.3 Interrupt Management Table
MASK INTERRUPT SOURCE
FLAG INTERRUPT SOURCE EVENT TO
ASSERT nINT EVENT TO
DE-ASSERT nINT
30.7 29.7 ENERGYON 17.1 ENERGYON Rising 17.1
(Note 3.3)Falling 17.1 or
Reading register 29
30.6 29.6 Auto-Negotiation
complete 1.5 Auto-Negotiate
Complete Rising 1.5 Falling 1.5 or
Reading register 29
30.5 29.5 Remote Fault
Detected 1.4 Remote Fault Rising 1.4 Falling 1.4, or
Reading register 1 or
Reading register 29
30.4 29.4 Link Down 1.2 Link Status Falling 1.2 Reading register 1 or
Reading register 29
30.3 29.3 Auto-Negotiation
LP Acknowledge 5.14 Acknowledge Rising 5.14 Falling 5.14 or
Read register 29
30.2 29.2 Parallel Detection
Fault 6.4 Parallel
Detection Fault Rising 6.4 Falling 6.4 or
Reading register 6, or
Reading register 29
or
Re-Auto Negotiate or
Link down
30.1 29.1 Auto-Negotiation
Page Received 6.1 Page Received Rising 6.1 Falling of 6.1 or
Reading register 6, or
Reading register 29
Re-Auto Negotiate, or
Link Down.
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Note: The ENERGYON bit in the Mode C ontrol/Status Register is defaulted to a ‘1 ’ at the start of the
signal acquisition process, therefore the INT7 bit in the Interrupt Mask Register will also read
as a ‘1’ at power-up. If no signal is present, then both ENERGYON and INT7 will clear within
a few milliseconds.
3.6.2 Alternate Interrupt System
The Alternate interrupt system is enabled by setting the ALTINT bit of the Mode Control/Status Register
to “1”. In this mode, to set an interrupt, set the corresponding bit of the in the Mask Register 30, (see
Table 3.4). To Clear an interrupt, either clear the corresponding bit in the Interrupt Mask Register to
deassert the nINT output, or clear the interrupt source, and write a ‘1’ to the corresponding Interrupt
Source Flag. Writing a ‘1’ to the Interrupt Source Flag will cause the state machine to check the
Interrupt Source to determin e if the Interrupt Source Flag should clear or stay as a ‘1’. If the C ondition
to deassert is true, then the Interrupt Source Flag is cleared and nINT is also deasserted. If the
Condition to deassert is false, then the Interrupt Source Flag remains set, and the nINT remains
asserted.
For example, setting the INT7 bit in the Interrupt Mask Register will enable the ENERGYON interrupt.
After a cable is plugged in, the ENERGYON bit in the Mode Control/Status Register goes active and
nINT will be asserted low. To de-assert the nINT interrupt output, either clear the ENERGYON bit in
the Mode Control/Status Register by removing the cable and then writing a ‘1’ to the INT7 bit in the
Interrupt Mask Register, OR clear the INT7 mask (bit 7 of the Interrupt Mask Register).
Note: The ENERGYON bit in the Mode C ontrol/Status Register is defaulted to a ‘1 ’ at the start of the
signal acquisition process, therefore the INT7 bit in the Interrupt Mask Register will also read
as a ‘1’ at power-up. If no signal is present, then both ENERGYON and INT7 will clear within
a few milliseconds.
Table 3.4 Alternativ e Interrupt System Management Table
MASK INTERRUPT SOURCE
FLAG INTERRUPT SOURCE EVENT TO
ASSERT nINT
CONDITION
TO
DE-ASSERT
BIT TO
CLEAR
nINT
30.7 29.7 ENERGYON 17.1 ENERGYON Rising 17.1 17.1 low 29.7
30.6 29.6 Auto-Negotiation
complete 1.5 Auto-Negotiate
Complete Rising 1.5 1.5 low 29.6
30.5 29.5 Remote Fault
Detected 1.4 Remote Fault Rising 1.4 1.4 low 29.5
30.4 29.4 Link Down 1.2 Link Status Falling 1.2 1.2 high 29.4
30.3 29.3 Auto-Negotiation
LP Acknowledge 5.14 Acknowledge Rising 5.14 5.14 low 29.3
30.2 29.2 Parallel
Detection Fault 6.4 Parallel Detection
Fault Rising 6.4 6.4 low 29.2
30.1 29.1 Auto-Negotiation
Page Received 6.1 Page Received Rising 6.1 6.1 low 29.1
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3.7 Configuration Straps
Configuration straps allow various fea tures of the device to be automati cally configured to user defin ed
values. Configuration straps are latched upon Power-On Reset (POR) and pin reset (nRST).
Configuration straps include internal resistors in order to prevent the signal from floating when
unconnected. If a particular configuration strap is connected to a load, an external pull-up o r pull-down
resistor should be used to augment the internal resistor to ensure that it reaches the required voltage
level prior to latching. The internal resistor can also be overridden by the addition of an external
resistor.
Note: The system designer must guarantee that configuration strap pins meet the timing
requirements specified in Section 5.5.3, "Power-On nRST & Configuration Strap Timing," on
page 72. If configuration strap pins are not at the correct voltage level prior to being latched,
the device may capture incorrect strap values.
Note: When externally pulling configuration straps high, the strap should be tied to VDDIO, except
for REGOFF and nINTSEL which should be tied to VDD2A.
3.7.1 PHYAD[2:0]: PHY Address Configuration
The PHYAD[2:0] configuration straps are driven high or low to give each PHY a unique address. This
address is latched into an internal register at the end of a hardware reset (default = 000b). In a multi-
transceiver application (such as a repeater), the controller is able to manage each transceiver via the
unique address. Each transceiver checks each management data frame for a matching address in the
relevant bits. When a match i s recognized, the transceiver resp onds to that particular frame. The PHY
address is also used to seed the scrambler. In a multi-transceiver application, this ensures that the
scramblers are out of synchronization and disperses the electromagnetic radiation across the
frequency spectrum.
The device’s SMI address may be configured using hardware configuration to any value between 0
and 7. The user can configure the PHY address using Software Configuration if an address greater
than 7 is required. The PHY address can be written (after SMI communication at some address is
established) using the PHYAD bits of the Special Mod es Register. The PHYAD[2:0] configuration straps
are multiplexed with other signals as shown in Table 3.5.
3.7.2 MODE[2:0]: Mode Configuration
The MODE[2:0] configuration straps control the configuration of the 10/100 digital block. When the
nRST pin is deasserted, the register bit values are loaded according to the MODE[2:0] configuration
straps. The 10/100 digital block is then configured by th e register bit values. When a soft reset occurs
via the Soft Reset bit of the Basic Control Register, the configuration of the 10/100 digital block is
controlled by the register bit values and the MODE[2:0] configuration straps have no affect.
The device’s mode may be configured using the hardware configuration straps as summarized in
Table 3.6. The user may configure the transceiver mode by writing the SMI registers.
Table 3.5 Pin Names for Address Bits
ADDRESS BIT PIN NAME
PHYAD[0] RXER/RXD4/PHYAD0
PHYAD[1] RXCLK/PHYAD1
PHYAD[2] RXD3/PHYAD2
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The MODE[2:0] hardware configuration pins are multiplexed with other signals as shown in Table 3.7.
3.7.3 RMIISEL: MII/RMII Mode Configuration
MII or RMII mode selection is latched on the rising edge of the internal reset (nRST) based on the
strapping of the RMIISEL configuration strap. The default mode is MII (via the internal pull-down
resistor). To select RMII mode, pull the RMIISEL configuration strap high with an external resistor to
VDDIO.
When the nRST pin is deasserted, th e MIIMODE bit of the Spe cial Modes Register is loaded accordi ng
to the RMIISEL configuration strap. The mode is reflected in the MIIMODE bit of the Special Modes
Register.
Refer to Section 3.4, "MAC Interface," on page 30 for additional information on MII and RMII modes.
Table 3.6 MODE[2:0] Bus
MODE[2:0] MODE DEFINITIONS
DEFAULT REGISTER BIT VALUES
REGISTER 0 REGISTER 4
[13,12,10,8] [8,7,6,5]
000 10Base-T Half Duplex. Auto-negotiation disabled. 0000 N/A
001 10Base-T Full Duplex. Auto-negotiation disabled. 0001 N/A
010 100Base-TX Half Duplex. Auto-negotiation
disabled.
CRS is active during Transmit & Receive.
1000 N/A
011 100Base-TX Full Duplex. Auto-ne gotiation disabled.
CRS is active during Receive. 1001 N/A
100 100Base-TX Half Duplex is advertised. Auto-
negotiation enabled.
CRS is active during Transmit & Receive.
1100 0100
101 Repeater mode. Auto-negotiation enabled.
100Base-TX Half Duplex is advertised.
CRS is active during Receive.
1100 0100
110 Power Down mode. In this mode the transceiver will
wake-up in Power-Down mode. The transceiver
cannot be used when the MODE[2:0] bits are set to
this mode. To exit this mode, the MODE bits in
Register 18.7:5(see Section 4.2.9, "Special Modes
Register," on page 60) must be configured to some
other value and a soft reset must be issued.
N/A N/A
111 All capable. Auto-negotiation enabled. X10X 1111
Table 3.7 Pin Names for Mode Bits
MODE BIT PIN NAME
MODE[0] RXD0/MODE0
MODE[1] RXD1/MODE1
MODE[2] COL/CRS_DV/MODE2
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3.7.4 REGOFF: Internal +1.2V Regulator Configuration
The incorporation of flexPWR technology provides the ability to disable the internal +1.2V regulator.
When the regulator is disabled, an external +1.2V must be supplied to the VDDCR pin. Disabling the
internal +1.2V regulator makes it possible to reduce total system power, since an external switching
regulator with greater efficiency (versus the internal linear regulator) can be used to provide +1.2V to
the transceiver circuitry.
Note: Because the REGOFF configuration strap shares functionality with the LED1 pin, proper
consideration must also be given to the LED polarity. Refer to Section 3.8.1.1, "REGOFF and
LED1 Polarity Selection," on page 39 for additional information on the relation between
REGOFF and the LED1 polarity.
3.7.4.1 Disabling the Internal +1.2V Regulator
To disable the +1.2V internal regulator, a pull-up strapping resistor should be connected from the
REGOFF configuration strap to VDD2A. At power-on, after both VDDIO and VDD2A are within
specification, the transceiver will sample REGOFF to determine whether the internal regulator should
turn on. If the pin is sampled at a voltage greater than VIH, then the internal regulator is disabled and
the system must supply +1.2V to the VDDCR pin. The VDDIO voltage must be at least 80% of the
operating voltage level (1.44V when operating at 1.8V, 2.0V when operating at 2.5V, 2.64V when
operating at 3.3V) before voltage is applied to VDDCR. As described in Section 3.7.4.2, when
REGOFF is left floating or connected to VSS, the internal regulator is enabled and the system is not
required to supply +1.2V to the VDDCR pin.
3.7.4.2 Enabling the Internal +1.2V Regulator
The +1.2V for VDD CR is supplied by the on-chip regulator unless th e transceiver is configured for the
regulator off mode using the REGOFF configuration strap as described in Section 3.7.4.1. By default,
the internal +1.2V regulator is enabled when REGOFF is floating (due to the internal pull-down
resistor). During power-on, if REGOFF is sampled below VIL, then the internal +1.2V regul ator will turn
on and operate with power from the VDD2A pin.
3.7.5 nINTSEL: nINT/TXER/TXD4 Configuration
The nINT, TXER, and TXD4 functions share a common pin. There are two functional modes for this
pin, the TXER/TXD4 mode and nINT (interrupt) mode. The nINTSEL configuration strap is latched at
POR and on the rising edge of the nRST. By default, nINTSEL is configured for nINT mode via the
internal pull-up resistor.
Note: Because the nINTSEL configuration strap shares functionality with the LED2 pin, proper
consideration must also be given to the LED polarity. Refer to Section 3.8.1.2, "nINTSEL and
LED2 Polarity Selection," on page 39 for additional information on the relation between
nINTSEL and the LED2 polarity.
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3.8 Miscellaneous Functions
3.8.1 LEDs
Two LED signals are provided as a convenient means to determine the transceiver's mode of
operation. All LED signals are either active high or active low as described in Section 3.8.1.2,
"nINTSEL and LED2 Polarity Selection" and Section 3.8.1.1, "REGOFF and LED1 Polarity Selection,"
on page 39.
The LED1 output is driven active whenever the device detects a valid link, and blinks when CRS is
active (high) indicating activity.
The LED2 output is driven active when the operating speed is 100Mbps. This LED will go inactive
when the operating speed is 10Mbps or during line isolation.
Note: When pulling the LED1 and LED2 pins high, they must be tied to VDD2A, NOT VDDIO.
3.8.1.1 REGOFF and LED1 Polarity Selection
The REGOFF configuration strap is shared with the LED1 pin. The LED1 output will automatically
change polarity based on the presence of an external pull-up resistor. If the LED1 pin is pul led high to
VDD2A by an external pull-up resistor to select a logical high for REGOFF, then the LED1 output will
be active low. If the LED1 pin is pulled low by the internal pull-down resistor to select a logical low for
REGOFF, the LED1 output will then be an active high output. Figure 3.7 details the LED1 polarity for
each REGOFF configuration.
Note: Refer to Section 3.7.4, "REGOFF: Internal +1.2V Regulator Configuration," on page 38 for
additional information on the REGOFF configuration strap.
3.8.1.2 nINTSEL and LED2 Polarity Selection
The nINTSEL configuration strap is shared with the LED2 pin. The LED2 output will automatically
change polarity b ased on the presence of an external pull-down resistor. If the LED2 pin is pulled high
to VDD2A to select a logical high for nINTSEL, then the LED2 output will be active low. If the LED2
Figure 3.7 LED1/REGOFF Polarity Configuration
LED1/REGOFF
~270 ohms
REGOFF = 0 (Regulator ON)
LED output = Active High
~270 ohms
VDD2A
REGOFF = 1 (Regulator O FF)
LED output = Active Low
LED1/REGOFF
10K
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pin is pulled low by an externa l pull-down resistor to select a logica l low for nINTSEL , the LED2 output
will then be an active high output. Figure 3.8 details the LED2 polarity for each nINTSEL confi guration.
Note: Refer to Section 3.7.5, "nINTSEL: nINT/TXER/TXD4 Configuration," on page 38 for additional
information on the nINTSEL configuration strap.
3.8.2 Variable Voltage I/O
The device’s digital I/O pins are variable voltage, allowing them to take advantage of low power savi ngs
from shrinking technologies. These pins can operate from a low I/O voltage of +1.62V up to +3.6V.
The applied I/O voltage must maintain its value with a tolerance of ± 10%. Varying the voltage up or
down after the transceiver has completed power-on reset can cau se errors in the tra nsceiver operation.
Refer to Chapter 5, "Operational Characteristics," on page 66 for additional information.
Note: Input signals must not be driven high before power is applied to the device.
3.8.3 Power-Down Modes
There are two device power-down modes: General Power-Down Mode and Energy Detect Power-
Down Mode. These modes are described in the following subsections.
3.8.3.1 General Power-Down
This power-down mode is controlled via the Power Down bit of the Basic Control Register. In this
mode, the entire transceiver (except the management interface) is powered-down and remains in this
mode as long as the Power Down bit is “1”. When the Power Down bit is cleared, the transceiver
powers up and is automatically reset.
3.8.3.2 Energy Detect Power-Down
This power-down mode is activated by setting the EDPWRDOWN bit of the Mode Control/Status
Register. In this mode, when no energy is present on the line the transceiver is powered down (except
for the management interface, the SQUELCH circuit, and the ENERGYON logic). The ENERGYON
logic is used to de tect the presence of valid ene rgy from 100BASE-TX, 10BASE-T, or Auto-negotiation
signals.
In this mode, when the ENERGYON bit of the Mode Control/Status Register is low, the transceiver is
powered-down and nothing is transmitted. When energy is received via link pulses or packets, the
ENERGYON bit goes high and the transceiver powers-up. The device automatically resets into the
Figure 3.8 LED2/nINTSEL Polarity Configuration
~270 ohms
nINTSEL = 0
LED output = Active High
10K
~270 ohms
VDD2A
nINTSEL = 1
LED output = Active Low
LED2/nINTSEL
LED2/nINTSEL
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state prior to power-down and asserts the nINT interrupt if the ENERGYON interrupt is enabled in the
Interrupt Mask Register. The first and possibly the second packet to activate ENERGYON may be lost.
When the EDPWRDOWN bit of the Mode Control/Status Register is low, energ y detect power-down is
disabled.
3.8.4 Isolate Mode
The device data paths may be electrically isolated from the MII/RMII interface by setting the Isolate bit
of the Basic Control Register to “1”. In isolation mode, the transceiver does not respond to the TXD,
TXEN and TXER inputs, but does respond to management transactions.
Isolation provides a means for multiple transceivers to be connected to the same MII/RMII interface
without contention. By default, the transceiver is not isolated (on power-up (Isolate=0).
3.8.5 Resets
The device provides two forms of reset: Hardware and Software. The device registers are reset by
both Hardware and Software resets. Select register bits, indicated as “NASR” in the register defi nitions,
are not cleared by a Software reset. The registers are not reset by the power-down modes described
in Section 3.8.3.
Note: For the first 16us after coming out of reset, the MII/RMII i nterface will run at 2.5 MHz. After this
time, it will switch to 25 MHz if auto-negotiation is enabled.
3.8.5.1 Hardware Reset
A Hardware reset is asserted by driving the nRST input pin low. When driven, nRST should be held
low for the minimum time detailed in Section 5.5.3, "Power-On nRST & Configuration Strap Timing,"
on page 72 to ensure a proper transceiver reset. During a Hardware reset, an external clock must be
supplied to the XTAL1/CLKIN signal.
Note: A hardware reset (nRST assertion) is required following power-up. Refer to Section 5.5.3,
"Power-On nRST & Configuration Strap Timing," on page 72 for additional information.
3.8.5.2 Software Reset
A Software reset is activated by setting the Soft Reset bit of the Basic Control Register to “1”. All
registers bits, except those indicated as “NASR” in the register definitions, are cleared by a Software
reset. The Soft Reset bit is self-clearing. Per the IEEE 802.3u standard, clause 22 (22.2.4.1.1) the reset
process will be completed within 0.5s from the setting of this bit.
3.8.6 Carrier Sense
The carrier sense (CRS) is output on the CRS pin in MII mode, and the CRS_DV pin in RMII mode.
CRS is a signal defined b y the MII specification in the IEEE 8 02.3u standard. The device asserts CRS
based only on receive activity whenever the transceiv er is either in repeater mode or fu ll-duplex mode.
Otherwise the transceiver asserts CRS based on either transmit or receive activity.
The carrier sense logic uses the encoded, unscrambled data to determine carrier activity status. It
activates carrier sense with the detection of 2 non-contiguous zeros within any 10 bit span. Carrier
sense terminates if a span of 10 consecutive ones is detected before a /J/K/ Start-of Stream Delimiter
pair. If an SSD pair is detected, carrier sense is asserted until either /T/R/ End–of-Stream Delimiter
pair or a pair of IDLE symbols is detected. Carrier is negated after the /T/ symbol or the first IDLE. If
/T/ is not followed by /R/, then carrier is maintained. Carrier is treated similarly for IDLE followed by
some non-IDLE symbol.
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3.8.7 Collision Detect
A collision is the occurrence of simultaneous transmit and receive operations. The COL output is
asserted to indicate that a collision has been detected. COL remains active for the duration of the
collision. COL is changed asynchronously to both RXCLK and TXCLK. The COL output becomes
inactive during full duplex mode.
The COL may be tested by setting the Collision Test bit of the Basic Control Register to “1”. This
enables the collision test. COL will be asserted within 512 bit times of TXEN rising and will be de-
asserted within 4 bit times of TXEN falling.
3.8.8 Link Integrity Test
The device performs the link integrity test as outlined in the IEEE 802.3u (Clause 24-15) Link Monitor
state diagram. The link status is multiplexed with the 10Mbps link status to form the Link Status bit in
the Basic Status Register and to drive the LINK LED (LED1).
The DSP indicates a valid MLT-3 waveform present on the RXP and RXN signals as defined by the
ANSI X3.263 TP-PMD standard, to the Link Monitor state-machine, using the internal DATA_VALID
signal. When DATA_VALID is asserted, the control logic moves into a Link-Ready state and waits for
an enable from the auto-negotiation block. When received, the Link-Up state is entered, and the
Transmit and Receive logic blocks become active. Should auto-negotiation be disabled, the link
integrity logic moves immediately to the Link-Up state when the DATA_VALID is asserted.
To allow the line to stabilize, the link integrity logic will wait a minimum of 330 μsec from the time
DATA_VALID is asserted until the Link-Ready state is entered. Should the DATA_VALID input be
negated at any time, this logic will immediately negate the Link signal and enter the Link-Down state.
When the 10/100 digital block is in 10BASE-T mode, the link status is derived from the 10BASE-T
receiver logic.
3.8.9 Loopback Operation
The device may be configured for near-end loopback and far loopback. These loopback modes are
detailed in the following subsections.
3.8.9.1 Near-end Loopback
Near-end loopback mode sends the digital transmit data back out the receive data signals for testing
purposes, as indicated by the blue arrows in Figure 3.9. The near-end loopback mode is enabled by
setting the Loopback bit of the Basic Control Register to “1”. A large percentage of the digital circuitry
is operational in near-end loopback mode because data is routed through the PCS and PMA layers
into the PMD sublayer before it is looped back. The COL signal will be inactive in this mode, unless
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Collision Test is enabled in the Basic Control Register. The transmi tters are powered down regardless
of the state of TXEN.
3.8.9.2 Far Loopback
Far loopback is a special test mode for MDI (analog) loopback as indicated by the blue arrows in
Figure 3.11. The far loopback mode is enabled by setting the FARLOOPBACK bit of the Mode
Control/Status Register to “1”. In this mode, data that is received from the link partner on the MDI is
looped back out to the link partner. The dig ital interf ace signals on the lo cal MAC interface are isolated.
Note: This special test mode is only available when operating in RMII mode.
3.8.9.3 Connector Loopback
The device maintains reliable transmission over very short cables, and can be tested in a connector
loopback as shown in Figure 3.11. An RJ45 loopback cable can be used to route the transmit signals
Figure 3.9 Near-end Loopback Block Diagram
Figure 3.10 Far Loopback Block Diagram
SMSC
Ethernet Transceiver
10/100
Ethernet
MAC
CAT-5
XFMR
Digital
RXD
TXD
Analog
RX
TX
X
X
Far-end system
SMSC
Ethernet Transceiver
10/100
Ethernet
MAC
CAT-5
XFMR
Digital
RXD
TXD
Analog
RX
TX Link
Partner
X
X
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an the output of the transformer back to the receiver inputs, and this loo pback will work at both 10 and
100.
3.9 Application Diagrams
This section provides typical application diagrams for the following:
Simplified System Level Application Diagram
Power Supply Diagram (1.2V Supplied by Internal Regulator)
Power Supply Diagram (1.2V Supplied by External Source)
Twisted-Pair Interface Diagram (Single Power Supply)
Twisted-Pair Interface Diagram (Dual Power Supplies)
Figure 3.11 Connector Loopback Block Diagram
SMSC
Ethernet Transceiv er
10/100
Ethernet
MAC XFMR
Digital
RXD
TXD
Analog
RX
TX 1
2
3
4
5
6
7
8
RJ45 Loopback Cable .
Created by connecting pin 1 to pin 3
and connectin g pin 2 to pin 6.
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3.9.1 Simplified System Level Application Diagram
Figure 3.12 Simplified System Level Application Diagram
LAN8710A/LAN8710Ai
10/100 PHY
32-QFN
MII
TXP
TXN
Mag RJ45
RXP
RXN
25MHz
XTAL1/CLKIN
XTAL2
TXD[3:0]
4
RXD[3:0]
RXCLK
RXDV
4
MII
LED[2:1]
2
Interface
MDIO
MDC
nINT
nRST
TXCLK
TXER
TXEN
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3.9.2 Power Supply Diagram (1.2V Supplied by Internal Regulator)
Figure 3.13 Power Supply Diagram (1.2V Supplied by Internal Regulator)
LAN8710A/LAN8710Ai
32-QFN
RBIAS
VSS 12.1k
VDD2A
CBYPASS
CBYPASS
VDD1A
VDDIO
CBYPASS
CF
VDDDIO
Supply
1.8 - 3.3V
Power
Supply
3.3V
VDDCR
LED1/
REGOFF
~270 Ohm
Core Logic
Internal
Regulator
Ch.2 3.3V
Circuitry
INOUT
Ch.1 3.3V
Circuitry
470 pF
1 uF
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3.9.3 Power Supply Diagram (1.2V Supplied by External Source)
Figure 3.14 Power Supply Diagram (1.2V Supplied by External Source)
LAN8710A/LAN8710Ai
32-QFN
RBIAS
VSS 12.1k
VDD2A
CBYPASS
CBYPASS
VDD1A
VDDIO
CBYPASS
CF
VDDDIO
Supply
1.8 - 3.3V
Power
Supply
3.3V
VDDCR
LED1/
REGOFF
Core Logic
Intern al
Regulator
(Disabled)
Ch.2 3.3V
Circuitry
INOUT
Ch.1 3.3V
Circuitry
VDDCR
Supply
1.2V
~270 Ohm
10k
470 pF
1 uF
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3.9.4 Twisted-Pair Interface Diagram (Single Power Supply)
Figure 3.15 Twisted-Pair Interface Diagram (Single Power Supply)
Magnetics
LAN8710A/LAN8710Ai
32-QFN
VDD2A CBYPASS
TXP
TXN
Power
Supply
3.3V
1
2
3
4
5
6
7
8
1000 pF
3 kV
RJ45
75
75
RXP
RXN
CBYPASS
VDD1A CBYPASS
49.9 Ohm Resistors
Ferrite
bead
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3.9.5 Twisted-Pair Interface Diagram (Dual Power Supplies)
Figure 3.16 Twisted-Pair Interface Diagram (Dual Power Supplies)
Magnetics
LAN8710A/LAN8710Ai
32-QFN
VDD2A CBYPASS
TXP
TXN
Power
Supply
3.3V
1
2
3
4
5
6
7
8
1000 pF
3 kV
RJ45
75
75
RXP
RXN
CBYPASS
VDD1A CBYPASS
49.9 Ohm Resistors Power
Supply
2.5V - 3.3V
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Chapter 4 Register Descriptions
This chapter describes the various control and status registers (CSR’s). All registers follow the IEEE
802.3 (clause 22.2.4) management register set. All functionality and bit definitions comply with these
standards. The IEEE 802.3 specified register index (in decimal) is included with each register definition,
allowing for addressing of these registers via the Serial Management Interface (SMI) protocol.
4.1 Register Nomenclature
Table 4.1 describes the register bit attribute notation used throughout this document.
Many of these register bit notations can be combined. Some examples of this are shown below:
R/W: Can be written. Will return current setting on a read.
R/WAC: Will return current setting on a read. Writing anything clears the bit.
Table 4.1 Register Bit Types
REGISTER BIT TYPE
NOTATION REGISTER BIT DESCRIPTION
RRead: A register or bit with this attribute can be read.
WRead: A register or bit with this attribute can be written.
RO Read only: Read only. Writes have no effect.
WO Write only: If a register or bit is write-only, reads will return unspecified data.
WC Write One to Clear: writing a one clears the value. Writing a zero has no effect
WAC Write Anything to Clear: writing anything clears the value.
RC Read to Clear: Contents is cleared after the read. Writes have no effect.
LL Latch Low: Clear on read of register.
LH Latch High: Clear on read of register.
SC Self-Clearing: Contents are self-cleared after the being set. Writes of zero have no
effect. Contents can be read.
SS Self-Setting: Contents are self-setting after being cleared. Writes of one have no
effect. Contents can be read.
RO/LH Read Only, Latch High: Bits with this attribute will stay hi gh until the bit is read. After
it is read, the bit will eit her remain high if the high condition remains, or will go low if
the high conditio n has been removed. If the bit has n ot been read, the bit will remain
high regardless of a change to the high condition. This mode is used in some Ethernet
PHY registers.
NASR Not Affected by Software Reset. The state of NASR bits do not change on assertion
of a software reset.
RESERVED Reserved Field: Reserved fields must be written with zeros to ensure future
compatibility. The value of reserved bits is not guaranteed on a read.
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4.2 Control and Status Registers
Table 4.2 provides a list of supported registers. Register details, including bit definitions, are provided
in the proceeding subsections.
Table 4.2 SMI Registe r Map
REGISTER INDEX
(DECIMAL) REGISTER NAME GROUP
0 Basic Control Register Basic
1 Basic Status Register Basic
2 PHY Identifier 1 Extended
3 PHY Identifier 2 Extended
4 Auto-Negotiation Advertisement Register Extended
5 Auto-Negotiation Link Partner Ability Register Extended
6 Auto-Negotiation Expansion Register Extended
17 Mode Control/Status Register Vendor-specific
18 Special Modes Vendor-specific
26 Symbol Error Counter Register Vendor-specific
27 Control / Status Indication Register Vendor-specific
29 Interrupt Source Register Vendor-specific
30 Interrupt Mask Register Vendor-specific
31 PHY Special Control/Status Register Vendor-specific
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4.2.1 Basic Control Register
Note 4.1 The default value of this bit is determined by the MODE[2:0] configuration straps. Refer to
Section 3.7.2, "MODE[2:0]: Mode Configuration," on page 36 for additional information.
Index (In Decimal): 0 Size: 16 bits
BITS DESCRIPTION TYPE DEFAULT
15 Soft Reset
1 = software reset. Bit i s self-clearing. When setting this bit do not set other
bits in this register. The configuration (as described in Section 3.7.2,
"MODE[2:0]: Mode Configuration," on page 36) is set from the register bit
values, and not from the mode pins.
R/W
SC 0b
14 Loopback
0 = normal operation
1 = loopback mode
R/W 0b
13 Speed Select
0 = 10Mbps
1 = 100Mbps
Note: Ignored if Auto-negotiation is enabled (0.12 = 1).
R/W Note 4.1
12 Auto-Negotiation Enable
0 = disable auto-negotiate process
1 = enable auto-negotiate process (overrides 0.13 and 0.8)
R/W Note 4.1
11 Power Down
0 = normal operation
1 = General power down mode
Note: The Auto-Negotiation Enable must be cleared before setting the
Power Down.
R/W 0b
10 Isolate
0 = normal operation
1 = electrical isolation of PHY from the MII/RMII
R/W 0b
9Restart Auto-Negotiate
0 = normal operation
1 = restart auto-negotiate process
Note: Bit is self-clearing.
R/W
SC 0b
8Duplex Mode
0 = half duplex
1 = full duplex
Note: Ignored if Auto-Negotiation is enabled (0.12 = 1).
R/W Note 4.1
7Collision Test
0 = disable COL test
1 = enable COL test
R/W 0b
6:0 RESERVED RO -
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4.2.2 Basic Status Register
Index (In Decimal): 1 Size: 16 bits
BITS DESCRIPTION TYPE DEFAULT
15 100BASE-T4
0 = no T4 ability
1 = T4 able
RO 0b
14 100BASE-TX Full Duplex
0 = no TX full duplex ability
1 = TX with full duplex
RO 1b
13 100BASE-TX Half Duplex
0 = no TX half duplex ability
1 = TX with half duplex
RO 1b
12 10BASE-T Full Duplex
0 = no 10Mbps with full duplex ability
1 = 10Mbps with full duplex
RO 1b
11 10BASE-T Half Duplex
0 = no 10Mbps with half duplex ability
1 = 10Mbps with half duplex
RO 1b
10 100BASE-T2 Full Duplex
0 = PHY not able to perform full duplex 100BASE-T2
1 = PHY able to perform full duplex 100BASE-T2
RO 0b
9100BASE-T2 Half Duplex
0 = PHY not able to perform half duplex 100BASE-T2
1 = PHY able to perform half duplex 100BASE-T2
RO 0b
8Extended Status
0 = no extended status information in register 15
1 = extended status information in register 15
RO 0b
7:6 RESERVED RO -
5Auto-Negotiate Complete
0 = auto-negotiate process not completed
1 = auto-negotiate process completed
RO 0b
4Remote Fault
1 = remote fault condition detected
0 = no remote fault
RO/LH 0b
3Auto-Negotiate Ability
0 = unable to perform auto-negotiation function
1 = able to perform auto-negotiation function
RO 1b
2Link Status
0 = link is down
1 = link is up
RO/LL 0b
1Jabber Detect
0 = no jabber condition detected
1 = jabber condition detected
RO/LH 0b
0Extended Capabilities
0 = does not support extended capabilities registers
1 = supports extended capabilities registers
RO 1b
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4.2.3 PHY Identifier 1 Register
Index (In Decimal): 2 Size: 16 bits
BITS DESCRIPTION TYPE DEFAULT
15:0 PHY ID Number
Assigned to the 3rd through 18th bits of the Organizationally Unique
Identifier (OUI), respectively.
R/W 0007h
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4.2.4 PHY Identifier 2 Register
Note 4.2 The default value of this field will vary dependant on the silicon revision number.
Index (In Decimal): 3 Size: 16 bits
BITS DESCRIPTION TYPE DEFAULT
15:10 PHY ID Number
Assigned to the 19th through 24th bits of the OUI. R/W 110000b
9:4 Model Number
Six-bit manufacturer’s model number. R/W 001111b
3:0 Revision Number
Four-bit manufacturer ’s revision number. R/W Note 4.2
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4.2.5 Auto Negotiation Advertisement Register
Note 4.3 The default value of this bit is determined by the MODE[2:0] configuration straps. Refer to
Section 3.7.2, "MODE[2:0]: Mode Configuration," on page 36 for additional information.
Index (In Decimal): 4 Size: 16 bits
BITS DESCRIPTION TYPE DEFAULT
15:14 RESERVED RO -
13 Remote Fault
0 = no remote fault
1 = remote fault detected
R/W 0b
12 RESERVED RO -
11:10 Pause Operation
00 = No PAUSE
01 = Symmetric PAUSE
10 = Asymmetric PAUSE toward link partner
11 = Advert ise support for both Symmetric PAUSE and Asymmetric PAUSE
toward local device
Note: When both Symmetric PAUSE and Asymmetric PAUSE are set, the
device will only be configured to, at most, one of the two settings
upon auto-negotiation completion.
R/W 00b
9RESERVED RO -
8100BASE-TX Full Duplex
0 = no TX full duplex ability
1 = TX with full duplex
R/W Note 4.3
7100BASE-TX
0 = no TX ability
1 = TX able
R/W 1b
610BASE-T Full Duplex
0 = no 10Mbps with full duplex ability
1 = 10Mbps with full duplex
R/W Note 4.3
510BASE-T
0 = no 10Mbps ability
1 = 10Mbps able
R/W Note 4.3
4:0 Selector Field
00001 = IEEE 802.3 R/W 00001b
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4.2.6 Auto Negotiation Link Partner Ability Register
Index (In Decimal): 5 Size: 16 bits
BITS DESCRIPTION TYPE DEFAULT
15 Next Page
0 = no next page ability
1 = next page capable
Note: This device does not support next page ability.
RO 0b
14 Acknowledge
0 = link code word not yet received
1 = link code word received from partner
RO 0b
13 Remote Fault
0 = no remote fault
1 = remote fault detected
RO 0b
12:11 RESERVED RO -
10 Pause Operation
0 = No PAUSE supported by partner station
1 = PAUSE supported by partner station
RO 0b
9100BASE-T4
0 = no T4 ability
1 = T4 able
Note: This device does not support T4 ability.
RO 0b
8100BASE-TX Full Duplex
0 = no TX full duplex ability
1 = TX with full duplex
RO 0b
7100BASE-TX
0 = no TX ability
1 = TX able
RO 0b
610BASE-T Full Duplex
0 = no 10Mbps with full duplex ability
1 = 10Mbps with full duplex
RO 0b
510BASE-T
0 = no 10Mbps ability
1 = 10Mbps able
RO 0b
4:0 Selector Field
00001 = IEEE 802.3 RO 00001b
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4.2.7 Auto Negotiation Expansion Register
Index (In Decimal): 6 Size: 16 bits
BITS DESCRIPTION TYPE DEFAULT
15:5 RESER VED RO -
4Parallel Detection Fault
0 = no fault detected by parallel detection logic
1 = fault detected by parallel detection logic
RO/LH 0b
3Link Partner Next Page Able
0 = link partner does not have next page ability
1 = link partner has next page ability
RO 0b
2Next Page Able
0 = local device does not have next page ability
1 = local device has next page ability
RO 0b
1Page Received
0 = new page not yet received
1 = new page received
RO/LH 0b
0Link Partner Auto-Negotiation Able
0 = link partner does not have auto-negotiation ability
1 = link partner has auto-negotiation ability
RO 0b
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4.2.8 Mode Control/Status Register
Index (In Decimal): 17 Size: 16 bits
BITS DESCRIPTION TYPE DEFAULT
15:14 RESERVED RO -
13 EDPWRDOWN
Enable the Energy Detect Power-Down mode:
0 = Energy Detect Power-Down is disabled
1 = Energy Detect Power-Down is enabled
R/W 0b
12:10 RESERVED RO -
9FARLOOPBACK
Enables far loopback mode (i.e., all the received packets are sent back
simultaneously (in 100BASE-TX only)). This bit is only active in RMII mode.
This mode works even if the Isolate bit (0.10) is set.
0 = Far loopback mode is disabled
1 = Far loopback mode is enabled
Refer to Section 3.8.9.2, "Far Loopback," on page 43 for additional
information.
R/W 0b
8:7 RESERVED RO -
6ALTINT
Alternate Interrupt Mode:
0 = Primary interrupt system enabled (Default)
1 = Alternate interrupt system enabled
Refer to Section 3.6, "Interrupt Management," on page 34 for additional
information.
R/W 0b
5:2 RESERVED RO -
1ENERGYON
Indicates whether energy is detected. This bit transitions to “0” if no valid
energy is detected within 256ms. It is reset to “1” by a hardware reset and
is unaffected by a software reset. Refer to Section 3.8.3.2, "Energy Detect
Power-Down," on page 40 for additional information.
RO 1b
0RESERVED R/W 0b
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4.2.9 Special Modes Register
Note 4.4 The default value of this field is determined by the RMIISEL configuration strap. Refer to
Section 3.7.3, "RMIISEL: MII/RMII Mode Configuration," on page 37 for additional
information.
Note 4.5 The default value of this field is determined by the MODE[2:0] configuration straps. Refer
to Section 3.7.2, "MODE[2:0]: Mode Configuration," on page 36 for additional information.
Note 4.6 The default valu e of this field is determined by the PHYAD[2:0] confi guration straps. Refer
to Section 3.7.1, "PHYAD[2:0]: PHY Address Configuration," on page 36 for additional
information.
Index (In Decimal): 18 Size: 16 bits
BITS DESCRIPTION TYPE DEFAULT
15 RESERVED RO -
14 MIIMODE
Reflects the mode of the digital interface:
0 = MII Mode
1 = RMII Mode
Note: When writing to this register, the default value of this bit must
always be written back.
R/W
NASR Note 4.4
13:8 RESERVED RO -
7:5 MODE
Transceiver mode of operation. Refer to Section 3.7.2, "MODE[2:0]: Mode
Configuration," on page 36 for additional details.
R/W
NASR Note 4.5
4:0 PHYAD
PHY Address. The PHY Address is used for the SMI address and for
initialization of the Cipher (Scrambler) key. Refer to Section 3.7.1,
"PHYAD[2: 0]: PHY Address Configuration," on page 36 for additional details.
R/W
NASR Note 4.6
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4.2.10 Symbol Error Counter Register
Index (In Decimal): 26 Size: 16 bits
BITS DESCRIPTION TYPE DEFAULT
15:0 SYM_ERR_CNT
The symbol error counter increments whenever an invalid code symbol is
received (including IDLE symbols) in 100BASE-TX mode. The counter is
incremented only once per packet, even when the received packet contains
more than one symbol error. This counter incremen ts up to 65,536 (216) and
rolls over to 0 after reaching the maximum value.
Note: This register is cleared on reset, but is not cleared by reading the
register. This register does not increment in 10BASE-T mode.
RO 0000h
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4.2.11 Special Control/Status Indications Register
Index (In Decimal): 27 Size: 16 bits
BITS DESCRIPTION TYPE DEFAULT
15 AMDIXCTRL
HP Auto-MDIX control:
0 = Enable Auto-MDIX
1 = Disable Auto-MDIX (use 27.13 to control channel)
R/W 0b
14 RESERVED RO -
13 CH_SELECT
Manual channel select:
0 = MDI (TX transmits, RX receives)
1 = MDIX (TX receives, RX transmits)
R/W 0b
12 RESERVED RO -
11 SQEOFF
Disable the SQE test (Heartbeat):
0 = SQE test is enabled
1 = SQE test is disabled
R/W
NASR 0b
10:5 RESERVED RO -
4XPOL
Polarity state of the 10BASE-T:
0 = Normal polarity
1 = Reversed polarity
RO 0b
3:0 RESERVED RO -
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4.2.12 Interrupt Source Flag Register
Index (In Decimal): 29 Size: 16 bits
BITS DESCRIPTION TYPE DEFAULT
15:8 RESERVED RO -
7INT7
0 = not source of interrupt
1 = ENERGYON generated
RO/LH 0b
6INT6
0 = not source of interrupt
1 = Auto-Negotiation complete
RO/LH 0b
5INT5
0 = not source of interrupt
1 = Remote Fault Detected
RO/LH 0b
4INT4
0 = not source of interrupt
1 = Link Down (link status negated)
RO/LH 0b
3INT3
0 = not source of interrupt
1 = Auto-Negotiation LP Acknowledge
RO/LH 0b
2INT2
0 = not source of interrupt
1 = Parallel Detection Fault
RO/LH 0b
1INT1
0 = not source of interrupt
1 = Auto-Negotiation Page Received
RO/LH 0b
0RESERVED RO 0b
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4.2.13 Interrupt Mask Register
Index (In Decimal): 30 Size: 16 bits
BITS DESCRIPTION TYPE DEFAULT
15:8 RESERVED RO -
7:1 Mask Bits
0 = interrupt source is masked
1 = interrupt source is enabled
Note: Refer to Section 4.2.12, "Interrupt Source Flag Register," on
page 63 for details on the corresponding interrupt definitions.
R/W 0000000b
0RESERVED RO -
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4.2.14 PHY Special Control/Status Register
Index (In Decimal): 31 Size: 16 bits
BITS DESCRIPTION TYPE DEFAULT
15:13 RESERVED RO -
12 Autodone
Auto-negotiation done indication:
0 = Auto-negotiation is not done or disabled (or not active)
1 = Auto-negotiation is done
RO 0b
11:7 RESERVED R/W -
6Enable 4B5B
0 = bypass encoder/decoder
1 = enable 4B5B encoding/decoding. MAC Interface must be configured in
MII mode.
R/W 1b
5RESERVED RO -
4:2 Speed Indication
HCDSPEED value:
001 = 10BASE-T half-duplex
101 = 10BASE-T full-duplex
010 = 100BASE-TX half-duplex
110 = 100BASE-TX full-duplex
RO XXX
1:0 RESERVED RO -
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Chapter 5 Operational Characteristics
5.1 Absolute Maximum Ratings*
Supply Voltage (VDDIO, VDD1A, VDD2A) (Note 5.1) . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +3.6V
Digital Core Supply Voltage (VDDCR) (Note 5.1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +1.5V
Ethernet Magnetics Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +3.6V
Positive voltage on signal pins, with respect to ground (Note 5.2) . . . . . . . . . . . . . . . . . . . . . . . . . .+6V
Negative voltage on signal pins, with respect to ground (Note 5.3) . . . . . . . . . . . . . . . . . . . . . . . .-0.5V
Positive voltage on XTAL1/ CLKIN, with respect to ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.6V
Positive voltage on XTAL2, with respect to ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +2.5V
Ambient Operating Temperature in Still Air (TA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Note 5.40
Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55oC to +150oC
Junction to Ambient (θJA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..48.3C/W
Junction to Case (θJC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..10.6oC/W
Lead Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Refer to JEDEC Spec. J-STD-020
HBM ESD Performance per JEDEC JESD22-A114. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Class 3A
IEC61000-4-2 Contact Discharge ESD Performance (Note 5.5) . . . . . . . . . . . . . . . . . . . . . . . . . .+/-8kV
IEC61000-4-2 Air-Gap Discharge ESD Performance (Note 5.5). . . . . . . . . . . . . . . . . . . . . . . . .+/-15kV
Latch-up Performance per EIA/JESD 78 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..+/-150mA
Note 5.1 When powering this device from laboratory or system power supplies, it is important that
the absolute maximum ratings not be exceeded or device failure can result. Some power
supplies exhibit voltage spikes on their outputs when AC power is switched on or off. In
addition, voltage transients on the AC power line may appear on the DC output. If this
possibility exists, it is suggested that a clamp circuit be used.
Note 5.2 This rating does not apply to the following pins: XTAL1/CLKIN, XTAL2, RBIAS.
Note 5.3 This rating does not apply to the following pins: RBIAS.
Note 5.4 0oC to +85oC for extended commercial version, -40oC to +85oC for industrial version.
Note 5.5 Performed by independent 3rd party test facility.
*Stresses exceeding those listed in this section could cause permanent damage to the device. This is
a stress rating only. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability. Functional operation of the device at any condition exceeding those indicated in
Section 5.2, "Operating Conditions**", Section 5.1, "Absolute Maximum Ratings*", or any other
applicable section of this specification is not implied. Note, device signals are NOT 5 volt tolerant
unless specified otherwise.
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5.2 Operating Conditions**
Supply Voltage (VDDIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+1.62V to +3.6V
Analog Port Supply Voltage (VDD1A, VDD2A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+3.0V to +3.6V
Digital Core Supply Voltage (VDDCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+1.14V to +1.26V
Ethernet Magnetics Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+2.25V to +3.6V
Ambient Operating Temperature in Still Air (TA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Note 5.4
**Proper operation of the device is guaranteed only within the ranges specified in this section. After
the device has completed power-up, VDDIO and the magnetics power supply must maintain their
voltage level with +/-10%. Varying the voltage greater than +/-10% after the device has completed
power-up can cause errors in device operation.
Note: Do not drive input signals without power supplied to the device.
5.3 Power Consumption
This section details the device power measurements taken over various operating conditions. Unless
otherwise noted, all measurements were taken with power supplies at nominal values (VDDIO, VDD1A,
VDD2A = 3.3V, VDDCR = 1.2V). See Section 3.8.3, "Power-Down Modes," on page 40 for a
description of the power down modes.
Note: The current at VDDCR is either supplied by the internal regulator from current entering at
VDD2A, or from an external 1.2V supply when the internal regulator is disabled.
Table 5.1 Device Only Current Consumption and Power Dissipation
POWER PIN GROUP
VDDA3.3
POWER
PINS(mA)
VDDCR
POWER
PIN(mA)
VDDIO
POWER
PIN(mA)
TOTAL
CURRENT
(mA)
TOTAL
POWER
(mW)
100BASE-TX /W TRAFFIC
Max 28 21 5.2 54 176
Typical 26 18 4.3 48 158
Min 23 18 2.4 43 101
Note 5.6
10BASE-T /W TRAFFIC
Max 10.2 12.9 0.98 24.1 79.5
Typical 9.4 11.4 0.4 21.2 70
Min 9.2 10.9 0.3 20.4 44
Note 5.6
ENERGY DETECT
POWER DOWN
Max 4.5 3 0.3 7.8 25
Typical 4.3 1.4 0.2 5.9 19.5
Min 3.9 1.3 0 5.2 15.9
Note 5.6
GENERAL POWER DOWN
Max 0.4 2.6 0.3 3.3 10.9
Typical 0.3 1.2 0.2 1.7 5.6
Min 0.3 1.1 0 1.4 2.4
Note 5.6
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Note: Current measurements do not include power applied to the magnetics or the optional external
LEDs. The Ethernet componen t current is typicall y 41mA in 100BASE-TX mode and 100mA in
10BASE-T mode, independent of the 2.5V or 3.3V supply rail of the transformer.
Note 5.6 Calculate d with full flexPWR fe atures activa ted: VDDIO=1.8V & inte rnal regulator disabled.
5.4 DC Specifications
Table 5.2 details the non-vari able I/O buffer characteristics. These buffer types do not support variable
voltage operation. Table 5.3 details the variable voltage I/O buffer characteristics. Typical values are
provided for 1.8V, 2.5V, and 3.3V VDDIO cases.
Note 5.7 This specification applies to all inputs and tri-stated bi-directional pins. Internal pull-down
and pull-up resistors add +/- 50uA per-pin (typical).
Note 5.8 XTAL1/CLKIN can optionally be driven from a 25MHz single-ended clock oscillator.
Table 5.2 Non-Variable I/O Buffer Character istics
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
IS Type Input Buffer
Low Input Level
High Input Level
Negative-Going Threshold
Positive-Going Threshold
Schmitt Trigger Hysteresis
(VIHT - VILT)
Input Leakage
(VIN = VSS or VDDIO)
Input Capacitance
VILI
VIHI
VILT
VIHT
VHYS
IIH
CIN
-0.3
1.01
1.39
336
-10
1.19
1.59
399
3.6
1.39
1.79
459
10
2
V
V
V
V
mV
uA
pF
Schmitt trigger
Schmitt trigger
Note 5.7
O12 Type Buffers
Low Output Level
High Output Level
VOL
VOH VDD2A - 0.4
0.4 V
V
IOL = 12mA
IOH = -12mA
ICLK Type Buffer
(XTAL1 Input)
Low Input Level
High Input Level
VILI
VIHI
-0.3
1.4
0.35
VDD2A + 0.4
V
V
Note 5.8
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Note 5.9 This specification applies to all inputs and tri-stated bi-directional pins. Internal pull-down
and pull-up resistors add +/- 50uA per-pin (typical).
Note 5.10 Measured at line side of transformer, line replaced by 100Ω (+/- 1%) resistor.
Note 5.11 Offset from 16nS pulse width at 50% of pulse peak.
Note 5.12 Measured differentially.
Table 5.3 Variable I/O Buffer Characteristics
PARAMETER SYMBOL MIN 1.8V
TYP 2.5V
TYP 3.3V
TYP MAX UNITS NOTES
VIS Type Input Buffer
Low Input Level
High Input Level
Neg-Going Threshold
Pos-Going Threshold
Schmitt Trigger
Hysteresis (VIHT - VILT)
Input Leakage
(VIN = VSS or VDDIO)
Input Capacitance
VILI
VIHI
VILT
VIHT
VHYS
IIH
CIN
-0.3
0.64
0.81
102
-10
0.83
0.99
158
1.15
1.29
136
1.41
1.65
138
3.6
1.76
1.90
288
10
2
V
V
V
V
mV
uA
pF
Schmitt trigger
Schmitt trigger
Note 5.9
VO8 Type Buffers
Low Output Level
High Output Level
VOL
VOH VDDIO - 0.4
0.4 V
V
IOL = 8mA
IOH = -8mA
VOD8 Type Buffer
Low Output Level VOL 0.4 V IOL = 8mA
Table 5.4 100BASE-TX Transceiver Character istics
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Peak Differential Output Voltage High VPPH 950 - 1050 mVpk Note 5.10
Peak Differential Output Voltage Low VPPL -950 - -1050 mVpk Note 5.10
Signal Amplitude Symmetry VSS 98 - 102 % Note 5.10
Signal Rise and Fall Time TRF 3.0 - 5.0 nS Note 5.10
Rise and Fall Symmetry TRFS --0.5nSNote 5.10
Duty Cycle Distortion DCD 35 50 65 % Note 5.11
Overshoot and Undershoot VOS --5%
Jitter 1.4 nS Note 5.12
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Note 5.13 Min/max voltages guaranteed as measured with 100Ω resistive load.
5.5 AC Specifications
This section details the various AC timing specifications of the device.
Note: The MII/SMI timing adheres to the IEEE 802.3 specification. Refer to the IEEE 802.3
specification for additional timing information.
Note: The RMII timing adheres to the RMII Consortium RMII Specification R1.2.
5.5.1 Equivalent Test Load
Output timing specificati ons assume a 25pF equival ent test l oad, unless ot herwise noted, as illustrat ed
in Figure 5.1 below.
Table 5.5 10BASE-T Transceiver Characteristics
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Transmitter Peak Di fferential Out put Vol tage VOUT 2.2 2.5 2.8 V Note 5.13
Receiver Differential Squelch Threshold VDS 300 420 585 mV
Figure 5.1 Output Equivalent Test Load
25 pF
OUTPUT
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5.5.2 Power Sequence Timing
This diagram illust rates the device power sequencing requirements. The VDDIO, VDD1A, VDD2A and
magnetics power supplies can turn on in any order provided they all reach operational levels within
the specified time period tpon. Device power supplies can turn off in any order provided they all reach
0 volts within the specified time period poff.
Note: When the internal regulator is disabled, a power-up sequencing relationship exists between
VDDCR and the 3.3V power supply. For additional information refer to Section 3.7.4,
"REGOFF: Internal +1.2V Regulator Configuration," on page 38.
Figure 5.2 Power Sequence Timing
Table 5.6 Power Sequence Timing Values
SYMBOL DESCRIPTION MIN TYP MAX UNITS
tpon Power supply turn on time 50 mS
tpoff Power supply turn off time 500 mS
VDDIO
Magnetics
Power
tpon tpoff
VDD1A,
VDD2A
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5.5.3 Power-On nRST & Configuration Strap Timing
This diagram illustrates the nRST reset and configuration strap timing requirements in relation to
power-on. A hardware reset (nRST assertion) is required following power-up. For proper operation,
nRST must be asserted for no less than trstia. The nRST pin can be asserted at any time, but must
not be deasserted before tpurstd after all external power supplies have reached 80% of their nominal
operating levels. In order for valid configuration strap values to be read at power-up, the tcss and tcsh
timing constraints must be followed. Refer to Section 3.8.5, "Resets," on page 41 for additional
information.
Note: nRST deassertion must be monotonic.
Note: Device configuration straps are latched as a result of nRST assertion. Refer to Section 3.7,
"Configuration Straps," on page 36 for details. Configuration straps must only be pulled high or
low and must not be driven as inputs.
Note 5.14 20 clock cycles for 25MHz, or 40 clock cycles for 50MHz.
Figure 5.3 Power-On nRST & Configuration Strap Timing
Table 5.7 Power-On nRST & Configuration Strap Timing Values
SYMBOL DESCRIPTION MIN TYP MAX UNITS
tpurstd External power supplies at 80% to nRST deassertion 25 mS
tpurstv External power supplies at 80% to nRST valid 0 nS
trstia nRST input assertion time 100 μS
tcss Configuration strap pins setup to nRST deassertion 200 nS
tcsh Configuration strap pins hold after nRST deassertion 1 nS
totaa Output tri-state after nRST assertion 50 nS
todad Output drive after nRST deassertion 2 800
(Note 5.14)nS
tcss
nRST
Configuration Strap
Pins Input
trstia
tcsh
Configurati on Strap
Pins Output Drive
todad
All External
Power Supplies tpurstd
80%
tpurstv
totaa
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5.5.4 MII Interface Timing
This section specifi es the MII interface tran smit and receive timing. Please refer to Section 3.4. 1, "MII,"
on page 30 for additional details.
Note 5.15 40ns for 100BASE-TX operation, 400ns for 10BASE-T operation.
Note 5.16 Timing was designed for system load between 10 pf and 25 pf.
Figure 5.4 MII Receive Timing
Table 5.8 MII Receive Timing Values
SYMBOL DESCRIPTION MIN MAX UNITS NOTES
tclkp RXCLK period Note 5.15 ns
tclkh RXCLK high time tclkp*0.4 tclkp*0.6 ns
tclkl RXCLK low time tclkp*0.4 tclkp*0.6 ns
tval RXD[3:0], RXDV output valid from rising edge of
RXCLK 28.0 ns Note 5.16
thold RXD[3:0], RXDV output hold from rising edge of
RXCLK 10.0 ns Note 5.16
RXCLK
RXD[3:0]
RXDV
tclkh tclkl
tclkp
tval thold
tval
tval
thold
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Note 5.17 40ns for 100BASE-TX operation, 400ns for 10BASE-T operation.
Note 5.18 Timing was designed for system load between 10 pf and 25 pf.
Figure 5.5 MII Transmit Timing
Table 5.9 M II Transmit Timing Values
SYMBOL DESCRIPTION MIN MAX UNITS NOTES
tclkp TXCLK period Note 5.17 ns
tclkh TXCLK high time tclkp*0.4 tclkp*0.6 ns
tclkl TXCLK low time tclkp*0.4 tclkp*0.6 ns
tsu TXD[3:0], TXEN setup time to rising edge of
TXCLK 12.0 ns Note 5.18
thold TXD[3:0], TXEN hold time after rising edge of
TXCLK 0nsNote 5.18
TXCLK tsu
TXD[3:0]
TXEN
tclkh tclkl
tclkp
thold tsu thold thold
tsu
thold
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DATASHEET
5.5.5 RMII Interface Timing
Note 5.19 Timing was designed for system load between 10 pf and 25 pf.
Figure 5.6 RMII Timing
Table 5.10 RMII Timing Values
SYMBOL DESCRIPTION MIN MAX UNITS NOTES
tclkp CLKIN period 20 ns
tclkh CLKIN high time tclkp*0.35 tclkp*0.65 ns
tclkl CLKIN low time tclkp*0.35 tclkp*0.65 ns
toval RXD[1:0], RXER, CRS_DV output valid from
rising edge of CLKIN 14.0 ns Note 5.19
tohold RXD[1:0], RXER, CRS_DV output hold from
rising edge of CLKIN 3.0 ns Note 5.19
tsu TXD[1:0], TXEN setup time to rising edge of
CLKIN 4.0 ns Note 5.19
tihold TXD[1:0], TXEN input hold time after rising edge
of CLKIN 1.5 ns Note 5.19
CLKIN
(REF_CLK)
RXD[1:0],
RXER
CRS_DV
tclkh tclkl
tclkp
toval tohold
toval
toval
tohold
tsu
TXD[1:0]
TXEN
tihold tsu tihold tihold
tsu
tihold
Small Footprint MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX and flexPWR® Technology
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Revision 1.4 (08-23-12) 76 SMSC LAN8710A/LAN8710Ai
DATASHEET
5.5.5.1 RMII CLKIN Requirements
5.5.6 SMI Timing
This section specifies the SMI timing of the device. Please refer to Section 3.5, "Serial Management
Interface (SMI)," on page 33 for additional details.
Table 5.11 RMII CLKIN (REF_CLK) Timing Values
PARAMETER MIN TYP MAX UNITS NOTES
CLKIN frequency 50 MHz
CLKIN Frequency Drift ± 50 ppm
CLKIN Duty Cycle 40 60 %
CLKIN Jitter 150 psec p-p – not RMS
Figure 5.7 SMI Timing
Table 5.12 SMI Timing Values
SYMBOL DESCRIPTION MIN MAX UNITS NOTES
tclkp MDC period 400 ns
tclkh MDC high time 160 (80%) ns
tclkl MDC low time 160 (80%) ns
tval MDIO (read from PHY) output valid from rising
edge of MDC 300 ns
tohold MDIO (read from PHY) output hold from rising
edge of MDC 0ns
tsu MDIO (write to PHY) setup time to rising edge
of MDC 10 ns
tihold MDIO (write to PHY) input hold time after rising
edge of MDC 10 ns
MDC
MDIO
tclkh tclkl
tclkp
tohold
MDIO
tsu tihold
(Data-Out)
(Data-In)
tohold
tval
Small Footprint MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX and flexPWR® Technology
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SMSC LAN8710A/LAN8710Ai 77 Revision 1.4 (08-23-12)
DATASHEET
5.6 Clock Circuit
The device can accept either a 25MHz crystal or a 25MHz single-ended clock oscillator (±50ppm)
input. If the single-ended clock oscillator method is implemented, XTAL2 should be left unconnected
and XTAL1/CLKIN should be driven with a nominal 0-3.3V clock signal. See Table 5.13 for the
recommended crystal specifications.
Note 5.20 The maximum allowable values for Frequency Tolerance and Frequency Stability are
application depend ant. Since any particular appl ication must meet the IEEE ±50 PPM Total
PPM Budget, the combination of these two values must be approximately ±45 PPM
(allowing for aging).
Note 5.21 Frequency Deviation Over Time is also referred to as Aging.
Note 5.22 The total deviation for the Transmitter Clock Frequency is specified by IEEE 802.3u as
±100 PPM.
Note 5.23 0oC for extended commercial version, -40oC for industrial version.
Note 5.24 This number includes the pad, the bond wire and the lead frame. PCB capacitance is not
included in this value . The XTAL1/CLKIN pin, XTAL2 pin an d PCB capacitance values are
required to accurately calcula te the valu e of the t wo ext ernal load capacito rs. The total load
capacitance must be equivalent to what the crystal expects to see in the circuit so that the
crystal oscillator will operate at 25.000 MHz.
Table 5.13 Crystal Specifications
PARAMETER SYMBOL MIN NOM MAX UNITS NOTES
Crystal Cut AT, typ
Crystal Oscillation Mode Fundamental Mode
Crystal Calibration Mode Parallel Resonant Mode
Frequency Ffund - 25.000 - MHz
Frequency Tolerance @ 25oCF
tol - - ±50 PPM Note 5.20
Frequency Stability Over Temp Ftemp - - ±50 PPM Note 5.20
Frequency Deviation Over Time Fage - +/-3 to 5 - PPM Note 5.21
Total Allowable PPM Budget - - ±50 PPM Note 5.22
Shunt Capacitance CO-7 typ-pF
Load Capacitance CL- 20 typ - pF
Drive Level PW300 - - uW
Equivalent Series Resistance R1--30Ohm
Operating Temperature Range Note 5.23 -+85
oC
XTAL1/CLKIN Pin Capacitance - 3 typ - pF Note 5.24
XTAL2 Pin Capacitance - 3 typ - pF Note 5.24
Small Footprint MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX and flexPWR® Technology
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Revision 1.4 (08-23-12) 78 SMSC LAN8710A/LAN8710Ai
DATASHEET
Chapter 6 Package Outline
Notes:
1. All dimensions are in millimeters unless otherwise noted.
2. Dimension “b” applies to plated terminals and is measured between 0.15 and 0.30 mm from the terminal tip.
3. The pin 1 identifier may vary, but is always located within the zone indicated.
Figure 6.1 32-QFN Package
Table 6.1 32-QFN Dimensions
MIN NOMINAL MAX REMARKS
A 0.70 0.85 1.00 Overall Package Height
A1 0 0.02 0.05 Standoff
A2 - 0.65 0.90 Mold Cap Thickness
D/E 4.90 5.00 5.10 X/Y Body Size
D1/E1 4.55 4.75 4.95 X/Y Mold Cap Size
D2/E2 3.20 3.30 3.40 X/Y Exposed Pad Size
L 0.30 0.40 0.50 Terminal Length
b 0.18 0.25 0.30 Terminal Width
k 0.35 0.45 - Terminal to Exposed Pad Clearance
e 0.50 BSC Terminal Pitch
Small Footprint MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX and flexPWR® Technology
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SMSC LAN8710A/LAN8710Ai 79 Revision 1.4 (08-23-12)
DATASHEET
Figure 6.2 Recommended PCB Land Pattern
Figure 6.3 Taping Dimensions and Part Orientation
Small Footprint MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX and flexPWR® Technology
Datasheet
Revision 1.4 (08-23-12) 80 SMSC LAN8710A/LAN8710Ai
DATASHEET
Note: Standard reel size is 4,000 pieces per reel.
Figure 6.4 Reel Dimensions
Figure 6.5 Tape Length and Part Quantity
Small Footprint MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX and flexPWR® Technology
Datasheet
SMSC LAN8710A/LAN8710Ai 81 Revision 1.4 (08-23-12)
DATASHEET
Chapter 7 Datasheet Revision History
Table 7.1 Customer Revision History
REVISION LEVEL & DATE SECTION/FIGURE/ENTRY CORRECTION
Rev. 1.4
(08-23-12) Section 4.2.2, "Basic Status
Register," on page 53 Updated definitions of bits 10:8.
Section 4.2.11, "Special
Control/Status Indications
Register," on page 62
Updated bit 11 definition.
Section 4.2.14, "PHY
Special Control/Status
Register," on page 65
Updated bit 6 definition.
Rev. 1.3
(03-12-12) Company disclaimer on
page 2 Removed company address and phone numbers.
Cover Ordering information modified.
Rev. 1.3
(04-20-11) Cover Added copper bond wire ordering codes to
LAN8710 ordering codes
Table 2.7, “Power Pins,” on
page 16 Updated VDDCR pin note to include requirement
of 1uF and 470pF decoupling capaci tors in parallel
to ground on the VDDCR pin.
Figure 3.13 Power Supply
Diagram (1.2V Supplied by
Internal Regulator) on
page 46 and Figure 3.13
Power Supply Diagram
(1.2V Supplied by Internal
Regulator) on page 46
Updated diagrams to include 1uF and 470pF
decoupling capacitors on the VDDCR pin.
Table 4.2 .9, “Special Modes
Register,” on page 60 Updated MIIMODE bit description and added note:
“When writing to this register the default value of
this bit must always be written back.”
Section 3.7.3, "RMIISEL:
MII/RMII Mode
Configuration," on page 37
Updated second paragraph to:
“When the nRST pin is deasserted, the MIIMODE
bit of the Special Modes Register is loaded
according to the RMII SEL configuration strap. The
mode is reflected in the MIIMODE bit of the Special
Modes Register.”
Section 3.8.9.2, "Far
Loopback," on page 43 Updated section to defeature information about
register control of the MII/RMII mode.
Rev. 1.2 (11-10-10) Section 5.5.5, "RMII
Interface Timing," on
page 75
Updated diagrams and tables to include RXER.
Figure 6.1 32-QFN Package
on page 78 & Figure 6.2
Recommended PCB Land
Pattern on page 79
Updated package drawings.
Section 5.5.5, "RMII
Interface Timing," on
page 75
Corrected signal names on RMII timing diagrams
and tables.
Small Footprint MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX and flexPWR® Technology
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Revision 1.4 (08-23-12) 82 SMSC LAN8710A/LAN8710Ai
DATASHEET
Section 5.5.4, "MII Interface
Timing," on page 73 Corrected signal names on MII timing diagrams
and tables. Updated Table 5.8 tval max to 28. 0 ns.
Updated Table 5.9 tsu and thold values to 12.0 ns
and 0 ns, respectively.
Table 5.7 , “Power-On nRST
& Configuration Strap
Timing Values,” on page 72
Updated todad description: “Output drive after
nRST deassertion”
Rev. 1.1 (04-09-10) Section 5.1, "Absolute
Maximum Ratings*" Modified “HBM ESD Performance by adding “per
JEDEC JESD22-A114” and changed “+/-5kV” to
“Class 3A”
Section 5.3, "Power
Consumption," on page 67 Corrected typo in the current consumption table
row title: “100BASE-TX /W TRAFFIC”
Section 5.3, "Power
Consumption," on page 67 Corrected typo in note regarding Ethernet
component current:
“The Ethernet component current is typically 41mA
in 100BASE-TX mode and 100mA in 10BASE-T
mode, independent of the 2.5V or 3.3V supply rail
of the transformer.”
Table 5.2 , “Non-Variable I /O
Buffer Characteristics,” on
page 68
Corrected O12 VOH minimum value to “VDD2A -
0.4”
Corrected ICLK VILI maximum value to “0.35”
Corrected ICLK VIHI maximum value to “VDD2A +
0.4”
Section 5.2, "Operating
Conditions**," on page 67 Added note: “Do not drive input signals without
power supplied to the device.”
Section 5.1, "Absolute
Maximum Ratings*," on
page 66
Corrected IEC61000-4-2 Contact Discharge ESD
Performance to +/-8kV.
Section 4.2.4, "PHY
Identifier 2 Register," on
page 55
Corrected Model Number default value to
“001111b”.
Section 3.8.9.2, "Far
Loopback," on page 43 Added far loopback description.
Section 4.2.8, "Mode
Control/Status Register, " on
page 59
Added FARLOOPBACK (bit 9) description.
Table 5.9, “MII Transmit
Timing Values,” on page 74 Corrected tsu and thold minimum values to 10 ns.
Rev. 1.0 (12-09-09) Document reworked for clarity and consistency with other SMSC documentation.
Rev. 1.0 (04-15-09) Initial Release
Table 7.1 Customer Revision History (continued)
REVISION LEVEL & DATE SECTION/FIGURE/ENTRY CORRECTION
