SN54AC374, SN74AC374
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS543E − OCTOBER 1995 - REVISED OCTOBER 2003
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D2-V to 6-V VCC Operation
DInputs Accept Voltages to 6 V
DMax tpd of 9.5 ns at 5 V
D3-State Noninverting Outputs Drive Bus
Lines Directly
DFull Parallel Access for Loading
description/ordering information
These 8-bit flip-flops feature 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. The devices
are particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.
The eight flip-flops of the ’AC374 devices are
D-type edge-triggered flip-flops. On the positive
transition of the clock (CLK) input, the Q outputs
are set to the logic levels set up at the data (D)
inputs.
A buffered output-enable (OE) input can be used
to place the eight outputs in either a normal logic
state (high or low logic levels) or the
high-impedance state. In the high-impedance
state, the outputs neither load nor drive the bus
lines significantly. The high-impedance state and
the increased drive provide the capability to drive
bus lines in bus-organized systems without need
for interface or pullup components.
OE does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
ORDERING INFORMATION
TAPACKAGE†ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP − N Tube SN74AC374N SN74AC374N
SOIC DW
Tube SN74AC374DW
AC374
SOIC − DW Tape and reel SN74AC374DWR AC374
−40°C to 85°CSOP − NS Tape and reel SN74AC374NSR AC374
40 C
to
85 C
SSOP − DB Tape and reel SN74AC374DBR AC374
TSSOP PW
Tube SN74AC374PW
AC374
TSSOP − PW Tape and reel SN74AC374PWR AC374
CDIP − J Tube SNJ54AC374J SNJ54AC374J
−55°C to 125°CCFP − W Tube SNJ54AC374W SNJ54AC374W
55 C
to
125 C
LCCC − FK Tube SNJ54AC374FK SNJ54AC374FK
†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Copyright ©2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OE
1Q
1D
2D
2Q
3Q
3D
4D
4Q
GND
VCC
8Q
8D
7D
7Q
6Q
6D
5D
5Q
CLK
SN54AC374 ...J OR W PACKAGE
SN74AC374 . . . DB, DW, N, NS, OR PW PACKAGE
(TOP VIEW)
3 2 1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
2D
2Q
3Q
3D
4D
SN54AC374...FK PACKAGE
(TOP VIEW)
1D
1Q
OE
5Q
5D 8Q
4Q
GND
CLK
V
CC
8D
7D
7Q
6Q
6D
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
SN54AC374, SN74AC374
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS543E − OCTOBER 1995 - REVISED OCTOBER 2003
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description/ordering information (continued)
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
FUNCTION TABLE
(each flip-flop)
INPUTS OUTPUT
OE CLK D
OUTPUT
Q
L↑H H
L↑LL
LH or L X Q0
H X X Z
logic diagram (positive logic)
1D
CLK
1Q
2
11
3
1
1D
OE
C1
To Seven Other Channels
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC −0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) −0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, VO (see Note 1) −0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0 or VI > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0 or VO > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO (VO = 0 to VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±200 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 2): DB package 70°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DW package 58°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package 69°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NS package 60°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 83°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
SN54AC374, SN74AC374
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS543E − OCTOBER 1995 - REVISED OCTOBER 2003
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions (see Note 3)
SN54AC374 SN74AC374
UNIT
MIN MAX MIN MAX UNIT
VCC Supply voltage 2 6 2 6 V
VCC = 3 V 2.1 2.1
VIH High-level input voltage VCC = 4.5 V 3.15 3.15 V
VIH
High level
input
voltage
VCC = 5.5 V 3.85 3.85
V
VCC = 3 V 0.9 0.9
VIL Low-level input voltage VCC = 4.5V 1.35 1.35 V
VIL
Low level
input
voltage
VCC = 5.5 V 1.65 1.65
V
VIInput voltage 0 VCC 0 VCC V
VOOutput voltage 0 VCC 0 VCC V
VCC = 3 V −12 −12
IOH High-level output current VCC = 4.5 V −24 −24 mA
IOH
High level
output
current
VCC = 5.5 V −24 −24
mA
VCC = 3 V 12 12
IOL Low-level output current VCC = 4.5 V 24 24 mA
IOL
Low level
output
current
VCC = 5.5 V 24 24
mA
Δt/ΔvInput transition rise or fall rate 8 8 ns/V
TAOperating free-air temperature −55 125 −40 85 °C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
V
TA = 25°C SN54AC374 SN74AC374
UNIT
PARAMETER TEST CONDITIONS VCC MIN TYP MAX MIN MAX MIN MAX UNIT
3 V 2.9 2.9 2.9
IOH = −50 μA4.5 V 4.4 4.4 4.4
V
IOH
50
μA
5.5 V 5.4 5.4 5.4
V
VOH IOH = −12 mA 3 V 2.56 2.4 2.46 V
I24 mA
4.5 V 3.86 3.7 3.76
IOH = −24 mA 5.5 V 4.86 4.7 4.76
3 V 0.1 0.1 0.1
IOL = 50 μA4.5 V 0.1 0.1 0.1
V
IOL
50
μA
5.5 V 0.1 0.1 0.1
V
VOL IOL = 12 mA 3 V 0.36 0.5 0.44 V
I24 mA
4.5 V 0.36 0.5 0.44
IOL = 24 mA 5.5 V 0.36 0.5 0.44
IIVI = VCC or GND 5.5 V ±0.1 ±1±1μA
IOZ VO = VCC or GND 5.5 V ±0.25 ±5±2.5 μA
ICC VI = VCC or GND, IO = 0 5.5 V 4 80 40 μA
CiVI = VCC or GND 5 V 4.5 pF
SN54AC374, SN74AC374
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS543E − OCTOBER 1995 - REVISED OCTOBER 2003
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
timing requirements over recommended operating free-air temperature range, VCC = 3.3 V ±0.3 V
(unless otherwise noted) (see Figure 1)
TA = 25°C SN54AC374 SN74AC374
MIN MAX MIN MAX MIN MAX UNIT
fclock Clock frequency 60 60 60 MHz
twPulse duration, CLK high or low 5.5 6.5 6 ns
tsu Setup time, data before CLK↑5.5 6.5 6 ns
thHold time, data after CLK↑1 1 1 ns
timing requirements over recommended operating free-air temperature range, VCC = 5 V ±0.5 V
(unless otherwise noted) (see Figure 1)
TA = 25°C SN54AC374 SN74AC374
UNIT
MIN MAX MIN MAX MIN MAX UNIT
fclock Clock frequency 100 95 100 MHz
twPulse duration, CLK high or low 4 5 4.5 ns
tsu Setup time, data before CLK↑4 5 4.5 ns
thHold time, data after CLK↑1.5 1.5 1.5 ns
switching characteristics over recommended operating free-air temperature range,
VCC = 3.3 V ±0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER
TO TO TA = 25°C SN54AC374 SN74AC374
PARAMETER
TO
(INPUT)
TO
(OUTPUT) MIN TYP MAX MIN MAX MIN MAX UNIT
fmax 60 110 60 60 MHz
tPLH
CLK
Q
311 13.5 3 16.5 1.5 15.5
tPHL
CLK Q 2.5 10 12.5 3 15 2 14 ns
tPZH
OE
Q
3 9.5 11.5 1 14 1.5 13
tPZL
OE Q3.5 9 11.5 1 14 1.5 13 ns
tPHZ
OE
Q
3 10.5 12.5 1 16 2 14.5
tPLZ
OE Q2 8 11.5 1 13 1 12.5 ns
switching characteristics over recommended operating free-air temperature range,
VCC = 5 V ±0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
TO TO TA = 25°C SN54AC374 SN74AC374
PARAMETER
TO
(INPUT)
TO
(OUTPUT) MIN TYP MAX MIN MAX MIN MAX UNIT
fmax 100 155 95 100 MHz
tPLH
CLK
Q
2.5 8 9.5 3 12 1.5 10.5
tPHL
CLK Q 2 7 9 3 11 1.5 10 ns
tPZH
OE
Q
2 7 8.5 1.5 10 1 9.5
tPZL
OE Q2 6.5 8.5 1.5 10.5 1 9.5 ns
tPHZ
OE
Q
2 8 11 1.5 12.5 2 12.5
tPLZ
OE Q1.5 6.5 8.5 1.5 10.5 1 10 ns
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
Cpd Power dissipation capacitance CL = 50 pF, f = 1 MHz 40 pF
SN54AC374, SN74AC374
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS543E − OCTOBER 1995 - REVISED OCTOBER 2003
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
50% VCC
50% VCC
50% VCC
50% VCC
VCC
VCC
0 V
0 V
th
tsu
VOLTAGE WAVEFORMS
Data Input
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
VCC
0 V
50% VCC
50% VCC
Input
Out-of-Phase
Output
In-Phase
Output
Timing Input
50% VCC
VOLTAGE WAVEFORMS
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1
2 × VCC
500 Ω
500 Ω
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
Output
Waveform 2
S1 at Open
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
≈VCC
0 V
50% VCC VOL + 0.3 V
50% VCC
≈0 V
Open
VOLTAGE WAVEFORMS
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
Open
TEST S1
3 V
0 V
tw
VOLTAGE WAVEFORMS
Input
50% VCC 50% VCC
VOH − 0.3 V
50% VCC
50% VCC
50% VCC
50% VCC
VCC
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
PACKAGE OPTION ADDENDUM
www.ti.com 4-Feb-2021
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
5962-87694012A ACTIVE LCCC FK 20 1 Non-RoHS
& Green POST-PLATE N / A for Pkg Type -55 to 125 5962-
87694012A
SNJ54AC
374FK
5962-8769401RA ACTIVE CDIP J 20 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 5962-8769401RA
SNJ54AC374J
5962-8769401SA ACTIVE CFP W 20 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 5962-8769401SA
SNJ54AC374W
SN74AC374DBR ACTIVE SSOP DB 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AC374
SN74AC374DW ACTIVE SOIC DW 20 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AC374
SN74AC374DWR ACTIVE SOIC DW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AC374
SN74AC374DWRE4 ACTIVE SOIC DW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AC374
SN74AC374N ACTIVE PDIP N 20 20 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 SN74AC374N
SN74AC374NSR ACTIVE SO NS 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AC374
SN74AC374NSRE4 ACTIVE SO NS 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AC374
SN74AC374PW ACTIVE TSSOP PW 20 70 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AC374
SN74AC374PWR ACTIVE TSSOP PW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AC374
SNJ54AC374FK ACTIVE LCCC FK 20 1 Non-RoHS
& Green POST-PLATE N / A for Pkg Type -55 to 125 5962-
87694012A
SNJ54AC
374FK
SNJ54AC374J ACTIVE CDIP J 20 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 5962-8769401RA
SNJ54AC374J
SNJ54AC374W ACTIVE CFP W 20 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 5962-8769401SA
SNJ54AC374W
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
PACKAGE OPTION ADDENDUM
www.ti.com 4-Feb-2021
Addendum-Page 2
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN54AC374, SN74AC374 :
•Catalog: SN74AC374
•Military: SN54AC374
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
PACKAGE OPTION ADDENDUM
www.ti.com 4-Feb-2021
Addendum-Page 3
•Military - QML certified for Military and Defense Applications
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74AC374DBR SSOP DB 20 2000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1
SN74AC374DWR SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1
SN74AC374NSR SO NS 20 2000 330.0 24.4 8.4 13.0 2.5 12.0 24.0 Q1
SN74AC374PWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 30-Dec-2020
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74AC374DBR SSOP DB 20 2000 853.0 449.0 35.0
SN74AC374DWR SOIC DW 20 2000 367.0 367.0 45.0
SN74AC374NSR SO NS 20 2000 367.0 367.0 45.0
SN74AC374PWR TSSOP PW 20 2000 853.0 449.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 30-Dec-2020
Pack Materials-Page 2
www.ti.com
PACKAGE OUTLINE
C
18X 0.65
2X
5.85
20X 0.38
0.22
8.2
7.4 TYP
SEATING
PLANE
0.05 MIN
0.25
GAGE PLANE
0 -8
2 MAX
B5.6
5.0
NOTE 4
A
7.5
6.9
NOTE 3
0.95
0.55
(0.15) TYP
SSOP - 2 mm max heightDB0020A
SMALL OUTLINE PACKAGE
4214851/B 08/2019
1
10 11
20
0.1 C A B
PIN 1 INDEX AREA
SEE DETAIL A
0.1 C
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-150.
A 15
DETAIL A
TYPICAL
SCALE 2.000
www.ti.com
EXAMPLE BOARD LAYOUT
0.07 MAX
ALL AROUND 0.07 MIN
ALL AROUND
20X (1.85)
20X (0.45)
18X (0.65)
(7)
(R0.05) TYP
SSOP - 2 mm max heightDB0020A
SMALL OUTLINE PACKAGE
4214851/B 08/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SYMM
SYMM
1
10 11
20
15.000
METAL
SOLDER MASK
OPENING METAL UNDER
SOLDER MASK SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
SOLDER MASK DETAILS
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
www.ti.com
EXAMPLE STENCIL DESIGN
20X (1.85)
20X (0.45)
18X (0.65)
(7)
(R0.05) TYP
SSOP - 2 mm max heightDB0020A
SMALL OUTLINE PACKAGE
4214851/B 08/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
SYMM
SYMM
1
10 11
20
www.ti.com
PACKAGE OUTLINE
C
TYP
10.63
9.97
2.65 MAX
18X 1.27
20X 0.51
0.31
2X
11.43
TYP
0.33
0.10
0 - 8
0.3
0.1
0.25
GAGE PLANE
1.27
0.40
A
NOTE 3
13.0
12.6
B7.6
7.4
4220724/A 05/2016
SOIC - 2.65 mm max heightDW0020A
SOIC
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side.
5. Reference JEDEC registration MS-013.
120
0.25 C A B
11
10
PIN 1 ID
AREA
NOTE 4
SEATING PLANE
0.1 C
SEE DETAIL A
DETAIL A
TYPICAL
SCALE 1.200
www.ti.com
EXAMPLE BOARD LAYOUT
(9.3)
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
20X (2)
20X (0.6)
18X (1.27)
(R )
TYP
0.05
4220724/A 05/2016
SOIC - 2.65 mm max heightDW0020A
SOIC
SYMM
SYMM
LAND PATTERN EXAMPLE
SCALE:6X
1
10 11
20
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
www.ti.com
EXAMPLE STENCIL DESIGN
(9.3)
18X (1.27)
20X (0.6)
20X (2)
4220724/A 05/2016
SOIC - 2.65 mm max heightDW0020A
SOIC
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SYMM
SYMM
1
10 11
20
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
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