REV. B
a
ADF4252
Dual Fractional-N/Integer-N
Frequency Synthesizer
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 www.analog.com
Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved.
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
FEATURES
3.0 GHz Fractional-N/1.2 GHz Integer-N
2.7 V to 3.3 V Power Supply
Separate V
P
Allows Extended Tuning Voltage to 5 V
Programmable Dual Modulus Prescaler
RF: 4/5, 8/9
IF: 8/9, 16/17, 32/33, 64/65
Programmable Charge Pump Currents
3-Wire Serial Interface
Digital Lock Detect
Power-Down Mode
Programmable Modulus on Fractional-N Synthesizer
Trade-Off Noise versus Spurious Performance
APPLICATIONS
Base Stations for Mobile Radio (GSM, PCS, DCS,
CDMA, WCDMA)
Wireless Handsets (GSM, PCS, DCS, CDMA, WCDMA)
Wireless LANs
Communications Test Equipment
CATV Equipment
FUNCTIONAL BLOCK DIAGRAM
ADF4252
ⴛ2
DOUBLER
OUTPUT
MUX
4-BIT R
COUNTER PHASE
FREQUENCY
DETECTOR
LOCK
DETECT
CHARGE
PUMP
REFERENCE
REFIN
REFOUT
VDD1VDD2VDD3DVDD VP1VP2RSET
24-BIT
DATA
REGISTER
CLK
DATA
LE
RFINA
RFINB
CPRF
CPIF
ⴛ2
DOUBLER
15-BIT R
COUNTER
CHARGE
PUMP
PHASE
FREQUENCY
DETECTOR
MUXOUT
AGND1 AGND2 DGND CPGND1 CPGND2
IFINB
IFINA
FRACTIONAL N
RF DIVIDER
INTEGER N
IF DIVIDER
GENERAL DESCRIPTION
The ADF4252 is a dual fractional-N/integer-N frequency
synthesizer that can be used to implement local oscillators
(LO) in the upconversion and downconversion sections of
wireless receivers and transmitters. Both the RF and IF syn-
thesizers consist of a low noise digital PFD (phase frequency
detector), a precision charge pump, and a programmable refer-
ence divider. The RF synthesizer has a ⌺-⌬-based fractional
interpolator that allows programmable fractional-N division.
The IF synthesizer has programmable integer-N counters. A
complete PLL (phase-locked loop) can be implemented if the
synthesizer is used with an external loop filter and VCO (volt-
age controlled oscillator).
Control of all the on-chip registers is via a simple 3-wire inter-
face. The devices operate with a power supply ranging from
2.7 V to 3.3 V and can be powered down when not in use.
REV. B–2–
ADF4252–SPECIFICATIONS
1
(VDD1 = VDD2 = VDD3 = DVDD = 3 V ⴞ 10%, DVDD < VP1, VP2 < 5.5 V, GND = 0 V,
RSET = 2.7 k⍀, dBm referred to 50 ⍀, TA = TMIN to TMAX, unless otherwise noted.)
Parameter B Version Unit Test Conditions/Comments
RF CHARACTERISTICS
RF Input Frequency (RF
IN
A, RF
IN
B)
2
0.25/3.0 GHz min/max
RF Input Sensitivity –10/0 dBm min/max
RF Input Frequency (RF
IN
A, RF
IN
B)
2
0.1/3.0 GHz min/max Input Level = –8/0 dBm min/max
RF Phase Detector Frequency 30 MHz max Guaranteed by Design
Allowable Prescaler Output Frequency 375 MHz max
IF CHARACTERISTICS
IF Input Frequency (IF
IN
A, IF
IN
B)
2
50/1200 MHz min/max
IF Input Sensitivity –10/0 dBm min/max
IF Phase Detector Frequency 55 MHz max Guaranteed by Design
Allowable Prescaler Output Frequency 150 MHz max
REFERENCE CHARACTERISTICS
REF
IN
Input Frequency 250 MHz max For f < 10 MHz, use dc-coupled square
wave (0 to V
DD
).
REF
IN
Input Sensitivity 0.5/V
DD
1V p-p min/max AC-coupled. When dc-coupled, use
0to V
DD
max (CMOS compatible).
REF
IN
Input Current ±100 µA max
REF
IN
Input Capacitance 10 pF max
CHARGE PUMP
RF I
CP
Sink/Source High Value 4.375 mA typ See Table V
Low Value 625 µA typ
IF I
CP
Sink/Source High Value 5 mA typ See Table IX
Low Value 625 µA typ
I
CP
Three-State Leakage Current 1 nA typ
RF Sink and Source Current Matching 2 % typ 0.5 V < V
CP
< V
P
– 0.5
R
SET
Range 1.5/1.6 ktyp See Table V
IF Sink and Source Current Matching 2 % typ
I
CP
vs. V
CP
2% typ 0.5 V < V
CP
< V
P
– 0.5
I
CP
vs. Temperature 2 % typ V
CP
= V
P
/2
LOGIC INPUTS
V
INH
, Input High Voltage 1.35 V min
V
INL
, Input Low Voltage 0.6 V max
I
INH
/I
INL
, Input Current ±1µA max
C
IN
Input Capacitance 10 pF max
LOGIC OUTPUTS
V
OH
, Output High Voltage V
DD
– 0.4 V min I
OH
= 0.2 mA
V
OL
, Output Low Voltage 0.4 V max I
OL
= 0.2 mA
POWER SUPPLIES
V
DD
1
,
V
DD
2, V
DD
32.7/3.3 V min/V max
DV
DD
V
DD
1
V
P
1, V
P
2V
DD
1/5.5 V min/V max
I
DD3
RF + IF 13 mA typ 16 mA max
RF Only 10 mA typ 13 mA max
IF Only 4 mA typ 5.5 mA max
Power-Down Mode 1 µA typ
RF NOISE AND SPURIOUS CHARACTERISTICS
Noise Floor –141 dBc/Hz typ @ 20 MHz PFD Frequency
In-Band Phase Noise Performance
4
@ VCO Output
Lowest Spur Mode –90 dBc/Hz typ RF
OUT
= 1.8 GHz, PFD = 20 MHz
Low Noise and Spur Mode –95 dBc/Hz typ RF
OUT
= 1.8 GHz, PFD = 20 MHz
Lowest Noise Mode –103 dBc/Hz typ RF
OUT
= 1.8 GHz, PFD = 20 MHz
Spurious Signals See Typical Performance Characteristics
NOTES
1
Operating Temperature Range (B Version): –40°C to +85°C.
2
Use a square wave for frequencies less than f
MIN
.
3
RF = 1 GHz, RF PFD = 10 MHz, MOD = 4095, IF = 500 MHz, IF PFD = 200 kHz, REF = 10 MHz, V
DD
= 3 V, V
P
1 = 5 V, and V
P
2 = 3 V.
4
The in-band phase noise is measured with the EVAL-ADF4252EB2 evaluation board and the HP5500E phase noise test system. The spectrum analyzer provides the
REF
IN
for the synthesizer (f
REFOUT
= 10 MHz @ 0 dBm). f
OUT
= 1.74 GHz, f
REF
= 20 MHz, N = 87, Mod = 100, Channel Spacing = 200 kHz, V
DD
= 3.3 V, and V
P
= 5 V.
Specifications subject to change without notice.
REV. B
ADF4252
–3–
TIMING CHARACTERISTICS
*
Limit at
T
MIN
to T
MAX
Parameter (B Version) Unit Test Conditions/Comments
t
1
10 ns min LE Setup Time
t
2
10 ns min DATA to CLOCK Setup Time
t
3
10 ns min DATA to CLOCK Hold Time
t
4
25 ns min CLOCK High Duration
t
5
25 ns min CLOCK Low Duration
t
6
10 ns min CLOCK to LE Setup Time
t
7
20 ns min LE Pulse Width
*Guaranteed by design, but not production tested.
(VDD1 = VDD2 = VDD3 = DVDD = 3 V ⴞ 10%, DVDD < VP1, VP2 < 5.5 V, GND = 0 V,
unless otherwise noted.)
CLOCK
DATA
LE
LE
t4
t2
t3
t5
t7
t6
DB22 DB2 DB1
(CONTROL BIT C2)
DB0 (LSB)
(CONTROL BIT C1)
DB23 (MSB)
t1
Figure 1. Timing Diagram
REV. B–4–
ADF4252
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
ADF4252 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
ORDERING GUIDE
Temperature Package
Mode Range Option
*
ADF4252BCP –40ºC to +85ºCCP-24
ADF4252BCP-REEL –40ºC to +85ºCCP-24
ADF4252BCP-REEL7 –40ºC to +85ºCCP-24
EVAL–ADF4252EB1
EVAL–ADF4252EB2
*CP = Chip Scale Package
PIN CONFIGURATION
PIN 1
INDICATOR
TOP VIEW
(Not to Scale)
18 CP
GND
2
17 DV
DD
16 IF
IN
A
15 IF
IN
B
CP
RF
1
CP
GND
1 2
RF
IN
A 3
24 V
P
1
14 A
GND
2
13 R
SET
REF
IN
7
REF
OUT
8
D
GND
9
CLK 10
DATA 11
LE 12
RF
IN
B 4
A
GND
1 5
MUXOUT 6
23 V
DD
1
22 V
DD
3
21 V
DD
2
20 V
P
2
19 CP
IF
ADF4252
ABSOLUTE MAXIMUM RATINGS
1, 2
(T
A
= 25°C, unless otherwise noted.)
V
DD
1, V
DD
2, V
DD
3, DV
DD
to GND
3
. . . . . . . . –0.3 V to +4 V
REF
IN
, RF
IN
A, RF
IN
B to GND . . . . . . –0.3 V to V
DD
+ 0.3 V
V
P
1, V
P
2 to GND . . . . . . . . . . . . . . . . . . . . . –0.3 V to +5.8 V
V
P
1, V
P
2 to V
DD
1 . . . . . . . . . . . . . . . . . . . . . –3.3 V to +3.5 V
Digital I/O Voltage to GND . . . . . . . . –0.3 V to V
DD
+ 0.3 V
Analog I/O Voltage to GND . . . . . . . . –0.3 V to V
DD
+ 0.3 V
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Maximum Junction Temperature . . . . . . . . . . . . . . . . . 150°C
CSP
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . 122°C/W
Soldering Reflow Temperature
Vapor Phase (60 sec max) . . . . . . . . . . . . . . . . . . . . . 240°C
IR Reflow (20 sec max) . . . . . . . . . . . . . . . . . . . . . . . 240°C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
This device is a high performance RF integrated circuit with an ESD rating
of <2 kΩ, and it is ESD sensitive. Proper precautions should be taken for handling
and assembly.
3
GND = CP
GND
1, A
GND
1, D
GND
, A
GND
2, and CP
GND
2.
REV. B
ADF4252
–5–
PIN FUNCTION DESCRIPTIONS
Mnemonic Function
CP
RF
RF Charge Pump Output. This is normally connected to a loop filter that drives the input to an external VCO.
CP
GND
1RF Charge Pump Ground.
RF
IN
AInput to the RF Prescaler. This small signal input is normally taken from the VCO.
RF
IN
BComplementary Input to the RF Prescaler.
A
GND
1Analog Ground for the RF Synthesizer.
MUXOUT This multiplexer output allows either the RF or IF lock detect, the scaled RF or IF, or the scaled reference fre-
quency to be accessed externally.
REF
IN
Reference Input. This is a CMOS input with a nominal threshold of V
DD
/2 and an equivalent input resistance of
100 kΩ. This input can be driven from a TTL or CMOS crystal oscillator.
REF
OUT
Reference Output.
D
GND
Digital Ground for the Fractional Interpolator.
CLK Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the
shift register on the CLK rising edge. This input is a high impedance CMOS input.
DATA Serial Data Input. The serial data is loaded MSB first with the three LSBs being the control bits. This input is a
high impedance CMOS input.
LE Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the
seven latches, the latch being selected using the control bits.
R
SET
Connecting a resistor between this pin and ground sets the minimum charge pump output current. The relationship
between I
CP
and R
SET
is
I
R
CP
SET
min
=1 6875.
Therefore, with R
SET
= 2.7 kΩ, I
CPmin
= 0.625 mA.
A
GND
2Ground for the IF Synthesizer.
IF
IN
BComplementary Input to the IF Prescaler.
IF
IN
AInput to the IF Prescaler. This small signal input is normally taken from the IF VCO.
DV
DD
Positive Power Supply for the Fractional Interpolator Section. Decoupling capacitors to the ground plane should
be placed as close as possible to this pin. DV
DD
must have the same voltage as V
DD
1, V
DD
2, and V
DD
3.
CP
GND
2IF Charge Pump Ground.
CP
IF
IF Charge Pump Output. This is normally connected to a loop filter that drives the input to an external VCO.
V
P
2IF Charge Pump Power Supply. Decoupling capacitors to the ground plane should be placed as close as possible
to this pin. This voltage should be greater than or equal to V
DD
2.
V
DD
2Positive Power Supply for the IF Section. Decoupling capacitors to the ground plane should be placed as close as
possible to this pin. V
DD
2 has a value 3 V ± 10%. V
DD
2 must have the same voltage as V
DD
1, V
DD
3, and DV
DD
.
V
DD
3Positive Power Supply for the RF Digital Section. Decoupling capacitors to the ground plane should be placed as close
as possible to this pin. V
DD
3 has a value 3 V ± 10%. V
DD
3 must have the same voltage as V
DD
1, V
DD
2, and DV
DD
.
V
DD
1Positive Power Supply for the RF Analog Section. Decoupling capacitors to the ground plane should be placed as close
as possible to this pin. V
DD
1 has a value 3 V ± 10%. V
DD
1 must have the same voltage as V
DD
2, V
DD
3, and DV
DD
.
V
P
1RF Charge Pump Power Supply. Decoupling capacitors to the ground plane should be placed as close as possible
to this pin. This voltage should be greater than or equal to V
DD
1.
REV. B–6–
ADF4252
ADF4252
2
DOUBLER
OUTPUT
MUX
VDD
DGND
VDD
NDIV
RDIV
HIGH Z
4-BIT R
COUNTER PHASE
FREQUENCY
DETECTOR
LOCK
DETECT
CHARGE
PUMP
REFERENCE
REFIN
REFOUT
VDD1 VDD2 VDD3DVDD VP1 VP2RSET
24-BIT
DATA
REGISTER
CLK
DATA
LE
FRACTION
REG
MODULUS
REG
INTEGER
REG
N
COUNTER
THIRD ORDER
FRACTIONAL
INTERPOLATOR
RFINA
RFINB
CPRF
6-BIT IF A
COUNTER
CPIF
2
DOUBLER
15-BIT R
COUNTER
CHARGE
PUMP
PHASE
FREQUENCY
DETECTOR
12-BIT IF B
COUNTER
IF PRE-
SCALER
MUXOUT
AGND1 AGND2 DGND CPGND1 CPGND2
IFINB
IFINA
Figure 2. Detailed Functional Block Diagram
REV. B
Typical Performance Characteristics–ADF4252
–7–
TPC plots 1 to 12 attained using EVAL-ADF4252EB1;
measurements from HP8562E spectrum analyzer.
FREQUENCY
0
–60
–2kHz –1kHz 1.7518GHz 1kHz 2kHz
–10
–50
–70
–90
–30
–40
–80
–20
–100
– 99.19dBc/Hz
V
DD
= 3V, V
P
= 5V
I
CP
= 1.875mA
PFD FREQUENCY = 10MHz
CHANNEL STEP = 200kHz
LOOP BANDWIDTH = 20kHz
FRACTION = 59/100
RBW = 10Hz
REFERENCE
LEVEL = – 4.2dBm
OUTPUT POWER (dB)
TPC 1. Phase Noise Plot, Lowest Noise Mode,
1.7518 GHz RF
OUT
, 10 MHz PFD Frequency,
200 kHz Channel Step Resolution
FREQUENCY
0
–60
–2kHz –1kHz 1.7518GHz 1kHz 2kHz
–10
–50
–70
–90
–30
–40
–80
–20
–100
–90.36dBc/Hz
V
DD
= 3V, V
P
= 5V
I
CP
= 1.875mA
PFD FREQUENCY = 10MHz
CHANNEL STEP = 200kHz
LOOP BANDWIDTH = 20kHz
FRACTION = 59/100
RBW = 10Hz
REFERENCE
LEVEL = – 4.2dBm
OUTPUT POWER (dB)
TPC 2. Phase Noise Plot, Low Noise and Spur
Mode, 1.7518 GHz RF
OUT
, 10 MHz PFD Frequency,
200 kHz Channel Step Resolution
FREQUENCY
0
–60
–2kHz –1kHz 1.7518GHz 1kHz 2kHz
–10
–50
–70
–90
–30
–40
–80
–20
–100
–85.86dBc/Hz
VDD = 3V, VP = 5V
ICP = 1.875mA
PFD FREQUENCY = 10MHz
CHANNEL STEP = 200kHz
LOOP BANDWIDTH = 20kHz
FRACTION = 59/100
RBW = 10Hz
REFERENCE
LEVEL = – 4.2dBm
OUTPUT POWER (dB)
TPC 3. Phase Noise Plot, Lowest Spur Mode,
1.7518 GHz RF
OUT
, 10 MHz PFD Frequency,
200 kHz Channel Step Resolution
FREQUENCY
0
–60
–10
–50
–70
–90
–30
–40
–80
–20
–100
–50dBc@
100kHz
V
DD
= 3V, V
P
= 5V
I
CP
= 1.875mA
PFD FREQUENCY = 10MHz
CHANNEL STEP = 200kHz
LOOP BANDWIDTH = 20kHz
FRACTION = 59/100
RBW = 1kHz
REFERENCE
LEVEL = – 4.2dBm
–400kHz –200kHz 1.7518GHz 200kHz 400kHz
OUTPUT POWER (dB)
TPC 4. Spurious Plot, Lowest Noise Mode,
1.7518 GHz RF
OUT
, 10 MHz PFD Frequency,
200 kHz Channel Step Resolution
FREQUENCY
0
–60
–400kHz –200kHz 1.7518GHz 200kHz 400kHz
–10
–50
–70
–90
–30
–40
–80
–20
–100
VDD = 3V, VP = 5V
ICP = 1.875mA
PFD FREQUENCY = 10MHz
CHANNEL STEP = 200kHz
LOOP BANDWIDTH = 20kHz
FRACTION = 59/100
RBW = 1kHz
REFERENCE
LEVEL = – 4.2dBm
–51dBc@
100kHz
OUTPUT POWER (dB)
TPC 5. Spurious Plot, Low Noise and Spur Mode,
1.7518 GHz RF
OUT
, 10 MHz PFD Frequency,
200 kHz Channel Step Resolution
FREQUENCY
0
–60
–400kHz –200kHz 1.7518GHz 200kHz 400kHz
–10
–50
–70
–90
–30
–40
–80
–20
–100
VDD = 3V, VP = 5V
ICP = 1.875mA
PFD FREQUENCY = 10MHz
CHANNEL STEP = 200kHz
LOOP BANDWIDTH = 20kHz
FRACTION = 59/100
RBW = 1kHz
REFERENCE
LEVEL = – 4.2dBm
–72dBc@
100kHz
OUTPUT POWER (dB)
TPC 6. Spurious Plot, Lowest Spur Mode,
1.7518 GHz RF
OUT
, 10 MHz PFD Frequency,
200 kHz Channel Step Resolution
REV. B–8–
ADF4252
FREQUENCY
0
–60
–2kHz –1kHz 1.7518GHz 1kHz 2kHz
–10
–50
–70
–90
–30
–40
–80
–20
–100
–102dBc/Hz
VDD = 3V, VP = 5V
ICP = 1.875mA
PFD FREQUENCY = 20MHz
CHANNEL STEP = 200kHz
LOOP BANDWIDTH = 20kHz
FRACTION = 59/100
RBW = 10Hz
REFERENCE
LEVEL = – 4.2dBm
OUTPUT POWER (dB)
TPC 7. Phase Noise Plot, Lowest Noise Mode,
1.7518 GHz RF
OUT
, 20 MHz PFD Frequency,
200 kHz Channel Step Resolution
FREQUENCY
0
–60
–2kHz –1kHz 1.7518GHz 1kHz 2kHz
–10
–50
–70
–90
–30
–40
–80
–20
–100
–93.86dBc/Hz
VDD = 3V, VP = 5V
ICP = 1.875mA
PFD FREQUENCY = 20MHz
CHANNEL STEP = 200kHz
LOOP BANDWIDTH = 20kHz
FRACTION = 59/100
RBW = 10Hz
REFERENCE
LEVEL = – 4.2dBm
OUTPUT POWER (dB)
TPC 8. Phase Noise Plot, Low Noise and Spur
Mode, 1.7518 GHz RF
OUT
, 20 MHz PFD Frequency,
200 kHz Channel Step Resolution
FREQUENCY
0
–60
–2kHz
OUTPUT POWER (dB)
–1kHz 1.7518GHz 1kHz 2kHz
–10
–50
–70
–90
–30
–40
–80
–20
–100
–89.52dBc/Hz
V
DD
= 3V, V
P
= 5V
I
CP
= 1.875mA
PFD FREQUENCY = 20MHz
CHANNEL STEP = 200kHz
LOOP BANDWIDTH = 20kHz
FRACTION = 59/100
RBW = 10Hz
REFERENCE
LEVEL = – 4.2dBm
TPC 9. Phase Noise Plot, Lowest Spur Mode,
1.7518 GHz RF
OUT
, 20 MHz PFD Frequency,
200 kHz Channel Step Resolution
FREQUENCY
0
–60
OUTPUT POWER (dB)
–10
–50
–70
–90
–30
–40
–80
–20
–100
–53dBc@
100kHz
VDD = 3V, VP = 5V
ICP = 1.875mA
PFD FREQUENCY = 20MHz
CHANNEL STEP = 200kHz
LOOP BANDWIDTH = 20kHz
FRACTION = 59/100
RBW = 1kHz
REFERENCE
LEVEL = – 4.2dBm
–400kHz –200kHz 1.7518GHz 200kHz 400kHz
TPC 10. Spurious Plot, Lowest Noise Mode,
1.7518 GHz RF
OUT
, 20 MHz PFD Frequency,
200 kHz Channel Step Resolution
FREQUENCY
0
–60
–400kHz
OUTPUT POWER (dB)
–200kHz 1.7518GHz 200kHz 400kHz
–10
–50
–70
–90
–30
–40
–80
–20
–100
VDD = 3V, VP = 5V
ICP = 1.875mA
PFD FREQUENCY = 20MHz
CHANNEL STEP = 200kHz
LOOP BANDWIDTH = 20kHz
FRACTION = 59/100
RBW = 1kHz
REFERENCE
LEVEL = – 4.2dBm
–63.2dBc@
100kHz
TPC 11. Spurious Plot, Low Noise and Spur Mode,
1.7518 GHz RF
OUT
, 20 MHz PFD Frequency, 200 kHz
Channel Step Resolution
FREQUENCY
0
–60
–400kHz
OUTPUT POWER (dB)
–200kHz 1.7518GHz 200kHz 400kHz
–10
–50
–70
–90
–30
–40
–80
–20
–100
VDD = 3V, VP = 5V
ICP = 1.875mA
PFD FREQUENCY = 20MHz
CHANNEL STEP = 200kHz
LOOP BANDWIDTH = 20kHz
FRACTION = 59/100
RBW = 1kHz
REFERENCE
LEVEL = – 4.2dBm
–72.33dBc@
100kHz
TPC 12. Spurious Plot, Lowest Spur Mode,
1.7518 GHz RF
OUT
, 20 MHz PFD Frequency,
200 kHz Channel Step Resolution
REV. B
ADF4252
–9–
*Across all fractional channel steps from f = 0/130 to f = 129/130.
RF
OUT
= 1.45 GHz, Int Reg = 55, Ref = 26 MHz, and LBW = 40 kHz. Plots attained using EVAL-ADF4252EB2 evaluation board.
FREQUENCY (GHz)
–70
–120
1.430 1.4601.435
PHASE NOISE (dBc/Hz)
1.440 1.445 1.450 1.455
–75
–90
–105
–110
–115
–80
–85
–95
–100
LOWEST SPUR MODE
LOW NOISE AND SPUR MODE
LOWEST NOISE MODE
TPC 13. In-Band Phase Noise vs. Frequency*
FREQUENCY (GHz)
–10
–110
1.430 1.4601.435
SPURIOUS LEVEL (dBc)
1.440 1.445 1.450 1.455
–20
–50
–80
–90
–100
–30
–40
–60
–70
LOWEST NOISE MODE
LOWEST SPUR MODE
TPC 14. 100 kHz Spur vs. Frequency*
FREQUENCY (GHz)
–20
–120
1.430 1.4601.435
SPURIOUS LEVEL (dBc)
1.440 1.445 1.450 1.455
–30
–60
–90
–100
–110
–40
–50
–70
–80
LOWEST NOISE MODE
LOWEST SPUR MODE
TPC 15. 200 kHz Spur vs. Frequency*
FREQUENCY (GHz)
–20
–120
1.430 1.4601.435
SPURIOUS LEVEL (dBc)
1.440 1.445 1.450 1.455
–30
–60
–90
–100
–110
–40
–50
–70
–80
LOWEST NOISE MODE
LOWEST SPUR MODE
TPC 16. 400 kHz Spur vs. Frequency*
FREQUENCY (GHz)
–20
–120
1.430 1.4601.435
SPURIOUS LEVEL (dBc)
1.440 1.445 1.450 1.455
–30
–60
–90
–100
–110
–40
–50
–70
–80
LOWEST NOISE MODE
LOWEST SPUR MODE
TPC 17. 600 kHz Spur vs. Frequency*
FREQUENCY (GHz)
–20
–120
1.430 1.4601.435
SPURIOUS LEVEL (dBc)
1.440 1.445 1.450 1.455
–30
–60
–90
–100
–110
–40
–50
–70
–80
LOWEST NOISE MODE
LOWEST SPUR MODE
TPC 18. 3 MHz Spur vs. Frequency*
REV. B–10–
ADF4252
FREQUENCY (GHz)
0
–35 061
AMPLITUDE (dBm)
2345
–5
–10
–15
–25
–30
–20
PRESCALER = 4/5
PRESCALER = 8/9
TPC 19. RF Input Sensitivity
IF INPUT FREQUENCY (GHz)
0
5
35
–0.4 1.60.1
IF INPUT POWER (dBm)
0.6 1.1
15
20
25
30
10
40
VDD = 3V
VP2 = 3V
TPC 20. IF Input Sensitivity
PHASE DETECTOR FREQUENCY (Hz)
–120
–130
–180
10k 10M
100k
PHASE NOISE (dB/Hz)
1M
–150
–160
–170
–140
VDD = 3V
VP = 5V
TPC 21. Phase Noise (Referred to CP Output) vs.
PFD Frequency, RF Side
PHASE DETECTOR FREQUENCY (Hz)
–120
–130
–18010k 10M100k
PHASE NOISE (dB/Hz)
1M
–150
–160
–170
–140
V
DD
= 3V
V
P
= 3V
TPC 22. Phase Noise (Referred to CP Output) vs.
PFD Frequency, IF Side
VCP (V)
6
4
0 0.5
ICP (mA)
1.5
0
–2
–4
2
–6
VDD = 3V
VP1 = 5.5V
1.0 2.0 3.0
2.5 4.03.5 4.5 5.5
5.0
TPC 23. RF Charge Pump Output Characteristics
VCP (V)
6
4
00.5
ICP (mA)
1.5
0
–2
–4
2
–6
VDD = 3V
VP2 = 3V
1.0 2.0 3.0
2.5
TPC 24. IF Charge Pump Output Characteristics
REV. B
ADF4252
–11–
CIRCUIT DESCRIPTION
Reference Input Section
The reference input stage is shown in Figure 3. SW1 and SW2
are normally closed switches. SW3 is normally open. When
power-down is initiated, SW3 is closed and SW1 and SW2 are
opened. This ensures that there is no loading of the REF
IN
pin
on power-down.
POWER-DOWN
CONTROL
REFIN NC
NC
NO
SW3
SW2
SW1
100k
BUFFER TO R
COUNTER
NC = NORMALLY CLOSED
NO = NORMALLY OPEN
REFOUT
XOEB
Figure 3. Reference Input Stage
RF and IF Input Stage
The RF input stage is shown in Figure 4. The IF input stage is
the same. It is followed by a two-stage limiting amplifier to
generate the CML clock levels needed for the N counter.
2k2k
1.6V
BIAS
GENERATOR
RF
IN
A
RF
IN
B
V
DD
1
A
GND
Figure 4. RF Input Stage
RF INT Divider
The RF INT CMOS counter allows a division ratio in the PLL
feedback counter. Division ratios from 31 to 255 are allowed.
INT, FRAC, MOD, and R Relationship
The INT, FRAC, and MOD values, in conjunction with the
RF R counter, make it possible to generate output frequencies
that are spaced by fractions of the RF phase frequency detector
(PFD). The equation for the RF VCO frequency (RF
OUT
) is
RF F INT FRAC
MOD
OUT PFD
=× +
(1)
where RF
OUT
is the output frequency of external voltage controlled
oscillator (VCO).
FREF
D
R
PFD IN
=×
+
()
1
(2)
REF
IN
= the reference input frequency, D= RF REF
IN
doubler
bit, R= the preset divide ratio of the binary 4-bit program-
mable reference counter (1 to 15), INT = the preset divide ratio of
the binary 8-bit counter (31 to 255), MOD = the preset modulus
ratio of binary 12-bit programmable FRAC counter (2 to 4095),
and FRAC = the preset fractional ratio of the binary 12-bit
programmable FRAC counter (0 to MOD).
N = INT + FRAC/MOD
FROM RF
INPUT STAGE TO PFD
RF N DIVIDER
THIRD ORDER
FRACTIONAL
INTERPOLATOR
MOD
REG
INT
REG
FRAC
VALUE
N-COUNTER
Figure 5. N Counter
RF R Counter
The 4-bit RF R counter allows the input reference frequency
(REF
IN
) to be divided down to produce the reference clock to
the RF PFD. Division ratios from 1 to 15 are allowed.
IF R Counter
The 15-bit IF R counter allows the input reference frequency
(REF
IN
) to be divided down to produce the reference clock to
the IF PFD. Division ratios from 1 to 32767 are allowed.
IF Prescaler (P/P + 1)
The dual modulus IF prescaler (P/P + 1), along with the IF A
and B counters, enables the large division ratio, N, to be realized
(N = PB + A). Operating at CML levels, it takes the clock from
the IF input stage and divides it down to a manageable frequency
for the CMOS IF A and B counters.
IF A and B Counters
The IF A and B CMOS counters combine with the dual modulus
IF prescaler to allow a wide ranging division ratio in the PLL
feedback counter. The counters are guaranteed to work when the
prescaler output is 150 MHz or less.
Pulse Swallow Function
The IF A and B counters, in conjunction with the dual modulus
IF prescaler, make it possible to generate output frequencies
that are spaced only by the reference frequency divided by R.
See Device Programming after Initial Power-Up section for
examples. The equation for the IF VCO (IF
OUT
) frequency is
IF P B A F
OUT PFD
=×
()
+
[]
×
(3)
where IF
OUT
= the output frequency of the external voltage controlled
oscillator (VCO), P = the preset modulus of IF dual modulus
prescaler, B= the preset divide ratio of the binary 12-bit counter
(3 to 4095), and A= the preset divide ratio of the binary 6-bit
swallow counter (0 to 63). F
PFD
is obtained using Equation 2.
REV. B–12–
ADF4252
Phase Frequency Detector (PFD) and Charge Pump
The PFD takes inputs from the R counter and N counter and
produces an output proportional to the phase and frequency
difference between them. Figure 6 is a simplified schematic. The
antibacklash pulse. This pulse ensures that there is no dead zone
in the PFD transfer function and minimizes phase noise and
reference spurs.
+IN
D1
Q1
CLR1
U1
U3
DELAY
ELEMENT
HI UP
D2
Q2
CLR2
U2
HI DOWN
CHARGE
PUMP
CP
–IN
Figure 6. PFD Simplified Schematic
MUXOUT and Lock Detect
The output multiplexer on the ADF4252 allows the user to
access various internal points on the chip. The state of MUXOUT
is controlled by M4, M3, M2, and M1 in the master register.
Table I shows the full truth table. Figure 7 shows the MUXOUT
section in block diagram format.
LOGIC LOW
IF ANALOG LOCK DETECT
IF R DIVIDER OUTPUT
IF N DIVIDER OUTPUT
RF ANALOG LOCK DETECT
IF/RF ANALOG LOCK DETECT
IF DIGITAL LOCK DETECT
LOGIC HIGH
RF R DIVIDER OUTPUT
RF N DIVIDER OUTPUT
THREE STATE OUTPUT
RF DIGITAL LOCK DETECT
RF/IF DIGITAL LOCK DETECT
LOGIC HIGH
LOGIC LOW
MUX CONTROL MUXOUT
DVDD
DGND
Figure 7. MUXOUT Circuit
Lock Detect
MUXOUT can be programmed for two types of lock detect: digital
and analog. Digital is active high. The N-channel open-drain
analog lock detect should be operated with an external pull-up
resistor of 10 kΩ nominal. When lock has been detected, this
output will be high with narrow low going pulses.
Input Shift Register
Data is clocked in on each rising edge of CLK. The data is
clocked in MSB first. Data is transferred from the input register
to one of seven latches on the rising edge of LE. The destination
latch is determined by the state of the three control bits (C2, C1,
and C0) in the shift register. These are the three LSBs: DB2,
DB1, and DB0, as shown in Figure 1. The truth table for these
bits is shown in Table I. Table II summarizes how the registers
are programmed.
Table I. Control Bit Truth Table
C2 C1 C0 Data Latch
000 RF N Divider Reg
001 RF R Divider Reg
010 RF Control Reg
011 Master Reg
100 IF N Divider Reg
101 IF R Divider Reg
110 IF Control Reg
REV. B
ADF4252
–13–
Table II. Register Summary
RF CONTROL REG
DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
C2 (0) C1 (0)A1A2A3A4A5B1B2B3B4B5B6B7B8B9B10B11B12P13 A6
6-BIT IF A COUNTER12-BIT IF B COUNTER
DB21
IF PRESCALER
DB22DB23
IF CP GAIN
P14P15 C3 (1)
DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
C2 (0) C1 (1)R1R2R3R4R5R6R7R8R9R10R11R12R13R15P16
15-BIT IF R COUNTER
C3 (1)R14
IF REF
IN
DOUBLER
RF N DIVIDER REG
IF R DIVIDER REG
RF R DIVIDER REG
DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
C2 (0) C1 (1)
M1
M2M3
M4M5
M6
M7
M8
M9M10
M11M12
R1R3
R4
P2
P3
12-BIT INTERPOLATOR MODULUS VALUE (MOD)
C3 (0)
4-BIT RF R COUNTER
R2
PRESCALER
RF REF
IN
DOUBLER
MASTER REG
IF N DIVIDER REG
IF CONTROL REG
DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
C2 (1) C1 (1)P9P10P11P12M1M2M3M4
MUXOUT
C3 (0)
XO
DISABLE
POWER-
DOWN
CP THREE-
STATE
COUNTER
RESET
DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10
DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
C2 (0)
C1 (0)
F1F2F3F4F5F6F7
F8
F9F10F11F12N1N3
N4N5
N6
CONTROL
BITS
12-BIT RF FRACTIONAL VALUE (FRAC)
DB23 DB22
DB21
N7
RESERVED
N8
P1
C3 (0)
8-BIT RF INTEGER VALUE (INT)
N2
DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
C2 (1) C1 (0)P4P5P6N1P8 0CP1CP2N2T1T2T3N3
RF CP
CURRENT
SETTING
RF PD
POLARITY
C3 (0)
RESERVED
NOISE AND
SPUR
SETTING 1
RF
POWER-
DOWN
RF CP
THREE-
STATE
RF
COUNTER
RESET
RESERVED
NOISE AND
SPUR
SETTING 2
NOISE AND
SPUR
SETTING 3
DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
C2 (1) C1 (0)P17P18P19P20P21CP1CP2CP3PR1T7T8PR2PR3
IF CP CURRENT
IF PD
POLARITY
C3 (1)
RESERVED
IF LDP
IF POWER-
DOWN
IF CP
THREE-
STATE
IF
COUNTER
RESET
RF PHASE
RESYNC
RF PHASE
RESYNC SETTING
CONTROL
BITS
CONTROL
BITS
CONTROL
BITS
CONTROL
BITS
CONTROL
BITS
CONTROL
BITS
REV. B–14–
ADF4252
Table III. RF N Divider Register Map
F12 F11 F10 F3 F2 F1 FRACTIONAL VALUE (FRAC)
000.......... 0 0 0 0
000.......... 0 0 1 1
000.......... 0 1 0 2
000.......... 0 1 1 3
............. . . . .
............. . . . .
............. . . . .
111.......... 1 0 0 4092
111.......... 1 0 1 4093
111.......... 1 1 0 4094
111.......... 1 1 1 4095
RF INTEGER
N8 N7 N6 N5 N4 N3 N2 N1
00011111 31
00100000 32
00100001 33
00100010 34
........ .
........ .
........ .
11111101 253
11111110 254
11111111 255
P1
0
DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
C2 (0) C1 (0)F1F2F3F4F5F6F7
F8
F9F10F11F12N1N3
N4N5
N6
CONTROL
BITS
12-BIT RF FRACTIONAL VALUE (FRAC)
DB23 DB22 DB21
N7
N8
P1 C3 (0)
8-BIT RF INTEGER VALUE (INT)
N2
RESERVED
VALUE (INT)*
*WHEN P = 8/9, NMIN = 91
RESERVED
RESERVED
REV. B
ADF4252
–15–
Table IV. RF R Divider Register Map
INTERPOLATOR MODULUS
M12 M11 M10 M3 M2 M1 VALUE (MOD) DIVIDE RATIO
000.......... 0102
000.......... 0113
000.......... 1004
............. ....
............. ....
............. ....
111.......... 1004092
111.......... 1014093
111.......... 1104094
111.......... 1114095
RF R COUNTER
R4 R3 R2 R1 DIVIDE RATIO
00011
00102
00113
.....
.....
.....
110113
111014
111115
P2 RF REF
IN
DOUBLER
0DISABLED
1ENABLED
DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
C2 (0) C1 (1)
M1M2M3M4M5M6M7
M8
M9M10M11M12R1R3R4P2
P3
CONTROL
BITS
12-BIT INTERPOLATOR MODULUS VALUE (MOD)
C3 (0)
4-BIT RF R COUNTER
R2
RF REF
IN
DOUBLER
PRE-
SCALER
P3 RF PRESCALER
0 4/5
1 8/9
REV. B–16–
ADF4252
Table V. RF Control Register Map
P6 RF POWER-DOWN
0DISABLED
1ENABLED
DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
C2 (1) C1 (0)P4P5P6N1P8 0CP1
CP2
N2T1T2T3N3
CONTROL
BITS
RF CP
CURRENT
SETTING
RF PD
POLARITY
C3 (0)
RESERVED
NOISE AND
SPUR
SETTING 1
RF POWER-
DOWN
RF CP
THREE-
STATE
RF
COUNTER
RESET
RESERVED
NOISE AND
SPUR
SETTING 2
NOISE AND
SPUR
SETTING 3
ICP (mA)
CP2 CP1 1.5k 2.7k 5.6k
001.125 0.625 0.301
013.375 1.875 0.904
105.625 3.125 1.506
117.7875 4.375 2.109
P8 RF PD POLARITY
0NEGATIVE
1POSITIVE
P5 RF CP THREE-STATE
0DISABLED
1THREE-STATE
P4 RF COUNTER
RESET
0DISABLED
1ENABLED
N3 N2 N1 NOISE AND SPUR
SETTING
000LOWEST SPUR
001LOW NOISE AND SPUR
111LOWEST NOISE
THESE BITS SHOULD
EACH BE SET TO 0 FOR
NORMAL OPERATION
REV. B
ADF4252
–17–
Table VI. Master Register Map
P11
0
1
P12
0 XO ENABLED (REF
OUT
= REF
IN
)
1 XO DISABLED (REF
OUT
= LOGIC LOW)
(REF
OUT
= LOGIC HIGH WHEN IN POWER-DOWN)
P10
0
1
P9
0
1
0 0 0 0 LOGIC LOW
0 0 0 1 IF ANALOG LOCK DETECT
0 0 1 0 IF R DIVIDER OUTPUT
0 0 1 1 IF N DIVIDER OUTPUT
0 1 0 0 RF ANALOG LOCK DETECT
0 1 0 1 RF/IF ANALOG LOCK DETECT
0 1 1 0 IF DIGITAL LOCK DETECT
0 1 1 1 LOGIC HIGH
1 0 0 0 RF R DIVIDER OUTPUT
1 0 0 1 RF N DIVIDER OUTPUT
1 0 1 0 THREE-STATE OUTPUT
1 0 1 1 LOGIC LOW
1 1 0 0 RF DIGITAL LOCK DETECT
1 1 0 1 RF/IF DIGITAL LOCK DETECT
1 1 1 0 LOGIC HIGH
1 1 1 1 LOGIC LOW
DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
C2 (1) C1 (1)P9P10P11P12M1M2M3M4
CONTROL
BITS
MUXOUT
C3 (0)
XO
DISABLE
POWER-
DOWN
CP THREE-
STATE
COUNTER
RESET
MUXOUT
M1
M2M3
M4 COUNTER RESET
DISABLED
ENABLED
CP THREE-STATE
DISABLED
THREE-STATE
POWER-DOWN
DISABLED
ENABLED
XO DISABLE
REV. B–18–
ADF4252
Table VII. IF N Divider Register Map
B12 B11 B10 B3 B2 B1 B COUNTER DIVIDE RATIO
000.......... 0113
000.......... 1004
............. ....
............. ....
............. ....
111.......... 1004092
111.......... 1014093
111.......... 1104094
111.......... 1114095
A COUNTER
A6 A5 .......... A2 A1 DIVIDE RATIO
00.......... 0 0 0
00.......... 0 1 1
00.......... 1 0 2
00.......... 1 1 3
............ . . .
............ . . .
............ . . .
11.......... 0 0 60
11.......... 0 1 61
11.......... 1 0 62
11.......... 1 1 63
*N = BP + A, P IS PRESCALER VALUE. B MUST BE GREATER THAN OR EQUAL TO A FOR CONTIGUOUS VALUES OF N, NMIN IS (P2 – P) .
P14 P13 PRESCALER VALUE
00 8/9
01 16/17
10 32/33
11 64/65
P15 IF CP GAIN
0DISABLED
1ENABLED
DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
C2 (0) C1 (0)
A1A2A3A4A5B1B2B3B4B5B6B7B8B9B10B11B12P13 A6
CONTROL
BITS
6-BIT IF A COUNTER*12-BIT IF B COUNTER*
DB21
IF
PRESCALER*
DB22DB23
IF CP
GAIN
P14
P15 C3 (1)
REV. B
ADF4252
–19–
Table VIII. IF R Divider Register Map
R14 R13 R12 .......... R3 R2 R1 DIVIDE RATIO
000.......... 0011
000.......... 0102
000.......... 0113
000.......... 1004
............. ....
............. ....
............. ....
111.......... 10016380
111.......... 10116381
111.......... 11016382
111.......... 11116383
P16 IF REF
IN
DOUBLER
0DISABLED
1ENABLED
DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
C2 (0) C1 (1)R1R2R3R4R5R6R7
R8
R9R10R11R12R13R15P16
CONTROL
BITS
15-BIT IF R COUNTER
C3 (1)
R14
IF REF
IN
DOUBLER
R15
0
0
0
0
.
.
.
32764
32765
32766
32767
REV. B–20–
ADF4252
Table IX. IF Control Register Map
P19 IF POWER-DOWN
0DISABLED
1ENABLED
P20 IF LDP
03
15
IF CP3 IF CP2 IF CP1 1.5k 2.7k 5.6k
000 1.125 0.625 0.301
001 2.25 1.25 0.602
010 3.375 1.875 0.904
011 4.5 2.5 1.205
100 5.625 3.125 1.506
101 6.75 3.75 1.808
110 7.7875 4.375 2.109
11195.0 2.411
P21 IF PD POLARITY
0NEGATIVE
1POSITIVE
P18 IF CP THREE-STATE
0DISABLED
1THREE-STATE
P17 IF COUNTER RESET
0DISABLED
1ENABLED
DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
C2 (1) C1 (0)P17P18P19P20P21CP1CP2
CP3
PR1T7T8PR2PR3
CONTROL
BITS
IF CP CURRENT
SETTING
IF PD
POLARITY
C3 (1)
RESERVED
IF LDP
IF POWER-
DOWN
IF CP
THREE-
STATE
IF
COUNTER
RESET
RF PHASE
RESYNC
RF PHASE
RESYNC
THESE BITS
SHOULD BE SET
TO 0 FOR NORMAL
OPERATION
PR3 PR2 PR1 RF PHASE RESYNC
000DISABLED
111ENABLED
ICP (mA)
REV. B
ADF4252
–21–
RF N DIVIDER REGISTER
(Address R0)
With R0[2, 1, 0] set to [0, 0, 0], the on-chip RF N divider register
will be programmed. Table III shows the input data format for
programming this register.
8-Bit RF INT Value
These eight bits control what is loaded as the INT value. This is
used to determine the overall feedback division factor. It is used in
Equation 1.
12-Bit RF FRAC Value
These 12 bits control what is loaded as the FRAC value into the
fractional interpolator. This is part of what determines the overall
feedback division factor. It is used in Equation 1. The FRAC
value must be less than or equal to the value loaded into the
MOD register.
RF R DIVIDER REGISTER
(Address R1)
With R1[2, 1, 0] set to [0, 0, 1], the on-chip RF R divider register
will be programmed. Table IV shows the input data format for
programming this register.
RF Prescaler (P/P + 1)
The RF dual-modulus prescaler (P/P +1), along with the INT,
FRAC, and MOD counters, determine the overall division ratio
from the RF
IN
to the PFD input. Operating at CML levels, it
takes the clock from the RF input stage and divides it down to
amanageable frequency for the CMOS counters. It is based on
a synchronous 4/5 core (see Table IV).
RF REFIN Doubler
Setting this bit to 0 feeds the REF
IN
signal directly to the 4-bit
RF R counter, disabling the doubler. Setting this bit to 1 multiplies
the REF
IN
frequency by a factor of 2 before feeding into the
4-bit RF R counter. When the doubler is disabled, the REF
IN
falling edge is the active edge at the PFD input to the fractional-N
synthesizer. When the doubler is enabled, both the rising and
falling edges of REF
IN
become active edges at the PFD input.
When the doubler is enabled and lowest spur mode is chosen,
the in-band phase noise performance is sensitive to the REF
IN
duty cycle. The phase noise degradation can be as much as 5 dB
for REF
IN
duty cycles outside a 45% to 55% range. The phase
noise is insensitive to REF
IN
duty cycle in the lowest noise mode
and in low noise and spur mode. The phase noise is insensitive
to REF
IN
duty cycle when the doubler is disabled.
4-Bit RF R Counter
The 4-bit RF R counter allows the input reference frequency
(REF
IN
) to be divided down to produce the reference clock to
the phase frequency detector (PFD). Division ratios from 1 to
15 are allowed.
12-Bit Interpolator Modulus
This programmable register sets the fractional modulus. This is
the ratio of the PFD frequency to the channel step resolution on
the RF output.
RF CONTROL REGISTER
(Address R2)
With R2[2, 1, 0] set to [0, 1, 0], the on-chip RF control register
will be programmed. Table V shows the input data format for
programming this register. Upon initialization, DB15–DB11
should all be set to 0.
Noise and Spur Setting
The noise and spur setting (R2[15, 11, 06]) is a feature that
allows the user to optimize his or her design either for improved
spurious performance or for improved phase noise performance.
When set to [0, 0, 0], the lowest spurs setting is chosen. Here,
dither is enabled. This randomizes the fractional quantization
noise so that it looks more like white noise than spurious noise.
This means that the part is optimized for improved spurious
performance. This operation would normally be used when the
PLL closed-loop bandwidth is wide
1
, for fastlocking applications.
A wide-loop filter does not attenuate the spurs to a level that a
narrow-loop
2
bandwidth would. When this bit is set to [0, 0, 1],
the low noise and spur setting is enabled. Here, dither is disabled.
This optimizes the synthesizer to operate with improved noise
performance. However, the spurious performance is degraded in
this mode compared to lowest spurs setting. To improve noise
performance even further, another option is available that reduces
the phase noise. This is the lowest noise setting [1, 1, 1]. As well
as disabling the dither, it also ensures the charge pump is oper-
ating in an optimum region for noise performance. This setting is
extremely useful where a narrow-loop filter bandwidth is available.
The synthesizer ensures extremely low noise and the filter attenu-
ates the spurs. The Typical Performance Characteristics (TPCs)
give the user an idea of the trade-off in a typical WCDMA setup
for the different noise and spur settings.
RF Counter Reset
DB3 is the RF counter reset bit for the ADF4252. When this is
1, the RF synthesizer counters are held in reset. For normal
operation, this bit should be 0.
RF Charge Pump Three-State
This bit puts the charge pump into three-state mode when pro-
grammed to a 1. It should be set to 0 for normal operation.
RF Power-Down
DB5 on the ADF4252 provides the programmable power-down
mode. Setting this bit to a 1 will perform a power-down on both
the RF and IF sections. Setting this bit to 0 will return the RF
and IF sections to normal operation. While in software
power-down, the part will retain all information in its registers.
Only when supplies are removed will the register contents be lost.
When a power-down is activated, the following events occur:
1. All active RF dc current paths are removed.
2. The RF synthesizer counters are forced to their load state
conditions.
3. The RF charge pump is forced into three-state mode.
4. The RF digital lock detect circuitry is reset.
5. The RF
IN
input is debiased.
6. The input register remains active and capable of loading and
latching data.
NOTES
1
Wide-loop bandwidth is seen as a loop bandwidth greater than 1/10th of the
RF
OUT
channel step resolution (F
RES
).
2
Narrow-loop bandwidth is seen as a loop bandwidth less than 1/10th of the
RF
OUT
channel step resolution (F
RES
).
REV. B–22–
ADF4252
RF Phase Detector Polarity
DB7 in the ADF4252 sets the RF phase detector polarity.
When the VCO characteristics are positive, this should be set to
1. When they are negative, it should be set to 0.
RF Charge Pump Current Setting
DB9 and DB10 set the RF charge pump current setting. This
should be set to whatever charge pump current the loop filter
has been designed with (see Table V).
RF Test Modes
These bits should be set to 0, 0, 0 for normal operation.
MASTER REGISTER
(Address R3)
With R3[2, 1, 0] set to 0, 1, 1, the on-chip master register will be
programmed. Table VI shows the input data format for program-
ming the master register.
RF and IF Counter Reset
DB3 is the counter reset bit for the ADF4252. When this is 1,
both the RF and IF R, INT, and MOD counters are held in reset.
For normal operation, this bit should be 0. Upon power-up, the
DB3 bit needs to be disabled, the INT counter resumes counting
in “close” alignment with the R counter. (The maximum error is
one prescaler cycle).
Charge Pump Three-State
This bit puts both the RF and IF charge pump into three-state
mode when programmed to a 1. It should be set to 0 for normal
operation.
Power-Down
R3[3] on the ADF4252 provides the programmable power-down
mode. Setting this bit to a 1 will perform a power-down on both
the RF and IF sections. Setting this bit to 0 will return the RF
and IF sections to normal operation. While in software power-
down, the part will retain all information in its registers. Only
when supplies are removed will the register contents be lost.
When a power-down is activated, the following events occur:
1. All active dc current paths are removed.
2. The RF and IF counters are forced to their load state conditions.
3. The RF and IF charge pumps are forced into three-state mode.
4. The digital lock detect circuitry is reset.
5. The RF
IN
input and IF
IN
input are debiased.
6. The oscillator input buffer circuitry is disabled.
7. The input register remains active and capable of loading and
latching data.
XO Disable
Setting this bit to 1 disables the REF
OUT
circuitry. This will
be set to 1 when using an external TCXO, VCXO, or other
reference sources. This will be set to 0 when using the REF
IN
and REF
OUT
pins to form an oscillator circuit.
MUXOUT Control
The on-chip multiplexer is controlled by R3[10–7] on the
ADF4252. Table VI shows the truth table.
If the user updates the RF control register or the IF control
register, the MUXOUT contents will be lost. To retrieve the
MUXOUT signal, the user must write to the master register.
Lock Detect
The digital lock detect output goes high if there are 40 successive
PFD cycles with an input error of less than 15 ns. It stays high
until a new channel is programmed or until the error at the PFD
input exceeds 30 ns for one or more cycles. If the loop bandwidth
is narrow compared to the PFD frequency, the error at the PFD
inputs may drop below 15 ns for 40 cycles around a cycle slip; thus
the digital lock detect may go falsely high for a short period until
the error again exceeds 30 ns. In this case the digital lock detect is
reliable only as a “loss of lock” indicator.
IF N DIVIDER REGISTER
(Address R4)
With R4[2, 1, 0] set to [1, 0, 0], the on-chip IF N divider register
will be programmed. Table VII shows the input data format for
programming this register.
IF CP Gain
When set to 1, this bit changes the IF charge pump current
setting to its maximum value. When the bit is set to 0, the
charge pump current reverts back to its previous state.
IF Prescaler
The dual-modulus prescaler (P/P + 1), along with the IF A and
Bcounters, determine the overall division ratio, N, to be realized
(N = PB + A) from the IF
IN
to the IF PFD input. Operating at
CML levels, it takes the clock from the IF input stage and divides it
down to a manageable frequency for the CMOS counters. It is
based on a synchronous 4/5 core. See Equation 2 and Table VII.
IF B and A Counter
The IF A and B counters, in conjunction with the dual modulus
prescaler, make it possible to generate output frequencies that
are spaced only by the reference frequency (REF
IN
) divided
by R. The equation for the IF
OUT
VCO frequency is given in
Equation 2.
IF R DIVIDER REGISTER
(Address R5)
With R5[2, 1, 0] set to [1, 0, 1], the on-chip IF R divider register
will be programmed. Table VIII shows the input data format for
programming this register.
IF REFIN Doubler
Setting this bit to 0 feeds the REF
IN
signal directly to the 15-bit
IF R counter. Setting this bit to 1 multiplies the REF
IN
frequency by a factor of 2 before feeding into the 15-bit IF R
counter.
15-Bit IF R Counter
The 15-bit IF R counter allows the input reference frequency
(REF
IN
) to be divided down to produce the reference clock to
the IF phase frequency detector (PFD). Division ratios from
1to 32767 are allowed.
IF CONTROL REGISTER
(Address R6)
With R6[2, 1, 0] set to [1, 1, 0], the on-chip IF control register
will be programmed. Table IX shows the input data format for
programming this register. Upon initialization, DB15–DB11
should all be set to 0.
REV. B
ADF4252
–23–
IF Counter Reset
DB3 is the IF counter reset bit for the ADF4252. When this is
1, the IF synthesizer counters are held in reset. For normal
operation, this bit should be 0.
IF Charge Pump Three-State
This bit puts the IF charge pump into three-state mode when pro-
grammed to a 1. It should be set to 0 for normal operation.
IF Power-Down
DB5 on the ADF4252 provides the programmable power-down
mode. Setting this bit to a 1 will perform a power-down on the IF
section. Setting this bit to 0 will return the section to normal
operation. While in software power-down, the part will retain all
information in its registers. Only when supplies are removed will
the register contents be lost.
When a power-down is activated, the following events occur:
1. All active IF dc current paths are removed.
2. The IF synthesizer counters are forced to their load state
conditions.
3. The IF charge pump is forced into three-state mode.
4. The IF digital lock detect circuitry is reset.
5. The IF
IN
input is debiased.
6. The input register remains active and capable of loading and
latching data.
IF Phase Detector Polarity
DB7 in the ADF4252 sets the IF phase detector polarity. When
the VCO characteristics are positive, this should be set to 1.
When they are negative, it should be set to 0.
IF Charge Pump Current Setting
DB8, DB9, and DB10 set the IF charge pump current setting.
This should be set to whatever charge pump current the loop
filter has been designed with (see Table VII).
IF Test Modes
These bits should be set to [0, 0] for normal operation.
RF Phase Resync
Setting the phase resync bits [15, 14, 11] to [1, 1, 1] enables
the phase resync feature. With a fractional modulus of M, a
fractional-N PLL can settle with any one of (2 )/M valid
phase offsets with respect to the reference input. This is different
to integer-N (where the RF output always settles to the same
static phase offset with respect to the input reference, which is
zero ideally) but does not matter in most applications where all
that is required is consistent frequency lock.
For applications where a consistent phase relationship between
the output and reference is required (i.e., digital beamforming),
the ADF4252 fractional-N synthesizer can be used with the phase
resync feature enabled. This ensures that if the user programs
the PLL to jump from Frequency (and Phase) A to Frequency
(and Phase) B and back again to Frequency A, the PLL will return
to the original phase (Phase A).
When enabled, it will activate every time the user programs
Register R0 or R1 to set a new output frequency. However if a
cycle slip occurs in the settling transient after the phase re-resync
operation, the phase resync will be lost. This can be avoided by
delaying the resync activation until the locking transient is close
to its final frequency. In the IF R divider register, Bits R5[17–3]
are used to set a time interval from when the new channel is pro-
grammed to the time the resync is activated. Although the time
interval resolution available from the 15-bit IF R register is one
REF
IN
clock cycle, IF R should be programmed to be a value that
is an integer multiple of the programmed MOD value to set a
time interval that is at least as long as the RF PLL loop’s lock time.
For example, if REF
IN
= 26 MHz, MOD = 130 to give 200 kHz
output steps (F
RES
), and the RF loop has a settling time of 150 µs,
then IF_R should be programmed to 3900, as
26 150 3900 MHz s×=µ
Note that if it is required to use the IF synthesizer with phase
resync enabled on the RF synth, the IF synth must operate with
a PFD frequency of 26 MHz/3900. In an application where the
IF synth is not required, the user should ensure that Registers
R4 and R6 are not programmed so that the rest of the IF circuitry
remains in power-down.
DEVICE PROGRAMMING AFTER INITIAL POWER-UP
After initially applying power to the supply pins, there are three
ways to operate the device.
RF and IF Synthesizers Operational
All registers must be written to when powering up both the RF
and IF synthesizer.
RF Synthesizer Operational, IF Power-Down
It is necessary to write only to Registers R3, R2, R1, and R0
when powering up the RF synthesizer only. The IF side will
remain in power-down until Registers R6, R5, R4, and R3 are
written to.
IF Synthesizer Operational, RF Power-Down
It is necessary to write to only Registers R6, R5, R4, and R3 when
powering up the IF synthesizer only. The RF side will remain in
power-down until registers R3, R2, R1, and R0 are written to.
RF Synthesizer: An Example
The RF synthesizer should be programmed as follows:
RF INT FRAC
MOD F
OUT PFD
=+
×
(4)
where RF
OUT
= the RF frequency output, INT = the integer division
factor, FRAC = the fractionality, and MOD = the modulus.
F REF D
R
PFD IN
=×
+
1
(5)
where REF
IN
= the reference frequency input, D = the RF
REF
IN
doubler bit, and R = the RF reference division factor.
For example, in a GSM 1800 system where 1.8 GHz RF frequency
output (RF
OUT
) is required, a 13 MHz reference frequency input
(REF
IN
) is available and a 200 kHz channel resolution (F
RES
) is
required on the RF output.
MOD
REF
F
MOD
IN
RES
=
==
13
200 65
MHz
kHz
REV. B–24–
ADF4252
So, from Equation 5:
FMHz
PFD
=×
+=
=×
13 10
113
18 13
MHz
. GHz MHz INT + FRAC
65
where INT = 138 and FRAC = 30.
IF Synthesizer: An Example
The IF synthesizer should be programmed as follows:
IF P B A F
OUT PFD
=×
()
+
[]
×
(6)
where IF
OUT
= the output frequency of external voltage controlled
oscillator (VCO), P = the IF prescaler, B = the B counter value,
and A = the A counter value.
Equation 5 applies in this example as well.
For example, in a GSM1800 system, where 540 MHz IF fre-
quency output (IF
OUT
) is required, a 13 MHz reference frequency
input (REF
IN
) is available and a 200 kHz channel resolution
(F
RES
) is required on the IF output. The prescaler is set to 16/17.
IF REF
IN
doubler is disabled.
By Equation 5,
200 13 10
kHz MHz=×
+
R
if R = 65.
By Equation 6,
540 200 16 MHz kHz=××
()
+
[]
BA
if B = 168 and A = 12.
Modulus
The choice of modulus (MOD) depends on the reference signal
(REF
IN
) available and the channel resolution (F
RES
) required at
the RF output. For example, a GSM system with 13 MHz
REF
IN
would set the modulus to 65. This means that the RF
output resolution (F
RES
) is the 200 kHz (13 MHz/65) necessary
for GSM.
Reference Doubler and Reference Divider
There is a reference doubler on-chip, which allows the input
reference signal to be doubled. This is useful for increasing the
PFD comparison frequency. Making the PFD frequency higher
improves the noise performance of the system. Doubling the
PFD frequency will usually result in an improvement in noise
performance of 3 dB. It is important to note that the PFD can-
not be operated above 30 MHz due to a limitation in the speed
of the - circuit of the N divider.
12-Bit Programmable Modulus
Unlike most other fractional-N PLLs, the ADF4252 allows the
user to program the modulus over a 12-bit range. This means
that the user can set up the part in many different configurations
for a specific application, when combined with the reference
doubler and the 4-bit R counter.
For example, in an application that requires 1.75 GHz RF and
200 kHz channel step resolution, the system has a 13 MHz
reference signal.
One possible setup is feeding the 13 MHz directly to the PFD
and programming the modulus to divide by 65. This results in
the required 200 kHz resolution.
Another possible setup is using the reference doubler to create
26 MHz from the 13 MHz input signal. This 26 MHz is then
fed into the PFD. The modulus is now programmed to divide by
130, which also results in 200 kHz resolution. This offers supe-
rior phase noise performance over the previous setup.
The programmable modulus is also very useful for multistandard
applications. If a dual-mode phone requires PDC and GSM1800
standards, the programmable modulus is a huge benefit. PDC
requires 25 kHz channel step resolution, whereas GSM1800
requires 200 kHz channel step resolution. A 13 MHz reference
signal could be fed directly to the PFD. The modulus would
then be programmed to 520 when in PDC mode (13 MHz /520 =
25 kHz). The modulus would be reprogrammed to 65 for
GSM1800 operation (13 MHz/65 = 200 kHz). It is important
that the PFD frequency remains constant (13 MHz). This allows
the user to design one loop filter that can be used in both setups
without any stability issues. It is the ratio of the RF frequency to
the PFD frequency that affects the loop design. Keeping this
relationship constant, and instead changing the modulus factor,
results in a stable filter.
Spurious Optimization and Fastlock
As mentioned in the Noise and Spur Setting section, the part can
be optimized for spurious performance. However, in fastlocking
applications, the loop bandwidth needs to be wide. Therefore,
the filter does not provide much attenuation of the spurious. The
programmable charge pump can be used to avoid this issue. The
filter is designed for a narrow-loop bandwidth so that steady-state
spurious specifications are met. This is designed using the low-
est charge pump current setting. To implement fastlock during
a frequency jump, the charge pump current is set to the maxi-
mum setting for the duration of the jump. This has the effect of
widening the loop bandwidth, which improves lock time. When the
PLL has locked to the new frequency, the charge pump is again
programmed to the lowest charge pump current setting. This
will narrow the loop bandwidth to its original cutoff frequency
to allow for better attenuation of the spurious than the wide-loop
bandwidth.
Spurious Signals—Predicting Where They Will Appear
Just as in integer-N PLLs, spurs will appear at PFD frequency
offsets on either side of the carrier (and multiples of the PFD
frequency). In a fractional-N PLL, spurs will also appear at
frequencies equal to the RF
OUT
channel step resolution (F
RES
).
The ADF4252 uses a high order fractional interpolator engine,
which results in spurs also appearing at frequencies equal to
half of the channel step resolution. For example, examine the
GSM1800 setup with a 26 MHz PFD and 200 kHz resolution.
Spurs will appear at ±26 MHz from the RF carrier (at an
extremely low level due to filtering). Also, there will be spurs at
±200 kHz from the RF carrier. Due to the fractional interpolator
architecture used in the ADF4252, spurs will also appear at
REV. B
ADF4252
–25–
±100 kHz from the RF carrier. Harmonics of all spurs mentioned
will also appear. With the lowest spur setting enabled, the spurs
will be attenuated into the noise floor.
Prescaler
The prescaler limits the INT value. With P = 4/5, Nmin = 31.
With P = 8/9, Nmin = 91.
The prescaler can also influence the phase noise performance.
If INT < 91, a prescaler of 4/5 should be used. For applications
where INT > 91, P = 8/9 should be used for optimum noise
performance.
Filter Design—ADIsimPLL
A filter design and analysis program is available to help users
implement their PLL design. Visit www.analog.com/pll for a
free download of the ADIsimPLL software. The software
designs, simulates, and analyzes the entire PLL frequency
domain and time domain response. Various passive and active
filter architectures are allowed.
INTERFACING
The ADF4252 has a simple SPI compatible serial interface for
writing to the device. SCLK, SDATA, and LE control the data
transfer. When LE (latch enable) goes high, the 24 bits that have
been clocked into the input register on each rising edge of SCLK
will be transferred to the appropriate latch. See Figure 1 for the
Timing Diagram and Table I for the Control Bit Truth Table.
The maximum allowable serial clock rate is 20 MHz, which
means that the maximum update rate possible for the device is
833 kHz or one update every 1.2 µs. This is certainly more than
adequate for systems that will have typical lock times in hun-
dreds of microseconds.
ADuC812 ADF4252
SCLK
SDATA
LE
CE
MUXOUT
(LOCK DETECT)
SCLOCK
MOSI
I/O PORTS
Figure 8. ADuC812 to ADF4252 Interface
ADuC812 Interface
Figure 8 shows the interface between the ADF4252 and the
ADuC812 microconverter. Since the ADuC812 is based on
an 8051 core, this interface can be used with any 8051 based
microcontroller. The microconverter is set up for SPI master
mode with CPHA = 0. To initiate the operation, the I/O port
driving LE is brought low. Each latch of the ADF4252 needs
(at most) a 24-bit word. This is accomplished by writing three
8-bit bytes from the microconverter to the device. When the third
byte has been written, the LE input should be brought high to
complete the transfer.
I/O port lines on the ADuC812 are also used to control power-
down (CE input) and to detect lock (MUXOUT configured as
lock detect and polled by the port input).
When operating in the mode described, the maximum SCLOCK
rate of the ADuC812 is 4 MHz. This means that the maximum
rate at which the output frequency can be changed will be 166 kHz.
ADSP-21xx
ADF4252
SCLK
SDATA
LE
CE
MUXOUT
(LOCK DETECT)
SCLK
DT
I/O FLAGS
TFS
Figure 9. ADSP-21xx to ADF4252 Interface
ADSP-2181 Interface
Figure 9 shows the interface between the ADF4252 and the
ADSP-21xx digital signal processor. Each latch of the ADF4252
needs (at most) a 24-bit word. The easiest way to accomplish this
using the ADSP-21xx family is to use the autobuffered transmit
mode of operation with alternate framing. This provides a means
for transmitting an entire block of serial data before an interrupt is
generated. Set up the word length for eight bits and use three memory
locations for each 24-bit word. To program each 24-bit latch, store
the three 8-bit bytes, enable the autobuffered mode, and then write
to the transmit register of the DSP. This last operation initiates the
autobuffer transfer.
PCB DESIGN GUIDELINES FOR CHIP SCALE PACKAGE
The leads on the chip scale package (CP-24) are rectangular. The
printed circuit board pad for these should be 0.1 mm longer than
the package land length and 0.05 mm wider than the package land
width. The land should be centered on the pad. This will ensure
that the solder joint size is maximized.
The bottom of the chip scale package has a central thermal pad.
The thermal pad on the printed circuit board should be at least
as large as this exposed pad. On the printed circuit board, there
should be a clearance of at least 0.25 mm between the thermal
pad and the inner edges of the pad pattern. This will ensure that
shorting is avoided.
Thermal vias may be used on the printed circuit board thermal pad
to improve thermal performance of the package. If vias are used,
they should be incorporated in the thermal pad at 1.2 mm pitch
grid. The via diameter should be between 0.3 mm and 0.33 mm,
and the via barrel should be plated with 1 oz copper to plug the via.
The user should connect the printed circuit board to A
GND
.
REV. B–26–
ADF4252
IF
OUT
J6
C15
100pF
R12
18
R13
18C16
100pF VCO2
RF
OUT
VCC
V
IN
10
14
2
C4
10pF
C3
22F
6.3V
R48
0
VVCO
R17
13k
C20
82pF
C19
2.2nF
C18
270pF
R16
7.5k
R15
51
C17
100pF
R14
18
C10
10pF
C9
22F
6.3V
R44
0
V
P
C6
10pF
C5
22F
6.3V
C8
10pF
C7
22F
6.3V
V
DD
1
V
DD
2
V
DD
3
DV
DD
V
P
2
CP
IF
IF
IN
A
R43
0
R1
20
VDD’
V
DD
RF
OUT
J7
C27
100pF
R22
18
R21
18
C26
100pF
VCO1
RF
OUT
VCC
V
IN
10
14
2
C30
10pF
C29
22F
6.3V
R49
0
VVCO
R20
470
C25
3.3nF
C24
100nF
C23
10nF
R19
270
R24
51
C28
100pF
R23
18
C12
10pF
C11
22F
6.3V
V
P
V
P
1
CP
RF
RF
IN
A
C44
100pF
CP
GND
1
RF
IN
B
A
GND
1
D
GND
A
GND
2
CP
GND
2
MUXOUT
R27
10k
T16 R28
10k
R29
10k
D4
V
DD
CLK
C43
100pF
R27
2.7k
DATA
LE
T14
R39
0
R26
1k
R4
1M
R11
51
Y2
10MHz
C31
33pF
C32
33pF
C14
1nF
C13
1nF
REF
IN
J5 T13
R47
0
Y3
B+
O/P
4
3
2
GND
C45
10pF
C46
22F
R46
0
R45
0
3V
5V
U1
ADF4252BCP
REF
OUT
J8
R38
0
U6
1
2
4
VCC
R35
0
R34
0
5V
3V
VCO190–540T VCO190–1730T
Figure 10. Typical PLL Circuit Schematic
REV. B
ADF4252
–27–
OUTLINE DIMENSIONS
24-Lead Lead Frame Chip Scale Package [LFCSP]
(CP-24)
Dimensions shown in millimeters
1
24
6
7
13
19
18
BOTTOM
VIEW
12
2.25
2.10
1.95
0.60 MAX
0.50
0.40
0.30
0.30
0.23
0.18
2.50 REF
0.50
BSC
12MAX
0.80 MAX
0.65 TYP
0.05 MAX
0.02 NOM
1.00
0.85
0.80
SEATING
PLANE
PIN 1
INDICATOR
TOP
VIEW
3.75
BSC SQ
4.0
BSC SQ PIN 1
INDICATOR
0.60 MAX
COPLANARITY
0.08
SQ
0.20 REF
0.25 MIN
COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-2
REV. B
C02946–0–10/03(B)
–28–
ADF4252
Revision History
Location Page
10/03—Data Sheet changed from REV. A to REV. B.
Change to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Change to TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Change to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Change to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Inserted Lock Detect section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Change to OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27