CPLD Family FLASH370TM UltraLogicTM High-Density Flash CPLDs Features General Description * Flash erasable CMOS CPLDs The FLASH370TM family of CMOS CPLDs provides a range of high-density programmable logic solutions with unparalleled performance. Each member of the family is designed with Cypress's state-of-the-art Flash technology. All of the devices are electrically erasable and reprogrammable, simplifying product inventory and reducing costs. * High density -- 32-128 macrocells -- 32-128 I/O pins -- Multiple clock pins * Bus Hold capabilities on all I/Os and dedicated inputs * High speed -- tPD = 8.5-12 ns -- tS = 5-7 ns -- tCO = 6-7 ns * Fast Programmable Interconnect Matrix (PIM) -- Uniform predictable delay, independent of routing * Intelligent product term allocator -- 0-16 product terms to any macrocell -- Provides product term steering on an individual basis -- Provides product term sharing among local macrocells -- Doesn't strand macrocells * Simple timing model -- No fanout delays The F LASH370 family is designed to bring the flexibility, ease of use and performance of the 22V10 to high-density CPLDs. The architecture is based on a number of logic blocks that are connected by a Programmable Interconnect Matrix (PIM). Each logic block features its own product term array, product term allocator array, and 16 macrocells. The PIM distributes signals from one logic block to another as well as all inputs from pins. The family features a wide variety of densities and pin counts to choose from. At each density there are two packaging options to choose from--one that is I/O intensive and another that is register intensive. For example, the CY7C374 and CY7C375 both feature 128 macrocells. On the CY7C374, available in an 84-pin package, half of the macrocells are buried and half are available on I/O pins. On the CY7C375 all of the macrocells are fed to I/O pins and the device is available in the 160-pin package. Figure 1 shows a block diagram of the CY7C374/5. Functional Description Programmable Interconnect Matrix -- No expander delays -- No dedicated vs. I/O pin delays -- No additional delay through PIM -- No penalty for using full 16 product terms -- No delay for steering or sharing product terms * Flexible clocking -- 2-4 clock pins per device The Programmable Interconnect Matrix (PIM) consists of a completely global routing matrix for signals from I/O pins and feedbacks from the logic blocks. The PIM is an extremely robust interconnect that avoids fitting and density limitations. Routing is automatically accomplished by software and the propagation delay through the PIM is transparent to the user. Signals from any pin or any logic block can be routed to any or all logic blocks. -- Clock polarity control * Security bit and user ID supported * Packages -- 44-160 pins -- PLCC, CLCC, PGA, and TQFP packages Table 1. FLASH370 Selection Guide Device 371 372 373 374 375 Pins 44 44 84 84 160 Macrocells 32 64 64 128 128 Cypress Semiconductor Corporation Dedicated Inputs 6 6 6 6 6 * I/O Pins 32 32 64 64 128 3901 North First Street * Flip-Flops 44 76 76 140 140 San Jose * Speed (tPD) 8.5 10 10 12 12 CA 95134 Speed (fMAX) 143 125 125 100 100 * 408-943-2600 July 20, 2000 CPLD Family FLASH370TM CLOCK INPUTS INPUTS Logic Block Diagram 2 4 INPUT MACROCELLS INPUT/CLOCK MACROCELLS 4 4 16 I/Os I/O0-I/O15 LOGIC BLOCK A 16 I/Os I/O16 -I/O31 LOGIC BLOCK B 16 I/Os I/O32 -I/O47 LOGIC BLOCK C 16 I/Os I/O48 -I/O63 LOGIC BLOCK D 36 LOGIC BLOCK 16 H 36 36 LOGIC BLOCK 16 16 G 36 36 LOGIC BLOCK 36 16 PIM 16 16 36 36 16 16 64 16 I/Os I/O112 -I/O127 16 I/Os I/O96-I/O111 16 I/Os I/O80-I/O95 F LOGIC BLOCK E 16 I/Os I/O64-I/O79 64 Figure 1. CY7C375 Block Diagram Logic Block Functional Description (continued) The logic block is the basic building block of the FLASH370 architecture. It consists of a product term array, an intelligent product-term allocator, 16 macrocells, and a number of I/O cells. The number of I/O cells varies depending on the device used. The inputs to the PIM consist of all I/O and dedicated input pins and all macrocell feedbacks from within the logic blocks. The number of PIM inputs increases with pincount and the number of logic blocks. The outputs from the PIM are signals routed to the appropriate logic block(s). Each logic block receives 36 inputs from the PIM and their complements, allowing for 32-bit operations to be implemented in a single pass through the device. The wide number of inputs to the logic block also improves the routing capacity of the FLASH370 family. There are two types of logic blocks in the F LASH370 family. The first type features an equal number (16) of I/O cells and macrocells and is shown in Figure 2. This architecture is best for I/O-intensive applications. The second type of logic block features a buried macrocell along with each I/O macrocell. In other words, in each logic block, there are eight macrocells that are connected to I/O cells and eight macrocells that are internally fed back to the PIM only. This organization is designed for register-intensive applications and is displayed in Figure 3. Note that at each FLASH370 density (except the smallest), an I/O intensive and a register-intensive device is available. An important feature of the PIM involves timing. The propagation delay through the PIM is accounted for in the timing specifications for each device. There is no additional delay for traveling through the PIM. In fact, all inputs travel through the PIM. Likewise, there are no route-dependent timing parameters on the FLASH370 devices. The worst-case PIM delays are incorporated in all appropriate FLASH370 specifications. Product Term Array Routing signals through the PIM is completely invisible to the user. All routing is accomplished by software--no hand routing is necessary. Warp TM and third-party development packages automatically route designs for the F LASH370 family in a matter of minutes. Finally, the rich routing resources of the FLASH370 family accommodate last minute logic changes while maintaining fixed pin assignments. Each logic block features a 72 x 86 programmable product term array. This array is fed with 36 inputs from the PIM, which originate from macrocell feedbacks and device pins. Active LOW and active HIGH versions of each of these inputs are generated to create the full 72-input field. The 86 product terms in the array can be created from any of the 72 inputs. 2 CPLD Family FLASH370TM 0-16 PRODUCT TERMS 2 2 MACROCELL 1 I/O CELL 1 MACROCELL 8 I/O CELL 8 MACROCELL 9 I/O CELL 9 MACROCELL 16 I/O CELL 16 2 6 0-16 PRODUCT TERMS FROM PIM 36 72 x 86 PRODUCT TERM ARRAY 80 PRODUCT TERM ALLOCATOR 0-16 PRODUCT TERMS 0-16 PRODUCT TERMS 16 TO PIM 16 flash370-2 Figure 2. Logic Block for CY7C371, CY7C373, and CY7C375 (I/O Intensive) 0-16 PRODUCT TERMS 0-16 PRODUCT TERMS 6 FROM PIM 36 72 x 86 PRODUCT TERM ARRAY 80 MACROCELL 1 MACROCELL 2 2 I/O CELL 1 to cells 3,5,7 PRODUCT TERM ALLOCATOR 0-16 PRODUCT TERMS 0-16 PRODUCT TERMS TO PIM 2 2 MACROCELL 9 MACROCELL 16 I/O CELL 9 to cells 11,13,15 16 8 flash370-3 Figure 3. Logic Block for CY7C372 and CY7C374 (Register Intensive) 3 CPLD Family FLASH370TM Of the 86 product terms, 80 are for general-purpose use for the 16 macrocells in the logic block. Four of the remaining six product terms in the logic block are output enable (OE) product terms. Each of the OE product terms controls up to eight of the 16 macrocells and is selectable on an individual macrocell basis. In other words, each I/O cell can select between one of two OE product terms to control the output buffer. The first two of these four OE product terms are available to the upper half of the I/O macrocells in a logic block. The other two OE product terms are available to the lower half of the I/O macrocells in a logic block. The final two product terms in each logic block are dedicated asynchronous set and asynchronous reset product terms. one output has one or more product terms in its equation that are common to other outputs, those product terms are only programmed once. The FLASH370 product term allocator allows sharing across groups of four output macrocells in a variable fashion. The software automatically takes advantage of this capability--the user does not have to intervene. Note that greater usable density can often be achieved if the user "floats" the pin assignment. This allows the compiler to group macrocells that have common product terms adjacently. Product Term Allocator FLASH370 Macrocell Note that neither product term sharing nor product term steering have any effect on the speed of the product. All worst-case steering and sharing configurations have been incorporated in the timing specifications for the FLASH370 devices. Through the product term allocator, software automatically distributes product terms among the 16 macrocells in the logic block as needed. A total of 80 product terms are available from the local product term array. The product term allocator provides two important capabilities without affecting performance: product term steering and product term sharing. I/O Macrocell Within each logic block there are 8 or 16 I/O macrocells depending on the device used. Figure 4 illustrates the architecture of the I/O macrocell. The macrocell features a register that can be configured as combinatorial, a D flip-flop, a T flip-flop, or a level-triggered latch. Product Term Steering The register can be asynchronously set or asynchronously reset at the logic block level with the separate set and reset product terms. Each of these product terms features programmable polarity. This allows the registers to be set or reset based on an AND expression or an OR expression. Product term steering is the process of assigning product terms to macrocells as needed. For example, if one macrocell requires ten product terms while another needs just three, the product term allocator will "steer" ten product terms to one macrocell and three to the other. On F LASH370 devices, product terms are steered on an individual basis. Any number between 0 and 16 product terms can be steered to any macrocell. Note that 0 product terms is useful in cases where a particular macrocell is unused or used as an input register. Clocking of the register is very flexible. Depending on the device, either two or four global synchronous clocks are available to clock the register. Furthermore, each clock features programmable polarity so that registers can be triggered on falling as well as rising edges (see the Dedicated/Clock Inputs section). Clock polarity is chosen at the logic block level. Product Term Sharing Product term sharing is the process of using the same product term among multiple macrocells. For example, if more than I/O MACROCELL I/O CELL 0-16 PRODUCT TERMS 0 P D/T/L 0 1 Q 2 3 S1 S0 Q Q 0 Q 1 1 C4 R DECODE C0 C1[1] "0" "1" 0 1 2 3 Q C5 C6 C2 C3 FEEDBACK TO PIM ASYNCHRONOUS BLOCK RESET ASYNCHRONOUS BLOCK PRESET FEEDBACK TO PIM 4 SYSTEM CLOCKS (CY7C373 - CY7C375) 2 SYSTEM CLOCKS (CY7C371 - CY7C372) flash370-4 2 BANK OE TERMS Figure 4. I/O Macrocell Notes: 1. C1 is not used on the CY7C371 and CY7C372. 4 CPLD Family FLASH370TM At the output of the macrocell, a polarity control mux is available to select active LOW or active HIGH signals. This has the added advantage of allowing significant logic reduction to occur in many applications. register has the same options as described for the I/O macrocell. The primary difference between the I/O macrocell and the buried macrocell is that the buried macrocell does not have the ability to output data directly to an I/O pin. The FLASH370 macrocell features a feedback path to the PIM separate from the I/O pin input path. This means that if the macrocell is buried (fed back internally only), the associated I/O pin can still be used as an input. One additional difference on the buried macrocell is the addition of input register capability. The buried macrocell can be configured to act as an input register (D-type or latch) whose input comes from the I/O pin associated with the neighboring macrocell. The output of all buried macrocells is sent directly to the PIM regardless of its configuration. Buried Macrocell Some of the devices in the FLASH370 family feature additional macrocells that do not feed individual I/O pins. Figure 5 displays the architecture of the I/O and buried macrocells for these devices. The I/O macrocell is identical to the one on devices without buried macrocells. FLASH370 I/O Cell The I/O cell on the F LASH370 devices is illustrated along with the I/O macrocell in Figures 4 and 5. The user can program the I/O cell to change the way the three-state output buffer is enabled and/or disabled. Each output can be set permanently on (output only), permanently off (input only), or dynamically controlled by one of two OE product terms. The buried macrocell is very similar to the I/O macrocell. Again, it includes a register that can be configured as combinatorial, a D flip-flop, a T flip-flop, or a latch. The clock for this I/O MACROCELL FROM PTM I/O CELL 0-16 PRODUCT TERMS 0 Q P D/T/L 0 1 2 3 Q C1C0 1 Q 0 Q 1 C4 R "0" "1" DECODE [1] 0 1 2 3 Q C5 C6 C2 C3 BURIED MACROCELL FROM PTM 0-16 PRODUCT TERMS 0 0 Q 1 0 1 2 3 P D/T/L Q Q 1 C7 Q C1 C0 R DECODE [1] C2 C3 FEEDBACK TO PIM FEEDBACK TO PIM FEEDBACK TO PIM ASYNCHRONOUS BLOCK RESET ASYNCHRONOUS BLOCK PRESET flash370-5 4 SYSTEM CLOCKS (CY7C373-CY7C375) 2 SYSTEM CLOCKS (CY7C371-CY7C372) 2 BANK OE TERMS Figure 5. I/O and Buried Macrocells 5 CPLD Family FLASH370TM Dedicated/Clock Inputs larity of the clock signal can also be controlled by the user. Note that this polarity is separately controlled for input registers and output registers. Six pins on each member of the FLASH370 family are designated as input-only. There are two types of dedicated inputs on FLASH370 devices: input pins and input/clock pins. Figure 6 illustrates the architecture for input pins. Four input options are available for the user: combinatorial, registered, double-registered, or latched. If a registered or latched option is selected, any one of the input clocks can be selected for control. Timing Model One of the most important features of the FLASH370 family is the simplicity of its timing. All delays are worst case and system performance is unaffected by the features used or not used on the parts. Figure 8 illustrates the true timing model for the 8.5-ns devices. For combinatorial paths, any input to any output incurs an 8.5-ns worst-case delay regardless of the amount of logic used. For synchronous systems, the input set-up time to the output macrocells for any input is 5.0 ns and the clock to output time is also 6.0 ns. Again, these measurements are for any output and clock, regardless of the logic used. Figure 7 illustrates the architecture of input/clock pins. There are either two or four input/clock pins available, depending on the device selected. (The CY7C371 and CY7C372 have two input/clock pins while the other devices have four input/clock pins.) Like the input pins, input/clock pins can be combinatorial, registered, double registered, or latched. In addition, these pins feed the clocking structures throughout the device. The clock path at the input is user-configurable in polarity. The poINPUT PIN FROM CLOCK POLARITY MUXES D 0 1 2 3 D Q Q 0 1 2 3 O TO PIM O C10 C11 C8 C9[2] D flash370-6 Q LE Figure 6. input Pins 0 TO CLOCK MUX ON ALL INPUT MACROCELLS Q 1 INPUT/CLOCK PIN C12 0 1 FROM CLOCK POLARITY INPUT CLOCK PINS 0 1 2 3 D Q D C13, C14, C15[4] , OR C16[4] 0 1 2 3 Q O TO PIM O C8[3] C9[3] TO CLOCK MUX IN EACH LOGIC BLOCK CLOCK POLARITY MUX ONE PER LOGIC BLOCK FOR EACH CLOCK INPUT C10 C11 D flash370-7 Q LE Figure 7. Input/Clock Pins Notes: 2. C9 is not used on the CY7C371 and CY7C372. 3. C8 and C9 are not included on the CY7C371 and CY7C372 since each input/clock pin has the other input/clock pin as its clock. 4. C15 and C16 are not used on the CY7C371 and CY7C372 since there are two clocks. 6 CPLD Family FLASH370TM Development Software Support COMBINATORIALSIGNAL WarpTM tPD = 8.5 ns REGISTEREDSIGNAL D,T,L Q flash370-8 CLOCK tS = 5.0 ns tCO = 6.0 ns Warp is a state-of-the-art compiler and complete CPLD design tool. For design entry, Warp provides an IEEE-STD-1076/1164 VHDL text editor, an IEEE-STD-1364 Verilog text editor, and a graphical finite state machine editor. It provides optimized synthesis and fitting by replacing basic circuits with ones pre-optimized for the target device, by implementing logic in unused memory and by perfect communication between fitting and synthesis. Warp provides other tools such as graphical timing simulation and analysis. Warp ProfessionalTM Figure 8. Timing Model for CY7C371 Stated another way, the FLASH370 features: * no fanout delays * no expander delays * no dedicated vs. I/O pin delays * no additional delay through PIM * no penalty for using 0-16 product terms * no added delay for steering product terms * no added delay for sharing product terms * no routing delays * no output bypass delays The simple timing model of the FLASH370 family eliminates unexpected performance penalties. Warp Professional contains several additional features. It provides an extra method of design entry with its graphical block diagram editor. It allows up to 5 ms timing simulation instead of only 2 ms. It allows comparing of waveforms before and after design changes. Warp EnterpriseTM Warp Enterprise provides even more features. It provides unlimited timing simulation and source-level behavioral simulation as well as a debugger. It has the ability to generate graphical HDL blocks from HDL text. It can even generate testbenches. Warp is available for PC and UNIX platforms. Some features are not available in the UNIX version. For further information see the Warp for PC, Warp for UNIX, Warp Professional and Warp Enterprise data sheets. Bus Hold Capabilities on all I/Os and Dedicated Inputs Third-Party Software A feature called bus-hold has been added to all FLASH370 I/Os and dedicated input pins. Bus-hold, which is an improved version of the popular internal pull-up resistor, is a weak latch connected to the pin that does not degrade the device's performance. As a latch, bus-hold recalls the last state of a pin when it is three-stated, thus reducing system noise in bus-interface applications. Bus-hold additionally allows unused device pins to remain unconnected on the board, which is particularly useful during prototyping as designers can route new signals to the device without cutting trace connections to VCC or GND. Although Warp is a complete CPLD development tool on its own, it interfaces with nearly every third party EDA tool. All major third-party software vendors provide support for the FLASH370 family of devices. To expedite this support, Cypress supplies vendors with all pertinent architectural information as well as design fitters for our products. Document #: 38-00215-G FLASH370, Warp, Warp Professional, Warp Enterprise, and UltraLogic are trademarks of Cypress Semiconductor Corporation. ABEL is a trademark of Data I/O Corporation. LOG/iC is a trademark of Isdata Corporation. CUPL is a trademark of Logical Devices, Inc. (c) Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.