DATA SH EET
Product specification
Supersedes data of 2003 May 26 2003 Oct 03
INTEGRATED CIRCUITS
74LVC573A
Octal D-type transparent latch with
5 V tolerant inputs/outputs; 3-state
2003 Oct 03 2
Philips Semiconductors Product specification
Octal D-type transparent latch with 5 V
tolerant inputs/outputs; 3-state 74LVC573A
FEATURES
•5 V tolerant inputs/outputs, for interfacing with 5 V logic
•Supply voltage range from 1.2 to 3.6 V
•Inputs accept voltages up to 5.5 V
•CMOS low power consumption
•Direct interface with TTL levels
•High impedance when VCC =0V
•Flow-through pin-out architecture
•Complies with JEDEC standard no. 8-1A
•ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V
•Specified from −40 to +85 °C and −40 to +125 °C.
DESCRIPTION
The 74LVC573A is a high-performance, low-power,
low-voltage, Si-gate CMOS device, superior to most
advanced CMOS compatible TTL families.
Inputs can be driven from either 3.3 or 5 V devices. In
3-state operation, outputs can handle 5 V. This feature
allows the use of these devices as translators in a mixed
3.3 or 5 V environment.
The 74LVC573A is an octal D-type transparent latch
featuring separate D-type inputs for each latch and 3-state
outputs for bus-oriented applications. A Latch Enable (LE)
input and an Output Enable (OE) input are common to all
internal latches.
The 74LVC573A consists of eight D-type transparent
latches with 3-state true outputs. When LE is HIGH, data
at the Dn inputs enters the latches. In this condition, the
latchesaretransparent,i.e.alatchoutputwillchangeeach
timeitscorresponding D-input changes. When LEisLOW,
the latches store the information that was present at the
D-inputs one set-up time preceding the HIGH-to-LOW
transition of LE. When OE is LOW, the contents of the
eight latches are available at the outputs. When OE is
HIGH, the outputs go to the high impedance OFF-state.
Operation of the OE input does not affect the state of the
latches.
The 74LVC573A is functionally identical to the
74LVC373A, but the 74LVC373A has a different pin
arrangement.
QUICK REFERENCE DATA
Notes
1. CPD is used to determine the dynamic power dissipation (PDin µW).
PD=C
PD ×VCC2×fi×N+Σ(CL×VCC2×fo) where:
fi= input frequency in MHz;
fo= output frequency in MHz;
CL= output load capacitance in pF;
VCC = supply voltage in Volts;
N = total load switching outputs;
Σ(CL×VCC2×fo) = sum of the outputs.
2. The condition is VI= GND to VCC.
SYMBOL PARAMETER CONDITIONS TYPICAL UNIT
tPHL/tPLH propagation delay CL= 50 pF; VCC = 3.3 V
Dn to Qn 3.4 ns
LE to Qn 3.1 ns
CIinput capacitance 5.0 pF
CPD power dissipation capacitance per latch notes 1 and 2 15 pF
2003 Oct 03 3
Philips Semiconductors Product specification
Octal D-type transparent latch with 5 V
tolerant inputs/outputs; 3-state 74LVC573A
FUNCTION TABLE
See note 1.
Note
1. H = HIGH voltage level;
h = HIGH voltage level one setup time prior to the HIGH-to-LOW LE transition;
L = LOW voltage level;
l = LOW voltage level one setup time prior to the HIGH-to-LOW LE transition;
Z = high-impedance OFF-state.
ORDERING INFORMATION
OPERATING MODES INPUT INTERNAL
LATCH OUTPUT
OE LE Dn Qn
Enable and read register
(transparent mode) LHLLL
LHHHH
Latch and read register L L l L L
LLhHH
Latch register and disable
outputs HLlLZ
HLhHZ
TYPE NUMBER TEMPERATURE
RANGE PACKAGE
PINS PACKAGE MATERIAL CODE
74LVC573AD −40 to +125 °C 20 SO20 plastic SOT163-1
74LVC573ADB −40 to +125 °C 20 SSOP20 plastic SOT339-1
74LVC573APW −40 to +125 °C 20 TSSOP20 plastic SOT360-1
74LVC573ABQ −40 to +125 °C 20 DHVQFN20 plastic SOT764-1
PINNING
PIN SYMBOL DESCRIPTION
1OE output enable input (active
LOW)
2 D0 data input
3 D1 data input
4 D2 data input
5 D3 data input
6 D4 data input
7 D5 data input
8 D6 data input
9 D7 data input
10 GND ground (0 V)
11 LE latch enable input (active HIGH)
12 Q7 data output
13 Q6 data output
14 Q5 data output
15 Q4 data output
16 Q3 data output
17 Q2 data output
18 Q1 data output
19 Q0 data output
20 VCC supply voltage
PIN SYMBOL DESCRIPTION
2003 Oct 03 4
Philips Semiconductors Product specification
Octal D-type transparent latch with 5 V
tolerant inputs/outputs; 3-state 74LVC573A
handbook, halfpage
OE
D0
D1
D2
D3 573
D4
D5
D6
D7
GND
VCC
Q0
Q1
Q2
Q4
Q5
Q3
Q6
Q7
LE
1
2
3
4
5
6
7
8
9
10 11
12
20
19
18
17
16
15
14
13
MNA806
Fig.1 Pin configuration SO20 and (T)SSOP20.
handbook, halfpage
1
2
3
4
5
6
7
8
9
D0
D1
D2
D3
D4
D5
D6
D7
19
18
17
16
15
14
13
12
Q1
Q0
Q2
Q3
Q4
Q5
Q6
Q7
20
OE VCC
10 11
GND
Top view LE
GND
(1)
MNA979
Fig.2 Pin configuration DHVQFN20.
(1) The die substrate is attached to this pad using conductive die
attach material. It can not be used as a supply pin or input.
handbook, halfpage
MNA807
D0
D1
D2
D3
D4
D5
D6
D7 LE
OE Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
1
11
12
13
14
15
16
17
18
19
9
8
7
6
5
4
3
2
Fig.3 Logic symbol.
handbook, halfpage
MNA808
12
13
14
15
16
17
18
11 C1
1EN1
1D 19
9
8
7
6
5
4
3
2
Fig.4 Logic symbol (IEEE/IEC).
2003 Oct 03 5
Philips Semiconductors Product specification
Octal D-type transparent latch with 5 V
tolerant inputs/outputs; 3-state 74LVC573A
handbook, halfpage
MNA809
3-STATE
OUTPUTS
LATCH
1 to 8
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7 12
13
14
15
16
17
18
19
D0
D1
D2
D3
D4
D5
D6
D7
LE
OE
9
11
1
8
7
6
5
4
3
2
Fig.5 Functional diagram.
handbook, full pagewidth
MNA810
Q4
D4
D
LE
Q
Q3
D3
D
LE
Q
Q2
D2
D
LE
Q
Q1
D1
D
LELELE
Q
Q0
D0
D
LATCH
1LATCH
2LATCH
3LATCH
4LATCH
5
Q
LE
OE
LE LE LE LE
Q5
D5
D
LE
Q
LATCH
6
LE
Q6
D6
D
LE
Q
LATCH
7
LE
Q7
D7
D
LE
Q
LATCH
8
LE
Fig.6 Logic diagram.
2003 Oct 03 6
Philips Semiconductors Product specification
Octal D-type transparent latch with 5 V
tolerant inputs/outputs; 3-state 74LVC573A
RECOMMENDED OPERATING CONDITIONS
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V).
Notes
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. For SO20 packages: above 70 °C the value of Ptot derates linearly with 8 mW/K.
For (T)SSOP20 packages: above 60 °C the value of Ptot derates linearly with 5.5 mW/K.
For DHVQFN20 packages: above 60 °C the value of Ptot derates linearly with 4.5 mW/K.
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VCC supply voltage for maximum speed performance 2.7 3.6 V
for low-voltage applications 1.2 3.6 V
VIinput voltage 0 5.5 V
VOoutput voltage output HIGH- or LOW-state 0 VCC V
output 3-state 0 5.5
Tamb operating ambient temperature in free air −40 +125 °C
tr, tfinput rise and fall times VCC = 1.2 to 2.7 V 0 20 ns/V
VCC = 2.7 to 3.6 V 0 10 ns/V
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VCC supply voltage −0.5 +6.5 V
IIK input diode current VI<0 −−50 mA
VIinput voltage note 1 −0.5 +6.5 V
IOK output diode current VO>V
CC or VO<0 −±50 mA
VOoutput voltage output HIGH- or LOW-state;
note 1 −0.5 VCC + 0.5 V
output 3-state; note 1 −0.5 +6.5 V
IOoutput source or sink current VO= 0 to VCC −±50 mA
ICC, IGND VCC or GND current −±100 mA
Tstg storage temperature −65 +150 °C
Ptot power dissipation Tamb =−40 to +125 °C; note 2 −500 mW
2003 Oct 03 7
Philips Semiconductors Product specification
Octal D-type transparent latch with 5 V
tolerant inputs/outputs; 3-state 74LVC573A
DC CHARACTERISTICS
At recommended operating conditions voltages are referenced to GND (ground = 0 V).
SYMBOL PARAMETER TEST CONDITIONS MIN. TYP.(1) MAX. UNIT
OTHER VCC (V)
Tamb =−40 °C to +85 °C
VIH HIGH level input voltage 1.2 VCC −−V
2.7 to 3.6 2.0 −−V
V
IL LOW-level input voltage 1.2 −−GND V
2.7 to 3.6 −−0.8 V
VOH HIGH-level output voltage VI=V
IH or VIL
IO=−12 mA 2.7 VCC −0.5 −−V
I
O
=−100 µA 3.0 VCC −0.2 VCC −V
IO=−18 mA 3.0 VCC −0.6 −−V
I
O
=−24 mA 3.0 VCC −0.8 −−V
V
OL LOW-level output voltage VI=V
IH or VIL
IO= 12 mA 2.7 −−0.40 V
IO= 100 µA 3.0 −GND 0.20 V
IO= 24 mA 3.0 −−0.55 V
ILI input leakage current VI= 5.5 Vor GND;
note 2 3.6 −±0.1 ±5µA
IOZ 3-state output OFF-state
current VI=V
IH or VIL;
VO= 5.5 Vor GND 3.6 −0.1 ±10 µA
Ioff power off leakage supply VIor VO= 5.5 V 0.0 −0.1 ±10 µA
ICC quiescent supply current VI=V
CC or GND;
IO=0 3.6 −0.1 10 µA
2003 Oct 03 8
Philips Semiconductors Product specification
Octal D-type transparent latch with 5 V
tolerant inputs/outputs; 3-state 74LVC573A
Notes
1. All typical values are measured at VCC = 3.3 V and Tamb =25°C.
2. The specified overdrive current at the data input forces the data input to the opposite logic input state.
∆ICC additional quiescent
supply current per input
pin
VI=V
CC −0.6 V;
IO=0 2.7 to 3.6 −5 500 µA
Tamb =−40 to +125 °C
VIH HIGH-level input voltage 1.2 VCC −−V
2.7 to 3.6 2.0 −−V
V
IL LOW-level input voltage 1.2 −−GND V
2.7 to 3.6 −−0.8 V
VOH HIGH-level output voltage VI=V
IH or VIL
IO=−100 µA 2.7 to 3.6 VCC −0.3 −−V
I
O
=−12 mA 2.7 VCC −0.65 −−V
I
O
=−18 mA 3.0 VCC −0.75 −−V
I
O
=−24 mA 3.0 VCC −1−−V
V
OL LOW-level output voltage VI=V
IH or VIL
IO= 100 µA 2.7 to 3.6 −−0.3 V
IO= 12 mA 2.7 −−0.6 V
IO= 24 mA 3.0 −−0.8 V
ILI input leakage current VI= 5.5 Vor GND 3.6 −−±20 µA
ICC quiescent supply current VI=V
CC or GND;
IO=0 3.6 −−40 µA
∆ICC additional quiescent
supply current per input
pin
VI=VCC −0.6 V;
IO=0 2.7 to 3.6 −−5000 µA
SYMBOL PARAMETER TEST CONDITIONS MIN. TYP.(1) MAX. UNIT
OTHER VCC (V)
2003 Oct 03 9
Philips Semiconductors Product specification
Octal D-type transparent latch with 5 V
tolerant inputs/outputs; 3-state 74LVC573A
AC CHARACTERISTICS
GND = 0 V; tr=t
f≤2.5 ns; CL= 50 pF; RL= 500 Ω.
SYMBOL PARAMETER TEST CONDITIONS MIN. TYP(1). MAX. UNIT
WAVEFORMS VCC (V)
Tamb =−40 to +85 °C
tPHL/tPLH propagation delay Dn to Qn see Figs 7 and 11 1.2 −16 −ns
2.7 1.5 4.0 7.2 ns
3.0 to 3.6 1.5 3.4(2) 6.2 ns
propagation delay LE to Qn see Figs 8 and 11 1.2 −16 −ns
2.7 1.5 3.4 7.5 ns
3.0 to 3.6 1.5 3.1(2) 6.5 ns
tPZH/tPZL 3-state output enable time
OE to Qn see Figs 9 and 11 1.2 −18 −ns
2.7 1.5 4.2 8.5 ns
3.0 to 3.6 1.5 3.5(2) 7.5 ns
3-state output disable time
OE to Qn see Figs 9 and 11 1.2 −8−ns
2.7 1.5 2.9 6.5 ns
3.0 to 3.6 1.5 2.4(2) 6.0 ns
tWLE pulse width HIGH see Fig.8 1.2 −−−ns
2.7 3.2 −−ns
3.0 to 3.6 3.2 1.6(2) −ns
tsu set-up time Dn to LE see Fig.10 1.2 −−−ns
2.7 1.7 −−ns
3.0 to 3.6 1.7 −−ns
thhold time Dn to LE see Fig.10 1.2 −−−ns
2.7 1.5 −−ns
3.0 to 3.6 1.4 −−ns
tsk(0) skew note 3 3.0 to 3.6 −−1.0 ns
2003 Oct 03 10
Philips Semiconductors Product specification
Octal D-type transparent latch with 5 V
tolerant inputs/outputs; 3-state 74LVC573A
Notes
1. All typical values are measured at Tamb =25°C.
2. These typical values are measured at VCC = 3.3 V
3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed
by design.
Tamb =−40 to +125 °C
tPHL/tPLH propagation delay Dn to Qn see Figs 7 and 11 1.2 −−−ns
2.7 1.5 −9.0 ns
3.0 to 3.6 1.5 −8.0 ns
propagation delay LE to Qn see Figs 8 and 11 1.2 −−−ns
2.7 1.5 −9.5 ns
3.0 to 3.6 1.5 −8.5 ns
tPZH/tPZL 3-state output enable time
OE to Qn see Figs 9 and 11 1.2 −−−ns
2.7 1.5 −11.0 ns
3.0 to 3.6 1.5 −9.5 ns
3-state output disable time
OE to Qn see Figs 9 and 11 1.2 −−−ns
2.7 1.5 −8.5 ns
3.0 to 3.6 1.5 −7.5 ns
tWLE pulse width HIGH see Fig.8 1.2 −−−ns
2.7 3.2 −−ns
3.0 to 3.6 3.2 −−ns
tsu set-up time Dn to LE see Fig.10 1.2 −−−ns
2.7 1.7 −−ns
3.0 to 3.6 1.7 −−ns
thhold time Dn to LE see Fig.10 1.2 −−−ns
2.7 1.5 −−ns
3.0 to 3.6 1.4 −−ns
tsk(0) skew note 3 3.0 to 3.6 −−1.0 ns
SYMBOL PARAMETER TEST CONDITIONS MIN. TYP(1). MAX. UNIT
WAVEFORMS VCC (V)
2003 Oct 03 11
Philips Semiconductors Product specification
Octal D-type transparent latch with 5 V
tolerant inputs/outputs; 3-state 74LVC573A
AC WAVEFORMS
handbook, halfpage
MNA811
Dn input
Qn output
tPHL tPLH
GND
VI
VM
VM
VOH
VOL
Fig.7 Input (Dn) to output (Qn) propagation delays.
VM= 1.5 V at VCC ≥2.7 V.
VM= 0.5VCC at VCC < 2.7 V.
VOL and VOH are the typical output voltage drop that occur with the output load.
handbook, full pagewidth
MNA812
LE input
Qn output
tPHL tPLH
tW
1/fmax
VM
VOH
VI
GND
VOL
VM
Fig.8 Latch Enable input (LE) pulse width, the latch enable input to output (Qn) propagation delays.
VM= 1.5 V at VCC ≥2.7 V.
VM= 0.5VCC at VCC < 2.7 V.
VOL and VOH are the typical output voltage drop that occur with the output load.
2003 Oct 03 12
Philips Semiconductors Product specification
Octal D-type transparent latch with 5 V
tolerant inputs/outputs; 3-state 74LVC573A
handbook, full pagewidth
MNA813
tPLZ
tPHZ
outputs
disabled outputs
enabled
VY
VX
outputs
enabled
Qn output
LOW-to-OFF
OFF-to-LOW
Qn output
HIGH-to-OFF
OFF-to-HIGH
OE input
VOL
VOH
VCC
VI
VM
GND
GND
tPZL
tPZH
VM
VM
Fig.9 3-state enable and disable times.
VM= 1.5 V at VCC ≥2.7 V.
VM= 0.5VCC at VCC < 2.7 V.
VOL and VOH are the typical output voltage drop that occur with the output load.
VX=V
OL + 0.3 V at VCC ≥2.7 V; VX=V
OL + 0.1VCC at VCC < 2.7 V.
VY=V
OH −0.3 V at VCC ≥2.7 V; VY=V
OH −0.1VCC at VCC < 2.7 V.
handbook, full pagewidth
MNA814
th
tsu
th
tsu
VM
VM
VI
GND
VI
GND
LE input
Dn input
Fig.10 Data set-up and hold times for the Dn input to the LE input.
VM= 1.5 V at VCC ≥2.7 V.
VM= 0.5 VCC at VCC < 2.7 V.
The shaded areas indicate when the input is permitted to change for predictable output performance.
2003 Oct 03 13
Philips Semiconductors Product specification
Octal D-type transparent latch with 5 V
tolerant inputs/outputs; 3-state 74LVC573A
handbook, full pagewidth
open
GND
2 × VCC
VCC
VIVO
MNA815
D.U.T. CL =
50 pF
RTRL = 500 Ω
RL = 500 Ω
PULSE
GENERATOR
S1
Fig.11 Load circuitry for switching times.
TEST S1
tPLH/tPHL open
tPLZ/tPZL 2×VCC
tPHZ/tPZH GND
VCC VI
<2.7 V VCC
2.7 to 3.6 V 2.7 V
Definitions for test circuit:
RL= load resistor.
CL= load capacitance includes jig and probe capacitance.
RT= termination resistance should be equal to Zo of pulse generators.
2003 Oct 03 14
Philips Semiconductors Product specification
Octal D-type transparent latch with 5 V
tolerant inputs/outputs; 3-state 74LVC573A
PACKAGE OUTLINES
UNIT A
max. A1A2A3bpcD
(1) E(1) (1)
eH
ELL
pQZ
ywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm
inches
2.65 0.3
0.1 2.45
2.25 0.49
0.36 0.32
0.23 13.0
12.6 7.6
7.4 1.27 10.65
10.00 1.1
1.0 0.9
0.4 8
0
o
o
0.25 0.1
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
1.1
0.4
SOT163-1
10
20
wM
bp
detail X
Z
e
11
1
D
y
0.25
075E04 MS-013
pin 1 index
0.1 0.012
0.004 0.096
0.089 0.019
0.014 0.013
0.009 0.51
0.49 0.30
0.29 0.05
1.4
0.055
0.419
0.394 0.043
0.039 0.035
0.016
0.01
0.25
0.01 0.004
0.043
0.016
0.01
0 5 10 mm
scale
X
θ
A
A1
A2
HE
Lp
Q
E
c
L
vMA
(A )
3
A
SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1
99-12-27
03-02-19
2003 Oct 03 15
Philips Semiconductors Product specification
Octal D-type transparent latch with 5 V
tolerant inputs/outputs; 3-state 74LVC573A
UNIT A1A2A3bpcD
(1) E(1) eH
ELL
pQ(1)
Zywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.21
0.05 1.80
1.65 0.38
0.25 0.20
0.09 7.4
7.0 5.4
5.2 0.65 7.9
7.6 0.9
0.7 0.9
0.5 8
0
o
o
0.131.25 0.2 0.1
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.2 mm maximum per side are not included.
1.03
0.63
SOT339-1 MO-150 99-12-27
03-02-19
X
wM
θ
A
A1
A2
bp
D
HE
Lp
Q
detail X
E
Z
e
c
L
vMA
(A )
3
A
110
20 11
y
0.25
pin 1 index
0 2.5 5 mm
scale
SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm SOT339-1
A
max.
2
2003 Oct 03 16
Philips Semiconductors Product specification
Octal D-type transparent latch with 5 V
tolerant inputs/outputs; 3-state 74LVC573A
UNIT A1A2A3bpcD
(1) E(2) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.15
0.05 0.95
0.80 0.30
0.19 0.2
0.1 6.6
6.4 4.5
4.3 0.65 6.6
6.2 0.4
0.3 0.5
0.2 8
0
o
o
0.13 0.10.21
DIMENSIONS (mm are the original dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
0.75
0.50
SOT360-1 MO-153 99-12-27
03-02-19
wM
bp
D
Z
e
0.25
110
20 11
pin 1 index
θ
A
A1
A2
Lp
Q
detail X
L
(A )
3
HE
E
c
vMA
X
A
y
0 2.5 5 mm
scale
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1
A
max.
1.1
2003 Oct 03 17
Philips Semiconductors Product specification
Octal D-type transparent latch with 5 V
tolerant inputs/outputs; 3-state 74LVC573A
terminal 1
index area
0.51
A1Eh
b
UNIT ye
0.2
c
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 4.6
4.4
Dh
3.15
2.85
y1
2.6
2.4 1.15
0.85
e1
3.5
0.30
0.18
0.05
0.00 0.05 0.1
DIMENSIONS (mm are the original dimensions)
SOT764-1 MO-241 - - -- - -
0.5
0.3
L
0.1
v
0.05
w
0 2.5 5 mm
scale
SOT764-1
DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
20 terminals; body 2.5 x 4.5 x 0.85 mm
A(1)
max.
AA1c
detail X
y
y1C
e
L
Eh
Dh
e
e1
b
29
19 12
11
10
1
20
X
D
E
C
BA
terminal 1
index area
AC
CB
vM
wM
E(1)
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
D(1)
02-10-17
03-01-27
2003 Oct 03 18
Philips Semiconductors Product specification
Octal D-type transparent latch with 5 V
tolerant inputs/outputs; 3-state 74LVC573A
DATA SHEET STATUS
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
LEVEL DATA SHEET
STATUS PRODUCT
STATUS(2)(3) DEFINITION
I Objective data Development This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
II Preliminary data Qualification This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
III Product data Production This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Relevant changes will
be communicated via a Customer Product/Process Change Notification
(CPCN).
DEFINITIONS
Short-form specification The data in a short-form
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
Limiting values definition Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
attheseoratany other conditions abovethosegiveninthe
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Application information Applications that are
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
norepresentationorwarrantythatsuchapplicationswillbe
suitable for the specified use without further testing or
modification.
DISCLAIMERS
Life support applications These products are not
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductorscustomers usingorsellingtheseproducts
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Right to make changes Philips Semiconductors
reserves the right to make changes in the products -
including circuits, standard cells, and/or software -
described or contained herein in order to improve design
and/or performance. When the product is in full production
(status ‘Production’), relevant changes will be
communicated via a Customer Product/Process Change
Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these
products, conveys no licence or title under any patent,
copyright, or mask work right to these products, and
makes no representations or warranties that these
products are free from patent, copyright, or mask work
right infringement, unless otherwise specified.
© Koninklijke Philips Electronics N.V. 2003 SCA75
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Philips Semiconductors – a worldwide company
Contact information
For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825
For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
Printed in The Netherlands R20/03/pp19 Date of release: 2003 Oct 03 Document order number: 9397 750 11938
