INTEGRATED CIRCUITS DATA SHEET 74LVC573A Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state Product specification Supersedes data of 2003 May 26 2003 Oct 03 Philips Semiconductors Product specification Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state 74LVC573A The 74LVC573A is an octal D-type transparent latch featuring separate D-type inputs for each latch and 3-state outputs for bus-oriented applications. A Latch Enable (LE) input and an Output Enable (OE) input are common to all internal latches. FEATURES * 5 V tolerant inputs/outputs, for interfacing with 5 V logic * Supply voltage range from 1.2 to 3.6 V * Inputs accept voltages up to 5.5 V * CMOS low power consumption The 74LVC573A consists of eight D-type transparent latches with 3-state true outputs. When LE is HIGH, data at the Dn inputs enters the latches. In this condition, the latches are transparent, i.e. a latch output will change each time its corresponding D-input changes. When LE is LOW, the latches store the information that was present at the D-inputs one set-up time preceding the HIGH-to-LOW transition of LE. When OE is LOW, the contents of the eight latches are available at the outputs. When OE is HIGH, the outputs go to the high impedance OFF-state. Operation of the OE input does not affect the state of the latches. * Direct interface with TTL levels * High impedance when VCC = 0 V * Flow-through pin-out architecture * Complies with JEDEC standard no. 8-1A * ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V * Specified from -40 to +85 C and -40 to +125 C. DESCRIPTION The 74LVC573A is functionally identical to the 74LVC373A, but the 74LVC373A has a different pin arrangement. The 74LVC573A is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3 or 5 V devices. In 3-state operation, outputs can handle 5 V. This feature allows the use of these devices as translators in a mixed 3.3 or 5 V environment. QUICK REFERENCE DATA SYMBOL tPHL/tPLH PARAMETER CONDITIONS propagation delay TYPICAL UNIT CL = 50 pF; VCC = 3.3 V Dn to Qn 3.4 ns LE to Qn 3.1 ns CI input capacitance 5.0 pF CPD power dissipation capacitance per latch notes 1 and 2 15 pF Notes 1. CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD x VCC2 x fi x N + (CL x VCC2 x fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts; N = total load switching outputs; (CL x VCC2 x fo) = sum of the outputs. 2. The condition is VI = GND to VCC. 2003 Oct 03 2 Philips Semiconductors Product specification Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state 74LVC573A FUNCTION TABLE See note 1. INPUT OUTPUT OE LE Dn INTERNAL LATCH Enable and read register (transparent mode) L H L L L L H H H H Latch and read register L L l L L L L h H H H L l L Z H L h H Z OPERATING MODES Latch register and disable outputs Qn Note 1. H = HIGH voltage level; h = HIGH voltage level one setup time prior to the HIGH-to-LOW LE transition; L = LOW voltage level; l = LOW voltage level one setup time prior to the HIGH-to-LOW LE transition; Z = high-impedance OFF-state. ORDERING INFORMATION PACKAGE TEMPERATURE RANGE PINS PACKAGE MATERIAL CODE 74LVC573AD -40 to +125 C 20 SO20 plastic SOT163-1 74LVC573ADB -40 to +125 C 20 SSOP20 plastic SOT339-1 74LVC573APW -40 to +125 C 20 TSSOP20 plastic SOT360-1 74LVC573ABQ -40 to +125 C 20 DHVQFN20 plastic SOT764-1 TYPE NUMBER PINNING PIN SYMBOL DESCRIPTION PIN SYMBOL DESCRIPTION 10 GND ground (0 V) 1 OE output enable input (active LOW) 11 LE latch enable input (active HIGH) 12 Q7 data output 2 D0 data input 13 Q6 data output 3 D1 data input 14 Q5 data output 4 D2 data input 15 Q4 data output 5 D3 data input 16 Q3 data output 6 D4 data input 17 Q2 data output 7 D5 data input 18 Q1 data output 8 D6 data input 19 Q0 data output 9 D7 data input 20 VCC supply voltage 2003 Oct 03 3 Philips Semiconductors Product specification Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state 74LVC573A handbook, halfpage OE VCC 1 20 D0 2 19 Q0 D1 3 18 Q1 18 Q1 D2 4 17 Q2 D2 4 17 Q2 D3 5 16 Q3 D3 5 16 Q3 handbook, halfpage OE 1 20 VCC D0 2 19 Q0 D1 3 GND(1) 573 D4 6 15 Q4 14 Q5 D5 7 14 Q5 D6 8 13 Q6 D6 8 13 Q6 D7 9 12 Q7 D7 9 12 Q7 GND 10 11 LE D4 6 15 Q4 D5 7 MNA806 Top view 10 11 GND LE MNA979 (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input. Fig.1 Pin configuration SO20 and (T)SSOP20. Fig.2 Pin configuration DHVQFN20. handbook, halfpage handbook, halfpage 1 1 2 3 4 5 6 7 8 9 OE D0 Q0 D1 Q1 D2 Q2 D3 Q3 D4 Q4 D5 Q5 D6 Q6 D7 Q7 19 2 18 C1 EN1 19 1D 17 3 18 16 4 17 15 5 16 6 15 7 14 8 13 9 12 14 13 12 LE 11 11 MNA807 MNA808 Fig.3 Logic symbol. 2003 Oct 03 Fig.4 Logic symbol (IEEE/IEC). 4 Philips Semiconductors Product specification Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state 74LVC573A handbook, halfpage 2 D0 Q0 19 3 D1 Q1 18 4 D2 Q2 17 5 D3 6 D4 7 D5 Q5 14 8 D6 Q6 13 9 D7 Q7 12 LATCH 1 to 8 Q3 16 3-STATE OUTPUTS Q4 15 11 LE 1 OE MNA809 Fig.5 Functional diagram. D0 D1 D2 D3 D4 D5 D6 D7 handbook, full pagewidth D Q D Q D Q D Q D Q D Q D Q D Q LATCH 1 LATCH 2 LATCH 3 LATCH 4 LATCH 5 LATCH 6 LATCH 7 LATCH 8 LE LE LE LE LE LE LE LE LE LE LE LE LE LE LE LE LE OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 MNA810 Fig.6 Logic diagram. 2003 Oct 03 5 Philips Semiconductors Product specification Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state 74LVC573A RECOMMENDED OPERATING CONDITIONS SYMBOL VCC PARAMETER supply voltage VI input voltage VO output voltage Tamb operating ambient temperature tr, tf input rise and fall times CONDITIONS MIN. MAX. UNIT for maximum speed performance 2.7 3.6 V for low-voltage applications 1.2 3.6 V 0 5.5 V V output HIGH- or LOW-state 0 VCC output 3-state 0 5.5 in free air -40 +125 C VCC = 1.2 to 2.7 V 0 20 ns/V VCC = 2.7 to 3.6 V 0 10 ns/V LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VCC supply voltage -0.5 +6.5 V IIK input diode current VI < 0 - -50 mA VI input voltage note 1 -0.5 +6.5 V IOK output diode current VO > VCC or VO < 0 - 50 mA VO output voltage output HIGH- or LOW-state; note 1 -0.5 VCC + 0.5 V output 3-state; note 1 -0.5 +6.5 V VO = 0 to VCC IO output source or sink current - 50 mA ICC, IGND VCC or GND current - 100 mA Tstg storage temperature -65 +150 C Ptot power dissipation - 500 mW Tamb = -40 to +125 C; note 2 Notes 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. For SO20 packages: above 70 C the value of Ptot derates linearly with 8 mW/K. For (T)SSOP20 packages: above 60 C the value of Ptot derates linearly with 5.5 mW/K. For DHVQFN20 packages: above 60 C the value of Ptot derates linearly with 4.5 mW/K. 2003 Oct 03 6 Philips Semiconductors Product specification Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state 74LVC573A DC CHARACTERISTICS At recommended operating conditions voltages are referenced to GND (ground = 0 V). TEST CONDITIONS SYMBOL PARAMETER MIN. OTHER TYP.(1) MAX. UNIT VCC (V) Tamb = -40 C to +85 C VIH VIL LOW-level input voltage VOH HIGH-level output voltage VOL 1.2 VCC - - V 2.7 to 3.6 2.0 - - V 1.2 - - GND V 2.7 to 3.6 - - 0.8 V IO = -12 mA 2.7 VCC - 0.5 - - V HIGH level input voltage LOW-level output voltage VI = VIH or VIL IO = -100 A 3.0 VCC - 0.2 VCC - V IO = -18 mA 3.0 VCC - 0.6 - - V IO = -24 mA 3.0 VCC - 0.8 - - V IO = 12 mA 2.7 - - 0.40 V IO = 100 A 3.0 - GND 0.20 V IO = 24 mA 3.0 - - 0.55 V VI = VIH or VIL ILI input leakage current VI = 5.5 V or GND; note 2 3.6 - 0.1 5 A IOZ 3-state output OFF-state current VI = VIH or VIL; VO = 5.5 V or GND 3.6 - 0.1 10 A Ioff power off leakage supply VI or VO = 5.5 V 0.0 - 0.1 10 A ICC quiescent supply current VI = VCC or GND; IO = 0 3.6 - 0.1 10 A 2003 Oct 03 7 Philips Semiconductors Product specification Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state 74LVC573A TEST CONDITIONS SYMBOL PARAMETER MIN. OTHER ICC additional quiescent supply current per input pin TYP.(1) MAX. UNIT VCC (V) VI = VCC - 0.6 V; IO = 0 2.7 to 3.6 - 5 500 A 1.2 VCC - - V 2.7 to 3.6 2.0 - - V 1.2 - - GND V 2.7 to 3.6 - - 0.8 V IO = -100 A 2.7 to 3.6 VCC - 0.3 - - V IO = -12 mA 2.7 VCC - 0.65 - - V IO = -18 mA 3.0 VCC - 0.75 - - V IO = -24 mA 3.0 VCC - 1 - - V Tamb = -40 to +125 C VIH HIGH-level input voltage VIL LOW-level input voltage VOH VOL HIGH-level output voltage LOW-level output voltage VI = VIH or VIL VI = VIH or VIL IO = 100 A 2.7 to 3.6 - - 0.3 V IO = 12 mA 2.7 - - 0.6 V IO = 24 mA 3.0 - - 0.8 V ILI input leakage current VI = 5.5 V or GND 3.6 - - 20 A ICC quiescent supply current VI = VCC or GND; IO = 0 3.6 - - 40 A ICC additional quiescent supply current per input pin VI =VCC - 0.6 V; IO = 0 2.7 to 3.6 - - 5000 A Notes 1. All typical values are measured at VCC = 3.3 V and Tamb = 25 C. 2. The specified overdrive current at the data input forces the data input to the opposite logic input state. 2003 Oct 03 8 Philips Semiconductors Product specification Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state 74LVC573A AC CHARACTERISTICS GND = 0 V; tr = tf 2.5 ns; CL = 50 pF; RL = 500 . TEST CONDITIONS SYMBOL PARAMETER MIN. WAVEFORMS TYP(1). MAX. UNIT VCC (V) Tamb = -40 to +85 C tPHL/tPLH propagation delay Dn to Qn propagation delay LE to Qn tPZH/tPZL 3-state output enable time OE to Qn 3-state output disable time OE to Qn tW tsu th tsk(0) 2003 Oct 03 LE pulse width HIGH set-up time Dn to LE hold time Dn to LE skew see Figs 7 and 11 see Figs 8 and 11 see Figs 9 and 11 see Figs 9 and 11 see Fig.8 see Fig.10 see Fig.10 note 3 9 1.2 - 16 - 2.7 1.5 4.0 7.2 ns 3.0 to 3.6 1.5 3.4(2) 6.2 ns 1.2 - 16 - ns 2.7 1.5 3.4 7.5 ns 3.0 to 3.6 1.5 3.1(2) 6.5 ns 1.2 - 18 - ns 2.7 1.5 4.2 8.5 ns 3.0 to 3.6 1.5 3.5(2) 7.5 ns 1.2 - 8 - ns 2.7 1.5 2.9 6.5 ns 3.0 to 3.6 1.5 2.4(2) 6.0 ns 1.2 - - - ns 2.7 3.2 - - ns 3.0 to 3.6 3.2 1.6(2) - ns 1.2 - - - ns 2.7 1.7 - - ns 3.0 to 3.6 1.7 - - ns 1.2 - - - ns 2.7 1.5 - - ns 3.0 to 3.6 1.4 - - ns 3.0 to 3.6 - - 1.0 ns ns Philips Semiconductors Product specification Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state 74LVC573A TEST CONDITIONS SYMBOL PARAMETER MIN. WAVEFORMS TYP(1). MAX. UNIT VCC (V) Tamb = -40 to +125 C tPHL/tPLH propagation delay Dn to Qn propagation delay LE to Qn tPZH/tPZL tW tsu th tsk(0) see Figs 7 and 11 see Figs 8 and 11 3-state output enable time OE to Qn see Figs 9 and 11 3-state output disable time OE to Qn see Figs 9 and 11 LE pulse width HIGH see Fig.8 set-up time Dn to LE hold time Dn to LE skew see Fig.10 see Fig.10 note 3 1.2 - - - ns 2.7 1.5 - 9.0 ns 3.0 to 3.6 1.5 - 8.0 ns 1.2 - - - ns 2.7 1.5 - 9.5 ns 3.0 to 3.6 1.5 - 8.5 ns 1.2 - - - ns 2.7 1.5 - 11.0 ns 3.0 to 3.6 1.5 - 9.5 ns 1.2 - - - ns 2.7 1.5 - 8.5 ns 3.0 to 3.6 1.5 - 7.5 ns 1.2 - - - ns 2.7 3.2 - - ns 3.0 to 3.6 3.2 - - ns 1.2 - - - ns 2.7 1.7 - - ns 3.0 to 3.6 1.7 - - ns 1.2 - - - ns 2.7 1.5 - - ns 3.0 to 3.6 1.4 - - ns 3.0 to 3.6 - - 1.0 ns Notes 1. All typical values are measured at Tamb = 25C. 2. These typical values are measured at VCC = 3.3 V 3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design. 2003 Oct 03 10 Philips Semiconductors Product specification Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state 74LVC573A AC WAVEFORMS handbook, halfpage VI VM Dn input GND tPLH tPHL VOH VM Qn output VOL MNA811 VM = 1.5 V at VCC 2.7 V. VM = 0.5VCC at VCC < 2.7 V. VOL and VOH are the typical output voltage drop that occur with the output load. Fig.7 Input (Dn) to output (Qn) propagation delays. 1/fmax handbook, full pagewidth VI LE input VM GND tW t PHL t PLH VOH VM Qn output VOL MNA812 VM = 1.5 V at VCC 2.7 V. VM = 0.5VCC at VCC < 2.7 V. VOL and VOH are the typical output voltage drop that occur with the output load. Fig.8 Latch Enable input (LE) pulse width, the latch enable input to output (Qn) propagation delays. 2003 Oct 03 11 Philips Semiconductors Product specification Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state 74LVC573A VI handbook, full pagewidth OE input VM GND t PLZ t PZL VCC Qn output LOW-to-OFF OFF-to-LOW VM VX VOL t PZH t PHZ VOH VY Qn output HIGH-to-OFF OFF-to-HIGH VM GND outputs enabled outputs enabled outputs disabled MNA813 VM = 1.5 V at VCC 2.7 V. VM = 0.5VCC at VCC < 2.7 V. VOL and VOH are the typical output voltage drop that occur with the output load. VX = VOL + 0.3 V at VCC 2.7 V; VX = VOL + 0.1VCC at VCC < 2.7 V. VY = VOH - 0.3 V at VCC 2.7 V; VY = VOH - 0.1VCC at VCC < 2.7 V. Fig.9 3-state enable and disable times. VI handbook, full pagewidth VM Dn input GND th th t su t su VI LE input VM GND MNA814 VM = 1.5 V at VCC 2.7 V. VM = 0.5 VCC at VCC < 2.7 V. The shaded areas indicate when the input is permitted to change for predictable output performance. Fig.10 Data set-up and hold times for the Dn input to the LE input. 2003 Oct 03 12 Philips Semiconductors Product specification Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state 74LVC573A S1 handbook, full pagewidth VCC PULSE GENERATOR VI RL = 500 VO 2 x VCC open GND D.U.T. CL = RT 50 pF RL = 500 MNA815 TEST S1 VCC VI tPLH/tPHL open <2.7 V VCC tPLZ/tPZL 2 x VCC 2.7 to 3.6 V 2.7 V tPHZ/tPZH GND Definitions for test circuit: RL = load resistor. CL = load capacitance includes jig and probe capacitance. RT = termination resistance should be equal to Zo of pulse generators. Fig.11 Load circuitry for switching times. 2003 Oct 03 13 Philips Semiconductors Product specification Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state 74LVC573A PACKAGE OUTLINES SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 D E A X c HE y v M A Z 11 20 Q A2 A (A 3) A1 pin 1 index Lp L 1 10 e bp detail X w M 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y mm 2.65 0.3 0.1 2.45 2.25 0.25 0.49 0.36 0.32 0.23 13.0 12.6 7.6 7.4 1.27 10.65 10.00 1.4 1.1 0.4 1.1 1.0 0.25 0.25 0.1 0.9 0.4 inches 0.1 0.012 0.096 0.004 0.089 0.01 0.019 0.013 0.014 0.009 0.51 0.49 0.30 0.29 0.05 0.419 0.043 0.055 0.394 0.016 0.043 0.039 0.01 0.01 0.004 0.035 0.016 Z (1) 8o 0o Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT163-1 075E04 MS-013 2003 Oct 03 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 14 Philips Semiconductors Product specification Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state 74LVC573A SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm D SOT339-1 E A X c HE y v M A Z 20 11 Q A2 A (A 3) A1 pin 1 index Lp L 1 10 bp e detail X w M 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 2 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 7.4 7.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.13 0.1 0.9 0.5 8 0o Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. OUTLINE VERSION SOT339-1 2003 Oct 03 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-150 15 o Philips Semiconductors Product specification Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state 74LVC573A TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 E D A X c HE y v M A Z 11 20 Q A2 (A 3) A1 pin 1 index A Lp L 1 10 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 6.6 6.4 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.5 0.2 8 0o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT360-1 2003 Oct 03 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-153 16 o Philips Semiconductors Product specification Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state 74LVC573A DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT764-1 20 terminals; body 2.5 x 4.5 x 0.85 mm A B D A A1 E c detail X terminal 1 index area terminal 1 index area C e1 e 2 9 y y1 C v M C A B w M C b L 1 10 Eh e 20 11 19 12 Dh X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A(1) max. A1 b c D (1) Dh E (1) Eh e e1 L v w y y1 mm 1 0.05 0.00 0.30 0.18 0.2 4.6 4.4 3.15 2.85 2.6 2.4 1.15 0.85 0.5 3.5 0.5 0.3 0.1 0.05 0.05 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT764-1 --- MO-241 --- 2003 Oct 03 17 EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27 Philips Semiconductors Product specification Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state 74LVC573A DATA SHEET STATUS LEVEL DATA SHEET STATUS PRODUCT STATUS(2)(3) Development DEFINITION I Objective data II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Production This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. DEFINITIONS DISCLAIMERS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Right to make changes Philips Semiconductors reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 2003 Oct 03 18 Philips Semiconductors - a worldwide company Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com. SCA75 (c) Koninklijke Philips Electronics N.V. 2003 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands R20/03/pp19 Date of release: 2003 Oct 03 Document order number: 9397 750 11938