Document Number: 91232 www.vishay.com
S09-0006-Rev. B, 19-Jan-09 1
Power MOSFET
IRFP450N, SiHFP450N
Vishay Siliconix
FEATURES
• Low Gate Charge Qg Results in Simple Drive
Requirement
• Improved Gate, Avalanche and Dynamic dV/dt
Ruggedness
• Fully Characterized Capacitance and
Avalanche Voltage and Current
• Effective Coss Specified
• Lead (Pb)-free
APPLICATIONS
• Switch Mode Power Supply (SMPS)
• Uninterruptible Power Supply
• High Speed Power Switching
TYPICAL SMPS TOPOLOGIES
• Two Transistor Forward
• Half Bridge and Full Bridge
• PFC Boost
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Starting TJ = 25 °C, L = 1.7 mH, RG = 25 Ω, IAS = 14 A (see fig. 12).
c. ISD ≤ 14 A, dI/dt ≤ 510 A/µs, VDD ≤ VDS, TJ ≤ 150 °C.
d. 1.6 mm from case.
PRODUCT SUMMARY
VDS (V) 500
RDS(on) (Max.) (Ω)V
GS = 10 V 0.37
Qg (Max.) (nC) 77
Qgs (nC) 26
Qgd (nC) 34
Configuration Single
N-
C
hannel M
OS
FET
G
D
S
TO-247
GD
S
RoHS
COMPLIANT
ORDERING INFORMATION
Package TO-247
Lead (Pb)-free IRFP450NPbF
SiHFP450N-E3
SnPb IRFP450N
SiHFP450N
ABSOLUTE MAXIMUM RATINGS TC = 25 °C, unless otherwise noted
PARAMETER SYMBOL LIMIT UNIT
Drain-Source Voltage VDS 500 V
Gate-Source Voltage VGS ± 30
Continuous Drain Current VGS at 10 V TC = 25 °C ID
14
ATC = 100 °C 8.8
Pulsed Drain CurrentaIDM 56
Linear Derating Factor 1.6 W/°C
Single Pulse Avalanche EnergybEAS 170 mJ
Repetitive Avalanche CurrentaIAR 14 A
Repetitive Avalanche EnergyaEAR 20 mJ
Maximum Power Dissipation TC = 25 °C PD200 W
Peak Diode Recovery dV/dtcdV/dt 5.0 V/ns
Operating Junction and Storage Temperature Range TJ, Tstg - 55 to + 150 °C
Soldering Recommendations (Peak Temperature) for 10 s 300d
Mounting Torque 6-32 or M3 screw 10 lbf · in
1.1 N · m
www.vishay.com Document Number: 91232
2S09-0006-Rev. B, 19-Jan-09
IRFP450N, SiHFP450N
Vishay Siliconix
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Pulse width ≤ 400 µs; duty cycle ≤ 2 %.
c. Coss eff. is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80 % VDS.
THERMAL RESISTANCE RATINGS
PARAMETER SYMBOL TYP. MAX. UNIT
Maximum Junction-to-Ambient RthJA -40
°C/W
Case-to-Sink, Flat, Greased Surface RthCS 0.24 -
Maximum Junction-to-Case (Drain) RthJC -0.64
SPECIFICATIONS TJ = 25 °C, unless otherwise noted
PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT
Static
Drain-Source Breakdown Voltage VDS VGS = 0 V, ID = 250 µA 500 - - V
VDS Temperature Coefficient ΔVDS/TJ Reference to 25 °C, ID = 1 mA -0.59-
V/°C
Gate-Source Threshold Voltage VGS(th) VDS = VGS, ID = 250 µA 3.0 - 5.0 V
Gate-Source Leakage IGSS V
GS = ± 30 V - - ± 100 nA
Zero Gate Voltage Drain Current IDSS
VDS = 500 V, VGS = 0 V - - 25 µA
VDS = 400 V, VGS = 0 V, TJ = 125 °C - - 250
Drain-Source On-State Resistance RDS(on) V
GS = 10 V ID = 8.4 Ab- - 0.37 Ω
Forward Transconductance gfs VDS = 50 V, ID = 8.4 A 7.9 - - S
Dynamic
Input Capacitance Ciss VGS = 0 V,
VDS = 25 V,
f = 1.0 MHz, see fig. 5
- 2260 -
pF
Output Capacitance Coss - 210 -
Reverse Transfer Capacitance Crss -14-
Output Capacitance Coss VGS = 0 V
VDS = 1.0 V, f = 1.0 MHz - 2410 -
VDS = 400 V, f = 1.0 MHz - 59 -
Effective Output Capacitance Coss eff. VDS = 0 V to 400 Vc- 110 -
Total Gate Charge Qg
VGS = 10 V ID = 14 A, VDS = 400 V,
see fig. 6 and 13b
--77
nC Gate-Source Charge Qgs --26
Gate-Drain Charge Qgd --34
Turn-On Delay Time td(on)
VDD = 250 V, ID = 14 A
RG = 6.2 Ω,VGS = 10 V,
see fig. 10b
-20-
ns
Rise Time tr -63-
Turn-Off Delay Time td(off) -29-
Fall Time tf -25-
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current IS
MOSFET symbol
showing the
integral reverse
p - n junction diode
--14
A
Pulsed Diode Forward CurrentaISM --56
Body Diode Voltage VSD TJ = 25 °C, IS = 14 A, VGS = 0 Vb--1.4V
Body Diode Reverse Recovery Time trr TJ = 25 °C, IF = 14 A, dI/dt = 100 A/µsb- 430 650 ns
Body Diode Reverse Recovery Charge Qrr -3.75.6µC
Forward Turn-On Time ton Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)
S
D
G
Document Number: 91232 www.vishay.com
S09-0006-Rev. B, 19-Jan-09 3
IRFP450N, SiHFP450N
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
Fig. 1 - Typical Output Characteristics
Fig. 2 - Typical Output Characteristics
Fig. 3 - Typical Transfer Characteristics
Fig. 4 - Normalized On-Resistance vs. Temperature
0.1
1
10
100
0.1 1 10 10
20μs PULSE WIDTH
T = 25 C
J°
TOP
BOTTOM
VGS
15V
12V
10V
8.0V
7.5V
7.0V
6.5V
6.0V
V , Drain-to-Source Voltage (V)
I , Drain-to-Source Current (A)
DS
D
6.0V
1
10
100
1 10 10
20μs PULSE WIDTH
T = 150 C
J°
TOP
BOTTOM
VGS
15V
12V
10V
8.0V
7.5V
7.0V
6.5V
6.0V
V , Drain-to-Source Voltage (V)
I , Drain-to-Source Current (A)
DS
D
6.0V
0.1
1
10
100
6.0 7.0 8.0 9.0 10.0
V = 50V
20μs PULSE WIDTH
DS
V , Gate-to-Source Voltage (V)
I , Drain-to-Source Current (A)
GS
D
T = 25 C
J°
T = 150 C
J°
-60 -40 -20 020 40 60 80 100 120 140 160
0.0
0.5
1.0
1.5
2.0
2.5
3.0
T , Junction Temperature ( C)
R , Drain-to-Source On Resistance
(Normalized)
J
DS(on)
°
V =
I =
GS
D
10V
14A
www.vishay.com Document Number: 91232
4S09-0006-Rev. B, 19-Jan-09
IRFP450N, SiHFP450N
Vishay Siliconix
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
Fig. 7 - Typical Source-Drain Diode Forward Voltage
Fig. 8 - Maximum Safe Operating Area
110 100 1000
VDS, Drain-to-Source Voltage (V)
1
10
100
1000
10000
100000
C,Capacitance(pF)
Coss
Crss
Ciss
VGS = 0V, f = 1 MHZ
Ciss = C
gs + C
gd, C
ds SHORTED
Crss
= C
gd
Coss
= C
ds
+ C
gd
020 40 60 80
0
4
8
12
16
20
Q , Total Gate Charge (nC)
V , Gate-to-Source Voltage (V)
G
GS
FOR TEST CIRCUIT
SEE FIGURE
I =
D
13
14A
V = 100V
DS
V = 250V
DS
V = 400V
DS
0.1
1
10
100
0.2 0.4 0.6 0.8 1.0 1.2 1.4
V ,Source-to-Drain Voltage (V)
I , Reverse Drain Current (A)
SD
SD
V = 0 V
GS
T = 25 C
J°
T = 150 C
J°
1 10 100 1000 10000
VDS , Drain-toSource Voltage (V)
0.1
1
10
100
1000
ID,Drain-to-SourceCurrent(A)
Tc = 25°C
Tj = 150°C
Single Pulse
1msec
10msec
OPERATION IN THIS AREA
LIMITED BY R DS(on)
100μsec
Document Number: 91232 www.vishay.com
S09-0006-Rev. B, 19-Jan-09 5
IRFP450N, SiHFP450N
Vishay Siliconix
Fig. 9 - Maximum Drain Current vs. Case Temperature
Fig. 10a - Switching Time Test Circuit
Fig. 10b - Switching Time Waveforms
Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case
25 50 75 100 125 150
0
2
4
6
8
10
12
14
T , Case Temperature ( C)
I , Drain Current (A)
°
C
D
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
RD
VGS
RG
D.U.T.
10 V
+
-
VDS
VDD
VDS
90 %
10 %
VGS
td(on) trtd(off) tf
0.01
0.1
1
0.00001 0.0001 0.001 0.01 0.1
Notes:
1. Duty factor D = t / t
2. Peak T = P x Z + T
1 2
JDM thJC C
P
t
t
DM
1
2
t , Rectangular Pulse Duration (sec)
Thermal Response (Z )
1
thJC
0.01
0.02
0.05
0.10
0.20
D = 0.50
SINGLE PULSE
(THERMAL RESPONSE)
www.vishay.com Document Number: 91232
6S09-0006-Rev. B, 19-Jan-09
IRFP450N, SiHFP450N
Vishay Siliconix
Fig. 12a - Unclamped Inductive Test Circuit Fig. 12b - Unclamped Inductive Waveforms
Fig. 12c - Maximum Avalanche Energy vs. Drain Current
Fig. 13a - Basic Gate Charge Waveform Fig. 13b - Gate Charge Test Circuit
A
R
G
I
AS
0.01
Ω
t
p
D.U.T.
L
VDS
+
-V
DD
Driver
A
15 V
20 V
IAS
VDS
tp
25 50 75 100 125 150
0
50
100
150
200
250
300
Starting T , Junction Temperature ( C)
E , Single Pulse Avalanche Energy (mJ)
J
AS
°
ID
TOP
BOTTOM
6.3A
8.9A
14A
QGS QGD
QG
V
G
Charge
V
GS
D.U.T.
3 mA
VGS
VDS
IGID
0.3 µF
0.2 µF
50 kΩ
12 V
Current regulator
Current sampling resistors
Same type as D.U.T.
+
-
Document Number: 91232 www.vishay.com
S09-0006-Rev. B, 19-Jan-09 7
IRFP450N, SiHFP450N
Vishay Siliconix
Fig. 14 - For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.c om/ppg?91232.
P.W.Period
dI/dt
Diode recovery
dV/dt
Ripple ≤5 %
Body diode forward drop
Re-applied
voltage
Reverse
recovery
current
Body diode forward
current
V
GS
= 10 V*
V
DD
I
SD
Driver gate drive
D.U.T. I
SD
waveform
D.U.T. V
DS
waveform
Inductor current
D = P.W.
Period
+
-
+
+
+
-
-
-
* VGS = 5 V for logic level devices
Peak Diode Recovery dV/dt Test Circuit
VDD
• dV/dt controlled by RG
• Driver same type as D.U.T.
• ISD controlled by duty factor "D"
• D.U.T. - device under test
D.U.T Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
RG
Document Number: 91000 www.vishay.com
Revision: 18-Jul-08 1
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