200-MHz 24-Output Buffer for 4 DDR
or 3 SDRAM DIMMS
W255
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-07255 Rev. *B Revised April 26, 2002
Features
• One input to 24-output buffer/driver
• Supports up to 4 DDR DIMMs or 3 SDRAM DIMMS
• One a dditional output for feedb ack
• SMBus interface for individual output control
• Low skew outputs (< 100 ps)
• Supports 266-, 333-, and 400-MHz DDR SDRAM
• Dedicated pin for power management support
• Space-saving 48-pin SSOP package
Functional Description
The W255 is a 3.3V/2.5V buffer designed to distribute
high-speed clocks in PC applications. The part has 24 outputs.
Designers can configure these outputs to support four unbuf-
fered DDR DIMMS or to support three unbuffered standard
SDRAM DIMMs and two DDR DIMMS. The W255 can be used
in conjunction with the W250 or similar clock synthesizer for
the VIA Pro 266 chipset.
The W255 also includes an SMBus interface which can enable
or disable each output clock. On power-up, all output clocks
are enabled (internal pull up).
Block Diagram
SMBus
BUF_IN
SDATA
SCLOCK
DDR0T_SDRAM10
DDR0C_SDRAM11
DDR1T_SDRAM0
DDR1C_SDRAM1
DDR2T_SDRAM2
DDR2C_SDRAM3
DDR3T_SDRAM4
DDR3C_SDRAM5
1
2
3
4
SEL_DDR*
VDD2.5
GND
DDR11T
DDR11C
DDR10T
DDR10C
VDD2.5
SSOP
Top View
Pin Configuration
Decoding
8
5
6
7
12
9
10
11
13
14
15
16
20
17
18
19
24
21
22
23
48
47
46
45
41
44
43
42
37
40
39
38
36
35
34
33
29
32
31
30
25
28
27
26
GND
DDR9T
DDR9C
VDD2.5
PWR_DWN#*
GND
DDR8T
DDR8C
VDD2.5
GND
DDR7T
DDR7C
DDR6T
DDR6C
GND
SCLK
FBOUT
VDD3.3_2.5
GND
DDR0T_SDRAM10
DDR0C_SDRAM11
DRR1T_SDRAM0
DDR1C_SDRAM1
VDD3.3_2.5
DDR2T_SDRAM2
DDR2C_SDRAM3
VDD3.3_2.5
BUF_IN
GND
DDR3T_SDRAM4
DDR3C_SDRAM5
VDD3.3_2.5
GND
DDR4T_SDRAM6
DDR4C_SDRAM7
DDR5T_SDRAM8
DDR5C_SDRAM9
VDD3.3_2.5
SDATA
GND
DDR4T_SDRAM6
DDR4C_SDRAM7
DDR5T_SDRAM8
DDR5C_SDRAM9
DDR6T
DDR6C
DDR7T
DDR7C
DDR8T
DDR8C
R_DWN#
DDR9T
DDR9C
DDR10T
DDR10C
DDR11T
DDR11C
FBOUT
Power Down Control
SEL_DDR
Note:
1. Internal 100K pull-up resistors present on inputs marked
with *. Design should not rely solely on internal pull-up resistor
to set I/O pins HIGH.
W255
Document #: 38-07255 Rev. *B Page 2 of 10
Pin Summary
Pin Name Pins Pin Description
SEL_DDR 48 Input to configure for DDR-ONLY mode or STANDARD SDRAM
mode.
1 = DDR-ONLY mode.
0 = STANDARD SDRAM mode.
When SEL_DDR is pulled HIGH or configured for DDR-ONL Y mode, pin
4, 5, 6, 7, 10, 11,15, 16, 19, 20, 21, 22, 27, 28, 29, 30, 33, 34, 38, 39,
42, 43, 44 and 45 will be configured as DDR outputs.
Connect VDD3.3_2.5 to a 2.5V power supply in DDR-ONLY mode.
When SEL_ D DR is p ull ed LO W or con fig ured for STANDARD SDRAM
output, pin 4, 5, 6, 7, 10 , 11, 15, 16 , 19 and 20, 21, 22 will be configu red
as STANDARD SDRAM outputs.Pin 27, 28, 29, 30, 33, 34, 38, 39, 42,
43, 44 and 45 will be configured as DDR outputs.
Connect VDD3.3_2.5 to a 3.3V power supply in STANDARD SDRAM
mode.
SCLK 25 SMBus clock input
SDATA 24 SMBus data input
BUF_IN 13 Referen ce i nput from ch ipse t . 2.5V input for DDR-ONLY mode; 3.3V
input for STANDARD SDRAM mode.
FBOUT 1Feedback clock for chipset. Output voltage depends on VDD3.3_2.5V.
PWR_DWN# 36 Active LOW input to enable power-down mode; all outputs will be
pulled LOW.
DDR[6:11]T 28, 30, 34, 39, 43, 45 Clock outputs. These outputs provide copies of BUF_IN.
DDR[6:11]C 27, 29, 33, 38, 42, 44 Clock outputs. These outputs provide complementary copies of
BUF_IN.
DDR[0:5]T_SDRAM
[10,0,2,4,6,8] 4, 6, 10, 15, 19, 21 Clock outputs. These outputs provide copies of BUF_IN. V oltage swing
depends on VDD3.3_2.5 power supply.
DDR[0:5]C_SDRAM
[11,1,3,5,7,9] 5, 7, 11, 16, 20, 22 Clock outputs. These outputs provide complementary copies of
BUF_IN when SEL_DDR is active. These outputs provide copies of
BUF_IN when SEL_DDR is inactive. Voltage swi ng depends on
VDD3.3_ 2.5 pow e r suppl y.
VDD3.3_2.5 2, 8, 12, 17, 23 Connect to 2.5V power supply when W255 is configured for
DDR-ONLY mo de. Connect to 3.3V power supply, when W255 is
configured for standard SDRAM mode.
VDD2.5 32, 37, 41, 47 2.5V voltage supp ly
GND 3, 9, 1 4, 18, 26, 3 1, 35, 40, 4 6 Ground
W255
Document #: 38-07255 Rev. *B Page 3 of 10
Serial Configuration Map
•The serial bits will be read by the clock driver in the following
order:
Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0
.
.
Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0
•Reserved and unused bits should be programmed to “0.”
•SMBus Address for the W255 is:
A6 A5 A4 A3 A2 A1 A0 R/W
1101001----
Byte 6: Outputs Active /Inactive Register
(1 = Active, 0 = Inactive), Default = Active
Bit Pin # Description Default
Bit 7 –Reserved, drive to 0 0
Bit 6 –Reserved, drive to 0 0
Bit 5 –Reserved, drive to 0 0
Bit 4 1FBOUT 1
Bit 3 45,44 DDR11T, DDR11C 1
Bit 2 43, 42 DDR10T, DDR10C 1
Bit 1 39, 38 DDR9T, DDR9C 1
Bit 0 34, 33 DDR8T, DDR8C 1
Byte 7: Outputs Active/Inactive Register
(1 = Active, 0 = Inactive), Defaul t = Active
Bit Pin # Description Default
Bit 7 30, 29 DDR7T, DDR7C 1
Bit 6 28, 27 DDR6T, DDR6C 1
Bit 5 21, 22 DDR5T_SDRAM8,
DDR5C_SDRAM9 1
Bit 4 19, 20 DDR4T_SDRAM6,
DDR4C_SDRAM7 1
Bit 3 15,16 DDR3T_SDRAM4,
DDR3C_SDRAM5 1
Bit 2 10, 11 DDR2T_SDRAM2,
DDR2C_SDRAM3 1
Bit 1 6, 7 DDR1T_SDRAM0,
DDR1C_SDRAM1 1
Bit 0 4, 5 DDR0T_SDRAM10,
DDR0C_SDRAM11 1
W255
Document #: 38-07255 Rev. *B Page 4 of 10
Maximum Ratings
Supply Voltage to Ground Potential..................–0.5 to +7.0V
DC Input Voltage (except BUF_IN)............–0.5V to VDD+0.5
Storage Temperature.................................. –65°C to +150°C
Static Discharge Voltage..........................................> 2000V
(per MIL-STD-883, Method 3015)
Operating Condit ions
Parameter Description Min. Typ. Max. Unit
VDD3.3 Supply Voltage 3.135 3.465 V
VDD2.5 Supply Voltage 2.375 2.625 V
TAOperating Temperature (Ambient Temperature) 0 70 °C
COUT Out put C apa ci tanc e 6 pF
CIN Input Capacitance 5 pF
Electri cal Characteristics Over the Operating Range
Parameter Description Test Conditions Min. Typ. Max. Unit
VIL Input LOW Voltage For all pins except SMBus 0.8 V
VIH Input HIGH Voltage 2.0 V
IIL Input LOW Current VIN = 0V 50 µA
IIH Input HIGH Current VIN = VDD 50 µA
IOH Output HIGH Current VDD = 2.375V
VOUT = 1V –18 –32 mA
IOL Out put LOW Current VDD = 2.375V
VOUT = 1.2V 26 35 mA
VOL Output LOW Voltage[2] IOL = 12 mA, VDD = 2.375V 0.6 V
VOH Output HIGH Voltage[2] IOH = –12 mA, VDD = 2. 375V 1.7 V
IDD Supply Current[2]
(DDR-only mode) U nl oad ed outputs, 13 3 MH z 400 mA
IDD Supply Current
(DDR-only mode) Loaded outputs, 133 MHz 500 mA
IDDS Supply Current PWR_DWN# = 0 100 µA
VOUT Output Voltage Swing See test circuity (refer to
Figure 1)0.7 VDD +0.6 V
VOC Output Crossing Voltage (VDD/2)
–0.1 VDD/2 (VDD/2)
+0.1 V
INDC Input Clock Duty Cycle 48 52 %
Switching Characteristics [3]
Parameter Name Test Conditions Min. Typ. Max. Unit
–Operati ng Frequency 66 200 MHz
–Duty Cycle[2, 4] = t2 ÷ t1Measured at 1.4V for 3.3V outputs
Measured at VDD/2 for 2.5V outputs INDC
–5% INDC
+5% %
t3SDRAM Rising Edge Rate[2] Measured between 0.4V and 2.4V 1.0 2.75 V/ns
t4SDRAM Falling Edge Rate[2] Measured between 2.4V and 0.4V 1.0 2.75 V/ns
t3d DDR Rising Edge Rate[2] Measured between 20% to 80% of
output (refer to Figure 1)0.5 1.50 V/ns
Notes:
2. Parameter is guaranteed by design and characterization. Not 100% tested in production.
3. All parameters specified with loaded outputs.
4. Duty cycle of input clock is 50%. Rising and falling edge rate is greater than 1 V/ns.
W255
Document #: 38-07255 Rev. *B Page 5 of 10
t4d DDR Falling Edge Rate[2] Measured between 20% to 80% of
output (refer to Figure 1)0.5 1.50 V/ns
t5Out put to O utput Sk ew fo r DDR[2] All outputs equally loaded 100 ps
t6Output to Output Skew for
SDRAM[2] All outputs equally loaded 150 ps
t7SDRAM Buffer LH Prop. Delay[2] Input edge grea ter than 1 V/ns 5 10 ns
t8SDRAM Buffer HL Prop. Delay[2] Input edge greater than 1 V/ns 5 10 ns
Switching Characteristics (continued)[3]
Parameter Name Test Conditions Min. Typ. Max. Unit
Switching Waveforms
Duty Cycle Timing
t1
t2
All Outputs Rise/Fall Time
OUTPUT
t3
3.3V
0V
0.4V
2.4V 2.4V
0.4V
t4
Output-Output Skew
t5
OUTPUT
OUTPUT
SDRAM Buffer HH and LL Propagation Delay
t6
INPUT
OUTPUT
t7
1.5V
1.5V
W255
Document #: 38-07255 Rev. *B Page 6 of 10
Order in g In fo rmat io n
Ordering Code Package Type Operating Range
W255H 48-pin SSOP Commercial
W255HT 48-pin SSOP–Tape and Reel Option Commercial
)
)RT =120Ω
Receiver
60W
60W
VCC
VCC
Device
Under
Test
Figure 1. Differential Signal Using Direct Termination Resistor
Figure 1 shows the differential clock directly terminated by a 120Ω resistor.
Out
Out VTR
VCP
W255
Document #: 38-07255 Rev. *B Page 7 of 10
Layout Example for DDR 2.5V Only
FB
C4 10 mF
0.005 mF
G G
VDDQ2
C3
48
47
46
45
44
43
42
41
40
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
39
G
V
G= VIA to GND plane layer V = VIA to respective supply plane layer
Note: Each supply plane or strip should have a
ferrite bead and capacitors
Ceramic Caps C3 = 10–22 µF C4 = 0.005 µF
FB = Dale ILB1206 - 300 (300Ω @ 100 MHz) or TDK ACB 2012L-120
All bypass caps = 0.1 µF ceram i c
GV
GV
GV
GV
GV
G
V
G
V
G
V
W255
G
G
G
GG
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
W255
Document #: 38-07255 Rev. *B Page 8 of 10
Layout Example SDRAM (Mixed Voltage)
FB
C4 10 mF
FB
C1 C2
0.005 mf
10 mF
0.005 mF
G G GG
VDDQ2
VDDQ3
C3
48
47
46
45
44
43
42
41
40
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
39
G
V
G= VIA to GND plane layer V= VIA to respective supply plane layer
Note: Each supply plane or strip should have a
ferrite bead and capacitors
Ceramic Caps C1 and C3 = 10–22 µFC2 & C4 = 0.005 µF
FB = Dale ILB1206 - 300 (300Ω @ 100 MHz) or TDK ACB 2012L-120
C6 = 0.1 µF
GV
All bypass caps = 0.1 µF ceramic
GV
GV
GV
GV
G
V
G
V
G
V
W255
G
G
GG
G
G
G
G G
G
G
G
G
GG
G
G
G
W255
Document #: 38-07255 Rev. *B Page 9 of 10
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry emb odied in a Cypress Semiconductor product. Nor does it convey or imply any license under paten t or other rights. Cypress Semi conductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconducto r products in life-support systems application implies that the manu factur er assume s all risk of such use and in doi
ng so indemnifies Cypress Semiconductor against all charges.
VIA is a t r ade ma rk of VI A Technologi es , In c. All produc t an d c om pa ny nam es m en tion ed in thi s d oc um ent are the trad em ark s of
their respective holders.
Package Diagram
48-lead Shrunk Small Outline Package O48
51-85061-*C
W255
Document #: 38-07255 Rev. *B Page 10 of 10
Document Title: W255 200MHz 24 Output Buffer for 4 DDR or 3 SDRAM DIMMs
Document Number: 38-07255
REV. ECN NO. Issue
Date Orig. of
Change Description of Change
** 110520 12/04/01 SZV Change from Spec number: 38-01082 to 38-07255
*A 11 2154 03/01/02 IKA Added 333 MHz for DDR SDRAM
*B 11 4554 05/07/02 INA Added 400 MHz for DDR SDRAM
