CCD39-01 Back Illuminated High Performance CCD Sensor FEATURES * 80 by 80 1:1 Image Format * Image Area 1.92 x 1.92 mm * Split-frame Transfer Operation * 24 mm Square Pixels * Symmetrical Anti-static Gate Protection * Four High Performance Very Low Noise Output Amplifiers * High Frame Rate Operation (up to 1000 fps) * High Spectral Response * 100% Active Area APPLICATIONS * Astronomy * Scientific Imaging INTRODUCTION The CCD39-01 is a small split-frame transfer device optimised for use at high frame rates which makes it particularly suited to the tracking of point source objects. To optimise the dynamic range, the sensitivity is maximised by combining back illumination technology with large pixels and non-antibloomed architecture. The noise floor of the chip is kept low by an advanced amplifier which permits operation at 1 MHz with noise levels typical of slow-scan operation. Dark signal noise is limited by cryogenic cooling or by an optional Peltier package which is sufficient for most applications when charge dithering effects are considered. The device has split-frame transfer architecture with four amplifiers, each reading a block of 40 x 40 pixels. The output circuit has a very small first-stage transistor to maximise the responsivity and minimise the noise, with only minimal loading from the much larger second-stage transistor, which provides a high level of drive capability. The connections to the circuit are identical to those of a single-stage type, the only difference being a standing current (1 mA) flowing in the substrate connection. There is no light emission to cause the generation of spurious charge. Designers are advised to consult e2v technologies should they be considering using CCD sensors in abnormal environments or if they require customised packaging. TYPICAL PERFORMANCE Maximum readout frequency Output responsivity . . . Peak signal . . . . . . Spectral range . . . . . Readout noise (at 20 kHz) . QE at 500 nm . . . . . . . . . . . . . . . . . . . . 43 MHz . . . 4.5 mV/e7 . . . 300 ke7/pixel 200 - 1100 nm . . . 3 e7 rms . . . 90 % . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32.89 x 20.07 mm . . . . . . . 24 . . . . . 2.54 mm quartz or removable glass . . ceramic DIL array GENERAL DATA Format Image area . . . . . . Active pixels (H) . . . . (V) . . . . Pixel size . . . . . . . Storage areas (x 2) . . . . Pixels (H) . . . . . . . (V) . . . . . . . Number of output amplifiers 1.92 x 1.92 mm . . 80 . . 80 + 4 . . 24 x 24 mm 1.92 x 0.96 mm each . . 80 . . 40 . . . . . . . 4 Package Package size . . Number of pins . Inter-pin spacing Window material Type . . . . . . . . . . . . . . . . . . . . . . . . e2v technologies (uk) limited, Waterhouse Lane, Chelmsford, Essex CM1 2QU, UK Telephone: +44 (0)1245 493493 Facsimile: +44 (0)1245 492492 e-mail: enquiries@e2v.com Internet: www.e2v.com Holding Company: e2v technologies plc e2v technologies inc. 4 Westchester Plaza, PO Box 1482, Elmsford, NY10523-1482 USA Telephone: (914) 592-6050 Facsimile: (914) 592-5148 e-mail: enquiries@e2vtechnologies-na.com # e2v technologies (uk) limited 2006 A1A-100036 Issue 6, March 2006 411/9572 PERFORMANCE Min Peak charge storage (see note 1) Peak output voltage (no binning) Dark signal at 293 K (see notes 2 and 3) Charge transfer efficiency (see note 4): parallel serial Output amplifier sensitivity (see note 3) Readout noise at 243 K (see notes 3 and 5) Readout frequency Dark signal non-uniformity (std. deviation) (see notes 3 and 7) Typical 200k - - 300k 1350 75k Max e7/pixel mV e7/pixel/s - - 145k - - 3 - - 99.9999 99.9993 4.5 3 20 - - 6 4 see note 6 - 7.5k 14.5k % % mV/e7 7 rms e /pixel kHz e7/pixel/s Spectral Response (with standard AR coating) Wavelength (nm) 350 400 500 650 900 Spectral Response Minimum Typical 40 75 80 75 30 Maximum Response Non-uniformity (1s) 70 85 90 85 35 5 3 3 3 5 % % % % % ELECTRICAL INTERFACE CHARACTERISTICS Electrode capacitances (measured at mid-clock level): Min I1/I1 interphase, S1/S1 interphase I1/SS, S1/SS R1/R1 interphase R1/SS 1R/SS Output impedance (at typ. operating condition) - - - - - - Typical 50 100 7 20 10 300 Max - - - - - - pF pF pF pF pF O NOTES 1. Peak signal capacity is limited by the output circuit. 2. Measured between 233 and 253 K and VSS +9.0 V. Dark signal at any temperature T (kelvin) is then estimated from: Qd/Qd0 = 122T3e76400/T where Qd0 is the dark signal at T = 293 K (20 8C). 3. Test carried out at e2v technologies on all sensors. 4. It is not practicable to measure charge transfer efficiency with so few pixels, but in general e2v technologies devices give the figures shown. 5. Measured using a dual-slope integrator technique (i.e. correlated double sampling) with a 10 ms integration period. 6. Readout at speeds in excess of 3 MHz can be achieved but performance to the parameters given cannot be guaranteed. 7. Measured between 233 and 253 K, excluding white defects. 100036, page 2 # e2v technologies BLEMISH SPECIFICATION Traps Slipped columns Black spots White spots White column Black column Pixels where charge is temporarily held. Traps are counted if they have a capacity greater than 200 e7 at 243 K. Are counted if they have an amplitude greater than 200 e7. Are counted when they have a signal level of less than 80% of the local mean at a signal level of approximately half full-well. Are counted when they have a generation rate 10 times the specified maximum dark signal generation rate (measured between 233 and 253 K). The amplitude of white spots will vary in the same manner as dark current, i.e.: Qd/Qd0 = 122T3e76400/T A column which contains at least 9 white defects. A column which contains at least 9 black defects. GRADE 0 1 5 Column defects: black or slipped white Black spots Traps 4200 e7 White spots 0 0 2 0 0 0 0 4 0 2 2 2 130 2 20 Note The effect of temperature on defects is that traps will be observed less at higher temperatures but more may appear below 243 K. The amplitude of white spots and columns will decrease rapidly with temperature. # e2v technologies 100036, page 3 TYPICAL OUTPUT CIRCUIT NOISE (Measured using clamp and sample) VSS = 9.0 V VRD = 17 V VOD = 29 V 10 7668 NOISE EQUIVALENT SIGNAL (e-- r.m.s.) 8 6 4 2 0 10k FREQUENCY (Hz) 50k 100k 500k 1M 5M TYPICAL SPECTRAL RESPONSE (at 720 8C) (No window, standard AR coating) 100 7748 80 QUANTUM EFFICIENCY (%) 60 40 20 0 200 300 WAVELENGTH (nm) 400 500 600 700 800 900 1000 TYPICAL VARIATION OF DARK SIGNAL WITH SUBSTRATE VOLTAGE (Two I1 phases held high at +20 8C) 200 7670 DARK SIGNAL (k e7/pixel/s) 150 TYPICAL RANGE 100 50 0 0 1 2 3 SUBSTRATE VOLTAGE VSS (V) 100036, page 4 4 5 6 7 8 9 10 # e2v technologies TYPICAL VARIATION OF DARK SIGNAL WITH TEMPERATURE (Vss = +9.0 V) 106 7671 105 104 103 DARK SIGNAL (e7/pixel/s) 102 10 1 1071 780 760 PACKAGE TEMPERATURE (8C) 740 720 0 20 40 DEVICE SCHEMATIC 7741A SS 24 1 OS4 Note: 1RR 23 2 SS I11 22 I12 21 I13 20 R12 19 R13 18 R11 17 S13 16 S12 15 40 x 80 ELEMENTS NOMINAL 24 mm SQUARE 80 x 80 ELEMENTS NOMINAL 24 mm SQUARE 40 x 80 ELEMENTS NOMINAL 24 mm SQUARE STORE AREA IMAGE AREA STORE AREA 3 OS3 4 ODR 5 RDR 6 OGR 7 OGL 8 RDL 9 ODL 10 OS2 S11 14 1RL 13 11 SS 12 OS1 Alignment of the store shield may cause the number of image rows from each quadrant to vary by +2 rows. # e2v technologies 100036, page 5 CONNECTIONS, TYPICAL VOLTAGES AND ABSOLUTE MAXIMUM RATINGS PULSE AMPLITUDE OR DC LEVEL (V) (See note 8) Min Typical Max MAXIMUM RATINGS with respect to VSS see note 9 70.3 to +25 V PIN REF DESCRIPTION 1 OS4 Output source: output circuit 4 2 SS Substrate 3 OS3 Output source: output circuit 3 4 ODR Output drain: output circuits 3 and 4 27 29 31 70.3 to +35 V 5 RDR Reset drain: output circuits 3 and 4 15 17 19 70.3 to +25 V 6 OGR Output gate: output circuits 3 and 4 1 3 5 +25 V 7 OGL Output gate: output circuits 1 and 2 1 3 5 +25 V 8 RDL Reset drain: output circuits 1 and 2 15 17 19 70.3 to +25 V 9 ODL Output drain: output circuits 1 and 2 27 29 31 70.3 to +35 V 10 OS2 Output source: output circuit 2 11 SS Substrate 12 OS1 Output source: output circuit 1 13 1RL Output reset pulse: output circuits 1 and 2 8 12 15 +25 V 14 S11 Store section, phase 1 (clock pulse) 8 12 15 +25 V 15 S12 Store section, phase 2 (clock pulse) 8 12 15 +25 V 16 S13 Store section, phase 3 (clock pulse) 8 12 15 +25 V 17 R11 Readout register, phase 1 (clock pulse) 8 11 15 +25 V 18 R13 Readout register, phase 3 (clock pulse) 8 11 15 +25 V 19 R12 Readout register, phase 2 (clock pulse) 8 11 15 +25 V 20 I13 Image section, phase 3 (clock pulse) 8 12 15 +25 V 21 I12 Image section, phase 2 (clock pulse) 8 12 15 +25 V 22 I11 Image section, phase 1 (clock pulse) 8 12 15 +25 V 23 1RR Output reset pulse: output circuits 3 and 4 8 12 15 +25 V 24 SS Substrate 0 9 10 - 0 9 10 70.3 to +25 V see note 9 0 9 - 70.3 to +25 V see note 9 10 - 70.3 to +25 V see note 9 Maximum voltages between pairs of pins: pin 4 (ODR) to pins 1, 3 (OS3, 4) . . . . . +15 V pin 9 (ODL) to pins 10, 12 (OS1, 2) . . . . +15 V Maximum output transistor current . . . . . . 10 mA NOTES 8. Readout register clock pulse low levels +1 V; other clock low levels 0 + 0.5 V. 9. Connect to ground via an external load (see note 16). 10. All devices will operate at the typical values given. However, some adjustment within the minimum to maximum range may be required to optimise performance for critical applications. It should be noted that conditions for optimum performance may differ from device to device. 100036, page 6 # e2v technologies FRAME TRANSFER TIMING DIAGRAM 7742 CHARGE COLLECTION PERIOD 40 CYCLES I11 I12 I13 Ti 540 CYCLES S11 S12 S13 SEE DETAIL OF LINE TRANSFER FRAME TRANSFER PERIOD 41 LINE TIME R11 R12 R13 1RL, 1RR OS1, 2, 3 OR 4 SEE DETAIL OF OUTPUT CLOCKING READOUT PERIOD DETAIL OF LINE TRANSFER twi tdir 7686 S11 1 toi /3Ti S12 toi toi S13 tdri R11 R12 R13 1R # e2v technologies 100036, page 7 DETAIL OF OUTPUT CLOCKING 7133A R11 Tr tor R12 R13 twx tdx 1R SIGNAL OUTPUT OUTPUT VALID OS RESET FEEDTHROUGH LINE OUTPUT FORMAT 7743 4 BLANK 40 ACTIVE OUTPUTS CLOCK TIMING REQUIREMENTS Symbol Ti twi tri tfi toi tdir tdri Tr trr tfr tor twx trx, tfx tdx Description Image clock period Image clock pulse width Image clock pulse rise time (10 to 90%) Image clock pulse fall time (10 to 90%) Image clock pulse overlap Delay time, S1 stop to R1 start Delay time, R1 stop to S1 start Output register clock cycle period Clock pulse rise time (10 to 90%) Clock pulse fall time (10 to 90%) Clock pulse overlap Reset pulse width Reset pulse rise and fall times Delay time, 1R low to R13 low Min Typical Max 0.2 0.1 30 30 0 1 Tr/3 330 10 10 0 30 0.2twx 30 2.0 1.0 100 100 0.5tri 2 Tr 1000 0.1Tr 0.1Tr 0.5trr 0.1Tr 0.5trr 0.5Tr see note see note 0.2Ti 0.2Ti 0.2Ti see note see note see note 0.2Tr 0.2Tr 0.1Tr 0.3Tr 0.1Tr 0.8Tr 11 11 11 11 11 ms ms ns ns ms ms ms ns ns ns ns ns ns ns NOTES 11. No maximum other than that necessary to achieve an acceptable dark signal at the longer readout times. 12. To minimise dark current, two of the I1 clocks should be held low during integration. I1 timing requirements are identical to S1 (as shown above). 100036, page 8 # e2v technologies OUTPUT CIRCUIT 7744 RD R13 1R S13 (SEE NOTE 13) OD OG OS OUTPUT EXTERNAL LOAD (SEE NOTE 14) SS SS 0V NOTES 13. The amplifier has a DC restoration circuit which is internally activated whenever S13 is high. 14. Not critical; can be a 2 to 5 mA constant current supply or an appropriate 3.3k - 10 kO load resistor. The quiescent voltage on OS is then approximately VOD 7 4 V. # e2v technologies 100036, page 9 OUTLINE (All dimensions without limits are nominal) 7745 A F IMAGE PLANE E D G B IMAGING AREA E H D C J PIN 1 K L 100036, page 10 Ref Millimetres A B C D E 32.89 20.07 3.3 1.92 0.96 F 0.254 G H J K L + 0.051 7 0.025 15.24 + 0.25 2.305 + 0.600 4.85 min 2.54 + 0.15 27.94 + 0.15 # e2v technologies ORDERING INFORMATION HANDLING CCD SENSORS Options include: CCD sensors, in common with most high performance MOS IC devices, are static sensitive. In certain cases a discharge of static electricity may destroy or irreversibly degrade the device. Accordingly, full antistatic handling precautions should be taken whenever using a CCD sensor or module. These include:- * Temporary Quartz Window * Permanent Quartz Window * Temporary Glass Window * Permanent Glass Window * Working at a fully grounded workbench Operator wearing a grounded wrist strap Fibre-optic Coupling * * UV Coating * All receiving socket pins to be positively grounded * X-ray Phosphor Coating * Unattended CCDs should not be left out of their conducting foam or socket. * For further information on the performance of these and other options, please contact e2v technologies. Evidence of incorrect handling will invalidate the warranty. All devices are provided with internal protection circuits to the gate electrodes (pins 6, 7, 13 to 23) but not to the other pins. HIGH ENERGY RADIATION Device characteristics will change when subject to ionising radiation. Users planning to operate CCDs in high radiation environments are advised to contact e2v technologies. TEMPERATURE LIMITS Min Typical Max Storage . . . . . . . 73 - 373 K Operating . . . . . . . 73 243 323 K Operation or storage in humid conditions may give rise to ice on the sensor surface on cooling, causing irreversible damage. Maximum device heating/cooling . . 5 K/min Whilst e2v technologies has taken care to ensure the accuracy of the information contained herein it accepts no responsibility for the consequences of any use thereof and also reserves the right to change the specification of goods without notice. e2v technologies accepts no liability beyond that set out in its standard conditions of sale in respect of infringement of third party patents arising from the use of tubes or other devices in accordance with information contained herein. # e2v technologies Printed in England 100036, page 11