An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

– Has Adjustments for Transmit Swing, De-

– May Be Marked as Removable or

– Has Independent Power Control and

• Requires No External Flash for Default

– Optional Serial EEPROM for Custom

the end of the data sheet.

5 Pin Configuration and Functions......................... 3

7.5 Register Maps ........................................................ 19

8.1 Application Information............................................ 95

8.2 Typical Application ................................................. 96

9.2 PCI Express Power Management......................... 105

11.4 Related Links ...................................................... 109

11.5 Trademarks......................................................... 109

11.6 Electrostatic Discharge Caution.......................... 109

11.7 Glossary.............................................................. 109

Information......................................................... 109

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional

Modes,Application and Implementation section, Power Supply Recommendations section, Layout section, Device

row ....................................................................................................................................................................................... 55

Changes from Revision K (March 2011) to Revision L Page

• Added text "If a 48 MHz reference clock is used instead of a crystal, GRST# must remain asserted until the 48 MHz

• Added text - "If a 48 MHz reference clock is used instead of a crystal, GRST# must remain asserted until the 48

MHz clock is stable"............................................................................................................................................................ 104

• Replaced the Power Up Sequence image ......................................................................................................................... 104

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RKM Package

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(1) The only failsafe pins in the device are WAKE and CLKREQ#. No other pins are failsafe.

NO. TUSB7340

CLOCK AND RESET SIGNALS

XO A22 A22 O Crystal output. This terminal is crystal output for the internal oscillator. If XI is driven by an external

FREQSEL B14 B14 I Frequency select. This terminal indicates the oscillator input frequency and is used to configure the

PERST# A40 A40 I PCI Express Reset Input. The PERST# signal is used to signal when the system power is stable. The

CLKREQ# B36 B36 O PCI Express REFCLK Request signal.

USB_SSTXP_DN1 A17 A17 O USB SuperSpeed transmitter differential pair (positive).

OVERCUR1# A36 A36 I

USB_SSTXP_DN2 A11 A11 O USB SuperSpeed transmitter differential pair (positive).

NO. TUSB7340

USB_SSRXN_DN2 A10 A10 I USB SuperSpeed receiver differential pair (negative).

USB_SSRXP_DN3 — B27 I USB SuperSpeed receiver differential pair (positive).

USB_SSRXN_DN3 — A29 I USB SuperSpeed receiver differential pair (negative).

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NO. TUSB7340

PCI Express REFCLK (single-ended) –0.5 VDD33 + 0.5 V

Miscellaneous 3.3 V IO –0.5 VDD33 + 0.5 V

Miscellaneous 3.3 V IO –0.5 VDD33 + 0.5 V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±1500 V

Charged-device model (CDM), per JEDEC specification JESD22-

C101(2) ±500

(1) A 1.05-V supply may be used as long as minimum supply conditions are met.

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RθJA Junction-to-ambient thermal resistance 25.6 °C/W

RθJC(top) Junction-to-case (top) thermal resistance 9.5 °C/W

RθJB Junction-to-board thermal resistance 15.2 °C/W

RθJC(bot) Junction-to-case (bottom) thermal resistance 0.4 °C/W

(1) Applies to external inputs and bidirectional buffers.

VIH High-level input voltage(1) VDD33 2 VDD33 V

VIInput voltage 0 VDD33 V

VOOutput voltage(2) 0 VDD33 V

ttInput transition time (trise and tfall) 0 25 ns

Vhys Input hysteresis(3) 0.13 VDD33 V

VOH High-level output voltage VDD33 IOH = -4 mA 2.4 V

VOL Low-level output voltage VDD33 IOL = 4 mA 0.4 V

IOZ High-impedance, output current(2) VDD33 VI= 0 to VDD33 ±20 µA

Frequency Tolerance Operational

Frequency Stability 1 year aging ±100 ppm

Rise / Fall Time 20% - 80% 6 ns

Reference Clock RJwith JTF (1 sigma)(1)(2) 0.8 ps

Reference Clock TJwith JTF (total p-p)(2)(3) 25 ps

Reference Clock Jitter

(absolute p-p)(4) 50 ps

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The host controller performs three basic serial-bus operations: single byte reads, single byte writes, and

multibyte reads. The single byte operations occur under software control. The multibyte read operations are

BCh, see Serial Bus Control and Status Register). Next, the EEPROM word address is sent by the host

first and expects a final acknowledgment before issuing the stop condition.

device address and the R/W command bit is equal to 0b (write). The slave device acknowledges if it recognizes

acknowledgment is expected. Then, the host controller issues a restart condition followed by the 7-bit slave

Bit 7 (PROT_SEL) in the serial-bus control and status register changes the serial-bus protocol. Each of the three

that are loaded through the EEPROM are provided in Table 4.

06h PCI D4h, General Control 0, Byte 0

07h PCI D5h, General Control 0, Byte 1

08h PCI D8h, General Control 1, Byte 0

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SERIAL EEPROM WORD ADDRESS BYTE DESCRIPTION

09h PCI DCh, General Control 2, Byte 0

0Ah PCI E0h, USB Control, Byte 0

0Bh PCI E1h, USB Control, Byte 1

0Ch PCI E2h, USB Control, Byte 2

0Dh PCI E3h, USB Control, Byte 3

0Eh PCI E4h, De-emphasis and Swing Control, Byte 0

0Fh PCI E5h, De-emphasis and Swing Control, Byte 1

18h PCI EEh, Custom PHY Transmit/Receive Control, Byte 2

19h PCI EFh, Custom PHY Transmit/Receive Control, Byte 3

1Ah PCI 61h, Frame Length Adjustment Register

1Bh End of List Indicator (80h)

EEPROM. All byte locations must be considered when programming the EEPROM.

(Figure 2) assumes the 1010b high-address nibble. The lower three address bits are terminal inputs to the chip,

and the sample application shows these terminal inputs tied to VSS.