V = 1.5 V (50 mV/div)
O2
Iout (2 A/div)
t - Time - 100 s/divm
Input Voltage
PGND
PGND
C4
SW1
VIN1
VBST1
EN1
VFB2
VFB1
GND VREG5
PGND1
6
VIN2
VBST2
EN2
SW2
PG1
5
1
3
PG2
9
10
11
PGND2
2
4
7
13
12
TPS542941
HTSSOP16
14
8
15
16
PGND
SGND SGND
C11
VO1
C21
R11
R21
L11 C31 C32 L12
C12
VO2
C22
R12
R22
(PowerPAD)
TPS542941
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SLVSBI3B –JULY 2012–REVISED OCTOBER 2013
2A/3A Dual Channel Synchronous Step-Down Switcher with Integrated FET
Check for Samples: TPS542941
1FEATURES APPLICATIONS
2• D-CAP2™ Control Mode • Point-of-Load Regulation in Low Power
Systems for Wide Range of Applications
– Fast Transient Response – Digital TV Power Supply
– No External Parts Required For Loop
Compensation – Networking Home Terminal
– Compatible with Ceramic Output – Digital Set Top Box (STB)
Capacitors – DVD Player/Recorder
• Wide Input Voltage Range : 4.5 V to 18 V – Gaming Consoles and Other
• Output Voltage Range : 0.76V to 7V DESCRIPTION
• Highly Efficient Integrated FETs Optimized for The TPS542941 is a dual, adaptive on-time D-
Low Duty Cycle Applications CAP2™ mode synchronous buck converter. The
– 150 mΩ(High Side) and 100 mΩ(Low Side) TPS542941 enables system designers to complete
• High Initial Reference Accuracy the suite of various end equipment’s power bus
regulators with a cost effective, low component count,
• 2A CH1 / 3A CH2 Continuous Load Current and low standby current solution. The main control
• Low-Side rDS(on) Loss-Less Current Sensing loops of the TPS542941 use the D-CAP2™ mode
• Fixed Soft Start : 1.0ms control which provides a very fast transient response
• Non-Sinking Pre-Biased Soft Start with no external compensation components. The
adaptive on-time control supports seamless transition
• Powergood between PWM mode at higher load conditions and
• 700 kHz Switching Frequency Eco-mode™ operation at light loads. Eco-mode™
• Cycle-by-Cycle Over-Current Limit Control allows the TPS542941 to maintain high efficiency
during lighter load conditions. The TPS542941 is able
• OCL/UVLO/TSD Protections to adapt to both low equivalent series resistance
• Hiccup Timer for Overload Protection (ESR) output capacitors such as POSCAP or SP-
• Adaptive Gate Drivers with Integrated Boost CAP, and ultra-low ESR, ceramic capacitors. The
PMOS Switch device provides convenient and efficient operation
with input voltages from 4.5V to 18V.
• OCP Constant Due To Thermally Compensated
rDS(on) with 4000ppm/℃℃ The TPS542941 is available in a 4.4mm × 5.0mm 16
pin TSSOP (PWP) package, and 4mm x 4mm 16-pin
• 16-Pin HTSSOP, 16-Pin VQFN VQFN (RSA) package specified for an ambient
• Auto-Skip Eco-mode™　　for High Efficiency at temperature range from –40°C to 85°C.
Light Load
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2D-CAP2, Eco-mode, PowerPAD are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Copyright © 2012–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TPS542941
SLVSBI3B –JULY 2012–REVISED OCTOBER 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION(1)
TAPACKAGE(2) (3) ORDERING PART NUMBER PINS OUTPUT SUPPLY
TPS542941PWPR Tape-and-Reel
PWP 16
TPS542941PWP Tube
–40℃to 85℃TPS542941RSAR
RSA 16 Tape-and-Reel
TPS542941RSAT
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(3) All packaging options have Cu NIPDAU lead/ball finish.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)(1) (2)
VALUE UNIT
VIN1, VIN2, EN1, EN2 –0.3 to 20
VBST1, VBST2 –0.3 to 26
VBST1, VBST2 (10ns transient) –0.3 to 28
Input voltage range VBST1–SW1 , VBST2–SW2 –0.3 to 6.5 V
VFB1, VFB2 –0.3 to 6.5
SW1, SW2 –2 to 20
SW1, SW2 (10ns transient) –3 to 22
VREG5, PG1, PG2 –0.3 to 6.5
Output voltage range V
PGND1, PGND2 –0.3 to 0.3
Human Body Model (HBM) 2 kV
Electrostatic discharge Charged Device Model (CDM) 500 V
TAOperating ambient temperature range –40 to 85 °C
TSTG Storage temperature range –55 to 150 °C
TJJunction temperature range –40 to 150 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" are not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to IC GND terminal.
THERMAL INFORMATION TPS542941
THERMAL METRIC(1) UNITS
PWP (16) PINS RSA (16) PINS
θJA Junction-to-ambient thermal resistance 47.5 34.9
θJCtop Junction-to-case (top) thermal resistance 27.1 40.0
θJB Junction-to-board thermal resistance 20.8 11.8 °C/W
ψJT Junction-to-top characterization parameter 1.0 0.7
ψJB Junction-to-board characterization parameter 20.6 11.8
θJCbot Junction-to-case (bottom) thermal resistance 2.7 3.3
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted) VALUES UNIT
MIN MAX
Supply input voltage range VIN1, VIN2 4.5 18 V
VBST1, VBST2 –0.1 24
VBST1, VBST2 (10ns transient) –0.1 27
VBST1–SW1, VBST2–SW2 –0.1 5.7
Input voltage range VFB1, VFB2 –0.1 5.7 V
EN1, EN2 –0.1 18
SW1, SW2 –1.0 18
SW1, SW2 (10ns transient) –3 21
VREG5, PG1 , PG2 –0.1 5.7
Output voltage range V
PGND1, PGND2 –0.1 0.1
TAOperating free-air temperature –40 85 °C
TJOperating Junction Temperature –40 150 °C
ELECTRICAL CHARACTERISTICS(1)
over recommended free-air temperature range, VIN = 12 V (unless otherwise noted)
PARAMETER CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT
TA= 25°C, EN1 = EN2 = 5 V,
IIN VIN supply current 1300 2000 µA
VFB1 = VFB2 = 0.8 V
IVINSDN VIN shutdown current TA= 25°C, 80 150 µA
FEEDBACK VOLTAGE
VVFBTHLx VFBx threshold voltage TA= 25°C, CH1 = 3.3 V, CH2 = 1.5 V 758 765 773 mV
TCVFBx Temperature coefficient On the basis of 25°C(2) –115 115 ppm/℃
IVFBx VFB Input Current VFBx = 0.8 V, TA= 25°C –0.4 0.2 0.4 µA
VREG5 OUTPUT
TA= 25°C, 6 V < VIN1 < 18 V,
VVREG5 VREG5 output voltage 5.5 V
IVREG = 5 mA
VIN1 = 6 V, VREG5 = 4.0 V,
IVREG5 Output current 75 mA
TA= 25°C(2)
MOSFETs
rDS(on)H High side switch resistance TA= 25℃, VBSTx-SWx = 5.5 V (2) 150 mΩ
rDS(on)L Low side switch resistance TA= 25℃(2) 100 mΩ
ON-TIME TIMER CONTROL
TON1 SW1 On Time SW1 = 12 V, VO1 = 1.2 V 165 ns
TON2 SW2 On Time SW2 = 12 V, VO2 = 1.2 V 165 ns
TOFF1 SW1 Min off time TA= 25℃, VFB1 = 0.7 V(2) 220 ns
TOFF2 SW2 Min off time TA= 25℃, VFB2 = 0.7 V(2) 220 ns
SOFT START
TSS Soft-start time Internal soft-start time 1.0 ms
(1) x means either 1 or 2, that is, VFBx means VFB1 or VFB2.
(2) Specified by design. Not production tested.
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ELECTRICAL CHARACTERISTICS(1) (continued)
over recommended free-air temperature range, VIN = 12 V (unless otherwise noted)
PARAMETER CONDITIONS MIN TYP MAX UNIT
POWER GOOD
PG from lower VOx (going high) 84%
VPGTH PGx threshold PG from higher VOx (going low) 116%
RPG PGx pull-down resistance VPGx = 0.5 V 50 75 110 Ω
Delay for PGx going high 1.5 ms
TPGDLY PGx delay time Delay for PGx going low 2 µs
TPGCOMPSS PGx comparator start-up delay PGx comparator wake-up delay 1.5 ms
UVLO
VREG5 rising 3.83
VUVREG5 VREG5 UVLO threshold V
Hysteresis 0.6
LOGIC THRESHOLDs
VENH ENx H-level threshold voltage 2.0 V
VENL ENx L-level threshold voltage 0.4 V
RENx_IN ENx input resistance ENx = 12 V 225 450 900 kΩ
CURRENT LIMITs
IOCL1 CH1 Current limit LOUT1 = 2.2 µH(3) 2.7 3.9 4.5 A
IOCL2 CH2 Current limit LOUT2 = 1.5 µH(3) 3.5 4.7 5.4 A
OUTPUT UNDERVOLTAGE AND OVERVOLTAGE PROTECTION (UVP, OVP)
VUVP Output UVP trip threshold measured on VFBx 63% 68% 73%
TUVPDEL Output UVP delay time 1.5 ms
TUVPEN Output UVP enable delay 1.5 ms
THERMAL SHUTDOWN
Shutdown temperature(3) 155
TSD Thermal shutdown threshold °C
Hysteresis(3) 25
(3) Specified by design. Not production tested.
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SW1
VIN1
VBST 1
EN1
VFB2
VFB1
GND VREG5
PGND1
6
VIN2
VBST2
EN2
SW 2
PG1
5
1
3
PG2
9
10
11
PGND 2
2
4
7
13
12
14
8
15
16
TPS542941
HTSSOP16
(PowerPAD)
PowerPAD
VFB1
VFB2
VIN1
SW2
VBST2
VBST1
EN1
14
75 6
2
3
4
1
PGND2
PGND1
SW1
VIN2
13
12
11
9
8
PG1
10 GND
PG2
EN2
16 15
VREG5
TPS542941
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SLVSBI3B –JULY 2012–REVISED OCTOBER 2013
DEVICE INFORMATION
HTSSOP PACKAGE RSA PACKAGE
(TOP VIEW) (TOP VIEW)
PIN FUNCTIONS(1)
PIN
NUMBER I/O DESCRIPTION
NAME PWP RSA
VIN1 1 3 Power inputs and connects to both high side NFET drains.
ISupply Input for 5.5V linear regulator.
VIN2 16 2
VBST1 2 4 Supply input for high-side NFET gate drive circuit. Connect 0.1µF ceramic capacitor
I between VBSTx and SWx pins. An internal diode is connected between VREG5 and
VBST2 15 1 VBSTx
SW1 3 5 Switch node connections for both the high-side NFETs and low–side NFETs. Input of
I/O current comparator.
SW2 14 16
PGND1 4 6 I/O Ground returns for low-side MOSFETs. Input of current comparator.
PGND2 13 15
EN1 5 7 I Enable. Pull High to enable according converter.
EN2 12 14
PG1 6 — Open drain power good outputs. Low indicates the corresponding output voltage is out of
Oregulation.
PG2 11 —
VFB1 7 9 I D-CAP2 feedback inputs. Connect to output voltage with resistor divider.
VFB2 10 12
GND 8 10 I/O Signal GND. Connect sensitive VFBx returns to GND at a single point.
Output of 5.5V linear regulator. Bypass to GND with a high-quality ceramic capacitor of at
VREG5 9 11 O least 1.0 µF. VREG5 is active when VIN1 is high.
Back Back Thermal pad of the package. Must be soldered to achieve appropriate dissipation. Must
PowerPAD™ I/O
side side be connected to GND.
(1) x means either 1 or 2, that is, VFBx means VFB1 or VFB2.
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SW1
VBST1
EN1
VFB2
VFB1
GND VREG5
PGND1
VO1
VBST2
EN2
SW2
VO2
VIN1
VIN2
5VREG
EN
Logic EN Logic
Ref1
Ref 2 SS2
SS1
UV2
UV1
UV2 UVLO
UVLO
Fixed
SoftStart
REF
TSD
Ref1
Ref2
- 32
SS1
SS2
PGND1
PGND2
- 16%
+16%
PG1
- 16%
+16%
PG2
CH1 Min-off timer
CH2 Min-off timer
VIN1
VIN1
VIN2
PGND2
PGND2
SW2
Ref_OCL
OCP2
ZC2
SW2
PGND1
SW1
Ref_OCL
OCP1 ZC1
SW1
Control logic
1.0 µF
Control logic
0.1 µF
PG
Comp
Err
Comp
Protection
Logic
0.1 µF
Err
Comp
PG
Comp
UV1
-32
TPS542941
SLVSBI3B –JULY 2012–REVISED OCTOBER 2013
www.ti.com
FUNCTIONAL BLOCK DIAGRAM
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( )
INx Ox Ox
Ox(LL)
SW INx
V V V
1
I = 2 L1x V
- ´
´
´ ´ f
TPS542941
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SLVSBI3B –JULY 2012–REVISED OCTOBER 2013
OVERVIEW
The TPS542941 is a 2A/3A dual synchronous step-down (buck) converter with two integrated N-channel
MOSFETs for each channel. It operates using D-CAP2™ control mode. The fast transient response of D-CAP2™
control reduces the required output capacitance to meet a specific level of performance. Proprietary internal
circuitry allows the use of low ESR output capacitors including ceramic and special polymer types.
DETAILED DESCRIPTION
PWM Operation
The main control loop of the TPS542941 is an adaptive on-time pulse width modulation (PWM) controller that
supports a proprietary D-CAP2™ control mode. D-CAP2™ control combines constant on-time control with an
internal compensation circuit for pseudo-fixed frequency and low external component count configuration with
both low ESR and ceramic output capacitors. It is stable even with virtually no ripple at the output.
At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off when the internal
timer expires. This timer is set by the converter’s input voltage, VINx, and the output voltage, VOx, to maintain a
pseudo-fixed frequency over the input voltage range hence it is called adaptive on-time control. The timer is reset
and the high-side MOSFET is turned on again when the feedback voltage falls below the nominal output voltage.
An internal ramp is added to the reference voltage to simulate output voltage ripple, eliminating the need for ESR
induced output ripple from D-CAP™ control.
PWM Frequency and Adaptive On-Time Control
TPS542941 uses an adaptive on-time control scheme and does not have a dedicated on board oscillator. The
TPS542941 runs with a pseudo-fixed frequency of 700 kHz by using the input voltage and output voltage to set
the on-time timer. The on-time is inversely proportional to the input voltage and proportional to the output voltage,
therefore, when the duty ratio is VOx/VINx, the frequency is constant.
Auto-Skip Eco-mode™ Control
The TPS542941 is designed with Auto-Skip Eco-mode™ to increase light load efficiency. As the output current
decreases from heavy load condition, the inductor current also reduces and eventually comes to the point where
its ripple valley touches the zero level, which is the boundary between continuous conduction and discontinuous
conduction modes. The rectifying MOSFET is turned off when zero inductor current is detected. As the load
current further decreases the converter runs into discontinuous conduction mode. The on-time is kept almost half
as it was in the continuous conduction mode because it takes longer to discharge the output capacitor with
smaller load current to the nominal output voltage. The transition point to the light load operation IOx(LL) current
can be estimated with Equation 1with 700-kHz used as fSW.
(1)
Soft Start and Pre-Biased Soft Start
The TPS542941 has an internal, 1.0ms, soft-start for each channel. When the ENx pin becomes high, an internal
DAC begins ramping up the reference voltage to the PWM comparator. Smooth control of the output voltage is
maintained during start up.
The TPS542941 contains a unique circuit to prevent current from being pulled from the output during startup if
the output is pre-biased. When the soft-start commands a voltage higher than the pre-bias level (internal soft
start becomes greater than internal feedback voltage, VFBx), the controller slowly activates synchronous
rectification by starting the first low side FET gate driver pulses with a narrow on-time. It then increments that on-
time on a cycle-by-cycle basis until it coincides with the time dictated by (1-D), where D is the duty cycle of the
converter. This scheme prevents the initial sinking of the pre-biased output, and ensures that the output voltage
(VOx) starts and ramps up smoothly into regulation from pre-biased startup to normal mode operation.
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POWERGOOD
The TPS542941 has power-good outputs that are measured on VFBx. The power-good function is activated after
the soft-start has finished. If the output voltage is within 16% of the target voltage, the internal comparator
detects the power good state and the power good signal becomes high after 1.5ms delay. During start-up, this
internal delay starts after 1.5ms of the UVP Enable delay time to avoid a glitch of the power-good signal. If the
feedback voltage goes outside of ±16% of the target value, the power-good signal becomes low after 2µs.
Current Sensing and Over-Current Protection
The output over-current protection (OCP) is implemented using a cycle-by-cycle valley detection control circuit.
The switch current is monitored by measuring the low-side FET switch voltage between the SWx and PGNDx
pins. This voltage is proportional to the switch current and the on-resistance of the FET. To improve the
measurement accuracy, the voltage sensing is temperature compensated.
During the on-time of the high-side FET switch, the switch current increases at a linear rate determined by VINx,
VOx, the on-time and the output inductor value. During the on-time of the low-side FET switch, this current
decreases linearly. The average value of the switch current is the load current IOUTx. If the sensed voltage on the
low-side FET is above the voltage proportional to the current limit, the converter keeps the low-side switch on
until the measured voltage falls below the voltage corresponding to the current limit and a new switching cycle
begins. In subsequent switching cycles, the on-time is set to the value determined for CCM and the current is
monitored in the same manner.
Important considerations for this type of over-current protection: The load current is one half of the peak-to-peak
inductor current higher than the over-current threshold. Also when the current is being limited, the output voltage
tends to fall as the demanded load current may be higher than the current available from the converter. When
the over current condition is removed, the output voltage returns to the regulated value. This protection is non-
latching.
Undervoltage Protection and Hiccup Mode
Hiccup mode of operation protects the power supply from being damaged during an over-current fault condition.
If the OCL comparator circuit detects an over-current event the output voltage falls. When the feedback voltage
falls below 68% of the reference voltage, the UVP comparator output goes high and an internal UVP delay
counter begins counting. After counting UVP delay time, the TPS542941 shuts off the power supply for a given
time (7x UVP Enable Delay Time) and then tries to re-start the power supply. If the over-load condition has been
removed, the power supply starts and operates normally; otherwise, the TPS542941 detects another over-current
event and shuts off the power supply again, repeating the previous cycle. Excess heat due to overload lasts for
only a short duration in the hiccup cycle, therefore the junction temperature of the power device is much lower.
UVLO Protection
Under-voltage lock out protection (UVLO) monitors the voltage of the VREG5 pin. When the VREG5 voltage is lower
than the UVLO threshold, the TPS542941 shuts down. As soon as the voltage increases above the UVLO
threshold, the converter starts again.
Thermal Shutdown
TPS542941 monitors its temperature. If the temperature exceeds the threshold value (typically 155°C), the
device shuts down. When the temperature falls below the threshold, the IC starts again.
When VIN1 starts up and VREG5 output voltage is below its nominal value, the thermal shutdown threshold is
lower than 155°C. As long as VIN1 rises, TJmust be kept below 110°C.
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1.45
1.46
1.47
1.48
1.49
1.50
1.51
1.52
1.53
1.54
1.55
0.0 0.5 1.0 1.5 2.0 2.5 3.0
Output Current (A)
Output Voltage (V)
VIN = 5 V
VIN = 12 V
VIN = 18 V
VOUT = 1.5 V
G005
3.20
3.22
3.24
3.26
3.28
3.30
3.32
3.34
3.36
3.38
3.40
0 2 4 6 8 10 12 14 16 18 20
Input Voltage (V)
Output Voltage (V)
IOUT = 10 mA
IOUT = 1 A
G006
0
5
10
15
20
25
30
35
40
45
50
0 5 10 15 20
EN Input Voltage (V)
EN Input Current (µA)
EN1
EN2
G003
3.20
3.22
3.24
3.26
3.28
3.30
3.32
3.34
3.36
3.38
3.40
0.0 0.2 0.5 0.8 1.0 1.2 1.5 1.8 2.0
Output Current (A)
Output Voltage (V)
VIN = 6 V
VIN = 12 V
VIN = 18 V
VOUT = 3.3 V
G004
0
200
400
600
800
1000
1200
1400
1600
1800
−50 0 50 100 150
Junction Temperature (°C)
Icc − Supply Current (µA)
VIN1, VIN2 = 12 V
EN1, EN2 = ON
G001
0
20
40
60
80
100
120
140
160
−50 0 50 100 150
Junction Temperature (°C)
Supply Current−Shutdown Current (µA)
VIN1, VIN2 = 12 V
EN1. EN2 = OFF
G002
TPS542941
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SLVSBI3B –JULY 2012–REVISED OCTOBER 2013
TYPICAL CHARACTERISTICS
One output is enabled unless otherwise noted. VIN = VIN1 or VIN2. VIN = 12 V, TA= 25°C (unless otherwise noted).
Figure 1. Input Current vs Junction Temperature Figure 2. Input Shutdown Current vs Junction Temperature
Figure 3. EN Current vs EN Voltage (VEN = 12V) Figure 4. VO1 = 3.3V Output Voltage vs Output Current
Figure 5. VO2 = 1.5V Output Voltage vs Output Current Figure 6. VO1 = 3.3V Output Voltage vs Input Voltage
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Vout2(0.5V/div)
400 s/divm
PG2(5V/div)
EN2(10V/div)
0
10
20
30
40
50
60
70
80
90
100
0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00
Output Current (A)
Efficiency (%)
VIN = 6 V
VIN = 12 V
VIN = 18 V
G012
Vout(50mV/div)
100 s/divm
Iout(2A/div)
Vout(1V/div)
PG1(5V/div)
400 s/divm
EN1(10V/div)
Iout(1A/div)
100 s/divm
Vout(50mV/div)
1.45
1.46
1.47
1.48
1.49
1.50
1.51
1.52
1.53
1.54
1.55
0 2 4 6 8 10 12 14 16 18 20
Input Voltage (V)
Output Voltage (V)
IOUT = 10 mA
IOUT = 1 A
G007
TPS542941
SLVSBI3B –JULY 2012–REVISED OCTOBER 2013
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TYPICAL CHARACTERISTICS (continued)
One output is enabled unless otherwise noted. VIN = VIN1 or VIN2. VIN = 12 V, TA= 25°C (unless otherwise noted).
Figure 7. VO2 = 1.5V Output Voltage vs Input Voltage Figure 8. VO1 = 3.3V, 0 A to 4 A Load Transient Response
Figure 9. VO2 = 1.5V, 0 A to 2 A Load Transient Response Figure 10. VO1 = 3.3V, PG1
Figure 11. VO2 = 1.5V, PG2 Figure 12. VO1 = 3.3V, Efficiency vs Output Current
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400
450
500
550
600
650
700
750
800
0 5 10 15 20
Input Voltage (V)
Switching Frequency (kHz)
VOUT2 = 1.5 VIOUT2 = 1 A
G017
0
100
200
300
400
500
600
700
800
900
0.01 0.1 1 10
Output Current (A)
Switching Frequency (kHz)
VOUT1 = 3.3 V
VIN1, VIN2 = 12 V
G018
0
10
20
30
40
50
60
70
80
90
100
0.001 0.01 0.1 1 10
Output Current (A)
Efficiency (%)
VIN = 5 V
VIN = 12 V
VIN = 18 V
G015
400
450
500
550
600
650
700
750
800
0 5 10 15 20
Input Voltage (V)
Switching Frequency (kHz)
VOUT1 = 3.3 VIOUT1 = 1 A
G016
0
10
20
30
40
50
60
70
80
90
100
0.001 0.01 0.1 1 10
Output Current (A)
Efficiency (%)
VIN = 6 V
VIN = 12 V
VIN = 18 V
G013
0
10
20
30
40
50
60
70
80
90
100
0.0 0.5 1.0 1.5 2.0 2.5 3.0
Output Current (A)
Efficiency (%)
VIN = 5 V
VIN = 12 V
VIN = 18 V
G014
TPS542941
www.ti.com
SLVSBI3B –JULY 2012–REVISED OCTOBER 2013
TYPICAL CHARACTERISTICS (continued)
One output is enabled unless otherwise noted. VIN = VIN1 or VIN2. VIN = 12 V, TA= 25°C (unless otherwise noted).
Figure 13. VO1 = 1.5V, Efficiency vs Output Current Figure 14. VO1 = 3.3V, Efficiency vs Output Current
Figure 15. VO2 = 1.5V, Efficiency vs Output Current Figure 16. VO1 = 3.3V, SW-frequency vs
Input Voltage (PWP)
Figure 17. VO2 = 1.5V, SW-frequency vs Figure 18. VO1 = 3.3V, SW-frequency vs
Input Voltage (PWP) Output Current (PWP)
Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Links: TPS542941
VIN2(50mV/div)
SW2(5V/div)
V 2 = 1.5 V
O
400 nsec/div)
I 2 = 3 A
O
VIN1(50mV/div)
SW1(5V/div)
V 1 = 3.3 V
O
400 nsec/div)
I 1 = 2 A
O
V (10mV/div)
O2
SW2(5V/div)
V = 1.5 V
O2
400 nsec/div)
I 2 = 3A
O
V (10mV/div)
O1
SW1(5V/div)
V = 3.3 V
O1
400 nsec/div)
I 1 = 2A
O
0
100
200
300
400
500
600
700
800
900
0.01 0.1 1 10
Output Current (A)
Switching Frequency (kHz)
VOUT2 = 1.5 V
VIN1, VIN2 = 12 V
G019
TPS542941
SLVSBI3B –JULY 2012–REVISED OCTOBER 2013
www.ti.com
TYPICAL CHARACTERISTICS (continued)
One output is enabled unless otherwise noted. VIN = VIN1 or VIN2. VIN = 12 V, TA= 25°C (unless otherwise noted).
Figure 19. VO2 = 1.5V, SW-frequency vs Figure 20. VO1 = 3.3V, VO1 Ripple Voltage (IO1= 4 A)
Output Current (PWP)
Figure 21. VO2 = 1.5V, Ripple Voltage (IO2= 2 A) Figure 22. VIN1 Input Voltage Ripple (IO1= 4 A)
Figure 23. VIN2 Input Voltage Ripple (IO2= 2 A)
12 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: TPS542941
Ox
R1x
V = 0.765 V 1+
R2x
æ ö
´ç ÷
è ø
VINx
12V ± 10%
PGND
1uF
PGND
C4
SW1
VIN1
VBST1
EN1
VFB2
VFB1
GND VREG5
PGND1
6
VIN2
VBST2
EN2
SW2
PG1
5
1
3
PG2
9
10
11
PGND2
2
4
7
13
12
TPS542941
HTSSOP16
14
8
15
16
PGND
SGND SGND
C11
10 Fm
VO1
3.3 V
C21
22 F
x2
m
R11
73.2 kW
R21
22.1 kW
L11
H2.2 m C31
0.1 Fm
C32
0.1 Fm
L12
1.5 Hm
C12
10 FmVO2
1.5 V
C22
22 F
x2
m
R12
21.5 kW
R22
22.1 kW
TPS542941
www.ti.com
SLVSBI3B –JULY 2012–REVISED OCTOBER 2013
DESIGN GUIDE
Step By Step Design Procedure
To begin the design process, you must know a few application parameters:
• Input voltage range
• Output voltage
• Output current
In all formulas x is used to indicate that they are valid for both converters. For the calculations the estimated
switching frequency of 700 kHz is used.
Figure 24. Schematic Diagram for the Design Example
Output Voltage Resistors Selection
The output voltage is set with a resistor divider from the output node to the VFBx pin. It is recommended to use
1% tolerance or better divider resistors. Start by using Equation 2 to calculate VOx.
To improve the efficiency at very light loads consider using larger value resistors, but too high resistance values
will be more susceptible to noise and voltage errors due to the VFBx input current will be more noticeable.
(2)
Output Filter Selection
The output filter used with the TPS542941 is an LC circuit. This LC filter has double pole at:
(3)
Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Links: TPS542941
( )
Ox INx Ox
COx(R MS )
INx Ox SW
V V V
I = 12 V L
´ -
´ ´ ´ f
2 2
LOx(RMS) Ox L
1
I = I + ΔI
12
L
Lpeakx Ox
ΔI
I = I + 2
INx(MAX) Ox
Ox
L1x
INx(MAX) SW
V V
V
ΔI = V L1x
-
´
´f
TPS542941
SLVSBI3B –JULY 2012–REVISED OCTOBER 2013
www.ti.com
At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal
gain of the TPS542941. The low frequency phase is 180 degrees. At the output filter pole frequency, the gain
rolls off at a –40 dB per decade rate and the phase drops rapidly. D-CAP2™ introduces a high frequency zero
that reduces the gain roll off to –20 dB per decade and increases the phase to 90 degrees one decade above the
zero frequency. The inductor and capacitor selected for the output filter must be selected so that the double pole
of Equation 3 is located below the high frequency zero but close enough that the phase boost provided by the
high frequency zero provides adequate phase margin for a stable circuit. To meet this requirement use the
values recommended in Table 1.
Table 1. Recommended Component Values
OUTPUT VOLTAGE (V) R1x (kΩ) R2x (kΩ) Cffx (pF)(1) L1x (µH) C2x (µF)
1 6.81 22.1 1.5 - 2.2 20 - 68
1.05 8.25 22.1 1.5 - 2.2 20 - 68
1.2 12.7 22.1 1.5 - 2.2 20 - 68
1.5 21.5 22.1 1.5 - 2.2 20 - 68
1.8 30.1 22.1 5 - 22 2.2 - 3.3 20 - 68
2.5 49.9 22.1 5 - 22 2.2 - 3.3 20 - 68
3.3 73.2 22.1 5 - 22 2.2 - 3.3 20 - 68
5 124 22.1 5 - 22 4.7 20 - 68
6.5 165 22.1 5 - 22 4.7 20 - 68
(1) Optional
For higher output voltages at or above 1.8 V, additional phase boost can be achieved by adding a feed forward
capacitor (Cff) in parallel with R1.
The inductor peak-to-peak ripple current, peak current and RMS current are calculated using Equation 4,
Equation 5 and Equation 6. The inductor saturation current rating must be greater than the calculated peak
current and the RMS or heating current rating must be greater than the calculated RMS current.
For the calculations, use 700 kHz as the switching frequency, fSW. Make sure the chosen inductor is rated for the
peak current of Equation 5 and the RMS current of Equation 6.
(4)
(5)
(6)
For the above design example, the calculated peak current is 2.78 A and the calculated RMS current is 2.05 A
for VO1. The inductor used is a TDK CLF7045-2R2N with a rated current of 5.5 A based on the inductance
change and of 4.3 A based on the temperature rise.
The capacitor value and ESR determines the amount of output voltage ripple. The TPS542941 is intended for
use with ceramic or other low ESR capacitors. The recommended value range is from 20µF to 68µF. Use
Equation 7 to determine the required RMS current rating for the output capacitor(s).
(7)
For this design two TDK C3216X5R0J226M 22µF output capacitors are used. The typical ESR is 2 mΩeach.
The calculated RMS current is 0.488 A and each output capacitor is rated for 4A.
14 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: TPS542941
TPS542941
www.ti.com
SLVSBI3B –JULY 2012–REVISED OCTOBER 2013
Input Capacitor Selection
The TPS542941 requires an input decoupling capacitor and a bulk capacitor is needed depending on the
application. A ceramic capacitor of or above 10µF is recommended for the decoupling capacitor. Additionally, 0.1
µF ceramic capacitors from pin 1 and Pin 16 to ground are recommended to improve the stability and reduce the
SWx node overshoots. The capacitors voltage rating needs to be greater than the maximum input voltage.
Bootstrap Capacitor Selection
A 0.1 µF ceramic capacitors must be connected between the VBSTx and SWx pins for proper operation. It is
recommended to use ceramic capacitors with a dielectric of X5R or better.
VREG5 Capacitor Selection
A 1 µF ceramic capacitor must be connected between the VREG5 and GND pins for proper operation. It is
recommended to use a ceramic capacitor with a dielectric of X5R or better.
Thermal Information
This 16-pin PWP package incorporates an exposed thermal pad. The thermal pad must be soldered directly to
the printed circuit board (PCB). After soldering, the PCB is used as a heatsink. In addition, through the use of
thermal vias, the thermal pad can be attached directly to the appropriate copper plane shown in the electrical
schematic for the device, or alternatively, can be attached to a special heatsink structure designed into the PCB.
This design optimizes the heat transfer from the integrated circuit (IC).
For additional information on the exposed thermal pad and how to use the advantage of its heat dissipating
abilities, refer to the Technical Brief, PowerPAD™ Thermally Enhanced Package, Texas Instruments Literature
No. SLMA002 and Application Brief, PowerPAD™ Made Easy, Texas Instruments Literature No. SLMA004.
The exposed thermal pad dimensions for this package are shown in the following illustration.
Figure 25. Thermal Pad Dimensions
Layout Considerations
1. Keep the input current loop as small as possible. And avoid the input switching current through the thermal
pad.
2. Keep the SW node as physically small and short as possible to minimize parasitic capacitance and
inductance and to minimize radiated emissions.
3. Keep analog and non-switching components away from switching components.
4. Make a single point connection from the signal ground to power ground.
5. Do not allow switching currents to flow under the device.
6. Keep the pattern lines for VINx and PGNDx broad.
Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Links: TPS542941
SW1
VIN1
VBST1
EN1
VFB1
GND VREG 5
PGND1
6
VIN2
VBST2
EN2
SW2
PG1
5
1
3
PG2
9
10
11
PGND2
2
4
7
13
12
14
8
15
16
VFB2
VIN2
BIAS
CAP
VIN HIGH
FREQUENCY
BYPASS
CAPACITOR
～0.1µF
VIN INPUT
BYPASS
CAPACITOR
10µF x2
OUTPUT
INDUCTOR
OUTPUT
FILTER
CAPACITOR
POWER GND
TO ENABLE
CONTROL
Keep
distance more
than 1inch
Recommend to keep
distance more than 3-4mm.
(to avoid noise scattering,
especially GND plane.)
To feedback
resisters
VO2
Feedback
resisters
GND
PLANE
2,3 or bottom
layer
Symmetrical Layout
for CH1 and CH2
Switching noise
flows through IC
and CIN . It avoids
the thermal Pad.
Via to GND Plane
- Blue parts can be placed on the bottom side
- Connect the SWx pins through another layer with the inductor
(yellow line)
TPS542941
SLVSBI3B –JULY 2012–REVISED OCTOBER 2013
www.ti.com
7. Exposed pad of device must be soldered to PGND.
8. VREG5 capacitor should be placed near the device, and connected to GND.
9. Output capacitors should be connected with a broad pattern to the PGND.
10. Voltage feedback loops should be as short as possible, and preferably with ground shields.
11. Kelvin connections should be brought from the output to the feedback pin of the device.
12. Providing sufficient vias is preferable for VIN, SW and PGND connections.
13. PCB pattern for VIN, SW, and PGND should be as broad as possible.
14. VIN Capacitor should be placed as near as possible to the device.
Figure 26. TPS542941 Layout
16 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: TPS542941
EXPOSED THERMAL
PAD AREA
BOOST
CAPACITOR
VOUT2
VIA to Internal or
Bottom Layer Ground Plane
OUTPUT2
INDUCTOR
OUTPUT2
FILTER
CAPACITORS
TO POWER
GOOD PULL
UP 2
ANALOG
GROUND
TRACE
VIN INPUT
BYPASS
CAPACITORS
VIN
FEEDBACK
RESISTORS
Etch on Bottom Layer,
Internal Layer or
Under Component
BIAS
CAP
VIN HIGH
FREQUENCY
BYPASS
CAPACITOR
VBST1
SW1 SW2
VIN1
VIN2
VFB1
VREG5
GND
PG2
EN2
PGND2
PGND1
16
7
56
2
3
4
1
15
12
11
9
8
10
14 13
VFB2
VBST2
E 1N
PG1
TO ENABLE
CONTROL
BOOST
CAPACITOR
OUTPUT1
INDUCTOR
OUTPUT1
FILTER
CAPACITORS
VIN INPUT
BYPASS
CAPACITORS
FEEDBACK
RESISTORS
POWER
GROUND
VIN HIGH
FREQUENCY
BYPASS
CAPACITOR
KEEP
VIAS > 3-4 mm
FROM OUTPUT
CAPACITORS
KEEP OUTPUT
VIAS > 25 mm
FROM INPUT VIAS
KEEP
VIAS > 3-4 mm
FROM INPUT
CAPACITORS
NOTE: IT IS POSSIBLE TO PLACE
SOME COMPONENTS SUCH AS
BOOST CAPACITOR AND FEEDBACK
RESISTORS ON BOTTOM LAYER
VOUT1
TO ENABLE
CONTROL
POWER
GROUND
KEEP
VIAS > 3-4 mm
FROM OUTPUT
CAPACITORS
KEEP OUTPUT
VIAS > 25 mm
FROM INPUT VIAS
KEEP
VIAS > 3-4 mm
FROM INPUT
CAPACITORS
Internal or Bottom
Layer Ground Plane
VIA to internal or
Bottom Layer Etch
Etch or Copper Fill
on Top Layer
INTERNAL OR
BOTTOM LAYER
GROUND PLANE
TO POWER
GOOD PULL
UP 1
TPS542941
www.ti.com
SLVSBI3B –JULY 2012–REVISED OCTOBER 2013
Figure 27. RSA Package Layout
Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Links: TPS542941
TPS542941
SLVSBI3B –JULY 2012–REVISED OCTOBER 2013
www.ti.com
REVISION HISTORY
Changes from Original (July 2012) to Revision A Page
• Changed Feature From: 16-Pin HTSSOP To: 16-Pin HTSSOP, 16-Pin VQFN ................................................................... 1
• Added 16-pin VQFN (RSA) package to the Description text ................................................................................................ 1
• Added RSA -16 pin to the Ordering Information table .......................................................................................................... 2
• Added the RSA (16-Pins) to the Thermal Information table ................................................................................................. 2
• Added the RSA 16 - Package to the Device Information section ......................................................................................... 5
• Added Figure 27 ................................................................................................................................................................. 17
Changes from Revision A (April 2013) to Revision B Page
• Deleted VO1 and VO2 from the RECOMMENDED OPERATING CONDITIONS table ....................................................... 3
• Changed the GND pin description From: Connect sensitive SSx and VFBx returns to GND at a single point. To:
Connect sensitive VFBx returns to GND at a single point. ................................................................................................... 5
18 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: TPS542941
PACKAGE OPTION ADDENDUM
www.ti.com 25-Sep-2013
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
TPS542941PWP ACTIVE HTSSOP PWP 16 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 S542941
TPS542941PWPR ACTIVE HTSSOP PWP 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 S542941
TPS542941RSAR ACTIVE QFN RSA 16 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 TPS
542941
TPS542941RSAT ACTIVE QFN RSA 16 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 TPS
542941
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
PACKAGE OPTION ADDENDUM
www.ti.com 25-Sep-2013
Addendum-Page 2
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS542941PWPR HTSSOP PWP 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
TPS542941RSAR QFN RSA 16 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
TPS542941RSAT QFN RSA 16 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 13-Feb-2016
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS542941PWPR HTSSOP PWP 16 2000 367.0 367.0 38.0
TPS542941RSAR QFN RSA 16 3000 367.0 367.0 35.0
TPS542941RSAT QFN RSA 16 250 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 13-Feb-2016
Pack Materials-Page 2
www.ti.com
PACKAGE OUTLINE
C
14X 0.65
2X
4.55
16X 0.30
0.19
6.6
6.2 TYP
SEATING
PLANE
0.15
0.05
0.25
GAGE PLANE
0 -8
1.2 MAX
2X 0.95 MAX
NOTE 5
2X 0.23 MAX
NOTE 5
2.30
1.54
2.46
1.86
B4.5
4.3
A
5.1
4.9
NOTE 3
0.75
0.50
(0.15) TYP
4X (0.3)
PowerPAD TSSOP - 1.2 mm max heightPWP0016K
SMALL OUTLINE PACKAGE
4224484/A 08/2018
1
89
16
0.1 C A B
PIN 1 INDEX
AREA
SEE DETAIL A
0.1 C
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
5. Features may differ or may not be present.
TM
PowerPAD is a trademark of Texas Instruments.
A 20
DETAIL A
TYPICAL
SCALE 2.500
THERMAL
PAD
1
8 9
16
17
www.ti.com
EXAMPLE BOARD LAYOUT
0.05 MAX
ALL AROUND 0.05 MIN
ALL AROUND
16X (1.5)
16X (0.45)
14X (0.65)
(5.8)
(R0.05) TYP
(3.4)
NOTE 9
(5)
NOTE 9
(1.1) TYP
(0.6)
(1.2) TYP
( 0.2) TYP
VIA
(2.46)
(2.3)
PowerPAD TSSOP - 1.2 mm max heightPWP0016K
SMALL OUTLINE PACKAGE
4224484/A 08/2018
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
10. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged
or tented.
TM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SYMM
SYMM
1
89
16
METAL COVERED
BY SOLDER MASK
SOLDER MASK
DEFINED PAD SEE DETAILS
17
15.000
METAL
SOLDER MASK
OPENING METAL UNDER
SOLDER MASK SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
SOLDER MASK DETAILS
NON-SOLDER MASK
DEFINED SOLDER MASK
DEFINED
www.ti.com
EXAMPLE STENCIL DESIGN
16X (1.5)
16X (0.45)
14X (0.65)
(5.8)
(R0.05) TYP
(2.3)
BASED ON
0.125 THICK
STENCIL
(2.46)
BASED ON
0.125 THICK
STENCIL
PowerPAD TSSOP - 1.2 mm max heightPWP0016K
SMALL OUTLINE PACKAGE
4224484/A 08/2018
2.08 X 1.940.175 2.25 X 2.100.15 2.46 X 2.30 (SHOWN)0.125 2.75 X 2.570.1
SOLDER STENCIL
OPENING
STENCIL
THICKNESS
NOTES: (continued)
11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.
TM
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
SYMM
SYMM
1
89
16
METAL COVERED
BY SOLDER MASK
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
17
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consequences of failures, (2) monitor failures and their consequences, and (3) lessen the likelihood of failures that might cause harm and
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thoroughly test such applications and the functionality of such TI products as used in such applications.
TI’s provision of technical, application or other design advice, quality characterization, reliability data or other services or information,
including, but not limited to, reference designs and materials relating to evaluation modules, (collectively, “TI Resources”) are intended to
assist designers who are developing applications that incorporate TI products; by downloading, accessing or using TI Resources in any
way, Designer (individually or, if Designer is acting on behalf of a company, Designer’s company) agrees to use any particular TI Resource
solely for this purpose and subject to the terms of this Notice.
TI’s provision of TI Resources does not expand or otherwise alter TI’s applicable published warranties or warranty disclaimers for TI
products, and no additional obligations or liabilities arise from TI providing such TI Resources. TI reserves the right to make corrections,
enhancements, improvements and other changes to its TI Resources. TI has not conducted any testing other than that specifically
described in the published documentation for a particular TI Resource.
Designer is authorized to use, copy and modify any individual TI Resource only in connection with the development of applications that
include the TI product(s) identified in such TI Resource. NO OTHER LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE
TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT, AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY
RIGHT OF TI OR ANY THIRD PARTY IS GRANTED HEREIN, including but not limited to any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
regarding or referencing third-party products or services does not constitute a license to use such products or services, or a warranty or
endorsement thereof. Use of TI Resources may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
TI RESOURCES ARE PROVIDED “AS IS” AND WITH ALL FAULTS. TI DISCLAIMS ALL OTHER WARRANTIES OR
REPRESENTATIONS, EXPRESS OR IMPLIED, REGARDING RESOURCES OR USE THEREOF, INCLUDING BUT NOT LIMITED TO
ACCURACY OR COMPLETENESS, TITLE, ANY EPIDEMIC FAILURE WARRANTY AND ANY IMPLIED WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL
PROPERTY RIGHTS. TI SHALL NOT BE LIABLE FOR AND SHALL NOT DEFEND OR INDEMNIFY DESIGNER AGAINST ANY CLAIM,
INCLUDING BUT NOT LIMITED TO ANY INFRINGEMENT CLAIM THAT RELATES TO OR IS BASED ON ANY COMBINATION OF
PRODUCTS EVEN IF DESCRIBED IN TI RESOURCES OR OTHERWISE. IN NO EVENT SHALL TI BE LIABLE FOR ANY ACTUAL,
DIRECT, SPECIAL, COLLATERAL, INDIRECT, PUNITIVE, INCIDENTAL, CONSEQUENTIAL OR EXEMPLARY DAMAGES IN
CONNECTION WITH OR ARISING OUT OF TI RESOURCES OR USE THEREOF, AND REGARDLESS OF WHETHER TI HAS BEEN
ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
Unless TI has explicitly designated an individual product as meeting the requirements of a particular industry standard (e.g., ISO/TS 16949
and ISO 26262), TI is not responsible for any failure to meet such industry standard requirements.
Where TI specifically promotes products as facilitating functional safety or as compliant with industry functional safety standards, such
products are intended to help enable customers to design and create their own applications that meet applicable functional safety standards
and requirements. Using products in an application does not by itself establish any safety features in the application. Designers must
ensure compliance with safety-related requirements and standards applicable to their applications. Designer may not use any TI products in
life-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use.
Life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., life
support, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). Such equipment includes, without limitation, all
medical devices identified by the U.S. Food and Drug Administration as Class III devices and equivalent classifications outside the U.S.
TI may expressly designate certain products as completing a particular qualification (e.g., Q100, Military Grade, or Enhanced Product).
Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications
and that proper product selection is at Designers’ own risk. Designers are solely responsible for compliance with all legal and regulatory
requirements in connection with such selection.
Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer’s non-
compliance with the terms and provisions of this Notice.
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