A6800 and A6801 DABiC-5 Latched Sink Drivers Features and Benefits Description 3.3 to 5 V logic supply range Up to 10 MHz data input rate High-voltage, high-current outputs Darlington current-sink outputs, with improved low-saturation voltages CMOS, TTL compatible inputs Output transient protection Internal pull-down resistors Low-power CMOS latches The A6800 and A6801 latched-input BiMOS ICs merge high-current, high-voltage outputs with CMOS logic. The CMOS input section consists of 4 or 8 data (D type) latches with associated common CLEAR, STROBE, and OUTPUT ENABLE circuitry. The power outputs are bipolar NPN Darlingtons. This merged technology provides versatile, flexible interface. These BiMOS power interface ICs greatly benefit the simplification of computer or microprocessor I/O. The A6800 ICs each contain four latched drivers. A6801 ICs contain eight latched drivers. Packages A6800 14-pin SOICN (L package) A6800 14-pin 7.62 mm DIP (A package) A6801 24-pin SOICW (LW package) A6801 28-pin PLCC (EP package) The CMOS inputs are compatible with standard CMOS circuits. TTL circuits may mandate the addition of input pull-up resistors. The bipolar Darlington outputs are suitable for directly driving many peripheral/power loads: relays, lamps, solenoids, small DC motors, and so forth. All devices have open-collector outputs and integral diodes for inductive load transient suppression. The output transistors are capable of sinking 600 mA and can withstand at least 50 V in the off state. Because of limitations on package power dissipation, the simultaneous operation of all drivers at maximum rated current can only be accomplished by a reduction in duty cycle. Outputs may be paralleled for higher load current capability. Continued on the next page... Approximate scale 1:1 Functional Block Diagram C OMMON S UP P LY V DD OUT N IN N S T R OB E G R OUND C LE AR OUT P UT E NAB LE T Y P IC AL MOS LAT C H C OMMON MOS C ONT R OL 26180.110H T Y P IC AL B IP OLAR DR IV E A6800 and A6801 DABiC-5 Latched Sink Drivers Description (continued) The A6800SA is furnished in a 14-pin DIP with 7.62 mm (0.300 in.) row centers, the A6800SL and A6801SLW in surfacemountable SOICs; and the A6801SEP in a 28-lead PLCC. These devices are lead (Pb) free, with 100% matte tin plated leadframes. Applications include: Relays Lamps Solenoids Small DC motors Selection Guide Part Number Package Packing 14-pin DIP 25 per tube A6800SLTR-T 14-pin SOIC 2500 per reel A6801SEPTR-T 28-pin PLCC 800 per reel A6801SLWTR-T 24-pin SOIC 1000 per reel A6800SA-T* *Variant is in production but has been determined to be NOT FOR NEW DESIGN. This classification indicates that sale of the variant is currently restricted to existing customer applications. The variant should not be purchased for new design applications because obsolescence in the near future is probable. Samples are no longer available. Status change: May 4, 2009. Absolute Maximum Ratings* Characteristic Symbol Rating Units 50 V VDD 7 V VIN -0.3 to VDD + 0.3 V IC 600 mA Output Voltage VCE Supply Voltage Input Voltage Range Continuous Collector Current Notes Operating Ambient Temperature TA -20 to 85 C Maximum Junction Temperature TJ(max) 150 C Tstg -55 to 150 C Storage Temperature Range S *Caution: CMOS devices have input-static protection, but are susceptible to damage when exposed to extremely high static-electrical charges. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 2 A6800 and A6801 DABiC-5 Latched Sink Drivers Allowable Power Dissipation 2.5 28-LEAD PLCC, RQJA = 68oC/W 14-PIN DIP, RQJA = 73oC/W PACKAGE POWER DISSIPATION (W) 2.0 24-LEAD SOIC, RQJA = 85oC/W 1.5 1.0 0.5 14-LEAD SOIC, RQJA = 120oC/W 0 25 50 75 100 125 150 AMBIENT TEMPERATURE (C) Typical Input Circuit VDD IN Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 3 A6800 and A6801 DABiC-5 Latched Sink Drivers ELECTRICAL CHARACTERISTICS1 Unless otherwise noted: TA = 25C, logic supply operating voltage VDD = 3.0 to 5.5 V VDD = 3.3 V Characteristic Min. Typ. Typ. Max. Units VOUT = 50 V - - 10 - - 10 A IOUT = 350 mA, L = 3 mH 35 - - 35 - - V IOUT = 100 mA - 0.8 1.0 - 0.8 1.0 V IOUT = 200 mA - 0.9 1.1 - 0.9 1.1 V Symbol Output Leakage Current ICEX Output Sustaining Voltage VCE(SUS) Collector-Emitter Saturation Voltage VCE(SAT) Test Conditions IOUT = 350 mA (See note 2) Input Voltage Input Resistance Logic Supply Current VDD = 5 V Max. Min. - 1.0 1.3 - 1.0 1.3 V VIN(1) 2.2 - - 3.3 - - V VIN(0) - - 1.1 - - 1.7 V RIN 50 - - 50 - - k mA IDD(1) One output on, IOUT = 100 mA - - 1.0 - - 1.0 IDD(0) All outputs off - 130 150 - 130 150 A Clamp Diode Leakage Current Ir Vr = 50 V - - 50 - - 50 A Clamp Diode Forward Voltage Vf If = 350 mA - - 2.0 - - 2.0 V Output Fall Time tf VCC = 50 V, R1 = 500 , C1 30 pF - 80 - - 80 - ns Output Rise Time tr VCC = 50 V, R1 = 500 , C1 30 pF - 100 - - 100 - ns 1 Operation of these devices with standard TTL or DTL may require the use of appropriate pull-up resistors to ensure a minimum logic 1. 2 Because of limitations on package power dissipation, the simultaneous operation of multiple drivers can only be accomplished by reduction in duty cycle. Truth Table OUT N OUT P UT IN N S T R OB E CLE AR E NA B L E t-1 t 0 1 X X X X 1 1 X X 0 0 0 0 1 X 0 0 0 0 X 1 0 0 X X X X ON OF F OF F ON OF F OF F ON OF F X = irrelevant t-1 = previous output s tate t = pres ent output s tate Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 4 A6800 and A6801 DABiC-5 Latched Sink Drivers Timing Requirements and Specifications (Logic Levels are VDD and Ground) CLEAR G STROBE A C B B C C A H B H INN D E E F OUTN HIGH = ALL OUTPUTS DISABLED (OFF) OUTPUT ENABLE 50% t en(BQ) tr tf t dis(BQ) OUT N Key DATA 10% 90% 50% Description Time (ns) A Minimum data active time before Strobe enabled (Data Set-Up Time) 25 B Minimum data active time after Strobe disabled (Data Hold Time) 25 C Minimum Strobe pulse width 50 D Maximum time between Strobe activation and transition from output on to output off* 500 E Maximum time between Strobe activation and transition from output off to output on* 500 F Maximum time between Clear activation and transition from output on to output off* 500 G Minimum Clear pulse width 50 H Minimum data pulse width 100 tdis(BQ) Output Enable to output off delay* 500 ten(BQ) Output Enable to output on delay* 500 *Conditions for output transition testing are: VCC = 50 V, VDD = 5 V, R1 = 500 , C1 30 pF. NOTE: Information present at an input is transferred to its latch when the STROBE is high. A high CLEAR input will set all latches to the output off condition regardless of the data or STROBE input levels. A high OUTPUT ENABLE will set all outputs to the off contdition, regardless of any other input conditions. When the OUTPUT ENABLE is low, the outputs depend on the state of their respective latches. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 5 A6800 and A6801 DABiC-5 Latched Sink Drivers A6800 L Package 1 14 A6800 A-14 Package 1 14 OUTPUT ENABLE STROBE 2 VDD 13 SUPPLY IN 1 3 12 OUT 1 IN 2 4 11 OUT 2 IN 3 5 10 OUT 3 IN 4 6 9 OUT 4 GROUND 7 8 COMMON LATCHES CLEAR Dwg. PP-014A Note: The A6800 SOIC and DIP packages are electrically identical and share a common terminal number assignment. A6801 LW Package OUT1 6 OUT 2 IN 3 7 23 OUT 3 IN 4 8 22 OUT4 IN 5 9 21 OUT 5 OUT8 16 LAMP DIODE COMMON 15 17 NC OUT7 GROUND 23 SUPPLY 3 22 OUT 1 IN 2 4 21 OUT 2 IN 3 5 20 OUT 3 IN 4 6 19 OUT 4 IN5 7 18 OUT 5 IN 6 8 17 OUT 6 IN 7 9 16 OUT 7 IN 8 10 15 OUT 8 GROUND 11 14 COMMON NO CONNECTION 12 13 NO CONNECTION STROBE 2 IN1 VDD 18 19 K IN 7 11 13 NC OUT 6 14 NC 20 12 IN 6 10 IN 8 OUTPUT ENABLE 1 LATCHES NC 25 24 LATCHES 5 IN 2 IN1 24 CLEAR 26 27 SUPPLY V DD CLEAR 28 OUTPUT ENABLE 1 C OE NC 2 3 ST NC 4 STROBE A6801 EP Package Dwg. PP-037 NC NC Dwg. PP-015-1 Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 6 A6800 and A6801 DABiC-5 Latched Sink Drivers TYPICAL APPLICATION UNIPOLAR STEPPER-MOTOR DRIVE +30 V OUT P UT E NAB LE (AC T IV E LOW) C LE AR S T R OB E 1 14 2 V DD 13 3 12 V DD IN 2 IN 3 IN 4 4 5 LAT C HE S IN 1 OUT 1 OUT 2 11 OUT 3 10 OUT 4 6 9 7 8 A6800S A +30 V Dwg. No. B -1537 UNIPOLAR WAVE DRIVE UNIPOLAR 2-PHASE DRIVE S T R OB E S T R OB E IN 1 IN 1 IN 2 IN 2 IN 3 IN 3 IN 4 IN 4 OUT 1 OUT 1 OUT 2 OUT 2 OUT 3 OUT 3 OUT 4 OUT 4 Dwg. G P -060 Dwg. G P -060-1 Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 7 A6800 and A6801 DABiC-5 Latched Sink Drivers Package A (A6800) 14-pin DIP +0.64 19.05 -0.38 14 +0.10 0.25 -0.05 +0.76 6.35 -0.25 +0.38 10.92 -0.25 7.62 A 1 2 5.33 MAX +0.51 3.30 -0.38 +0.25 1.52 -0.38 2.54 0.46 0.12 SEATING PLANE C For Reference Only Dimensions in millimeters (reference JEDEC MS-001 AA) Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown A Terminal #1 mark area Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 8 A6800 and A6801 DABiC-5 Latched Sink Drivers Package EP (A6801) 28-pin PLCC 12.450.13 11.510.08 2 1 0.51 28 A 12.450.13 5.210.36 11.510.08 5.210.36 0.51 MIN 0.740.08 +0.20 4.37 -0.18 28X 0.10 C SEATING PLANE C 0.430.10 1.27 5.210.36 5.210.36 For Reference Only (reference JEDEC MS-018 AB) Dimensions in millimeters Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown A Terminal #1 mark area Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 9 A6800 and A6801 DABiC-5 Latched Sink Drivers Package L (A6800) 14-pin SOICN 9.90 0.10 1.27 4 4 0.65 14 0.21 0.04 3.90 0.10 6.00 0.20 1 5.60 +0.43 0.84 -0.44 A 2 1.75 0.25 14X SEATING PLANE 0.10 C 0.41 0.10 B PCB Layout Reference View SEATING PLANE GAUGE PLANE C 1.75 MAX 1.27 +0.07 0.18 -0.08 For Reference Only Dimensions in millimeters (reference JEDEC MS-012 AB) Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown A Terminal #1 mark area B Reference pad layout (reference IPC SOIC127P600X175-14M) All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances Package LW (A6801) 24-pin SOICW 15.400.20 4 4 24 +0.07 0.27 -0.06 10.300.33 7.500.10 A 1 24 2.20 9.60 +0.44 0.84 -0.43 2 1 2 0.65 0.25 24X SEATING PLANE 0.10 C 0.41 0.10 1.27 2.65 MAX 0.20 0.10 C SEATING PLANE GAUGE PLANE 1.27 B PCB Layout Reference View For Reference Only (Reference JEDEC MS-013 AD) Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown A Terminal #1 mark area B Reference pad layout (reference IPC SOIC127P1030X265-24M) All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 10 A6800 and A6801 DABiC-5 Latched Sink Drivers Copyright (c)2003-2009, Allegro MicroSystems, Inc. The products described here are manufactured under one or more U.S. patents or U.S. patents pending. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro's products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. For the latest version of this document, visit our website: www.allegromicro.com Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 11