CY7C109D
CY7C1009D
1-Mbit (128 K × 8) St atic RAM
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document #: 38-05468 Rev. *G Revised April 15, 201 1
Features
■Pin- and function-compatible with CY7C109B/CY7C1009B
■High speed
❐tAA = 10 ns
■Low active po w e r
❐ICC = 80 mA at 10 ns
■Low CMOS standby power
❐ISB2 = 3 mA
■2.0 V Data Retention
■Automatic power-down when deselected
■TTL-compatible inputs and outputs
■Easy memory expansion with CE1, CE2 and OE optio ns
■CY7C109D available in Pb-free 32-pin 400-Mil wide Molded
SOJ and 32-pin TSOP I packages. CY7C1009D available in
Pb-free 32-pin 300-Mil wide Molded SOJ package
Functional Description [1]
The CY7C109D/CY7C1009D is a high-performance CMOS
static RAM organized as 131,072 words by 8 bits. Easy
memory expansion is provided by an active LOW Chip Enable
(CE1), an active HIGH Chip Enable (CE2), an active LOW
Output Enable (OE), and tri-state drivers.The eight input and
output pins (I/O0 through I/O7) are placed in a high-impedance
state w he n:
■Deselected (CE1 HIGH or CE2 LOW),
■Outputs are disabled (OE HIGH),
■When the write operation is active (CE1 LOW, CE2 HIGH,
and WE LOW)
Write to the device by taking Chip Enable One (CE1) and Write
Enable (WE) inputs LOW and Chip Enable Two (CE2) input
HIGH. Data on the eight I/O pins (I/O0 through I/O7) is then
written into the location specified on the address pin s (A0
through A16).
Read from the device by taking Chip Enable One (CE1) and
Output Enable (OE) LOW while forcing Write Enable (WE) and
Chip Enable Two (CE2) HIGH. Under these conditions, the
contents of the memory location specified by the address pins
appears on the I/O pins.
Logic Block Diagram
IO0
IO7
IO1
IO2
IO3
IO4
IO5
IO6
SENSE AMPS
POWER
DOWN
WE
OE
A0
A1
A2
A3
A4
A5
A6
A7
A8
ROW DECODER
128K x 8
ARRAY
INPUT BUFFER
CE1
CE2
A9
A10
A11
A12
A13
A14
A15
A16
COLUMN DECODER
Note
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
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CY7C1009D
Document #: 38-05468 Rev. *G Page 2 of 14
Contents
Pin Configuration .............................................................3
Selection Guide ................................................................3
Maximum Ratings .............................................................4
Operating Range ..................... .. ............................ ............4
Electrical Characteristics (Ove r the Operating Range) ...4
Capacitance ......................................................................5
Thermal Resistance ..........................................................5
AC Test Loads and Waveforms .......................................5
Switching Characteristics (Over the Operating Range) ..6
Data Retention Characteristics
(Over the Operating Range) ...............................................7
Data Retention Waveform ................................................7
Switching Waveforms ......................................................7
Truth Table ........................................................................9
Ordering Information ......................................................10
Ordering Code Definitions .........................................10
Package Diagrams ..........................................................11
Acronyms ........................................................................ 12
Document Conventions ..................... ... .........................12
Units of Measure ............. ............................ ... ...........12
Document History Page ...................................... ...........13
Sales, Solutions, and Legal Information ......................14
Worldwide Sales and Design Support .......................14
Products .................................................................... 14
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CY7C1009D
Document #: 38-05468 Rev. *G Page 3 of 14
Pin Configuration [2]
Selection Guide
CY7C109D-10
CY7C1009D-10 Unit
Maximum Access Time 10 ns
Maximum Operating Current 80 mA
Maximum CMOS Standby Current 3 mA
1
2
3
4
5
6
7
8
9
10
11
14 19
20
24
23
22
21
25
28
27
26
12
13
29
32
31
30
16
15 17
18
GND
A
16
A
14
A
12
A
7
A
6
A
5
A
4
A
3
WE
V
CC
A
15
A
13
A
8
A
9
I/O
7
I/O
6
I/O
5
I/O
4
A
2
NC
I/O
0
I/O
1
I/O
2
CE
1
OE
A
10
I/O
3
A
1
A
0
A
11
CE
2
A
6
A
7
A
16
A
14
A
12
WE
V
CC
A
4
A
13
A
8
A
9
OE
TSOP I
Top View
(not to scale)
1
6
2
3
4
5
7
32
27
31
30
29
28
26
21
25
24
23
22
19
20
I/O
2
I/O
1
GND
I/O
7
I/O
4
I/O
5
I/O
6
I/O
0
CE
A
11
A
5
17
18
8
9
10
11
12
13
14
15
16
CE
2
A
15
NC
A
10
I/O
3
A
1
A
0
A
3
A
2
Top View
SOJ
Note
2. NC pins are not connected on the die.
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CY7C1009D
Document #: 38-05468 Rev. *G Page 4 of 14
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User gui d el i ne s are not tested.
Storage Temperature ........................... ... .. .–65°C to +150°C
Ambient Temperature with
Power Applied ............ ................................ –55°C to +125°C
Supply Voltage on VCC to Relative GND [3]..–0.5 V to +6.0 V
DC Voltage Applied to Outputs
in High-Z S tate [3].................................–0.5 V to VCC + 0.5 V
DC Input Voltage [3] .............................–0.5 V to VCC + 0.5 V
Current into Outputs (LOW ).........................................20 mA
Static Discharge Voltage............. ... .. ... .....................> 2001 V
(per MIL-STD-883, Method 3015)
Latch-up Current.....................................................> 200 mA
Operating Range
Range Ambient
Temperature VCC Speed
Industrial –40°C to +85°C 5 V ± 0.5 V 10 ns
Electrical Characteristics (Over the Operating Range)
Parameter Description Test Conditions 7C109D-10
7C1009D-10 Unit
Min Max
VOH Output HIGH Voltage IOH = –4.0 mA 2.4 V
VOL Output LOW Voltage IOL = 8.0 mA 0.4 V
VIH Input HIGH Voltage 2.2 VCC + 0.5 V
VIL Input LOW Voltage [3] –0.5 0.8 V
IIX Input Leakage Current GND < VI < VCC –1 +1 μA
IOZ Output Leakage Current GND < VI < VCC, Output Di sabled –1 +1 μA
ICC VCC Operating Supply Current VCC = Max,
IOUT = 0 mA,
f = fmax = 1/tRC
100 MHz 80 mA
83 MHz 72 mA
66 MHz 58 mA
40 MHz 37 mA
ISB1 Automatic CE Power-Down
Current—TTL Inputs Max VCC,
CE1 > VIH or CE2 < VIL,
VIN > VIH or VIN < VIL, f = fmax
10 mA
ISB2 Automatic CE Power-Down
Current—CMOS Inputs Max VCC,
CE1 > VCC – 0.3 V, or CE2 < 0.3 V,
VIN > VCC – 0.3 V, or VIN < 0.3 V, f = 0
3mA
Note
3. VIL (min) = –2.0 V and VIH(max) = VCC + 1 V for pulse durations of less than 5 ns.
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CY7C1009D
Document #: 38-05468 Rev. *G Page 5 of 14
Capacitance [4]
Parameter Description Test Conditions Max Unit
CIN Input Capacitance TA = 25°C, f = 1 MHz, VCC = 5.0 V 8 pF
COUT Output Capacitance 8 pF
Thermal Resist ance [4]
Parameter Description Test Conditions 300-Mil
Wide SOJ 400-Mil
Wide SOJ TSOP I Unit
ΘJA Thermal Resistance
(Junction to Ambient) Still Air , soldered on a 3 × 4.5 inch,
four-layer printed circuit board 57.61 56.29 50.72 °C/W
ΘJC Thermal Resistance
(Junction to Case) 40.53 38.14 16.21 °C/W
AC Test Loads and Waveforms [5]
90%
10%
3.0 V
GND
90%
10%
ALL INPUT PULSES
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT Rise Time: ≤ 3 ns Fall Time: ≤ 3 ns
30 pF*
OUTPUT
Z = 50
Ω
50Ω
1.5 V (b)
(a)
5 V
OUTPUT
5 pF
(c)
R1 480Ω
R2
255Ω
High-Z characteristics:
INCLUDING
JIG AND
SCOPE
Notes
4. Tested initially and after any desig n or process changes that may affect these parameters.
5. AC characteristics (except High-Z) are tested using the load conditions shown in Figure (a). High-Z characteristics are tested for all speeds using the t est load
shown in Figure (c).
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CY7C1009D
Document #: 38-05468 Rev. *G Page 6 of 14
Switching Characteristics (Over the Operating Range) [6]
Parameter Description 7C109D-10
7C1009D-10 Unit
Min Max
Read Cycle
tpower [7] VCC(typical) to the first access 100 μs
tRC Read Cycle Time 10 ns
tAA Address to Data Valid 10 ns
tOHA Data Hold from Address Change 3 ns
tACE CE1 LOW to Data Valid, CE2 HIGH to Data Valid 10 ns
tDOE OE LOW to Data Valid 5 ns
tLZOE OE LOW to Low Z 0 ns
tHZOE OE HIGH to High Z [8, 9] 5ns
tLZCE CE1 LOW to Low Z, CE2 HIGH to Low Z [9] 3ns
tHZCE CE1 HIGH to High Z, CE2 LOW to High Z [8, 9] 5ns
tPU [10] CE1 LOW to Power-Up, CE2 HIGH to Power-Up 0 ns
tPD [10] CE1 HIGH to Po wer-Down, CE2 LOW to Power-D ow n 10 ns
Write Cycle [11, 12]
tWC Write Cycle Time 10 ns
tSCE CE1 LOW to Write End, CE2 HIGH to Write End 7 ns
tAW Address Set-Up to Write End 7 ns
tHA Address Hold from Write End 0 ns
tSA Address Set-Up to Write Start 0 ns
tPWE WE Pulse Widt h 7 ns
tSD Data Set-Up to Write End 6 ns
tHD Dat a Ho l d from Write End 0 ns
tLZWE WE HIGH to Low Z [9] 3ns
tHZWE WE LOW to High Z [8, 9] 5ns
Notes
6. Test conditions assume signal transition time of 3 ns or less, timing ref ere nce levels of 1. 5 V, input pulse levels of 0 to 3.0 V, and output loading of the sp ecifi ed
IOL/IOH and 30-pF load capacitance.
7. tPOWER gives the minimum amount of time that the power supply should be at typical VCC value s until the first memory access can be performed
8. tHZOE, tHZCE and tHZWE are specified with a load capacitance of 5 pF as in part (c) of “AC T est Loads and W aveforms [5]” on page 5. T ransition is measured when the outputs enter
a high impeda nce state.
9. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
10.This parameter is guaranteed by design and is not tested.
11. The internal write time of the memory is defin ed by t he ove rlap of CE1 LOW, C E2 HIGH, and WE LOW . CE1 and WE must be LOW and CE2 HIGH to initiate a wri te, and
the transit ion of any of th ese signals can ter minate the write. The input dat a set-up and hold timing shoul d be referenced to the leading edge of the sign al that terminat es the write.
12.The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
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Document #: 38-05468 Rev. *G Page 7 of 14
Data Retention Characteristics (Over the Operating Range)
Parameter Description Conditions Min Max Unit
VDR VCC for Data Retention VCC = VDR = 2.0 V,
CE1 > VCC – 0.3 V or CE2 < 0.3 V,
VIN > VCC – 0.3 V or VIN < 0.3 V
2.0 V
ICCDR Data Retention Current 3mA
tCDR [4] Chip Deselect to Data Retention Time 0 ns
tR [13] Operation Recovery Ti me tRC ns
Data Retention Waveform
Switching Waveforms
Figure 1. Read Cycle No. 1 (Address Transition Controlled) [14, 15]
Figure 2. Read Cycle No. 2 (OE Controlled) [15, 16]
4.5 V4.5 V
tCDR
VDR >2 V
DATA RETENTION MODE
tR
CE
V
CC
PREVIOUS DATA VALID DATA VALID
tRC
tAA
tOHA
ADDRESS
DATA OUT
50%
50%
DATA VALID
tRC
tACE
tDOE
tLZOE
tLZCE
tPU
HIGH IMPEDANCE
tHZOE tHZCE
tPD
OE
CE1
ADDRESS
CE2
DATA OUT
VCC
SUPPLY
CURRENT
HIGH
ICC
ISB
IMPEDANCE
Notes
13.Full device operation requires linear VCC ramp from VDR to VCC(min) > 50 μs or stable at VCC(min) > 50 μs.
14.Device is continuously selected. OE, CE1 = VIL, CE2 = VIH.
15.WE is HIGH for read cycle.
16.Address valid prior to or coincident with CE1 transition LOW and CE2 transition HIGH.
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CY7C1009D
Document #: 38-05468 Rev. *G Page 8 of 14
Figure 3. Write Cycle No. 1 (CE1 or CE2 Controlled) [17, 18]
Figure 4. Write Cycle No. 2 (WE Controlled, OE HIGH During Write) [17, 18]
Switching Waveforms (continued)
tWC
DATA VALID
tAW
tSA
tPWE
tHA
tHD
tSD
tSCE
tSCE
CE1
ADDRESS
CE2
WE
DATA I/O
tHD
tSD
tPWE
tSA
tHA
tAW
tSCE
tSCE
tWC
tHZOE
DATAIN VALID
NOTE 19
CE1
ADDRESS
CE2
WE
DATA I/O
OE
Notes
17.Data I/O is high impedance if OE = VIH.
18.If CE1 goes HIGH or CE2 goes LOW simultaneously with WE going HIGH, the output remains in a high-impedance st ate.
19.During this period the I/Os are in the output state and input signals should not be applied.
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Document #: 38-05468 Rev. *G Page 9 of 14
Figure 5. Write Cycle No. 3 (WE Controlled, OE LOW) [12, 18]
Truth Table
CE1CE2OE WE I/O0–I/O7Mode Power
H X X X High Z Power-down Standby (ISB)
X L X X High Z Power-down Standby (ISB)
LHLHData Out Read Active (I
CC)
L H X L Data In Write Active (ICC)
L H H H High Z Selected, Outputs Disabled Active (ICC)
Switching Waveforms (continued)
DATA VALID
tHD
tSD
tLZWE
tPWE
tSA
tHA
tAW
tSCE
tSCE
tWC
tHZWE
NOTE 19
CE1
ADDRESS
CE2
WE
DATA I/O
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CY7C1009D
Document #: 38-05468 Rev. *G Page 10 of 14
Ordering Information
Speed
(ns) Ordering Code Package
Diagram Package Type Operating
Range
10 CY7C109D-10VXI 51-85033 32-pin (400-Mil) Molded SOJ (Pb-free) Industrial
CY7C109D-10ZXI 51-85056 32-pin TSOP Type I (Pb-free)
CY7C1009D-10VXI 51-85041 32-pin (300-Mil) Molded SOJ (Pb-free)
Ordering Code Definitions
Please contact your local Cypress sales representative for availability of these parts.
Temperature Range:
I = Industrial
Package Type: XX = VX or ZX
VX = 32-pin Molded SOJ (Pb-free)
ZX = 32-pin TSOP Type I (Pb-free)
Speed: 10 ns
D = C9, 90 nm Technology
xx9 = 09 or 009 = (400-Mil / 300-Mil) 1-Mbit density
1 = Fast Asynchronous SRAM family
Technology Code: C = CMOS
7 = SRAM
CY = Cypress
CCY 1 - 10 XX7 xx9 D I
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Document #: 38-05468 Rev. *G Page 12 of 14
Acronyms Document Conventions
Units of Measure
Figure 8. 32-pin Thin Small Outline Package Type I (8 × 20 mm), 51-85056
Package Diagrams (continued)
51-85056 *F
Acronym Description
CE chip enable
CMOS Complementary metal oxide semiconductor
I/O Input/output
OE output enabl e
SRAM Static random access memory
SOJ Small Outline J-Lead
TSOP Thin Small Outline Package
VFBGA Very Fine-Pitch Ball Grid Array
Symbol Unit of Measure
ns nano seconds
VVolts
µA micro Amperes
mA milli Amperes
mV milli Volts
mW milli Wa tts
MHz Mega Hertz
pF pico Farad
°C degree Celcius
WWatts
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Document #: 38-05468 Rev. *G Page 13 of 14
Document History Page
Document Title: CY7C109D/CY7C1009D, 1-Mbit (128 K × 8) Static RAM
Document Number: 38-05468
Revision ECN Submission
Date Orig. of
Change Description of Ch ange
** 201560 See ECN S WI Advance Information data sheet for C9 IPP
*A 233722 See ECN RKF DC parameters are modified as per EROS (Spec # 01-2165)
Pb-free offering in Ordering Information
*B 262950 See ECN RKF Added Data Retention Characteristics table
Added Tpower Spec in Switching Characteristics Table
Shaded Ordering Information
*C See ECN See ECN RKF Reduced Sp eed bins to -10 and -12 ns
*D 560995 See ECN VKN Converted from Preliminary to Final
Removed Commercial Operating rang e
Removed 12 ns speed bin
Added ICC values for the frequencie s 83MHz, 66MHz and 40MHz
Updated Thermal Resistance table
Updated Ordering Information Table
Changed Overshoot spec from VCC+2 V to VCC+1 V in footnote #3
*E 802877 See ECN VKN Changed ICC spec from 60 mA to 80 mA for 100MHz, 55 mA to 72 mA for
83MHz, 45 mA to 58 mA for 66MHz, 30 mA to 37 mA for 40MHz
*F 3104943 12/08/2010 AJU Added Ordering Code Definitions.
Updated Package Diagrams.
*G 3220123 04/08/2011 PRAS Updated template and styles as per current Cypress standards.
Added Acronyms and units of measure.
Updated package diagrams:
51-85033 to *D
51-85056 to *F
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Document #: 38-05468 Rev. *G Revised April 15, 2011 Page 14 of 14
All products and company names mentioned in this document may be the trademarks of their respective holders.
CY7C109D
CY7C1009D
© Cypress Semico nducto r Co rpor ation , 20 04-2 011. The information cont ai ned he rein is subj ect to chang e with out no tice. Cypr ess Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypre ss prod uc ts are n ot war r ant ed no r inte nd ed to be used fo r
medical, life supp or t, l if e savin g, cr it ical control or safety applicatio ns, unl ess pu r suan t to an express written agreement wit h Cy press. Fu rth er m ore, Cyp ress doe s not author i ze its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (C ypress) and is protected by and subject to worldwide patent pro tectio n (United States and foreign),
United S t ates copyright laws and international treaty provis ions. Cyp ress he reby gr ant s to l icense e a pers onal, no n-excl usive , non-tr ansfer able license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee prod uct to be used only in conjunction with a Cyp ress
integrated circui t as specified in the applicab le agreement. Any r eproduction, mod ification, translati on, compilatio n, or represent ation of this Sour ce Code except a s specified abo ve is prohibit ed without
the express written permission of Cypres s.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY A ND FITNESS FOR A PARTICULAR PURPOSE. C ypress reserves the right to make changes without further notice to the materials described he rein. Cypress d oes not
assume any liabil ity ar ising ou t of the a pplic ation or use o f any pr oduct or circ uit descri bed herein . Cypress d oes not a uthor ize its p roducts fo r use as critical componen ts in life-su pport systems whe re
a malfuncti on or failure may reason ably be expected to res ult in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
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