Regarding the change of names mentioned in the document, such as Mitsubishi
Electric and Mitsubishi XX, to Renesas Technology Corp.
The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi
Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names
have in fact all been changed to Renesas Technology Corp. Thank you for your understanding.
Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been
made to the contents of the document, and these changes do not constitute any alteration to the
contents of the document itself.
Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices
and power devices.
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
To all our customers
Description
1
Mitsubishi microcomputer
s
M16C / 30 Grou
p
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTE
R
Description
The M16C/30 group of single-chip microcomputers are built using the high-performance silicon gate CMOS
process using a M16C/60 Series CPU core and are packaged in a 100-pin plastic molded QFP. These
single-chip microcomputers operate using sophisticated instructions featuring a high level of instruction
efficiency. With 1M bytes of address space, they are capable of executing instructions at high speed. They
also feature a built-in multiplier and DMAC, making them ideal for controlling office, communications, indus-
trial equipment, and other high-speed processing applications.
The M16C/30 group includes a wide range of products with different internal memory sizes and various
package types.
Features
• Memory capacity..................................ROM (See Figure 1.1.4. ROM Expansion)
RAM 2K to 3K bytes
• Shortest instruction execution time......62.5ns (f(XIN)=16MHZ, VCC=5V)
100ns (f(XIN)=10MHZ, VCC=3V, with software one-wait)
• Supply voltage .....................................4.2V to 5.5V (f(XIN)=16MHZ, without software wait)
2.7V to 5.5V (f(XIN)=10MHZ with software one-wait)
• Low power consumption ......................25.5mW ( f(XIN)=10MHZ, with software one-wait, VCC = 3V)
• Interrupts..............................................16 internal and 5 external interrupt sources, 4 software
interrupt sources; 7 levels (including key input interrupt)
• Multifunction 16-bit timer......................3 output timers + 2 input timers
• Serial I/O..............................................3 channels (3 for UART or clock synchronous)
• DMAC ..................................................1 channels (trigger: 14 sources)
• A-D converter.......................................10 bits X 8 channels (Expandable up to 10 channels)
• Watchdog timer....................................1 line
• Programmable I/O port ........................87 lines
• Input port.............................................. _______
1 line (P85 shared with NMI pin)
• Memory expansion ..............................Available (to a maximum of 1M bytes)
• Chip select output ................................4 lines
• Clock generating circuit .......................2 built-in clock generation circuits
(built-in feedback resistor, and external ceramic or quartz oscillator)
Applications
Audio, cameras, office equipment, communications equipment, portable equipment
------Table of Contents------
Timer.............................................................75
Serial I/O .......................................................93
A-D Converter .............................................130
Programmable I/O Ports .............................136
Electrical characteristics .............................146
Central Processing Unit (CPU) .....................11
Reset.............................................................14
Processor Mode............................................21
Clock Generating Circuit ...............................34
Protection......................................................43
Interrupt.........................................................44
Watchdog Timer............................................64
DMAC ...........................................................66
Rev.1.0
Description
2
Mitsubishi microcomputer
s
M16C / 30 Grou
p
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTE
R
1 2 3 4 5 6 7 8 9101112131415161718192021222324252627282930
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
515253545556575859606162636465666768697071727374757677787980
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
P0
0
/D
0
P0
1
/D
1
P0
2
/D
2
P0
3
/D
3
P0
4
/D
4
P0
5
/D
5
P0
6
/D
6
P0
7
/D
7
P1
0
/D
8
P1
1
/D
9
P1
2
/D
10
P1
3
/D
11
P1
4
/D
12
V
REF
AV
SS
V
CC
X
IN
X
OUT
V
SS
RESET
CNVss
P8
7
/X
CIN
P8
6
/X
COUT
BYTE P2
0
/A
0
(/D
0
/-)
P2
1
/A
1
(/D
1
/D
0
)
P2
2
/A
2
(/D
2
/D
1
)
P2
3
/A
3
(/D
3
/D
2
)
P2
4
/A
4
(/D
4
/D
3
)
P2
5
/A
5
(/D
5
/D
4
)
P2
6
/A
6
(/D
6
/D
5
)
P2
7
/A
7
(/D
7
/D
6
)
P3
0
/A
8
(/-/D
7
)
P3
1
/A
9
P3
2
/A
10
P3
3
/A
11
P3
4
/A
12
P3
5
/A
13
P3
6
/A
14
P3
7
/A
15
P4
0
/A
16
P4
1
/A
17
P4
2
/A
18
P4
3
/A
19
P7
4
/TA2
OUT
P7
6
P5
6
/ALE
P7
7
P5
5
/HOLD
P5
4
/HLDA
P5
3
/BCLK
P5
2
/RD
Vcc
Vss
P5
7
/RDY/CLK
OUT
P4
5
/CS1
P4
6
/CS2
P4
7
/CS3
AVcc
P6
3
/T
X
D
0
P6
5
/CLK
1
P6
6
/RxD
1
P6
7
/T
X
D
1
P6
1
/CLK
0
P6
2
/RxD
0
P10
0
/AN
0
P10
1
/AN
1
P10
2
/AN
2
P10
3
/AN
3
P9
3
P9
4
P9
5
/ANEX0
P9
6
/ANEX1
P9
1
/TB1
IN
P9
2
/TB2
IN
P8
0
P6
0
/CTS
0
/RTS
0
P6
4
/CTS
1
/RTS
1
/CLKS
1
P7
2
/CLK
2
/TA1
OUT
P8
2
/INT
0
P7
1
/RxD
2
/SCL/TA0
IN
(Note)
P8
3
/INT
1
P8
5
/NMI
P9
7
/AD
TRG
P4
4
/CS0
P5
0
/WRL/WR
P5
1
/WRH/BHE
P9
0
P7
0
/T
X
D
2
/SDA/TA0
OUT
(Note)
P8
4
/INT
2
P8
1
P7
5
/TA2
IN
P1
5
/D
13
P1
6
/D
14
P1
7
/D
15
P10
7
/AN
7
/KI
3
P10
6
/AN
6
/KI
2
P10
5
/AN
5
/KI
1
P10
4
/AN
4/
KI
0
P7
3
/CTS
2
/RTS
2
/TA1
IN
Note: P7
0
and P7
1
are N channel open-drain output pin.
Pin Configuration
Figures 1.1.1 and 1.1.2 show the pin configurations (top view).
PIN CONFIGURATION (top view)
Package: 100P6S-A
Figure 1.1.1. Pin configuration (top view)
M16C/30 Group
Description
3
Mitsubishi microcomputer
s
M16C / 30 Grou
p
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTE
R
1 2 3 4 5 6 7 8 9 101112131415161718192021 22 23 24 25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
525354555657585960616263646566676869707172737475
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
P0
0
/D
0
P0
1
/D
1
P0
2
/D
2
P0
3
/D
3
P0
4
/D
4
P0
5
/D
5
P0
6
/D
6
P0
7
/D
7
P1
0
/D
8
P1
1
/D
9
P1
2
/D
10
P1
3
/D
11
P1
4
/D
12
V
REF
AV
SS
V
CC
X
IN
X
OUT
V
SS
CNVss
P8
7
/X
CIN
P8
6
/X
COUT
BYTE P2
0
/A
0
(/D
0
/-)
P2
1
/A
1
(/D
1
/D
0
)
P2
2
/A
2
(/D
2
/D
1
)
P2
3
/A
3
(/D
3
/D
2
)
P2
4
/A
4
(/D
4
/D
3
)
P2
5
/A
5
(/D
5
/D
4
)
P2
6
/A
6
(/D
6
/D
5
)
P2
7
/A
7
(/D
7
/D
6
)
P3
0
/A
8
(/-/D
7
)
P3
1
/A
9
P3
2
/A
10
P3
3
/A
11
P3
4
/A
12
P3
5
/A
13
P3
6
/A
14
P3
7
/A
15
P4
0
/A
16
P4
1
/A
17
P4
2
/A
18
P4
3
/A
19
P7
4
/TA2
OUT
P7
6
P5
6
/ALE
P7
7
P5
5
/HOLD
P5
4
/HLDA
P5
3
/BCLK
P5
2
/RD
Vcc
Vss
P5
7
/RDY/CLK
OUT
P4
5
/CS1
P4
6
/CS2
P4
7
/CS3
AVcc
P6
3
/T
X
D
0
P6
5
/CLK
1
P6
6
/RxD
1
P6
7
/T
X
D
1
P6
1
/CLK
0
P6
2
/RxD
0
P10
0
/AN
0
P10
1
/AN
1
P10
2
/AN
2
P10
3
/AN
3
P9
3
P9
4
P9
5
/ANEX0
P9
6
/ANEX1
P9
1
/TB1
IN
P9
2
/TB2
IN
P8
1
P8
0
P6
0
/CTS
0
/RTS
0
P6
4
/CTS
1
/RTS
1
/CLKS
1
P9
7
/AD
TRG
P4
4
/CS0
P5
0
/WRL/WR
P5
1
/WRH/BHE
P9
0
P7
2
/CLK
2
/TA1
OUT
P7
1
/RxD
2
/SCL/TA0
IN
(Note)
P7
0
/T
X
D
2
/SDA/TA0
OUT
(Note)
P7
5
/TA2
IN
P1
5
/D
13
P1
6
/D
14
P1
7
/D
15
P10
7
/AN
7
/KI
3
P10
6
/AN
6
/KI
2
P10
5
/AN
5
/KI
1
P10
4
/AN
4/
KI
0
Note: P7
0
and P7
1
are N channel open-drain output pin.
P8
2
/INT
0
P8
3
/INT
1
P8
5
/NMI
P8
4
/INT
2
P7
3
/CTS
2
/RTS
2
/TA1
IN
RESET
Figure 1.1.2. Pin configuration (top view)
Package: 100P6Q-A
PIN CONFIGURATION (top view)
M16C/30 Group
Description
4
Mitsubishi microcomputer
s
M16C / 30 Grou
p
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTE
R
Block Diagram
Figure 1.1.3 is a block diagram of the M16C/30 group.
AAAA
AAAA
Timer
Timer TA0 (16 bits)
Timer TA1 (16 bits)
Timer TA2 (16 bits)
Timer TB1 (16 bits)
Timer TB2 (16 bits)
Internal peripheral functions
Watchdog timer
(15 bits)
DMAC
(1 channel)
A-D converter
(10 bits X 8 channels
Expandable up to 10 channels)
UART/clock synchronous SI/O
(8 bits X 3 channels)
System clock generator
X
IN
-X
OUT
X
CIN
-X
COUT
M16C/60 series16-bit CPU core
I/O ports Port P0
8
Port P1
8
Port P2
8
Port P3
8
Port P4
8
Port P5
8
Port P6
8
8
R0LR0H
R1H R1L
R2
R3
A0
A1
FB
R0LR0H
R1H R1L
R2
R3
A0
A1
FB
Registers
ISP
USP
Stack pointer
Multiplier
788
Port P10
Port P9
Port P8
Port P7
AAAAAA
A
AAAA
A
A
AAAA
A
A
AAAA
A
AAAAAA
Memory
Port P8
5
ROM
(Note 1)
RAM
(Note 2)
Note 1: ROM size depends on MCU type.
Note 2: RAM size depends on MCU type.
SB FLG
PC
Program counter
Vector table
INTB
Flag register
Figure 1.1.3. Block diagram of M16C/30 group
Description
5
Mitsubishi microcomputer
s
M16C / 30 Grou
p
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTE
R
Item Performance
Number of basic instructions 91 instructions
Shortest instruction execution time 62.5ns(f(XIN)=16MHZ,
V
CC
=5V
)
100ns (f(XIN)=10MHZ, VCC=3V, with software one-wait)
Memory ROM (See the figure 1.1.4. ROM Expansion)
capacity RAM 2K to 3K bytes
I/O port P0 to P10 (except P85) 8 bits x 10, 7 bits x 1
Input port P851 bit x 1
Multifunction TA0, TA1, TA2 16 bits x 3
timer TB1, TB2 16 bits x 2
Serial I/O UART0, UART1, UART2 (UART or clock synchronous) x 3
A-D converter 10 bits x (8+2) channels
DMAC 1 channels (trigger: 14 sources)
Watchdog timer 15 bits x 1 (with prescaler)
Interrupt
16 internal and 5 external sources, 4 software sources, 7 levels
Clock generating circuit 2 built-in clock generation circuits
(built-in feedback resistor, and external ceramic or quartz oscillator)
Supply voltage 4.2V to 5.5V (f(XIN)=16MHZ, without software wait)
2.7V to 5.5V (f(XIN)=10MHZ with software one-wait)
Power consumption
25.5mW (f(XIN) = 10MHZ, VCC=3V with software one-wait)
I/O I/O withstand voltage 5V
characteristics
Output current 5mA
Memory expansion Available (to a maximum of 1M bytes)
Device configuration CMOS high performance silicon gate
Package 100-pin plastic mold QFP
Table 1.1.1. Performance outline of M16C/30 group
Performance Outline
Table 1.1.1 is a performance outline of M16C/30 group.
Description
6
Mitsubishi microcomputer
s
M16C / 30 Grou
p
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTE
R
Mitsubishi plans to release the following products in the M16C/30 group:
(1) Support for mask ROM version
(2) ROM capacity
(3) Package
100P6S-A : Plastic molded QFP
100P6Q-A : Plastic molded QFP
The M16C/30 group products currently supported are listed in Table 1.1.2.
Table 1.1.2. M16C/30 group
ROM Size
(Byte)
128K
96K
64K
32K
M30302M8-XXXFP/GP
M30302MA-XXXFP/GP
M30302MC-XXXFP/GP
Mask ROM version
M30302M4-XXXFP/GP
RAM capacity
ROM capacity Package type Remarks
Type No. June, 2002
M30302M4-XXXFP
2K byte
100P6S-A
M30302M4-XXXGP 100P6Q-A
M30302M8-XXXFP 64K byte 100P6S-A
Mask ROM version
M30302M8-XXXGP 100P6Q-A
3K byte
100P6S-A
100P6Q-A
100P6S-A
128K byte 100P6Q-A
32K byte
M30302MA-XXXFP
M30302MA-XXXGP
M30302MC-XXXFP
M30302MC-XXXGP
96K byte
**
**
**
**
**
**
*
*
**: Under development
* : New product
Figure 1.1.4. ROM expansion
Description
7
Mitsubishi microcomputer
s
M16C / 30 Grou
p
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTE
R
Package type:
FP : Package 100P6S-A
GP : 100P6Q-A
ROM No.
ROM capacity:
4 : 32K bytes
8 : 64K bytes
A : 96K bytes
C : 128K bytes
Memory type:
M : Mask ROM version
Type No. M 3 0 3 0 2 M 8 – X X X G P
M16C/30 Group
M16C Family
Shows RAM capacity, pin count, etc
(The value itself has no specific meaning)
Figure 1.1.5. Type No., memory size, and package
Pin Description
8
Mitsubishi microcomputer
s
M16C / 30 Grou
p
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTE
R
V
CC
, V
SS
CNV
SS
X
IN
X
OUT
BYTE
AV
CC
AV
SS
V
REF
P0
0
to P0
7
D
0
to D
7
P1
0
to P1
7
D
8
to D
15
P2
0
to P2
7
A
0
to A
7
A
0
/D
0
to
A
7
/D
7
A
0
A
1
/D
0
to A
7
/D
6
P3
0
to P3
7
A
8
to A
15
A
8
/D
7
,
A
9
to A
15
P4
0
to P4
7
Signal name
Power supply
input
CNV
SS
Reset input
Clock input
Clock output
External data
bus width
select input
Analog power
supply input
Reference
voltage input
I/O port P0
I/O port P1
I/O port P2
I/O port P3
I/O port P4
Supply 2.7V to 5.5 V to the V
CC
pin. Supply 0 V to the V
SS
pin.
Function
This pin switches between processor modes. Connect this pin to the
V
SS
pin when after a reset you want to start operation in single-chip
mode (memory expansion mode) or the V
CC
pin when starting
operation in microprocessor mode.
A “L” on this input resets the microcomputer.
These pins are provided for the main clock generating circuit.Connect
a ceramic resonator or crystal between the X
IN
and the X
OUT
pins. To
use an externally derived clock, input it to the X
IN
pin and leave the
X
OUT
pin open.
This pin selects the width of an external data bus. A 16-bit width is
selected when this input is “L”; an 8-bit width is selected when this
input is “H”. This input must be fixed to either “H” or “L”. Connect this
pin to the V
SS
pin when not using external data bus.
This pin is a power supply input for the A-D converter. Connect this
pin to V
CC
.
This pin is a power supply input for the A-D converter. Connect this
pin to V
SS
.
This pin is a reference voltage input for the A-D converter.
This is an 8-bit CMOS I/O port. It has an input/output port direction
register that allows the user to set each pin for input or output
individually. When used for input in single-chip mode, the port can be
set to have or not have a pull-up resistor in units of four bits by
software. In memory expansion and microprocessor modes, selection
of the internal pull-resistor is not available.
When set as a separate bus, these pins input and output data (D
0
–D
7
).
This is an 8-bit I/O port equivalent to P0.
When set as a separate bus, these pins input and output data
(D8–D15).
This is an 8-bit I/O port equivalent to P0.
These pins output 8 low-order address bits (A0–A7).
If the external bus is set as an 8-bit wide multiplexed bus, these pins
input and output data (D
0
–D
7
) and output 8 low-order address bits
(A
0
–A
7
) separated in time by multiplexing.
If the external bus is set as a 16-bit wide multiplexed bus, these pins
input and output data (D
0
–D
6
) and output address (A
1
–A
7
) separated
in time by multiplexing. They also output address (A
0
).
This is an 8-bit I/O port equivalent to P0.
These pins output 8 middle-order address bits (A
8
–A
15
).
If the external bus is set as a 16-bit wide multiplexed bus, these pins
input and output data (D
7
) and output address (A
8
) separated in time
by multiplexing. They also output address (A
9
–A
15
).
This is an 8-bit I/O port equivalent to P0.
Pin name
Input
Input
Input
Output
Input
Input
Input/output
Input/output
Input/output
Input/output
I/O type
Analog power
supply input
Input/output
Output
Input/output
Output
Input/output
Input/output
Output
Input/output
Output
Input/output
Output
Output
A
16
to A
19
,
CS
0
to CS
3
These pins output A
16
–A
19
and CS
0
–CS
3
signals. A
16
–A
19
are 4 high-
order address bits. CS
0
–CS
3
are chip select signals used to specify an
access space.
RESET
Pin Description
Pin Description
9
Mitsubishi microcomputer
s
M16C / 30 Grou
p
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTE
R
Pin Description
Signal name FunctionPin name I/O type
I/O port P5 Input/output
Input/output
Input/output
Input/output
Input/output
Input/output
Input
Input/output
Input/output
I/O port P6
I/O port P7
I/O port P8
I/O port P85
I/O port P9
I/O port P10
P50 to P57
P60 to P67
P70 to P77
P80 to P84,
P86,
P87,
P85
P90 to P97
P100 to P107
This is an 8-bit I/O port equivalent to P0. In single-chip mode, P57 in
this port outputs a divide-by-8 or divide-by-32 clock of XIN or a clock of
the same frequency as XCIN as selected by software.
Output
Output
Output
Output
Output
Input
Output
Input
This is an 8-bit I/O port equivalent to P0. When used for input in single-
chip, memory expansion, and microprocessor modes, the port can be
set to have or not have a pull-up resistor in units of four bits by
software. Pins in this port also function as UART0 and UART1 I/O pins
as selected by software.
This is an 8-bit I/O port equivalent to P6 (P70 and P71 are N channel
open-drain output). Pins in this port also function as timer A0–A2, or
UART2 I/O pins as selected by software.
This is an 8-bit I/O port equivalent to P6. Pins in this port also function
as, timer B1, B2 input pins, A-D converter extended input pins, or A-D
trigger input pins as selected by software.
This is an 8-bit I/O port equivalent to P6. Pins in this port also function
as A-D converter input pins as selected by software. Furthermore, P104
–P107 also function as input pins for the key input interrupt function.
WRL / WR,
WRH / BHE,
RD,
BCLK,
HLDA,
HOLD,
ALE,
RDY
Output WRL, WRH (WR and BHE), RD, BCLK, HLDA, and ALE
signals. WRL and WRH, and BHE and WR can be switched using
software control.
WRL, WRH, and RD selected
With a 16-bit external data bus, data is written to even addresses
when the WRL signal is “L” and to the odd addresses when the WRH
signal is “L”. Data is read when RD is “L”.
WR, BHE, and RD selected
Data is written when WR is “L”. Data is read when RD is “L”. Odd
addresses are accessed when BHE is “L”. Use this mode when using
an 8-bit external data bus.
While the input level at the HOLD pin is “L”, the microcomputer is
placed in the hold state. While in the hold state, HLDA outputs a “L”
level. ALE is used to latch the address. While the input level of the
RDY pin is “L”, the microcomputer is in the ready state.
P80 to P84, P86, and P87 are I/O ports with the same functions as P6.
Using software, they can be made to function as the I/O pins for the
input pins for external interrupts. P86 and P87 can be set using
software to function as the I/O pins for a sub clock generation
circuit. In this case, connect a quartz oscillator between P86 (XCOUT
pin) and P87 (XCIN pin). P85 is an input-only port that also functions
for NMI. The NMI interrupt is generated when the input at this pin
changes from “H” to “L”. The NMI function cannot be cancelled using
software. The pull-up cannot be set for this pin.
Mitsubishi microcomputer
s
M16C / 30 Grou
p
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTE
R
Memory
10
Operation of Functional Blocks
The M16C/30 group accommodates certain units in a single chip. These units include ROM and RAM to
store instructions and data and the central processing unit (CPU) to execute arithmetic/logic operations.
Also included are peripheral units such as timers, serial I/O, DMAC, A-D converter, and I/O ports.
The following explains each unit.
Memory
Figure 1.3.1 is a memory map of the M16C/30 group. The address space extends the 1M bytes from
address 0000016 to FFFFF16. From FFFFF16 down is ROM. For example, in the M30302MC-XXXGP,
there is 128K bytes of internal ROM from E000016 to FFFFF16. The vector table for fixed interrupts such as
_______
the reset and NMI are mapped to FFFDC16 to FFFFF16. The starting address of the interrupt routine is
stored here. The address of the vector table for timer interrupts, etc., can be set as desired using the
internal register (INTB). See the section on interrupts for details.
From 0040016 up is RAM. For example, in the M30302MC-XXXGP, 3K bytes of internal RAM is mapped to
the space from 0040016 to 00FFF16. In addition to storing data, the RAM also stores the stack used when
calling subroutines and when interrupts are generated.
The SFR area is mapped to 0000016 to 003FF16. This area accommodates the control registers for periph-
eral devices such as I/O ports, A-D converter, serial I/O, and timers, etc. Figures 1.6.1 to 1.6.3 are location
of peripheral unit control registers. Any part of the SFR area that is not occupied is reserved and cannot be
used for other purposes.
The special page vector table is mapped to FFE0016 to FFFDB16. If the starting addresses of subroutines
or the destination addresses of jumps are stored here, subroutine call instructions and jump instructions
can be used as 2-byte instructions, reducing the number of program steps.
In memory expansion mode and microprocessor mode, a part of the spaces are reserved and cannot be
used. For example, in the M30302MC-XXXGP, the following spaces cannot be used.
• The space between 0180016 and 03FFF16 (Memory expansion and microprocessor modes)
• The space between D000016 and DFFFF16 (Memory expansion mode)
Figure 1.3.1. Memory map
00000
16
YYYYY
16
FFFFF
16
00400
16
04000
16
XXXXX
16
D0000
16
AAAAAA
A
AAAA
A
A
AAAA
A
AAAAAA
External area
Internal ROM area
SFR area
For details, see Figures
1.6.1 to 1.6.3
Internal RAM area
Internal reserved
area (Note 1)
Internal reserved
area (Note 2)
FFE00
16
FFFDC
16
FFFFF
16
Note 1: During memory expansion and microprocessor modes, can not be used.
Note 2: In memory expansion mode, can not be used.
Undefined instruction
Overflow
BRK instruction
Address match
Single step
Watchdog timer
Reset
Special page
vector table
DBC
NMI
Address YYYYY
16
ROM size
32K bytes
E8000
16
F0000
16
E0000
16
96K bytes
64K bytes
128K bytes
F8000
16
2K bytes 00BFF
16
Address XXXXX
16
RAM size
3K bytes 00FFF
16
Mitsubishi microcomputer
s
M16C / 30 Grou
p
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTE
R
CPU
11
Central Processing Unit (CPU)
The CPU has a total of 13 registers shown in Figure 1.4.1. Seven of these registers (R0, R1, R2, R3, A0,
A1, and FB) come in two sets; therefore, these have two register banks.
(1) Data registers (R0, R1, R1H, R2, and R3)
Data registers (R0, R1, R2, and R3) are configured with 16 bits, and are used primarily for transfer and
arithmetic/logic operations.
Register R0 can be used as separate 8-bit data registers, R0H and R0L. Register R1 can be used as
separate 8-bit data registers, R1H and R1L. In some instructions, registers R2 and R0, as well as R3 and
R1 can use as 32-bit data registers (R2R0 or R3R1).
(2) Address registers (A0 and A1)
Address registers (A0 and A1) are configured with 16 bits, and have functions equivalent to those of data
registers. These registers can also be used for address register indirect addressing and address register
relative addressing.
In some instructions, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0).
AAAAAAA
AAAAAAA
HL
b15 b8 b7 b0
R0(Note)
AAAAAAA
HL
b15 b8 b7 b0
R1(Note)
R2(Note)
AAAAAAA
AAAAAAA
b15 b0
R3(Note)
AAAAAAA
AAAAAAA
b15 b0
A0(Note)
AAAAAAA
AAAAAAA
b15 b0
A1(Note)
AAAAAAA
AAAAAAA
b15 b0
FB(Note)
AAAAAAA
b15 b0
Data
registers
Address
registers
Frame base
registers
b15 b0
b15 b0
b15 b0
b15 b0
b0
b19
b0
b19
HL
Program counter
Interrupt table
register
User stack pointer
Interrupt stack
pointer
Static base
register
Flag register
PC
INTB
USP
ISP
SB
FLG
Note: These re
g
isters consist of two re
g
ister banks.
A
A
AA
AA
AA
AA
A
A
AAAAAAA
AAAAAAA
A
A
AA
AA
AA
AA
AA
AA
A
A
CDZSBOIU
IPL
Figure 1.4.1. Central processing unit register
Mitsubishi microcomputer
s
M16C / 30 Grou
p
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTE
R
CPU
12
(3) Frame base register (FB)
Frame base register (FB) is configured with 16 bits, and is used for FB relative addressing.
(4) Program counter (PC)
Program counter (PC) is configured with 20 bits, indicating the address of an instruction to be executed.
(5) Interrupt table register (INTB)
Interrupt table register (INTB) is configured with 20 bits, indicating the start address of an interrupt vector
table.
(6) Stack pointer (USP or ISP)
Stack pointer comes in two types: user stack pointer (USP) and interrupt stack pointer (ISP), each config-
ured with 16 bits.
Your desired type of stack pointer (USP or ISP) can be selected by a stack pointer select flag (U flag).
This flag is located at the position of bit 7 in the flag register (FLG).
(7) Static base register (SB)
Static base register (SB) is configured with 16 bits, and is used for SB relative addressing.
(8) Flag register (FLG)
Flag register (FLG) is configured with 11 bits, each bit is used as a flag. Figure 1.4.2 shows the flag
register (FLG). The following explains the function of each flag:
• Bit 0: Carry flag (C flag)
This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit.
• Bit 1: Debug flag (D flag)
This flag enables a single-step interrupt.
When this flag is “1”, a single-step interrupt is generated after instruction execution. This flag is
cleared to “0” when the interrupt is acknowledged.
• Bit 2: Zero flag (Z flag)
This flag is set to “1” when an arithmetic operation resulted in 0; otherwise, cleared to “0”.
• Bit 3: Sign flag (S flag)
This flag is set to
“1”
when an arithmetic operation resulted in a negative value; otherwise, cleared to
“0”
.
• Bit 4: Register bank select flag (B flag)
This flag chooses a register bank. Register bank 0 is selected when this flag is “0” ; register bank 1 is
selected when this flag is “1”.
• Bit 5: Overflow flag (O flag)
This flag is set to “1” when an arithmetic operation resulted in overflow; otherwise, cleared to “0”.
• Bit 6: Interrupt enable flag (I flag)
This flag enables a maskable interrupt.
An interrupt is disabled when this flag is “0”, and is enabled when this flag is “1”. This flag is cleared to
“0” when the interrupt is acknowledged.
Mitsubishi microcomputer
s
M16C / 30 Grou
p
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTE
R
CPU
13
• Bit 7: Stack pointer select flag (U flag)
Interrupt stack pointer (ISP) is selected when this flag is “0” ; user stack pointer (USP) is selected
when this flag is “1”.
This flag is cleared to “0” when a hardware interrupt is acknowledged or an INT instruction of software
interrupt Nos. 0 to 31 is executed.
• Bits 8 to 11: Reserved area
• Bits 12 to 14: Processor interrupt priority level (IPL)
Processor interrupt priority level (IPL) is configured with three bits, for specification of up to eight
processor interrupt priority levels from level 0 to level 7.
If a requested interrupt has priority greater than the processor interrupt priority level (IPL), the interrupt
is enabled.
• Bit 15: Reserved area
The C, Z, S, and O flags are changed when instructions are executed. See the software manual for
details.
Figure 1.4.2. Flag register (FLG)
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved area
Processor interrupt priority level
Reserved area
Flag register (FLG)
AA
AA
AA
AA
A
A
AA
AA
AAAAAAA
AAAAAAA
AA
AA
AA
AA
AA
AA
A
A
AA
AA
CDZSBOIU
IPL b0b15
Mitsubishi microcomputer
s
M16C / 30 Grou
p
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTE
R
Reset
14
Figure 1.5.2. Reset sequence
Reset
There are two kinds of resets; hardware and software. In both cases, operation is the same after the reset.
(See “Software Reset” for details of software resets.) This section explains on hardware resets.
When the supply voltage is in the range where operation is guaranteed, a reset is effected by holding the
reset pin level “L” (0.2VCC max.) for at least 20 cycles. When the reset pin level is then returned to the “H”
level while main clock is stable, the reset status is cancelled and program execution resumes from the
address in the reset vector table.
The RAM is undefined at power on. The initial value must therefore be set. When a reset signal is applied
while the CPU is writing a value to the RAM, the value may be set as unknown due to the termination of the
CPU access.
Figure 1.5.1 shows the example reset circuit. Figure 1.5.2 shows the reset sequence.
Figure 1.5.1. Example reset circuit
BCLK
Address
Address
Address
Microprocessor
mode BYTE = “H”
Microprocessor
mode BYTE = “L”
Content of reset vector
Single chip
mode
BCLK 24cycles
FFFFC16 FFFFD16 FFFFE16
Content of reset vector
FFFFC16 FFFFE16
Content of reset vector
FFFFE16
XIN
RESET
RD
WR
CS0
RD
WR
CS0
FFFFC16
More than 20 cycles are needed
RESET V
CC
0.8V
RESET
V
CC
0V
0V
5V
5V
4.0V
Example when V
CC
= 5V.More than 20 cycles of X
IN
are needed.
Mitsubishi microcomputer
s
M16C / 30 Grou
p
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTE
R
Reset
15
____________
Table 1.5.1 shows the statuses of the other pins while the RESET pin level is “L”. Figures 1.5.3 and 1.5.4
show the internal status of the microcomputer immediately after the reset is cancelled.
____________
Table 1.5.1. Pin status when RESET pin level is “L”
Status
CNV
SS
= V
CC
CNV
SS
= V
SS
BYTE = V
SS
BYTE = V
CC
Pin name
P0
P1
P2, P3, P4
0
to P4
3
P4
4
P4
5
to P4
7
P5
0
P5
1
P5
2
P5
3
P5
4
P5
5
P5
6
P5
7
P6, P7, P8
0
to P8
4
,
P8
6
, P8
7
, P9, P10
Input port (floating)
Input port (floating)
Input port (floating)
Input port (floating)
Input port (floating)
Input port (floating)
Input port (floating)
Input port (floating)
Input port (floating)
Input port (floating)
Input port (floating)
Input port (floating)
Input port (floating)
Input port (floating)
Data input (floating)
Data input (floating)
Address output (undefined)
BCLK output
ALE output (“L” level is output)
CS0 output (“H” level is output)
WR output (“H” level is output)
RD output (“H” level is output)
RDY input (floating)
Input port (floating)
BCLK output
BHE output (undefined)
HLDA output (The output value
depends on the input to the
HOLD pin)
HOLD input (floating)
Data input (floating)
Address output (undefined)
CS0 output (“H” level is output)
Input port (floating)
(pull-up resistor is on)
Input port (floating) Input port (floating)
RDY input (floating)
ALE output (“L” level is output)
HOLD input (floating)
HLDA output (The output value
depends on the input to the
HOLD pin)
RD output (“H” level is output)
BHE output (undefined)
WR output (“H” level is output)
Input port (floating)
(pull-up resistor is on)
Mitsubishi microcomputer
s
M16C / 30 Grou
p
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTE
R
Reset
16
Figure 1.5.3. Device's internal status after a reset is cleared
x : Nothing is mapped to this bit
? : Undefined
The content of other registers are undefined when the microcomputer is reset. The initial values must therefore be set.
The RAM is undefined at power on. The initial values must therefore be set. When a reset signal is applied while the
CPU is writing a value to the RAM, the value may be set as unknown due to the termination of the CPU access.
Note 1: When the V
CC
level is applied to the CNV
SS
pin, it is 03
16
at a reset.
Note 2: “00
16
” is read out when set bit 7 (SDDS) of the UART2 special mode register ( address 0377
16
) to “1”.
(1) (000416)···Processor mode register 0 (Note 1) 0016
(3) (000616)···System clock control register 0 10000100
(4) (000716)···System clock control register 1 00010000
(5) (000816)···Chip select control register 00000010
(6) (000916)···Address match interrupt enable register 00
(7) Protect register (000A16)··· 000
(001516)··· 0016
(001616)··· 0 0 0 0
(11) (002C16)···DMA0 control register 00000?00
(000F16)···Watchdog timer control register 00?0 ????
(8)
(9) (001016)···Address match interrupt register 0 0016
(001116)··· 0016
(001216)··· 0 0 0 0
(001416)···Address match interrupt register 1 0016
(10)
(004A16)···
Bus collision detection interrupt
control register 0 0 0?
(12)
(14) (004D16)···Key input interrupt control register ? 0 0 0
(004B16)···DMA0 interrupt control register ? 0 0 0
(13)
(15) A-D conversion interrupt control register (004E16)··· ? 0 0 0
(2) (000516)···Processor mode register 1 000000
(16) UART2 transmit interrupt control register (004F16)··· ? 0 0 0
(17) UART2 receive interrupt control register (005016)··· ? 0 0 0
(18) UART0 transmit interrupt control register (005116)··· ? 0 0 0
(19) UART0 receive interrupt control register (005216)··· ? 0 0 0
(20) UART1 transmit interrupt control register (005316)··· ? 0 0 0
(30) Interrupt cause select register 0016
(035F16)···
(21) UART1 receive interrupt control register (005416)··· ? 0 0 0
(22) Timer A0 interrupt control register (005516)··· ? 0 0 0
(23) Timer A1 interrupt control register (005616)··· ? 0 0 0
(24) Timer A2 interrupt control register (005716)··· ? 0 0 0
(25) Timer B1 interrupt control register (005B16)··· ? 0 0 0
(26) Timer B2 interrupt control register (005C16)··· ? 0 0 0
(27) INT0 interrupt control register (005D16)··· ?00000
(28) INT1 interrupt control register (005E16)··· ?00000
(29) INT2 interrupt control register (005F16)··· ?00000
(037D16)···UART2 transmit/receive control register 1 01000000
(36)
(037816)··· 0016
UART2 transmit/receive mode register(34)
(037C16)···UART2 transmit/receive control register 0 00000001
(35)
(33) UART2 special mode register (037716)··· 0016
(32) UART2 special mode register 2 (037616)··· 0016
(31) UART2 special mode register 3 (Note 2) (037516)··· ?
(038316)···Trigger select flag(40) 0016
(038416)···Up-down flag(41) 0016
(038216)···One-shot start flag(39) 0000 000
Count start flag (038016)··· 0016(37)
0(038116)···Clock prescaler reset flag(38)
Mitsubishi microcomputer
s
M16C / 30 Grou
p
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTE
R
Reset
17
(0396
16
)···Timer A0 mode register(42) 00
16
(0397
16
)···Timer A1 mode register(43) 00
16
(0398
16
)···Timer A2 mode register(44) 00
16
(039C
16
)···Timer B1 mode register(45) 00? 0000
(039D
16
)···Timer B2 mode register(46) 00? 0000
(03A0
16
)···UART0 transmit/receive mode register(47) 00
16
(03A4
16
)···UART0 transmit/receive control register 0(48) 000 10000
(03A5
16
)···UART0 transmit/receive control register 1(49) 000 00100
(03A8
16
)···UART1 transmit/receive mode register(50) 00
16
(03AC
16
)···UART1 transmit/receive control register 0(51) 000 10000
(03AD
16
)···UART1 transmit/receive control register 1(52) 000 00100
(03B0
16
)···UART transmit/receive control register 2(53) 00 00000
x : Nothing is mapped to this bit
? : Undefined
The content of other registers are undefined when the microcomputer is reset. The initial values must therefore be set.
The RAM is undefined at power on. The initial values must therefore be set. When a reset signal is applied while the
CPU is writing a value to the RAM, the value may be set as unknown due to the termination of the CPU access.
Note: When the V
CC
level is applied to the CNV
SS
pin, it is 02
16
at a reset.
(03D7
16
)···A-D control register 1 00
16
(57)
(03E2
16
)···Port P0 direction register
(58) 00
16
(03E3
16
)···Port P1 direction register
(59) 00
16
(03E6
16
)···Port P2 direction register
(60) 00
16
(03E7
16
)···Port P3 direction register
(61) 00
16
(56) (03D6
16
)···A-D control register 0 000 0???0
(03D4
16
)···A-D control register 2(55) 0
0000
(54) (03B8
16
)···DMA0 cause select register 00
16
(03EA
16
)···Port P4 direction register(62) 00
16
(03EB
16
)···Port P5 direction register(63) 00
16
(03EE
16
)···Port P6 direction register(64) 00
16
(03EF
16
)···Port P7 direction register(65) 00
16
(03F3
16
)···Port P9 direction register(67) 00
16
(03F6
16
)···Port P10 direction register(68) 00
16
(03FC
16
)···Pull-up control register 0(69) 00
16
(03FD
16
)···Pull-up control register 1(Note)(70) 00
16
(03F2
16
)···Port P8 direction register(66) 00 00000
Address registers (A0/A1)(74) 0000
16
Frame base register (FB)(75) 0000
16
Interrupt table register (INTB)(76) 00000
16
User stack pointer (USP)(77) 0000
16
Interrupt stack pointer (ISP)(78) 0000
16
(03FE
16
)···Pull-up control register 2 00
16
(71)
(73) Data registers (R0/R1/R2/R3) 0000
16
Port control register 00
16
(72) (03FF
16
)···
Static base register (SB) 0000
16
(79)
Flag register (FLG) 0000
16
(80)
???
Figure 1.5.4. Device's internal status after a reset is cleared
SFR
18
Mitsubishi microcomputer
s
M16C / 30 Grou
p
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTE
R
Figure 1.6.1. Location of peripheral unit control registers (1)
0000
16
0001
16
0002
16
0003
16
0004
16
0005
16
0006
16
0007
16
0008
16
0009
16
000A
16
000B
16
000C
16
000D
16
000E
16
000F
16
0010
16
0011
16
0012
16
0013
16
0014
16
0015
16
0016
16
0017
16
0018
16
0019
16
001A
16
001B
16
001C
16
001D
16
001E
16
001F
16
0020
16
0021
16
0022
16
0023
16
0024
16
0025
16
0026
16
0027
16
0028
16
0029
16
002A
16
002B
16
002C
16
002D
16
002E
16
002F
16
0030
16
0031
16
0032
16
0033
16
0034
16
0035
16
0036
16
0037
16
0038
16
0039
16
003A
16
003B
16
003C
16
003D
16
003E
16
003F
16
0040
16
0041
16
0042
16
0043
16
0044
16
0045
16
0046
16
0047
16
0048
16
0049
16
004A
16
004B
16
004C
16
004D
16
004E
16
004F
16
0050
16
0051
16
0052
16
0053
16
0054
16
0055
16
0056
16
0057
16
0058
16
0059
16
005A
16
005B
16
005C
16
005D
16
005E
16
005F
16
0060
16
0061
16
0062
16
0063
16
0064
16
0065
16
032A
16
032B
16
032C
16
032D
16
032E
16
032F
16
0330
16
0331
16
0332
16
0333
16
0334
16
0335
16
0336
16
0337
16
0338
16
0339
16
033A
16
033B
16
033C
16
033D
16
033E
16
033F
16
DMA0 control register (DM0CON)
DMA0 source pointer (SAR0)
DMA0 transfer counter (TCR0)
Watchdog timer start register (WDTS)
Watchdog timer control register (WDC)
Processor mode register 0 (PM0)
Address match interrupt register 0 (RMAD0)
Address match interrupt register 1 (RMAD1)
Chip select control register (CSR)
System clock control register 0 (CM0)
System clock control register 1 (CM1)
Address match interrupt enable register (AIER)
Protect register (PRCR)
Processor mode register 1(PM1)
DMA0 destination pointer (DAR0)
Timer A1 interrupt control register (TA1IC)
UART0 transmit interrupt control register (S0TIC)
Timer A0 interrupt control register (TA0IC)
Timer A2 interrupt control register (TA2IC)
UART0 receive interrupt control register (S0RIC)
UART1 transmit interrupt control register (S1TIC)
UART1 receive interrupt control register (S1RIC)
DMA0 interrupt control register (DM0IC)
Key input interrupt control register (KUPIC)
A-D conversion interrupt control register (ADIC)
Bus collision detection interrupt control register (BCNIC)
UART2 transmit interrupt control register (S2TIC)
UART2 receive interrupt control register (S2RIC)
INT1 interrupt control register (INT1IC)
Timer B2 interrupt control register (TB2IC)
INT2 interrupt control register (INT2IC)
INT0 interrupt control register (INT0IC)
Timer B1 interrupt control register (TB1IC)
Note : Locations in the SFR area where nothing is allocated are reserved areas. Do not access these areas for read or write.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTE
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SFR
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Figure 1.6.2. Location of peripheral unit control registers (2)
0380
16
0381
16
0382
16
0383
16
0384
16
0385
16
0386
16
0387
16
0388
16
0389
16
038A
16
038B
16
038C
16
038D
16
038E
16
038F
16
0390
16
0391
16
0392
16
0393
16
0394
16
0395
16
0396
16
0397
16
0398
16
0399
16
039A
16
039B
16
039C
16
039D
16
039E
16
039F
16
03A0
16
03A1
16
03A2
16
03A3
16
03A4
16
03A5
16
03A6
16
03A7
16
03A8
16
03A9
16
03AA
16
03AB
16
03AC
16
03AD
16
03AE
16
03AF
16
03B0
16
03B1
16
03B2
16
03B3
16
03B4
16
03B5
16
03B6
16
03B7
16
03B8
16
03B9
16
03BA
16
03BB
16
03BC
16
03BD
16
03BE
16
03BF
16
0340
16
0341
16
0342
16
0343
16
0344
16
0345
16
0346
16
0347
16
0348
16
0349
16
034A
16
034B
16
034C
16
034D
16
034E
16
034F
16
0350
16
0351
16
0352
16
0353
16
0354
16
0355
16
0356
16
0357
16
0358
16
0359
16
035A
16
035B
16
035C
16
035D
16
035E
16
035F
16
0360
16
0361
16
0362
16
0363
16
0364
16
0365
16
0366
16
0367
16
0368
16
0369
16
036A
16
036B
16
036C
16
036D
16
036E
16
036F
16
0370
16
0371
16
0372
16
0373
16
0374
16
0375
16
0376
16
0377
16
0378
16
0379
16
037A
16
037B
16
037C
16
037D
16
037E
16
037F
16
Interrupt cause select register (IFSR)
Timer A0 register (TA0)
Timer A1 register (TA1)
Timer A2 register (TA2)
Timer B1 register (TB1)
Timer B2 register (TB2)
Count start flag (TABSR)
One-shot start flag (ONSF)
Timer A0 mode register (TA0MR)
Timer A1 mode register (TA1MR)
Timer A2 mode register (TA2MR)
Timer B1 mode register (TB1MR)
Timer B2 mode register (TB2MR)
Up-down flag (UDF)
Trigger select register (TRGSR)
Clock prescaler reset flag (CPSRF)
UART0 transmit/receive mode register (U0MR)
UART0 transmit buffer register (U0TB)
UART0 receive buffer register (U0RB)
UART1 transmit/receive mode register (U1MR)
UART1 transmit buffer register (U1TB)
UART1 receive buffer register (U1RB)
UART0 bit rate generator (U0BRG)
UART0 transmit/receive control register 0 (U0C0)
UART0 transmit/receive control register 1 (U0C1)
UART1 bit rate generator (U1BRG)
UART1 transmit/receive control register 0 (U1C0)
UART1 transmit/receive control register 1 (U1C1)
DMA0 request cause select register (DM0SL)
UART2 special mode register (U2SMR)
UART2 receive buffer register (U2RB)
UART2 transmit buffer register (U2TB)
UART2 transmit/receive control register 0 (U2C0)
UART2 transmit/receive mode register (U2MR)
UART2 transmit/receive control register 1 (U2C1)
UART2 bit rate generator (U2BRG)
UART transmit/receive control register 2 (UCON)
UART2 special mode register 2(U2SMR2)
Note : Locations in the SFR area where nothing is allocated are reserved areas. Do not access these areas for
read or write.
UART2 special mode register 3(U2SMR3)
SFR
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Figure 1.6.3. Location of peripheral unit control registers (3)
03C016
03C116
03C216
03C316
03C416
03C516
03C616
03C716
03C816
03C916
03CA16
03CB16
03CC16
03CD16
03CE16
03CF16
03D016
03D116
03D216
03D316
03D416
03D516
03D616
03D716
03D816
03D916
03DA16
03DB16
03DC16
03DD16
03DE16
03DF16
03E016
03E116
03E216
03E316
03E416
03E516
03E616
03E716
03E816
03E916
03EA16
03EB16
03EC16
03ED16
03EE16
03EF16
03F016
03F116
03F216
03F316
03F416
03F516
03F616
03F716
03F816
03F916
03FA16
03FB16
03FC16
03FD16
03FE16
03FF16
A-D register 7 (AD7)
A-D register 0 (AD0)
A-D register 1 (AD1)
A-D register 2 (AD2)
A-D register 3 (AD3)
A-D register 4 (AD4)
A-D register 5 (AD5)
A-D register 6 (AD6)
Port P0 register (P0)
Port P0 direction register (PD0)
Port P1 register (P1)
Port P1 direction register (PD1)
Port P2 register (P2)
Port P2 direction register (PD2)
Port P3 register (P3)
Port P3 direction register (PD3)
Port P4 register (P4)
Port P4 direction register (PD4)
Port P5 register (P5)
Port P5 direction register (PD5)
Port P6 register (P6)
Port P6 direction register (PD6)
Port P7 register (P7)
Port P7 direction register (PD7)
Port P8 register (P8)
Port P8 direction register (PD8)
Port P9 register (P9)
Port P9 direction register (PD9)
Port P10 register (P10)
Port P10 direction register (PD10)
Pull-up control register 0 (PUR0)
Pull-up control register 1 (PUR1)
Pull-up control register 2 (PUR2)
A-D control register 0 (ADCON0)
A-D control register 1 (ADCON1)
A-D control register 2 (ADCON2)
Port control register (PCR)
Note : Locations in the SFR area where nothing is allocated are reserved
areas. Do not access these areas for read or write.
Software Reset
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Software Reset
Writing “1” to bit 3 of the processor mode register 0 (address 000416) applies a (software) reset to the
microcomputer. A software reset has the same effect as a hardware reset. The contents of internal RAM
are preserved.
Software Reset
Processor Mode
(1) Types of Processor Mode
One of three processor modes can be selected: single-chip mode, memory expansion mode, and micro-
processor mode. The functions of some pins, the memory map, and the access space differ according to
the selected processor mode.
• Single-chip mode
In single-chip mode, only internal memory space (SFR, internal RAM, and internal ROM) can be
accessed. However, after the reset has been released and the operation of shifting from the micropro-
cessor mode has started (“H” applied to the CNVSS pin), the internal ROM area cannot be accessed
even if the CPU shifts to the single-chip mode.
Ports P0 to P10 can be used as programmable I/O ports or as I/O ports for the internal peripheral
functions.
• Memory expansion mode
In memory expansion mode, external memory can be accessed in addition to the internal memory
space (SFR, internal RAM, and internal ROM). However, after the reset has been released and the
operation of shifting from the microprocessor mode has started (“H” applied to the CNVSS pin), the
internal ROM area cannot be accessed even if the CPU shifts to the memory expansion mode.
In this mode, some of the pins function as the address bus, the data bus, and as control signals. The
number of pins assigned to these functions depends on the bus and register settings. (See “Bus
Settings” for details.)
• Microprocessor mode
In microprocessor mode, the SFR, internal RAM, and external memory space can be accessed. The
internal ROM area cannot be accessed.
In this mode, some of the pins function as the address bus, the data bus, and as control signals. The
number of pins assigned to these functions depends on the bus width and register settings. (See “Bus
Settings” for details.)
(2) Setting Processor Modes
The processor mode is set using the CNVSS pin and the processor mode bits (bits 1 and 0 at address
000416). Do not set the processor mode bits to “102”.
Regardless of the level of the CNVSS pin, changing the processor mode bits selects the mode. Therefore,
never change the processor mode bits when changing the contents of other bits. Do not change the
processor mode bits simultaneously with other bits when changing the processor mode bits “012” or
“112”. Change the processor mode bits after changing the other bits. Also do not attempt to shift to or from
the microprocessor mode within the program stored in the internal ROM area.
• Applying VSS to CNVSS pin
The microcomputer begins operation in single-chip mode after being reset. Memory expansion mode
is selected by writing “012” to the processor mode bits.
• Applying VCC to CNVSS pin
The microcomputer starts to operate in microprocessor mode after being reset.
Processor Mode
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Figure 1.7.1. Processor mode register 0 and 1
Processor mode register 0 (Note 1)
Symbol Address When reset
PM0 000416 0016 (Note 2)
Bit name FunctionBit symbol WR
b7 b6 b5 b4 b3 b2 b1 b0
0 0: Single-chip mode
0 1: Memory expansion mode
1 0: Must not be set
1 1: Microprocessor mode
b1 b0
PM03
PM01
PM00
Processor mode bit
PM02
R/W mode select bit
0 : RD,BHE,WR
1 : RD,WRH,WRL
Software reset bit
The device is reset when this bit is set
to “1”. The value of this bit is “0” when
read.
PM04 0 0 : Multiplexed bus is not used
0 1 : Allocated to CS2 space
1 0 : Allocated to CS1 space
1 1 : Allocated to entire space (Note4)
b5 b4
Multiplexed bus space
select bit
PM05
PM06
PM07
Port P40 to P43 function
select bit (Note 3) 0 : Address output
1 : Port function
(Address is not output)
BCLK output disable bit 0 : BCLK is output
1 : BCLK is not output
(Pin is left floating)
Note 1: Set bit 1 of the protect register (address 000A16) to “1” when writing new
values to this register.
Note 2: If the VCC voltage is applied to the CNVSS, the value of this register when
reset is 0316. (PM00 and PM01 both are set to “1”.)
Note 3: Valid in microprocessor and memory expansion modes.
Note 4: If the entire space is of multiplexed bus in memory expansion mode, choose an 8-
bit width.The processor operates using the separate bus after reset is revoked, so the entire
space multiplexed bus cannot be chosen in microprocessor mode.
P31 to P37 become a port if the entire space multiplexed bus is chosen, so only 256 bytes can
be used in each chip select.
Processor mode register 1 (Note)
Symbol Address When reset
PM1 000516 00000XX02
Bit name FunctionBit symbol WR
b7 b6 b5 b4 b3 b2 b1 b0
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns
out to be
indeterminate.
Reserved bit Must always be set to “0”
0
Note: Set bit 1 of the protect register (address 000A16) to “1” when writing new values to this register.
AA
AA
A
A
AA
AA
A
A
AA
AA
A
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
AA
A
A
PM17 Wait bit 0 : No wait state
1 : Wait state inserted
AA
AA
A
A
AA
A
A
Reserved bit Must always be set to “0”
0
AA
00
AA
AA
A
A
Reserved bit Must always be set to “0”
AA
A
Reserved bit Must always be set to “0”
Reserved bit Must always be set to “0”
0
Figure 1.7.1 shows the processor mode register 0 and 1.
Figure 1.7.2 shows the memory maps in each processor modes.
Processor Mode
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Single-chip mode
SFR area
Internal
RAM area
Inhibited
Internal
ROM area
Microprocessor mode
SFR area
Internal
RAM area
External
area
Internally
reserved area
00000
16
00400
16
XXXXX
16
YYYYY
16
FFFFF
16
D0000
16
External area : Accessing this area allows the user to
access a device connected externally
to the microcomputer.
04000
16
Memory expansion mode
SFR area
Internal
RAM area
External
area
Internal
ROM area
Internally
reserved area
Internally
reserved area
Address YYYYY
16
2K bytes 00BFF
16
00FFF
16
Address XXXXX
16
ROM size
3K bytes
RAM size
32K bytes
E8000
16
F0000
16
E0000
16
96K bytes
64K bytes
128K bytes
F8000
16
Figure 1.7.2. Memory maps in each processor modes
Bus Settings
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Bus Settings
The BYTE pin and bits 4 to 6 of the processor mode register 0 (address 000416) are used to change the bus settings.
Table 1.8.1 shows the factors used to change the bus settings.
Bus setting Switching factor
Switching external address bus width Bit 6 of processor mode register 0
Switching external data bus width BYTE pin
Switching between separate and multiplex bus Bits 4 and 5 of processor mode register 0
(1) Selecting external address bus width
The address bus width for external output in the 1M bytes of address space can be set to 16 bits (64K
bytes address space) or 20 bits (1M bytes address space). When bit 6 of the processor mode register 0
is set to “1”, the external address bus width is set to 16 bits, and P2 and P3 become part of the address
bus. P40 to P43 can be used as programmable I/O ports. When bit 6 of processor mode register 0 is set
to “0”, the external address bus width is set to 20 bits, and P2, P3, and P40 to P43 become part of the
address bus.
(2) Selecting external data bus width
The external data bus width can be set to 8 or 16 bits. (Note, however, that only the separate bus can be
set.) When the BYTE pin is “L”, the bus width is set to 16 bits; when “H”, it is set to 8 bits. (The internal bus
width is permanently set to 16 bits.) While operating, fix the BYTE pin either to “H” or to “L”.
(3) Selecting separate/multiplex bus
The bus format can be set to multiplex or separate bus using bits 4 and 5 of the processor mode register 0.
• Separate bus
In this mode, the data and address are input and output separately. The data bus can be set using the
BYTE pin to be 8 or 16 bits. When the BYTE pin is “H”, the data bus is set to 8 bits and P0 functions as
the data bus and P1 as a programmable I/O port. When the BYTE pin is “L”, the data bus is set to 16
bits and P0 and P1 are both used for the data bus.
When the separate bus is used for access, a software wait can be selected.
• Multiplex bus
In this mode, data and address I/O are time multiplexed. With the BYTE pin = “H”, the 8 bits from D0 to
D7 are multiplexed with A0 to A7.
With the BYTE pin = “L”, the 8 bits from D0 to D7 are multiplexed with A1 to A8. D8 to D15 are not
multiplexed. In this case, the external devices connected to the multiplexed bus are mapped to the
microcomputer’s even addresses (every 2nd address). To access these external devices, access the
even addresses as bytes.
The ALE signal latches the address. It is output from P56.
Before using the multiplex bus for access, be sure to insert a software wait.
If the entire space is of multiplexed bus in memory expansion mode, choose an 8-bit width.
The processor operates using the separate bus after reset is revoked, so the entire space multiplexed
bus cannot be chosen in microprocessor mode.
P31 to P37 become a port if the entire space multiplexed bus is chosen, so only 256 bytes can be used
in each chip select.
Table 1.8.1. Factors for switching bus settings
Bus Settings
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P5
6
I/O port ALE ALE ALE ALE ALE
P5
7
I/O port RDY RDY RDY RDY RDY
P0
0
to P0
7
I/O port Data bus Data bus Data bus Data bus I/O port
Either CS1 or CS2 is for
multiplexed bus and others
are for separate bus (separate bus)
multiplexed
bus for the
entire
space
Single-chip
mode Memory expansion mode/microprocessor modes Memory
expansion mode
Data bus width
BYTE pin level
Port P4
0
to P4
3
function select bit = 0
“01”, “10” “00” “11” (Note 1)
8 bit
“H”
8 bits
“H”
16 bits
“L”
8 bits
“H” 16 bits
“L”
Note 1: If the entire space is of multiplexed bus in memory expansion mode, choose an 8-bit width.
The processor operates using the separate bus after reset is revoked, so the entire space multiplexed bus cannot be
chosen in microprocessor mode.
P3
1
to P3
7
become a port if the entire space multiplexed bus is chosen, so only 256 bytes can be used
in each chip select.
Note 2: Address bus when in separate bus mode.
Processor mode
Multiplexed bus
space select bit
CS (chip select) or programmable I/O port
(For details, refer to “Bus control”)
Outputs RD, WRL, WRH, and BCLK or RD, BHE, WR, and BCLK
(For details, refer to “Bus control”)
Port P4
0
to P4
3
function select bit = 1
P1
0
to P1
7
I/O port I/O port Data bus I/O port Data bus I/O port
P2
1
to P2
7
I/O port
Address bus Address bus
Address bus Address bus Address bus
/data bus(Note 2) /data bus(Note 2)
/data bus
P2
0
I/O port
Address bus
Address bus Address bus Address bus Address bus
/data bus(Note 2)
/data bus
P3
0
I/O port
Address bus
Address bus Address bus Address bus A
8
/D
7
/data bus(Note 2)
P3
1
to P3
7
I/O port Address bus Address bus Address bus Address bus I/O port
P4
0
to P4
3
I/O port I/O port I/O port I/O port I/O port I/O port
P4
0
to P4
3
I/O port Address bus Address bus Address bus Address bus I/O port
P4
4
to P4
7
I/O port
P5
0
to P5
3
I/O port
P5
4
I/O port HLDA HLDA HLDA HLDA HLDA
P5
5
I/O port HOLD HOLD HOLD HOLD HOLD
Table 1.8.2. Pin functions for each processor mode
Bus Control
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Bus Control
The following explains the signals required for accessing external devices and software waits. The signals
required for accessing the external devices are valid when the processor mode is set to memory expansion
mode and microprocessor mode. The software waits are valid in all processor modes.
(1) Address bus/data bus
The address bus consists of the 20 pins A0 to A19 for accessing the 1M bytes of address space.
The data bus consists of the pins for data I/O. When the BYTE pin is “H”, the 8 ports D0 to D7 function
as the data bus. When BYTE is “L”, the 16 ports D0 to D15 function as the data bus.
When a change is made from single-chip mode to memory expansion mode, the value of the address
bus is undefined until external memory is accessed.
(2) Chip select signal
The chip select signal is output using the same pins as P44 to P47. Bits 0 to 3 of the chip select control
register (address 000816) set each pin to function as a port or to output the chip select signal. The chip
select control register is valid in memory expansion mode and microprocessor mode. In single-chip
mode, P44 to P47 function as programmable I/O ports regardless of the value in the chip select control
register. _______
In microprocessor mode, only CS0 outputs the chip select signal after the reset state has been can-
_______ _______
celled. CS1 to CS3 function as input ports. Figure 1.9.1 shows the chip select control register.
The chip select signal can be used to split the external area into as many as four blocks. Tables 1.9.1
shows the external memory areas specified using the chip select signal.
Processor mode
Memory expansion mode
Chip select signal
CS0 CS1 CS2 CS3
3000016 to
CFFFF16
(640K bytes)
Microprocessor mode
2800016 to
2FFFF16
(32K bytes)
0800016 to
27FFF16
(128K bytes)
0400016 to
07FFF16
(16K bytes)
3000016 to
FFFFF16
(832K bytes)
Table 1.9.1. External areas specified by the chip select signals
Bus Control
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W
FunctionBit symbol Bit name
Chip select control register Symbol Address When reset
CSR 000816 0116
R
b7 b6 b5 b4 b3 b2 b1 b0
CS1
CS0
CS3
CS2
CS0 output enable bit
CS1 output enable bit
CS2 output enable bit
CS3 output enable bit
CS1W
CS0W
CS3W
CS2W
CS0 wait bit
CS1 wait bit
CS2 wait bit
CS3 wait bit
0 : Chip select output disabled
(Normal port pin)
1 : Chip select output enabled
0 : Wait state inserted
1 : No wait state
A
A
AA
AA
A
AA
A
AA
A
A
AA
AA
A
AA
A
A
AA
AA
A
AA
A
AA
Figure 1.9.1. Chip select control register
The timing of the chip select signal changing to “L”(active) is synchronized with the address bus. But the
timing of the chip select signal changing to “H” depends on the area which will be accessed in the next
cycle. Figure 1.9.2 shows the output example of the address bus and chip select signal.
Bus Control
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Figure 1.9.2. Output Examples about Address Bus and Chip Select Signal (Separated Bus without
Wait)
Example 1) After access the external area, both the address signal and
the chip select signal change concurrently in the next cycle.
In this example, after access to the external area(i), an access to the area
indicated by the other chip select signal(j) will occur in the next cycle. In
this case, both the address bus and the chip select signal change between
the two cycles.
Note : These examples show the address bus and chip select signal within the successive two cycles.
According to the combination of these examples, the chip select can be elongated to over 2cycles.
BCLK
Read/Write
signal
Data bus
Address bus
Chip select
(CS i)
Access to the
External Area( i )
Chip select
(CS j)
Access to the Other
External Area( j )
Address
Data
Example 2) After access the external area, only the chip select signal
changes in the next cycle (the address bus does not change).
In this example, an access to the internal ROM or the internal RAM in the
next cycle will occur, after access to the external area. In this case, the
chip select signal changes between the two cycles, but the address does
not change.
Example 4) After access the external area, either the address signal and
the chip select signal do not change in the next cycle.
In this example, any access to any area does not occur in the next cycle
(either instruction prefetch does not occur). In this case,either the address
bus and chip select signal do not change between the two cycles.
Example 3) After access the external area, only the address bus changes
in the next cycle (the chip select signal does not change).
In this example, after access to the external area(i), an access to the area
indicated by the same chip select signal(i) will occur in the next cycle. In
this case, the address bus changes between the two cycles, but the chip
select signal does not change.
BCLK
Access to the
External Area Internal ROM/RAM
Access
Read/Write
signal
Data bus
Address bus
Chip select
Address
Data
BCLK
Access to the
External Area No Access
Read/Write
signal
Data bus
Address bus
Chip select
Address
Data
BCLK
Access to the
External Area( i ) Access to the Same
External Area( i )
Read/Write
signal
Data bus
Address bus
Chip select
(CS i)
Address
Data
Bus Control
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_____ ______ ________
Table 1.9.4. Operation of RD, WR, and BHE signals
Status of external data bus
RD BHEWR
HLL
LHL
HLH
LHH
Write 1 byte of data to odd address
Read 1 byte of data from odd address
Write 1 byte of data to even address
Read 1 byte of data from even address
Data bus width A0
H
H
L
L
HLLL
LHLL
HL H / L
LH H / L
8-bit
(BYTE = “H”)
Write data to both even and odd addresses
Read data from both even and odd addresses
Write 1 byte of data
Read 1 byte of data
16-bit
(BYTE = “L”)
Not used
Not used
Status of external data bus
Read data
Write 1 byte of data to even address
Write 1 byte of data to odd address
Write data to both even and odd addresses
WRHWRLRD
Data bus width
16-bit
(BYTE = “L”) H
H
H
H
L
H
L
H
H
L
L
L
_____ ________ _________
Table 1.9.3. Operation of RD, WRL, and WRH signals
(3) Read/write signals
With a 16-bit data bus (BYTE pin =“L”), bit 2 of the processor mode register 0 (address 000416) select the
_____ ________ ______ _____ ________ _________
combinations of RD, BHE, and WR signals or RD, WRL, and WRH signals. With an 8-bit data bus (BYTE
_____ ______ _______
pin = “H”), use the combination of RD, WR, and BHE signals. (Set bit 2 of the processor mode register 0
(address 000416) to “0”.) Tables 1.9.3 and 1.9.4 show the operation of these signals.
_____ ______ ________
After a reset has been cancelled, the combination of RD, WR, and BHE signals is automatically selected.
_____ _________ _________
When switching to the RD, WRL, and WRH combination, do not write to external memory until bit 2 of the
processor mode register 0 (address 000416) has been set (Note).
Note: Before attempting to change the contents of the processor mode register 0, set bit 1 of the protect
register (address 000A16) to “1”.
(4) ALE signal
The ALE signal latches the address when accessing the multiplex bus space. Latch the address when the
ALE signal falls.
When BYTE pin = “H” When BYTE pin = “L”
ALE
Address Data (Note 1)
Address (Note 2)
D
0
/A
0
to D
7
/A
7
A
8
to A
19
ALE
Address Data (Note 1)
Address
D
0
/A
1
to D
7
/A
8
A
9
to A
19
Address
A
0
Note 1: Floating when reading.
Note 2: When multiplexed bus for the entire space is selected, these are I/O ports.
Figure 1.9.3. ALE signal and address/data bus
Bus Control
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_____ ________
Figure 1.9.4. Example of RD signal extended by RDY signal
BCLK
RD
CS
i
(i=0 to 3)
RDY
tsu(RDY - BCLK)
AAAA
BCLK
RD
CS
i
(i=0 to 3)
RDY
tsu(RDY - BCLK)
AAAAAA
AAAAAA
AA
AA
In an instance of separate bus
In an instance of multiplexed bus
Accept timing of RDY signal
: Wait using RDY signal
: Wait using software
Accept timing of RDY signal
________
Note: The RDY signal cannot be received immediately prior to a software wait.
Table 1.9.5. Microcomputer status in wait state (Note)
Item Status
Oscillation On
___ _____
R/W signal, address bus, data bus, CS ________
Maintain status when RDY signal received
__________
ALE signal, HLDA, programmable I/O ports
Internal peripheral circuits On
________
(5) The RDY signal
________
RDY is a signal that facilitates access to an external device that requires long access time. As shown in
________
Figure 1.9.4, if an “L” is being input to the RDY at the BCLK falling edge, the bus turns to the wait state. If
________
an “H” is being input to the RDY pin at the BCLK falling edge, the bus cancels the wait state. Table 1.9.5
shows the state of the microcomputer with the bus in the wait state, and Figure 1.9.4 shows an example
____ ________
in which the RD signal is prolonged by the RDY signal.
________
The RDY signal is valid when accessing the external area during the bus cycle in which bits 4 to 7 of the
________
chip select control register (address 000816) are set to “0”. The RDY signal is invalid when setting “1” to
________
all bits 4 to 7 of the chip select control register (address 000816), but the RDY pin should be treated as
properly as in non-using.
Bus Control
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Table 1.9.6. Microcomputer status in hold state
Item Status
Oscillation ON
___ _____ _______
R/W signal, address bus, data bus, CS, BHE Floating
Programmable I/O ports P0, P1, P2, P3, P4, P5 Floating
P6, P7, P8, P9, P10 Maintains status when hold signal is received
__________
HLDA Output “L”
Internal peripheral circuits ON (but watchdog timer stops)
ALE signal Undefined
__________
HOLD > DMAC > CPU
(6) Hold signal
The hold signal is used to transfer the bus privileges from the CPU to the external circuits. Inputting “L” to
__________
the HOLD pin places the microcomputer in the hold state at the end of the current bus access. This status
__________ __________
is maintained and “L” is output from the HLDA pin as long as “L” is input to the HOLD pin. Table 1.9.6
shows the microcomputer status in the hold state.
__________
Bus-using priorities are given to HOLD, DMAC, and CPU in order of decreasing precedence.
Figure 1.9.5. Bus-using priorities
(7) External bus status when the internal area is accessed
Table 1.9.7 shows the external bus status when the internal area is accessed.
Table 1.9.7. External bus status when the internal area is accessed
Item SFR accessed Internal ROM/RAM accessed
Address bus Address output Maintain status before accessed
address of external area
Data bus When read Floating Floating
When write Output data Undefined
RD, WR, WRL, WRH RD, WR, WRL, WRH output Output “H”
BHE BHE output Maintain status before accessed
status of external area
CS Output “H” Output “H”
ALE Output “L” Output “L”
Bus Control
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(9) Software wait
A software wait can be inserted by setting the wait bit (bit 7) of the processor mode register 1 (address
0005
16
) (Note) and bits 4 to 7 of the chip select control register (address 0008
16
).
A software wait is inserted in the internal ROM/RAM area and in the external memory area by setting the
wait bit of the processor mode register 1. When set to “0”, each bus cycle is executed in one BCLK cycle.
When set to “1”, each bus cycle is executed in two or three BCLK cycles. After the microcomputer has been
reset, this bit defaults to “0”. When
set to “1”, a wait is applied to all memory areas (two or three BCLK
cycles), regardless of the contents of bits 4 to 7 of the chip select control register
. Set this bit after referring
to the recommended operating conditions (main clock input oscillation frequency) of the electric character-
________
istics.
However, when the user is using the RDY signal, the relevant bit in the chip select control register’s
bits 4 to 7 must be set to “0”.
When the wait bit of the processor mode register 1 is “0”, software waits can be set independently for
each of the 4 areas selected using the chip select signal. Bits 4 to 7 of the chip select control register
_______ _______
correspond to chip selects CS0 to CS3. When one of these bits is set to “1”, the bus cycle is executed in
one BCLK cycle. When set to “0”, the bus cycle is executed in two or three BCLK cycles. These bits
default to “0” after the microcomputer has been reset.
The SFR area is always accessed in two BCLK cycles regardless of the setting of these control bits. Also,
insert a software wait if using the multiplex bus to access the external memory area.
Table 1.9.8 shows the software wait and bus cycles. Figure 1.9.6 shows example of bus timing when
using software waits.
Note: Before attempting to change the contents of the processor mode register 1, set bit 1 of the protect
register (address 000A16) to “1”.
Area Bus status Wait bit Bits 4 to 7 of chip select
control register Bus cycle
Invalid1 2 BCLK cycles
External
memory
area
Separate bus 0 1 1 BCLK cycle
Separate bus 0 0 2 BCLK cycles
Separate bus 1 0 (Note) 2 BCLK cycles
Multiplex bus 0 0 3 BCLK cycles
Multiplex bus 1 3 BCLK cycles0 (Note)
SFR
Internal
ROM/RAM 0 Invalid 1 BCLK cycle
Invalid Invalid 2 BCLK cycles
Note: When using the RDY signal, always set to “0”.
Table 1.9.8. Software waits and bus cycles
(8) BCLK output
The user can choose the BCLK output by use of bit 7 of processor mode register 0 (000416) (Note).
When set to “1”, the output floating.
Note: Before attempting to change the contents of the processor mode register 0, set bit 1 of the protect
register (address 000A16) to “1”.
Bus Control
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Figure 1.9.6. Typical bus timings using software wait
Output Input
Address Address
< Separate bus (with wait) >
BCLK
Read signal
Write signal
Data bus
BCLK
Read signal
Address bus/
Data bus
Chip select (Note 2)
Address
Address
Data output
Address
Address
Input
ALE
< Multiplexed bus >
Write signal
BCLK
Read signal
Write signal
Address bus (Note 2) Address Address
Bus cycle (Note 1)
< Separate bus (no wait) >
Output
Data bus
Input
Note 1: These example timing charts indicate bus cycle length.
After this bus cycle sometimes come read and write cycles in succession.
Note 2: The address bus and chip select may be extended depending on the CPU status
such as that of the instruction queue buffer.
Bus cycle (Note 1)
Bus cycle (Note 1) Bus cycle (Note 1)
Bus cycle (Note 1) Bus cycle (Note 1)
Address bus (Note 2)
Address bus (Note 2)
Chip select (Note 2)
Chip select (Note 2)
Clock Generating Circuit
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Figure 1.10.2. Examples of sub-clock
Table 1.10.1. Main clock and sub-clock generating circuits
Clock Generating Circuit
The clock generating circuit contains two oscillator circuits that supply the operating clock sources to the
CPU and internal peripheral units.
Example of oscillator circuit
Figure 1.10.1 shows some examples of the main clock circuit, one using an oscillator connected to the
circuit, and the other one using an externally derived clock for input. Figure 1.10.2 shows some examples
of sub-clock circuits, one using an oscillator connected to the circuit, and the other one using an externally
derived clock for input. Circuit constants in Figures 1.10.1 and 1.10.2 vary with each oscillator used. Use
the values recommended by the manufacturer of your oscillator.
Figure 1.10.1. Examples of main clock
Main clock generating circuit Sub-clock generating circuit
Use of clock • CPU’s operating clock source • CPU’s operating clock source
• Internal peripheral units’ • Timer A/B’s count clock
operating clock source source
Usable oscillator Ceramic or crystal oscillator Crystal oscillator
Pins to connect oscillator XIN, XOUT XCIN, XCOUT
Oscillation stop/restart function Available Available
Oscillator status immediately after reset
Oscillating Stopped
Other Externally derived clock can be input
Microcomputer
(Built-in feedback resistor)
X
IN
X
OUT
Externally derived clock
Open
Vcc
Vss
Microcomputer
(Built-in feedback resistor)
X
IN
X
OUT
R
d
C
IN
C
OUT
(Note)
Note: Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive
capacity setting. Use the value recommended by the maker of the oscillator.
When the oscillation drive capacity is set to low, check that oscillation is stable. Also, if the oscillator manufacturer's
data sheet specifies that a feedback resistor be added external to the chip, insert a feedback resistor between XIN
and XOUT following the instruction.
Microcomputer
(Built-in feedback resistor)
XCIN XCOUT
Externally derived clock
Open
Vcc
Vss
Note: Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive
capacity setting. Use the value recommended by the maker of the oscillator.
When the oscillation drive capacity is set to low, check that oscillation is stable. Also, if the oscillator manufacturer's
data sheet specifies that a feedback resistor be added external to the chip, insert a feedback resistor between XCIN
and XCOUT following the instruction.
Microcomputer
(Built-in feedback resistor)
XCIN XCOUT
(Note)
CCIN CCOUT
RCd
Clock Generating Circuit
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Clock Control
Figure 1.10.3 shows the block diagram of the clock generating circuit.
Sub clock
CM04
f
C32
CM0i : Bit i at address 0006
16
CM1i : Bit i at address 0007
16
WDCi : Bit i at address 000F
16
X
CIN
CM10 “1”
Write signal
1/32
X
COUT
Q
S
R
WAIT instruction
X
OUT
Main clock
CM05
f
C
CM02
f
1
QS
R
NMI
Interrupt request
level judgment
output
RESET
Software reset f
C
CM07=0
CM07=1
f
AD
AAA
AAA
Divider
ad
1/2 1/2 1/2 1/2
CM06=0
CM17,CM16=00
CM06=0
CM17,CM16=01
CM06=0
CM17,CM16=10
CM06=1
CM06=0
CM17,CM16=11
d
a
Details of divider
X
IN
f
8
f
32
c
b
b
1/2
c
f
32SIO2
f
8SIO2
f
1SIO2
BCLK
Figure 1.10.3. Clock generating circuit
Clock Generating Circuit
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The following paragraphs describes the clocks generated by the clock generating circuit.
(1) Main clock
The main clock is generated by the main clock oscillation circuit. After a reset, the clock is divided by 8 to
the BCLK. The clock can be stopped using the main clock stop bit (bit 5 at address 000616). Stopping the
clock, after switching the operating clock source of CPU to the sub-clock, reduces the power dissipation.
After the oscillation of the main clock oscillation circuit has stabilized, the drive capacity of the main clock
oscillation circuit can be reduced using the XIN-XOUT drive capacity select bit (bit 5 at address 000716).
Reducing the drive capacity of the main clock oscillation circuit reduces the power dissipation. This bit
changes to “1” when shifting from high-speed/medium-speed mode to stop mode and at a reset. When
shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is re-
tained.
(2) Sub-clock
The sub-clock is generated by the sub-clock oscillation circuit. No sub-clock is generated after a reset.
After oscillation is started using the port XC select bit (bit 4 at address 000616), the sub-clock can be
selected as the BCLK by using the system clock select bit (bit 7 at address 000616). However, be sure
that the sub-clock oscillation has fully stabilized before switching.
After the oscillation of the sub-clock oscillation circuit has stabilized, the drive capacity of the sub-clock
oscillation circuit can be reduced using the XCIN-XCOUT drive capacity select bit (bit 3 at address 000616).
Reducing the drive capacity of the sub-clock oscillation circuit reduces the power dissipation. This bit
changes to “1” when shifting to stop mode and at a reset.
When the XCIN/XCOUT is used, set ports P86 and P87 as the input ports without pull-up.
(3) BCLK
The BCLK is the clock that drives the CPU, and is fC or the clock is derived by dividing the main clock by
1, 2, 4, 8, or 16. The BCLK is derived by dividing the main clock by 8 after a reset. The BCLK signal can
be output from BCLK pin by the BCLK output disable bit (bit 7 at address 000416) in the memory expan-
sion and the microprocessor modes.
The main clock division select bit 0(bit 6 at address 000616) changes to “1” when shifting from high-
speed/medium-speed to stop mode and at reset. When shifting from low-speed/low power dissipation
mode to stop mode, the value before stop mode is retained.
(4) Peripheral function clock(f1, f8, f32, f1SIO2, f8SIO2,f32SIO2,fAD)
The clock for the peripheral devices is derived from the main clock or by dividing it by 1, 8, or 32. The
peripheral function clock is stopped by stopping the main clock or by setting the WAIT peripheral function
clock stop bit (bit 2 at 000616) to “1” and then executing a WAIT instruction.
(5) fC32
This clock is derived by dividing the sub-clock by 32. It is used for the timer A and timer B counts.
(6) fC
This clock has the same frequency as the sub-clock. It is used for the BCLK and for the watchdog timer.
Clock Generating Circuit
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Figure 1.10.4 shows the system clock control registers 0 and 1.
Figure 1.10.4. Clock control registers 0 and 1
System clock control register 0 (Note 1)
Symbol Address When reset
CM0 000616 4816
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
0 0 : I/O port P5
7
0 1 : f
C
output
1 0 : f
8
output
1 1 : f
32
output
b1 b0
CM07
CM05
CM04
CM03
CM01
CM02
CM00
CM06
Clock output function
select bit
(Valid only in single-chip
mode)
WAIT peripheral function
clock stop bit 0 : Do not stop peripheral function clock in wait mode
1 : Stop peripheral function clock in wait mode (Note 8)
X
CIN
-X
COUT
drive capacity
select bit (Note 2) 0 : LOW
1 : HIGH
Port X
C
select bit 0 : I/O port
1 : X
CIN
-X
COUT
generation (Note 9)
Main clock (X
IN
-X
OUT
)
stop bit (Note 3, 4, 5) 0 : On
1 : Off
Main clock division select
bit 0 (Note 7) 0 : CM16 and CM17 valid
1 : Division by 8 mode
System clock select bit
(Note 6) 0 : X
IN
, X
OUT
1 : X
CIN
, X
COUT
Note 1: Set bit 0 of the protect register (address 000A16) to “1” before writing to this register.
Note 2: Changes to “1” when shiffing to stop mode and at a reset.
Note 3: When entering low power dissipation mode, main clock stops by using this bit. To stop the main clock, when the
sub clock oscillation is stable, set system clock select bit (CM07) to “1” before setting this bit to “1”.
Note 4: When inputting external clock, only clock oscillation buffer is stopped and clock input is acceptable.
Note 5: If this bit is set to “1”, XOUT turns “H”. The built-in feedback resistor remains being connected, so XIN turns
pulled up to XOUT (“H”) via the feedback resistor.
Note 6: Set port XC select bit (CM04) to “1” and stabilize the sub-clock oscillating before setting this bit from “0” to “1”.
Do not write to both bits at the same time. And also, set the main clock stop bit (CM05) to “0” and stabilize the
main clock oscillating before setting this bit from “1” to “0”.
Note 7: This bit changes to “1” when shifting from high-speed/medium-speed mode to stop mode and at a reset. When
shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained.
Note 8: fC32 is not included. Do not set to “1” when using low-speed or low power dissipation mode.
Note 9: When the XCIN/XCOUT is used, set ports P86 and P87 as the input ports without pull-up.
System clock control register 1 (Note 1)
Symbol Address When reset
CM1 000716 2016
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
CM10 All clock stop control bit
(Note4) 0 : Clock on
1 : All clocks off (stop mode)
Note 1: Set bit 0 of the protect register (address 000A16) to
“1” before writing to this register.
Note 2: This bit changes to “1” when shifting from high-speed/medium-speed mode to stop mode and at a reset. When
shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained.
Note 3: Can be selected when bit 6 of the system clock control register 0 (address 000616) is
“0”. If
“1”, division mode is
fixed at 8.
Note 4: If this bit is set to “1”, XOUT turns “H”, and the built-in feedback resistor is cut off. XCIN and XCOUT turn high-
impedance state.
CM15 X
IN
-X
OUT
drive capacity
select bit (Note 2) 0 : LOW
1 : HIGH
WR
WR
CM16
CM17
Reserved bit Must always be set to
“0”
Reserved bit Must always be set to
“0”
Main clock division
select bit 1 (Note 3) 0 0 : No division mode
0 1 : Division by 2 mode
1 0 : Division by 4 mode
1 1 : Division by 16 mode
b7 b6
00
Reserved bit Must always be set to
“0”
Reserved bit Must always be set to
“0”
00
AA
A
AA
AA
A
A
AA
AA
A
A
AA
AA
A
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
AA
A
A
AA
AA
A
A
AA
A
AA
AA
A
A
Clock Generating Circuit
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Pin Memory expansion mode Single-chip mode
Microprocessor mode
_______ _______
Address bus, data bus, CS0 to CS3,
Retains status before stop mode
________
BHE
_____ ______ ________ _________
RD, WR, WRL, WRH “H”
__________
HLDA, BCLK “H”
ALE “H”
Port
Retains status before stop mode
Retains status before stop mode
CLKOUT When fc selected Valid only in single-chip mode “H”
When f8, f32 selected Valid only in single-chip mode
Retains status before stop mode
Table 1.10.2. Port status during stop mode
Clock Output
In single-chip mode, the clock output function select bits (bits 0 and 1 at address 000616) enable f8, f32, or
fc to be output from the P57/CLKOUT pin. When the WAIT peripheral function clock stop bit (bit 2 at address
000616) is set to “1”, the output of f8 and f32 stops when a WAIT instruction is executed.
Stop Mode
Writing “1” to the all-clock stop control bit (bit 0 at address 000716) stops all oscillation and the microcom-
puter enters stop mode. In stop mode, the content of the internal RAM is retained provided that VCC re-
mains above 2V.
Because the oscillation , BCLK, f1 to f32, f1SIO2 to f32SIO2, fC, fC32, and fAD stops in stop mode, peripheral
functions such as the A-D converter and watchdog timer do not function. However, timer A and timer B
operate provided that the event counter mode is set to an external pulse, and UARTi(i = 0 to 2) functions
provided an external clock is selected. Table 1.10.2 shows the status of the ports in stop mode.
Stop mode is cancelled by a hardware reset or an interrupt. If an interrupt is to be used to cancel stop mode,
that interrupt must first have been enabled, and the priority level of the interrupt which is not used to cancel
must have been changed to 0. If returning by an interrupt, that interrupt routine is executed. If only a
_______
hardware reset or an NMI interrupt is used to cancel stop mode, change the priority level of all interrupt to
0, then shift to stop mode.
When shifting from high-speed/medium-speed mode to stop mode and at a reset, the main clock division
select bit 0 (bit 6 at address 000616) is set to “1”. When shifting from low-speed/low power dissipation mode
to stop mode, the value before stop mode is retained.
Wait Mode
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Table 1.10.3. Port status during wait mode
Pin Memory expansion mode Single-chip mode
Microprocessor mode
_______ _______
Address bus, data bus, CS0 to CS3,
Retains status before wait mode
________
BHE
_____ ______ ________ _________
RD, WR, WRL, WRH “H”
__________
HLDA,BCLK “H”
ALE “H”
Port
Retains status before wait mode Retains status before wait mode
CLKOUT When fC selected Valid only in single-chip mode Does not stop
When f8, f32 selected Valid only in single-chip mode Does not stop when the WAIT
peripheral function clock stop
bit is “0”.
When the WAIT peripheral
function clock stop bit is “1”,
the status immediately prior
to entering wait mode is main-
tained.
Wait Mode
When a WAIT instruction is executed, the BCLK stops and the microcomputer enters the wait mode. In this
mode, oscillation continues but the BCLK and watchdog timer stop. Writing “1” to the WAIT peripheral
function clock stop bit and executing a WAIT instruction stops the clock being supplied to the internal
peripheral functions, allowing power dissipation to be reduced. However, peripheral function clock fC32
does not stop so that the peripherals using fC32 do not contribute to the power saving. When the MCU
running in low-speed or low power dissipation mode, do not enter WAIT mode with this bit set to “1”. Table
1.10.3 shows the status of the ports in wait mode.
Wait mode is cancelled by a hardware reset or an interrupt. If an interrupt is used to cancel wait mode, that
interrupt must first have been enabled, and the priority level of the interrupt which is not used to cancel must
have been changed to 0. If returning by an interrupt, the clock in which the WAIT instruction executed is set
to BCLK by the microcomputer, and the action is resumed from the interrupt routine. If only a hardware
_______
reset or an NMI interrupt is used to cancel wait mode, change the priority level of all interrupt to 0,then shift
to wait mode.
Status Transition of BCLK
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01000Invalid Division by 2 mode
10000Invalid Division by 4 mode
Invalid Invalid 0 1 0 Invalid Division by 8 mode
11000Invalid Division by 16 mode
00000Invalid No-division mode
Invalid Invalid 1 Invalid 0 1 Low-speed mode
Invalid Invalid 1 Invalid 1 1 Low power dissipation mode
Status Transition of BCLK
Power dissipation can be reduced and low-voltage operation achieved by changing the count source for
BCLK. Table 1.10.4 shows the operating modes corresponding to the settings of system clock control
registers 0 and 1.
When reset, the device starts in division by 8 mode. The main clock division select bit 0(bit 6 at address
000616) changes to “1” when shifting from high-speed/medium-speed to stop mode and at a reset. When
shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained.
The following shows the operational modes of BCLK.
(1) Division by 2 mode
The main clock is divided by 2 to obtain the BCLK.
(2) Division by 4 mode
The main clock is divided by 4 to obtain the BCLK.
(3) Division by 8 mode
The main clock is divided by 8 to obtain the BCLK. When reset, the device starts operating from this
mode. Before the user can go from this mode to no division mode, division by 2 mode, or division by 4
mode, the main clock must be oscillating stably. When going to low-speed or lower power consumption
mode, make sure the sub-clock is oscillating stably.
(4) Division by 16 mode
The main clock is divided by 16 to obtain the BCLK.
(5) No-division mode
The main clock is divided by 1 to obtain the BCLK.
(6) Low-speed mode
fC is used as the BCLK. Note that oscillation of both the main and sub-clocks must have stabilized before
transferring from this mode to another or vice versa. At least 2 to 3 seconds are required after the sub-
clock starts. Therefore, the program must be written to wait until this clock has stabilized immediately
after powering up and after stop mode is cancelled.
(7) Low power dissipation mode
fC is the BCLK and the main clock is stopped.
Note : Before the count source for BCLK can be changed from XIN to XCIN or vice versa, the clock to which
the count source is going to be switched must be oscillating stably. Allow a wait time in software for
the oscillation to stabilize before switching over the clock.
CM17 CM16 CM07 CM06 CM05 CM04
Operating mode of BCLK
Table 1.10.4. Operating modes dictated by settings of system clock control registers 0 and 1
CM1i : Bit i of the address 000716
CM0i : Bit i of the address 000616
Power control
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Power control
The following is a description of the three available power control modes:
Modes
Power control is available in three modes.
(a) Normal operation mode
• High-speed mode
Divide-by-1 frequency of the main clock becomes the BCLK. The CPU operates with the BCLK.
Each peripheral function operates according to its assigned clock.
• Medium-speed mode
Divide-by-2, divide-by-4, divide-by-8, or divide-by-16 frequency of the main clock becomes the
BCLK. The CPU operates with the BCLK. Each peripheral function operates according to its as-
signed clock.
• Low-speed mode
fC becomes the BCLK. The CPU operates according to the fC clock. The fC clock is supplied by the
subclock. Each peripheral function operates according to its assigned clock.
• Low power dissipation mode
The main clock operating in low-speed mode is stopped. The CPU operates according to the fC
clock. The fC clock is supplied by the subclock. The only peripheral functions that operate are those
with the subclock selected as the count source.
(b) Wait mode
The CPU operation is stopped. The oscillators do not stop.
(c) Stop mode
All oscillators stop. The CPU and all built-in peripheral functions stop. This mode, among the three
modes listed here, is the most effective in decreasing power consumption.
Figure 1.10.5 is the state transition diagram of the above modes.
Power control
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Figure 1.10.5. State transition diagram of Power control mode
Transition of stop mode, wait mode
Transition of normal mode
Reset
Medium-speed mode
(divided-by-8 mode)
Interrupt
CM10 = “1”
All oscillators stopped CPU operation stopped
Medium-speed mode
(divided-by-8 mode)
BCLK : f(X
IN
)/8
CM07 = “0” CM06 = “1”
Low-speed mode
High-speed mode
Main clock is oscillating
Sub clock is stopped
Main clock is oscillating
Sub clock is stopped
Main clock is stopped
Sub clock is oscillating
Main clock is oscillating
Sub clock is oscillating
Low power dissipation mode
High-speed/medium-
speed mode
Low-speed/low power
dissipation mode
Normal mode
Stop mode
Stop mode
Stop mode
All oscillators stopped
All oscillators stopped
Wait mode
Wait mode
Wait mode
CPU operation stopped
CPU operation stopped
Interrupt
WAIT
instruction
Interrupt
WAIT
instruction
Interrupt
WAIT
instruction
CM10 = “1”
Interrupt
Interrupt
CM10 = “1”
BCLK : f(X
IN
)/2
CM07 = “0” CM06 = “0”
CM17 = “0” CM16 = “1”
Medium-speed mode
(divided-by-2 mode)
BCLK : f(X
IN
)/16
CM07 = “0” CM06 = “0”
CM17 = “1” CM16 = “1”
Medium-speed mode
(divided-by-16 mode)
BCLK : f(X
IN
)/4
CM07 = “0” CM06 = “0”
CM17 = “1” CM16 = “0”
Medium-speed mode
(divided-by-4 mode)
BCLK : f(X
IN
)
CM07 = “0” CM06 = “0”
CM17 = “0” CM16 = “0” BCLK : f(X
IN
)/8
Medium-speed mode
(divided-by-8 mode)
CM07 = “0”
CM06 = “1”
High-speed mode
BCLK : f(X
IN
)/2
CM07 = “0” CM06 = “0”
CM17 = “0” CM16 = “1”
Medium-speed mode
(divided-by-2 mode)
BCLK : f(X
IN
)/16
CM07 = “0” CM06 = “0”
CM17 = “1” CM16 = “1”
Medium-speed mode
(divided-by-16 mode)
BCLK : f(X
IN
)/4
CM07 = “0” CM06 = “0”
CM17 = “1” CM16 = “0”
Medium-speed mode
(divided-by-4 mode)
BCLK : f(X
IN
)
CM07 = “0” CM06 = “0”
CM17 = “0” CM16 = “0”
BCLK : f(X
CIN
)
CM07 = “1”
BCLK : f(X
CIN
)
CM07 = “1”
Main clock is oscillating
Sub clock is oscillating
CM07 = “0”
(Note 1, 3)
CM07 = “0” (Note 1)
CM06 = “1”
CM04 = “0”
CM07 = “1”
(Note 2)
CM07 = “0” (Note 1)
CM06 = “0” (Note 3)
CM04 = “1”
CM07 = “1” (Note 2)
CM05 = “1”
CM05 = “0” CM05 = “1”
CM04 = “0” CM04 = “1”
CM06 = “0”
(Notes 1,3)
CM06 = “1”
CM04 = “0” CM04 = “1”
(Notes 1, 3)
Note 1: Switch clock after oscillation of main clock is sufficiently stable.
Note 2: Switch clock after oscillation of sub clock is sufficiently stable.
Note 3: Change CM06 after changing CM17 and CM16.
Note 4: Transit in accordance with arrow.
(Refer to the following for the transition of normal mode.)
Protection
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Protection
The protection function is provided so that the values in important registers cannot be changed in the event
that the program runs out of control. Figure 1.10.6 shows the protect register. The values in the processor
mode register 0 (address 000416), processor mode register 1 (address 000516), system clock control reg-
ister 0 (address 000616), system clock control register 1 (address 000716), port P9 direction register (ad-
dress 03F316) can only be changed when the respective bit in the protect register is set to “1”. Therefore,
important outputs can be allocated to port P9.
If, after “1” (write-enabled) has been written to the port P9 direction register write-enable bit (bit 2 at address
000A16), a value is written to any address, the bit automatically reverts to “0” (write-inhibited). However, the
system clock control registers 0 and 1 write-enable bit (bit 0 at 000A16) and processor mode register 0 and
1 write-enable bit (bit 1 at 000A16) do not automatically return to “0” after a value has been written to an
address. The program must therefore be written to return these bits to “0”.
Protect register
Symbol Address When reset
PRCR 000A16 XXXXX0002
Bit nameBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
0 : Write-inhibited
1 : Write-enabled
PRC1
PRC0
PRC2
Enables writing to processor mode
registers 0 and 1 (addresses 000416
and 000516)
Function
0 : Write-inhibited
1 : Write-enabled
Enables writing to system clock
control registers 0 and 1 (addresses
000616 and 000716)
Enables writing to port P9 direction
register (address 03F316) (Note)0 : Write-inhibited
1 : Write-enabled
WR
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be
indeterminate.
Note: Writing a value to an address after “1” is written to this bit returns the bit
to “0” . Other bits do not automatically return to “0” and they must therefore
be reset by the program.
A
A
A
A
A
A
A
A
Figure 1.10.6. Protect register
Interrupt
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• Maskable interrupt : An interrupt which can be enabled (disabled) by the interrupt enable flag
(I flag) or whose interrupt priority can be changed by priority level.
• Non-maskable interrupt : An interrupt which cannot be enabled (disabled) by the interrupt enable flag
(I flag) or whose interrupt priority cannot be changed by priority level.
Figure 1.11.1. Classification of interrupts
Interrupt
Software
Hardware
Special
Peripheral I/O (Note)
Undefined instruction (UND instruction)
Overflow (INTO instruction)
BRK instruction
INT instruction
Reset
_______
NMI
________
DBC
Watchdog timer
Single step
Address matched
Note: Peripheral I/O interrupts are generated by the peripheral functions built into the microcomputer system.
Overview of Interrupt
Type of Interrupts
Figure 1.11.1 lists the types of interrupts.
Interrupt
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Software Interrupts
A software interrupt occurs when executing certain instructions. Software interrupts are non-maskable
interrupts.
• Undefined instruction interrupt
An undefined instruction interrupt occurs when executing the UND instruction.
• Overflow interrupt
An overflow interrupt occurs when executing the INTO instruction with the overflow flag (O flag) set to
“1”. The following are instructions whose O flag changes by arithmetic:
ABS, ADC, ADCF, ADD, CMP, DIV, DIVU, DIVX, NEG, RMPA, SBB, SHA, SUB
• BRK interrupt
A BRK interrupt occurs when executing the BRK instruction.
• INT interrupt
An INT interrupt occurs when specifying one of software interrupt numbers 0 through 63 and execut-
ing the INT instruction. Software interrupt numbers 0 through 31 are assigned to peripheral I/O inter-
rupts, so executing the INT instruction allows executing the same interrupt routine that a peripheral I/
O interrupt does.
The stack pointer (SP) used for the INT interrupt is dependent on which software interrupt number is
involved.
So far as software interrupt numbers 0 through 31 are concerned, the microcomputer saves the stack
pointer assignment flag (U flag) when it accepts an interrupt request. If change the U flag to “0” and
select the interrupt stack pointer (ISP), and then execute an interrupt sequence. When returning from
the interrupt routine, the U flag is returned to the state it was before the acceptance of interrupt re-
quest. So far as software numbers 32 through 63 are concerned, the stack pointer does not make a
shift.
Interrupt
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Hardware Interrupts
Hardware interrupts are classified into two types — special interrupts and peripheral I/O interrupts.
(1) Special interrupts
Special interrupts are non-maskable interrupts.
• Reset ____________
Reset occurs if an “L” is input to the RESET pin.
_______
• NMI interrupt
_______ _______
An NMI interrupt occurs if an “L” is input to the NMI pin.
________
• DBC interrupt
This interrupt is exclusively for the debugger, do not use it in other circumstances.
• Watchdog timer interrupt
Generated by the watchdog timer.
• Single-step interrupt
This interrupt is exclusively for the debugger, do not use it in other circumstances. With the debug
flag (D flag) set to “1”, a single-step interrupt occurs after one instruction is executed.
• Address match interrupt
An address match interrupt occurs immediately before the instruction held in the address indicated by
the address match interrupt register is executed with the address match interrupt enable bit set to “1”.
If an address other than the first address of the instruction in the address match interrupt register is set,
no address match interrupt occurs.
(2) Peripheral I/O interrupts
A peripheral I/O interrupt is generated by one of built-in peripheral functions. Built-in peripheral func-
tions are dependent on classes of products, so the interrupt factors too are dependent on classes of
products. The interrupt vector table is the same as the one for software interrupt numbers 0 through
31 the INT instruction uses. Peripheral I/O interrupts are maskable interrupts.
• Bus collision detection interrupt
This is an interrupt that the serial I/O bus collision detection generates.
• DMA0 interrupt
This is an interrupts that DMA generates.
• Key-input interrupt ___
A key-input interrupt occurs if an “L” is input to the KI pin.
• A-D conversion interrupt
This is an interrupt that the A-D converter generates.
• UART0, UART1, UART2/NACK transmission interrupt
These are interrupts that the serial I/O transmission generates.
• UART0, UART1, UART2/ACK reception interrupt
These are interrupts that the serial I/O reception generates.
• Timer A0 interrupt through timer A2 interrupt
These are interrupts that timer A generates
• Timer B1, timer B2 interrupt
These are interrupts that timer B generates.
________ ________
• INT0 interrupt through INT2 interrupt
______ ______
An INT interrupt occurs if either a rising edge or a falling edge or a both edge is input to the INT pin.
Interrupt
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Interrupt source Vector table addresses Remarks
Address (L) to address (H)
Undefined instruction FFFDC16 to FFFDF16 Interrupt on UND instruction
Overflow FFFE016 to FFFE316 Interrupt on INTO instruction
BRK instruction FFFE416 to FFFE716
If the vector contains FF16, program execution starts from
the address shown by the vector in the variable vector table
Address match FFFE816 to FFFEB16 There is an address-matching interrupt enable bit
Single step (Note) FFFEC16 to FFFEF16 Do not use
Watchdog timer FFFF016 to FFFF316
________
DBC (Note) FFFF416 to FFFF716 Do not use
_______
NMI FFFF816 to FFFFB16 _______
External interrupt by input to NMI pin
Reset FFFFC16 to FFFFF16
Note: Interrupts used for debugging purposes only.
Figure 1.11.2. Format for specifying interrupt vector addresses
AAAAAAAA
AAAAAAAA
Mid address
AAAAAAAA
AAAAAAAA
Low address
AAAAAAAA
AAAAAAAA
0 0 0 0 High address
AAAAAAAA
AAAAAAAA
0 0 0 0 0 0 0 0
Vector address + 0
Vector address + 1
Vector address + 2
Vector address + 3
LSB
MSB
Interrupts and Interrupt Vector Tables
If an interrupt request is accepted, a program branches to the interrupt routine set in the interrupt vector
table. Set the first address of the interrupt routine in each vector table. Figure 1.11.2 shows the format for
specifying the address.
Two types of interrupt vector tables are available — fixed vector table in which addresses are fixed and
variable vector table in which addresses can be varied by the setting.
• Fixed vector tables
The fixed vector table is a table in which addresses are fixed. The vector tables are located in an area
extending from FFFDC16 to FFFFF16. One vector table comprises four bytes. Set the first address of
interrupt routine in each vector table. Table 1.11.1 shows the interrupts assigned to the fixed vector
tables and addresses of vector tables.
Table 1.11.1. Interrupts assigned to the fixed vector tables and addresses of vector tables
Interrupt
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Table 1.11.2. Interrupts assigned to the variable vector tables and addresses of vector tables
Software interrupt number Interrupt source
Vector table address
Address (L) to address (H) Remarks
Cannot be masked I flag+0 to +3 (Note 1) BRK instructionSoftware interrupt number 0
Note 1: Address relative to address in interrupt table register (INTB).
Note 2: When IIC mode is selected, NACK and ACK interrupts are selected.
Cannot be masked I flag
+108 to +111 (Note 1)Software interrupt number 27
+112 to +115 (Note 1)Software interrupt number 28
+116 to +119 (Note 1)Software interrupt number 29
+120 to +123 (Note 1)Software interrupt number 30
+124 to +127 (Note 1)Software interrupt number 31
+128 to +131 (Note 1)Software interrupt number 32
+252 to +255 (Note 1)Software interrupt number 63
to to
Timer B1
Timer B2
INT0
INT1
INT2
Software interrupt
+44 to +47 (Note 1) Software interrupt number 11
+52 to +55 (Note 1)Software interrupt number 13
+56 to +59 (Note 1)Software interrupt number 14
+68 to +71 (Note 1)Software interrupt number 17
+72 to +75 (Note 1)Software interrupt number 18
+76 to +79 (Note 1)Software interrupt number 19
+80 to +83 (Note 1)Software interrupt number 20
+84 to +87 (Note 1)Software interrupt number 21
+88 to +91 (Note 1)Software interrupt number 22
+92 to +95 (Note 1)Software interrupt number 23
+40 to +43 (Note 1)Software interrupt number 10
+60 to +63 (Note 1)Software interrupt number 15
+64 to +67 (Note 1)Software interrupt number 16
DMA0
Key input interrupt
A-D
UART0 transmit
UART0 receive
UART1 transmit
UART1 receive
Timer A0
Timer A1
Timer A2
Bus collision detection
UART2 transmit/NACK (Note 2)
UART2 receive/ACK (Note 2)
• Variable vector tables
The addresses in the variable vector table can be modified, according to the user’s settings. Indicate
the first address using the interrupt table register (INTB). The 256-byte area subsequent to the ad-
dress the INTB indicates becomes the area for the variable vector tables. One vector table comprises
four bytes. Set the first address of the interrupt routine in each vector table. Table 1.11.2 shows the
interrupts assigned to the variable vector tables and addresses of vector tables.
Interrupt
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Interrupt Control
Descriptions are given here regarding how to enable or disable maskable interrupts and how to set the
priority to be accepted. What is described here does not apply to non-maskable interrupts.
Enable or disable a maskable interrupt using the interrupt enable flag (I flag), interrupt priority level selec-
tion bit, or processor interrupt priority level (IPL). Whether an interrupt request is present or absent is
indicated by the interrupt request bit. The interrupt request bit and the interrupt priority level selection bit
are located in the interrupt control register of each interrupt. Also, the interrupt enable flag (I flag) and the
IPL are located in the flag register (FLG).
Figure 1.11.3 shows the memory map of the interrupt control registers.
Interrupt
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Figure 1.11.3. Interrupt control registers
Symbol Address When reset
INTiIC(i=0 to 2) 005D16 to 005F16 XX00X0002
Bit name FunctionBit symbol
WR
b7 b6 b5 b4 b3 b2 b1 b0
A
A
AA
AA
ILVL0
IR
POL
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns
out to be indeterminate.
Interrupt priority level
select bit
Interrupt request bit
Polarity select bit
Reserved bit
0: Interrupt not requested
1: Interrupt requested
0 : Selects falling edge
1 : Selects rising edge
Must always be set to “0”
ILVL1
ILVL2
Note 1: This bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1).
Note 2: To rewrite the interrupt control register, do so at a point that does not generate the
interrupt request for that register. For details, see the precautions for interrupts.
(Note 1)
Interrupt control register (Note 2)
b7 b6 b5 b4 b3 b2 b1 b0
A
AA
AA
A
Bit name FunctionBit symbol
WR
Symbol Address When reset
BCNIC 004A16 XXXXX0002
DM0IC 004B16 XXXXX0002
KUPIC 004D
16
XXXXX0002
ADIC 004E
16
XXXXX0002
SiTIC(i=0 to 2) 0051
16
, 0053
16
, 004F
16
XXXXX0002
SiRIC(i=0 to 2) 0052
16
, 0054
16
, 0050
16
XXXXX0002
TAiIC(i=0 to 2) 0055
16
to 0057
16
XXXXX0002
TBiIC(i=1, 2) 005B
16
, 005C
16
XXXXX0002
ILVL0
IR
Interrupt priority level
select bit
Interrupt request bit 0 : Interrupt not requested
1 : Interrupt requested
ILVL1
ILVL2
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns
out to be indeterminate.
(Note 1)
Note 1: This bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1).
Note 2: To rewrite the interrupt control register, do so at a point that does not generate the
interrupt request for that register. For details, see the precautions for interrupts.
0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
b2 b1 b0
0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
b2 b1 b0
0
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
Interrupt
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Interrupt Enable Flag (I flag)
The interrupt enable flag (I flag) controls the enabling and disabling of maskable interrupts. Setting this
flag to “1” enables all maskable interrupts; setting it to “0” disables all maskable interrupts. This flag is set
to “0” after reset.
Interrupt Request Bit
The interrupt request bit is set to “1” by hardware when an interrupt is requested. After the interrupt is
accepted and jumps to the corresponding interrupt vector, the request bit is set to “0” by hardware. The
interrupt request bit can also be set to “0” by software. (Do not set this bit to “1”).
Table 1.11.4.
Interrupt levels enabled according
to the contents of the IPL
Table 1.11.3. Settings of interrupt priority
levels
Interrupt priority
level select bit Interrupt priority
level Priority
order
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Level 0 (interrupt disabled)
Level 1
Level 2
Level 3
Level 4
Level 5
Level 6
Level 7
Low
High
b2 b1 b0
Enabled interrupt priority levels
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Interrupt levels 1 and above are enabled
Interrupt levels 2 and above are enabled
Interrupt levels 3 and above are enabled
Interrupt levels 4 and above are enabled
Interrupt levels 5 and above are enabled
Interrupt levels 6 and above are enabled
Interrupt levels 7 and above are enabled
All maskable interrupts are disabled
IPL
2
IPL
1
IPL
0
IPL
Interrupt Priority Level Select Bit and Processor Interrupt Priority Level (IPL)
Set the interrupt priority level using the interrupt priority level select bit, which is one of the component bits
of the interrupt control register. When an interrupt request occurs, the interrupt priority level is compared
with the IPL. The interrupt is enabled only when the priority level of the interrupt is higher than the IPL.
Therefore, setting the interrupt priority level to “0” disables the interrupt.
Table 1.11.3 shows the settings of interrupt priority levels and Table 1.11.4 shows the interrupt levels
enabled, according to the contents of the IPL.
The following are conditions under which an interrupt is accepted:
· interrupt enable flag (I flag) = “1”
· interrupt request bit = “1”
· interrupt priority level > IPL
The interrupt enable flag (I flag), the interrupt request bit, the interrupt priority select bit, and the IPL are
independent, and they are not affected by one another.
Interrupt
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Example 1:
INT_SWITCH1:
FCLR I ; Disable interrupts.
AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit.
NOP ; Four NOP instructions are required when using HOLD function.
NOP
FSET I ; Enable interrupts.
Example 2:
INT_SWITCH2:
FCLR I ; Disable interrupts.
AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit.
MOV.W MEM, R0 ; Dummy read.
FSET I ; Enable interrupts.
Example 3:
INT_SWITCH3:
PUSHC FLG ; Push Flag register onto stack
FCLR I ; Disable interrupts.
AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit.
POPC FLG ; Enable interrupts.
The reason why two NOP instructions (four when using the HOLD function) or dummy read are inserted
before FSET I in Examples 1 and 2 is to prevent the interrupt enable flag I from being set before the
interrupt control register is rewritten due to effects of the instruction queue.
Rewrite the interrupt control register
To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for
that register. If there is possibility of the interrupt request occur, rewrite the interrupt control register after
the interrupt is disabled. The program examples are described as follow:
When changing an interrupt control register in a sate of interrupts being disabled, please read the
following precautions on instructions used before changing the register.
Changing a non-interrupt request bit
If an interrupt request for an interrupt control register is generated during an instruction to rewrite the
register is being executed, there is a case that the interrupt request bit is not set and consequently the
interrupt is ignored. This will depend on the instruction. If this creates problems, use the below instruc-
tions to change the register.
Instructions : AND, OR, BCLR, BSET
Changing the interrupt request bit
When attempting to clear the interrupt request bit of an interrupt control register, the interrupt request bit
is not cleared sometimes. This will depend on the instruction. If this creates problems, use the below
instructions to change the register.
Instructions : MOV
Interrupt
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Interrupt Sequence
An interrupt sequence — what are performed over a period from the instant an interrupt is accepted to the
instant the interrupt routine is executed — is described here.
If an interrupt occurs during execution of an instruction, the processor determines its priority when the
execution of the instruction is completed, and transfers control to the interrupt sequence from the next
cycle. If an interrupt occurs during execution of either the SMOVB, SMOVF, SSTR or RMPA instruction,
the processor temporarily suspends the instruction being executed, and transfers control to the interrupt
sequence.
In the interrupt sequence, the processor carries out the following in sequence given:
(1) CPU gets the interrupt information (the interrupt number and interrupt request level) by reading ad-
dress 0000016. After this, the corresponding interrupt request bit becomes “0”.
(2) Saves the content of the flag register (FLG) as it was immediately before the start of interrupt sequence
in the temporary register (Note) within the CPU.
(3) Sets the interrupt enable flag (I flag), the debug flag (D flag), and the stack pointer select flag (U flag) to
“0” (the U flag, however does not change if the INT instruction, in software interrupt numbers 32
through 63, is executed)
(4) Saves the content of the temporary register (Note) within the CPU in the stack area.
(5) Saves the content of the program counter (PC) in the stack area.
(6) Sets the interrupt priority level of the accepted instruction in the IPL.
After the interrupt sequence is completed, the processor resumes executing instructions from the first
address of the interrupt routine.
Note: This register cannot be utilized by the user.
Interrupt Response Time
'Interrupt response time' is the period between the instant an interrupt occurs and the instant the first
instruction within the interrupt routine has been executed. This time comprises the period from the
occurrence of an interrupt to the completion of the instruction under execution at that moment (a) and the
time required for executing the interrupt sequence (b). Figure 1.11.4 shows the interrupt response time.
Instruction Interrupt sequence Instruction in
interrupt routine
Time
Interrupt response time
(a) (b)
Interrupt request acknowledgedInterrupt request generated
(a) Time from interrupt request is generated to when the instruction then under execution is completed.
(b) Time in which the instruction sequence is executed.
Figure 1.11.4. Interrupt response time
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Interrupt sources without priority levels
7
Value set in the IPL
_______
Watchdog timer, NMI
Other Not changed
0
Variation of IPL when Interrupt Request is Accepted
If an interrupt request is accepted, the interrupt priority level of the accepted interrupt is set in the IPL.
If an interrupt request, that does not have an interrupt priority level, is accepted, one of the values shown
in Table 1.11.6 is set in the IPL.
Table 1.11.6. Relationship between interrupts without interrupt priority levels and IPL
Stack pointer (SP) valueInterrupt vector address 16-Bit bus, without wait 8-Bit bus, without wait
Even
Even
Odd (Note 2)
Odd (Note 2)
Even
Odd
Even
Odd
18 cycles (Note 1)
19 cycles (Note 1)
19 cycles (Note 1)
20 cycles (Note 1)
20 cycles (Note 1)
20 cycles (Note 1)
20 cycles (Note 1)
20 cycles (Note 1)
Table 1.11.5. Time required for executing the interrupt sequence
Reset
Indeterminate
123456789 101112 13 14 15 16 17 18
The indeterminate segment is dependent on the queue buffer.
If the queue buffer is ready to take an instruction, a read cycle occurs.
Indeterminate SP-2
contents SP-4
contents vec
contents vec+2
contents
Interrupt
information
Address
0000 Indeterminate SP-2 SP-4 vec vec+2 PC
BCLK
Address bus
Data bus
W
R
Time (a) is dependent on the instruction under execution. Thirty cycles is the maximum required for the
DIVX instruction (without wait).
Time (b) is as shown in Table 1.11.5.
________
Note 1: Add 2 cycles in the case of a DBC interrupt; add 1 cycle in the case either of an address match
interrupt or of a single-step interrupt.
Note 2: Locate an interrupt vector address in an even address, if possible.
Figure 1.11.5. Time required for executing the interrupt sequence
Interrupt
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Saving Registers
In the interrupt sequence, only the contents of the flag register (FLG) and that of the program counter
(PC) are saved in the stack area.
First, the processor saves the four higher-order bits of the program counter, and 4 upper-order bits and 8
lower-order bits of the FLG register, 16 bits in total, in the stack area, then saves 16 lower-order bits of the
program counter. Figure 1.11.6 shows the state of the stack as it was before the acceptance of the
interrupt request, and the state the stack after the acceptance of the interrupt request.
Save other necessary registers at the beginning of the interrupt routine using software. Using the
PUSHM instruction alone can save all the registers except the stack pointer (SP).
Address
Content of previous stack
Stack area
[SP]
Stack pointer
value before
interrupt occurs
m
m – 1
m – 2
m – 3
m – 4
Stack status before interrupt request
is acknowledged Stack status after interrupt request
is acknowledged
Content of previous stack
m + 1
MSB LSB
m
m – 1
m – 2
m – 3
m – 4
Address
Flag register (FLG
L
)
Content of previous stack
Stack area
Flag register
(FLG
H
)Program
counter (PC
H
)
[SP]
New stack
pointer value
Content of previous stack
m + 1
MSB LSB
Program counter (PC
L
)
Program counter (PC
M
)
Figure 1.11.6. State of stack before and after acceptance of interrupt request
Interrupt
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Figure 1.11.7. Operation of saving registers
(2) Stack pointer (SP) contains odd number
[SP] (Odd)
[SP] – 1 (Even)
[SP] – 2(Odd)
[SP] – 3 (Even)
[SP] – 4(Odd)
[SP] – 5 (Even)
Address Sequence in which order
registers are saved
(2)
(1)
Finished saving registers
in four operations.
(3)
(4)
(1) Stack pointer (SP) contains even number
[SP] (Even)
[SP] – 1(Odd)
[SP] – 2 (Even)
[SP] – 3(Odd)
[SP] – 4 (Even)
[SP] – 5 (Odd)
Note: [SP] denotes the initial value of the stack pointer (SP) when interrupt request is acknowledged.
After registers are saved, the SP content is [SP] minus 4.
Address
Program counter (PC
M
)
Stack area
Flag register (FLG
L
)
Program counter (PC
L
)
Sequence in which order
registers are saved
(2) Saved simultaneously,
all 16 bits
(1) Saved simultaneously,
all 16 bits
Finished saving registers
in two operations.
Program counter (PC
M
)
Stack area
Flag register (FLG
L
)
Program counter (PC
L
)
Saved simultaneously,
all 8 bits
Flag register
(FLG
H
)Program
counter (PC
H
)
Flag register
(FLG
H
)Program
counter (PC
H
)
The operation of saving registers carried out in the interrupt sequence is dependent on whether the
content of the stack pointer (Note) , at the time of acceptance of an interrupt request, is even or odd. If
the content of the stack pointer (Note) is even, the content of the flag register (FLG) and the content of the
program counter (PC) are saved, 16 bits at a time. If odd, their contents are saved in two steps, 8 bits at
a time. Figure 1.11.7 shows the operation of the saving registers.
Note: When any INT instruction in software numbers 32 to 63 has been executed, this is the stack pointer
indicated by the U flag. Otherwise, it is the interrupt stack pointer (ISP).
Interrupt
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Interrupt Priority
If there are two or more interrupt requests occurring at a point in time within a single sampling (checking
whether interrupt requests are made), the interrupt assigned a higher priority is accepted.
Assign an arbitrary priority to maskable interrupts (peripheral I/O interrupts) using the interrupt priority level
select bit. If the same interrupt priority level is assigned, however, the interrupt assigned a higher hardware
priority is accepted.
Priorities of the special interrupts, such as Reset (dealt with as an interrupt assigned the highest priority),
watchdog timer interrupt, etc. are regulated by hardware.
Figure 1.11.8 shows the priorities of hardware interrupts.
Software interrupts are not affected by the interrupt priority. If an instruction is executed, control branches
invariably to the interrupt routine.
Returning from an Interrupt Routine
Executing the REIT instruction at the end of an interrupt routine returns the contents of the flag register
(FLG) as it was immediately before the start of interrupt sequence and the contents of the program counter
(PC), both of which have been saved in the stack area. Then control returns to the program that was being
executed before the acceptance of the interrupt request, so that the suspended process resumes.
Return the other registers saved by software within the interrupt routine using the POPM or similar instruc-
tion before executing the REIT instruction.
Interrupt resolution circuit
When two or more interrupts are generated simultaneously, this circuit selects the interrupt with the highest
priority level. Figure 1.11.9 shows the circuit that judges the interrupt priority level.
Figure 1.11.8. Hardware interrupts priorities
_______ ________
Reset > NMI > DBC > Watchdog timer > Peripheral I/O > Single step > Address match
Interrupt
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Figure 1.11.9. Maskable interrupts priorities (peripheral I/O interrupts)
Timer B2
Timer A1
Timer B1
UART1 reception
UART0 reception
UART2 reception/ACK
A-D conversion
Bus collision detection
Timer A0
UART1 transmission
UART0 transmission
UART2 transmission/NACK
Key input interrupt
DMA0
Processor interrupt priority level (IPL)
Interrupt enable flag (I flag)
INT1
INT2
INT0
Watchdog timer
Reset
DBC
NMI
Interrupt
request
accepted
Level 0 (initial value)
Priority level of each interrupt
High
Low
Priority of peripheral I/O interrupts
(if priority levels are same)
Address match
Interrupt request level judgment output
to clock generating circuit (Fig.1.10.3)
Timer A2
______
INT Interrupt
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______
INT Interrupt
________ ________
INT0 to INT2 are triggered by the edges of external inputs. The edge polarity is selected using the polarity
select bit.
As for external interrupt input, an interrupt can be generated both at the rising edge and at the falling edge
by setting “1” in the INTi interrupt polarity switching bit of the interrupt request cause select register
(035F16). To select both edges, set the polarity switching bit of the corresponding interrupt control register
to ‘falling edge’ (“0”).
Figure 1.11.10 shows the Interrupt request cause select register.
Figure 1.11.10. Interrupt request cause select register
Interrupt request cause select register
Bit name Function
Bit symbol
WR
Symbol Address When reset
IFSR 035F
16
0016
IFSR0
b7 b6 b5 b4 b3 b2 b1 b0
AA
AA
A
A
AA
AA
A
A
INT0 interrupt polarity
switching bit 0 : One edge
1 : Two edges
0 : One edge
1 : Two edges
0 : One edge
1 : Two edges
Must always be set to “0”
INT1 interrupt polarity
switching bit
INT2 interrupt polarity
switching bit
IFSR1
IFSR2
Reserved bit
Reserved bit
Reserved bit
Reserved bit
Reserved bit
AA
AA
A
A
AA
AA
A
A
AA
A
AA
A
AA
A
AA
AA
A
A
AA
A
AA
A
Must always be set to “0”
Must always be set to “0”
Must always be set to “0”
Must always be set to “0”
00000
________
NMI Interrupt
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Interrupt control circuit
Key input interrupt control register (address 004D16)
Key input interrupt
request
P10
7
/KI
3
P10
6
/KI
2
P10
5
/KI
1
P10
4
/KI
0
Port P10
4
-P10
7
pull-up
select bit
Port P10
7
direction
register
Pull-up
transistor
Port P10
7
direction register
Port P10
6
direction
register
Port P10
5
direction
register
Port P10
4
direction
register
Pull-up
transistor
Pull-up
transistor
Pull-up
transistor
Figure 1.11.11. Block diagram of key input interrupt
______
NMI Interrupt
______ ______ ______
An NMI interrupt is generated when the input to the P85/NMI pin changes from “H” to “L”. The NMI interrupt
is a non-maskable external interrupt. The pin level can be checked in the port P85 register (bit 5 at address
03F016).
This pin cannot be used as a normal port input.
Key Input Interrupt
If the direction register of any of P104 to P107 is set for input and a falling edge is input to that port, a key
input interrupt is generated. A key input interrupt can also be used as a key-on wakeup function for cancel-
ling the wait mode or stop mode. However, if you intend to use the key input interrupt, do not use P104 to
P107 as A-D input ports. Figure 1.11.11 shows the block diagram of the key input interrupt. Note that if an
“L” level is input to any pin that has not been disabled for input, inputs to the other pins are not detected as
an interrupt.
Address Match Interrupt
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Address Match Interrupt
An address match interrupt is generated when the address match interrupt address register contents match
the program counter value. Two address match interrupts can be set, each of which can be enabled and
disabled by an address match interrupt enable bit. Address match interrupts are not affected by the inter-
rupt enable flag (I flag) and processor interrupt priority level (IPL). For an address match interrupt, the value
of the program counter (PC) that is saved to the stack area varies depending on the instruction being
executed. Note that when using the external data bus in width of 8 bits, the address match interrupt cannot
be used for external area.
Figure 1.11.12 shows the address match interrupt-related registers.
Bit nameBit symbol
Symbol Address When reset
AIER 000916 XXXXXX002
Address match interrupt enable register
Function WR
AAAAAAAAAAAAAA
A
AAAAAAAAAAAA
A
AAAAAAAAAAAAAA
AAAAAAAAAAAAAA
A
AAAAAAAAAAAA
A
AAAAAAAAAAAAAA
Address match interrupt 0
enable bit 0 : Interrupt disabled
1 : Interrupt enabled
AIER0
Address match interrupt 1
enable bit
AIER1
AAAAAAAAAAAAAA
AAAAAAAAAAAAAA
Symbol Address When reset
RMAD0 001216 to 001016 X0000016
RMAD1 001616 to 001416 X0000016
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to
be indeterminated.
b7 b6 b5 b4 b3 b2 b1 b0
WR
Address setting register for address match interrupt
Function Values that can be set
Address match interrupt register i (i = 0, 1)
0000016 to FFFFF16
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to
be indeterminated.
0 : Interrupt disabled
1 : Interrupt enabled
b0 b7 b0b3
(b19) (b16) b7 b0
(b15) (b8)
b7
(b23)
AA
A
AA
A
AA
AA
A
A
Figure 1.11.12. Address match interrupt-related registers
Precautions for Interrupts
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______
Figure 1.11.13. Switching condition of INT interrupt request
Set the interrupt priority level to level 0
(Disable INT
i
interrupt)
Set the polarity select bit
NOP X 2
Set the interrupt priority level to level 1 to 7
(Enable the accepting of INTi interrupt request)
Clear the interrupt enable flag to “0”
(Disable interrupt)
Set the interrupt enable flag to “1”
(Enable interrupt)
Note: Execute the setting above individually. Don't execute two or
more settings at once(by one instruction).
Clear the interrupt request bit to “0”
Precautions for Interrupts
(1) Reading address 0000016
• When maskable interrupt is occurred, CPU reads the interrupt information (the interrupt number and
interrupt request level) in the interrupt sequence.
The interrupt request bit of the certain interrupt written in address 0000016 will then be set to “0”.
Even if the address 0000016 is read out by software, “0” is set to the enabled highest priority interrupt
source request bit. Therefore interrupt can be canceled and unexpected interrupt can occur.
Do not read address 0000016 by software.
(2) Setting the stack pointer
• The value of the stack pointer immediately after reset is initialized to 000016. Accepting an interrupt
before setting a value in the stack pointer may become a factor of runaway. Be sure to set a value in
_______
the stack pointer before accepting an interrupt. When using the NMI interrupt, initialize the stack
pointer at the beginning of a program. Concerning the first instruction immediately after reset, generat-
_______
ing any interrupts including the NMI interrupt is prohibited.
_______
(3) The NMI interrupt
_______ _______
•The NMI interrupt can not be disabled. Be sure to connect NMI pin to Vcc via a pull-up resistor if
unused. Be sure to work on it.
_______
• The NMI pin also serves as P85, which is exclusively input. Reading the contents of the P8 register
allows reading the pin value. Use the reading of this pin only for establishing the pin level at the time
_______
when the NMI interrupt is input. _______
• Do not attempt to go into stop mode with the input to the NMI pin being in the “L” state. With the input to
_______
the NMI being in the “L” state, the CM10 is fixed to “0”, so attempting to go into stop mode is turned
down. _______
• Do not attempt to go into wait mode with the input to the NMI pin being in the “L” state. With the input to
_______
the NMI pin being in the “L” state, the CPU stops but the oscillation does not stop, so no power is saved.
In this instance, the CPU is returned to the normal state by a later interrupt.
_______
• Signals input to the NMI pin require “L” level and “H” level of 2 clock +300ns or more, from the operation
clock of the CPU.
(4) External interrupt ________
• Either an “L” level or an “H” level of at least 250 ns width is necessary for the signal input to pins INT0
________
through INT2 regardless of the CPU operation clock.
________ ________
• When the polarity of the INT0 to INT2 pins is changed, the interrupt request bit is sometimes set to “1”.
After changing the polarity, set the interrupt request bit to “0”. Figure 1.11.13 shows the procedure for
______
changing the INT interrupt generate factor.
Precautions for Interrupts
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Example 1:
INT_SWITCH1:
FCLR I ; Disable interrupts.
AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit.
NOP ; Four NOP instructions are required when using HOLD function.
NOP
FSET I ; Enable interrupts.
Example 2:
INT_SWITCH2:
FCLR I ; Disable interrupts.
AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit.
MOV.W MEM, R0 ; Dummy read.
FSET I ; Enable interrupts.
Example 3:
INT_SWITCH3:
PUSHC FLG ; Push Flag register onto stack
FCLR I ; Disable interrupts.
AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit.
POPC FLG ; Enable interrupts.
The reason why two NOP instructions (four when using the HOLD function) or dummy read are inserted
before FSET I in Examples 1 and 2 is to prevent the interrupt enable flag I from being set before the
interrupt control register is rewritten due to effects of the instruction queue.
(5) Rewrite the interrupt control register
• To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for
that register. If there is possibility of the interrupt request occur, rewrite the interrupt control register after
the interrupt is disabled. The program examples are described as follow:
When changing an interrupt control register in a sate of interrupts being disabled, please read the
following precautions on instructions used before changing the register.
Changing a non-interrupt request bit
If an interrupt request for an interrupt control register is generated during an instruction to rewrite the
register is being executed, there is a case that the interrupt request bit is not set and consequently the
interrupt is ignored. This will depend on the instruction. If this creates problems, use the below instruc-
tions to change the register.
Instructions : AND, OR, BCLR, BSET
Changing the interrupt request bit
When attempting to clear the interrupt request bit of an interrupt control register, the interrupt request bit
is not cleared sometimes. This will depend on the instruction. If this creates problems, use the below
instructions to change the register.
Instructions : MOV
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Watchdog Timer
64
Watchdog Timer
The watchdog timer has the function of detecting when the program is out of control. Therefore, we recom-
mend using the watchdog timer to improve reliability of a system. The watchdog timer is a 15-bit counter
which down-counts the clock derived by dividing the BCLK using the prescaler. A watchdog timer interrupt
is generated when an underflow occurs in the watchdog timer. When XIN is selected for the BCLK, bit 7 of
the watchdog timer control register (address 000F16) selects the prescaler division ratio (by 16 or by 128).
When XCIN is selected as the BCLK, the prescaler is set for division by 2 regardless of bit 7 of the watchdog
timer control register (address 000F16). Thus the watchdog timer's period can be calculated as given
below. The watchdog timer's period is, however, subject to an error due to the prescaler.
BCLK
Write to the watchdog timer
start register
(address 000E
16
)
RESET
Watchdog timer
interrupt request
Watchdog timer
Set to
“7FFF
16
”
1/128
1/16
“CM07 = 0”
“WDC7 = 1”
“CM07 = 0”
“WDC7 = 0”
“CM07 = 1”
HOLD
1/2
Prescaler
For example, suppose that BCLK runs at 16 MHz and that 16 has been chosen for the dividing ratio of the
prescaler, then the watchdog timer's period becomes approximately 32.8 ms.
The watchdog timer is initialized by writing to the watchdog timer start register (address 000E16) and when
a watchdog timer interrupt request is generated. The prescaler is initialized only when the microcomputer is
reset. After a reset is cancelled, the watchdog timer and prescaler are both stopped. The count is started by
writing to the watchdog timer start register (address 000E16). In stop mode, wait mode and hold state, the
watchdog timer and prescaler are stopped. Counting is resumed from the held value when the modes or
state are released.
Figure 1.12.1 shows the block diagram of the watchdog timer. Figure 1.12.2 shows the watchdog timer-
related registers.
With XIN chosen for BCLK
Watchdog timer period = prescaler dividing ratio (16 or 128) X watchdog timer count (32768)
BCLK
Figure 1.12.1. Block diagram of watchdog timer
With XCIN chosen for BCLK
Watchdog timer period = prescaler dividing ratio (2) X watchdog timer count (32768)
BCLK
Watchdog Timer
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Watchdog timer control register
Symbol Address When reset
WDC 000F16 000XXXXX2
FunctionBit symbol WR
b7 b6 b5 b4 b3 b2 b1 b0
High-order bit of watchdog timer
WDC7
Bit name
Prescaler select bit 0 : Divided by 16
1 : Divided by 128
Watchdog timer start register
Symbol Address When reset
WDTS 000E16 Indeterminate
WR
b7 b0
Function
The watchdog timer is initialized and starts counting after a write instruction to
this register. The watchdog timer value is always initialized to “7FFF16”
regardless of whatever value is written.
Reserved bit
Reserved bit Must always be set to “0”
Must always be set to “0”
00
AA
AA
A
AA
A
AA
A
A
Figure 1.12.2. Watchdog timer control and start registers
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DMAC
66
DMAC
This microcomputer has one DMAC (direct memory access controller) channel that allow data to be sent to
memory without using the CPU. DMAC shares the same data bus with the CPU. The DMAC is given a
higher right of using the bus than the CPU, which leads to working the cycle stealing method. On this
account, the operation from the occurrence of DMA transfer request signal to the completion of 1-word (16-
bit) or 1-byte (8-bit) data transfer can be performed at high speed. Figure 1.13.1 shows the block diagram
of the DMAC. Table 1.13.1 shows the DMAC specifications. Figures 1.13.2 to 1.13.4 show the registers
used by the DMAC.
Figure 1.13.1. Block diagram of DMAC
AA
AA
AA
AA
AA
AA
Data bus low-order bits
DMA latch high-order bits DMA latch low-order bits
Data bus high-order bits
AA
AA
AA
AA
AA
AA
AA
AAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAA
AAAAAAA
Address bus
A
A
A
A
A
A
A
A
DMA0 transfer counter reload register TCR0 (16)
DMA0 transfer counter TCR0 (16)
A
(addresses 002916, 002816)
(addresses 002616 to 002416)
Note: Pointer is incremented by a DMA request.
A
A
A
AA
AA
AA
AA
AA
DMA0 source pointer SAR0(20)
DMA0 destination pointer DAR0 (20)
DMA0 forward address pointer (20) (Note)
AA
(addresses 002216 to 002016)
A
A
A
A
A
A
AA
AA
A
A
A
A
Either a write signal to the software DMA request bit or an interrupt request signal is used as a DMA transfer
request signal. But the DMA transfer is affected neither by the interrupt enable flag (I flag) nor by the
interrupt priority level. The DMA transfer doesn't affect any interrupts either.
If the DMAC is active (the DMA enable bit is set to 1), data transfer starts every time a DMA transfer request
signal occurs. If the cycle of the occurrences of DMA transfer request signals is higher than the DMA
transfer cycle, there can be instances in which the number of transfer requests doesn't agree with the
number of transfers. For details, see the description of the DMA request bit.
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DMAC
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Item Specification
No. of channels 2 (cycle steal method)
Transfer memory space • From any address in the 1M bytes space to a fixed address
• From a fixed address to any address in the 1M bytes space
• From a fixed address to a fixed address
(Note that DMA-related registers [0020
16
to 003F
16
] cannot be accessed)
Maximum No. of bytes transferred
128K bytes (with 16-bit transfers) or 64K bytes (with 8-bit transfers)
DMA request factors (Note) ________
Falling edge of INT0 or both edge
Timer A0 to timer A2 interrupt requests
Timer B1 and timer B2 interrupt requests
UART0 transfer and reception interrupt requests
UART1 transfer and reception interrupt requests
UART2 transfer and reception interrupt requests
A-D conversion interrupt requests
Software triggers
Transfer unit 8 bits or 16 bits
Transfer address direction forward/fixed (forward direction cannot be specified for both source and
destination simultaneously)
Transfer mode •Single transfer mode
After the transfer counter underflows, the DMA enable bit turns to
“0”, and the DMAC turns inactive
• Repeat transfer mode
After the transfer counter underflows, the value of the transfer counter
reload register is reloaded to the transfer counter.
The DMAC remains active unless a “0” is written to the DMA enable bit.
DMA interrupt request generation timing
When an underflow occurs in the transfer counter
Active When the DMA enable bit is set to “1”.
When the DMAC is active, data transfer starts every time a DMA
transfer request signal occurs.
Inactive • When the DMA enable bit is set to “0”.
At the time of starting data transfer immediately after turning the DMAC active, the
value of one of source pointer and destination pointer - the one specified for the
forward direction - is reloaded to the forward direction address pointer, and the value
of the transfer counter reload register is reloaded to the transfer counter.
Writing to register
Registers specified for forward direction transfer are always write enabled.
Registers specified for fixed address transfer are write-enabled when
the DMA enable bit is “0”.
Reading the register Can be read at any time.
However, when the DMA enable bit is “1”, reading the register set up as the
forward register is the same as reading the value of the forward address pointer.
Table 1.13.1. DMAC specifications
Note: DMA transfer is not effective to any interrupt. DMA transfer is affected neither by the interrupt enable
flag (I flag) nor by the interrupt priority level.
Reload timing for forward
address pointer and transfer
counter
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DMAC
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DMA0 request cause select register
Symbol Address When reset
DM0SL 03B816 0016
Function
Bit symbol
b7 b6 b5 b4 b3 b2 b1 b0
DMA request cause
select bit
DSEL0
RW
DSEL1
DSEL2
DSEL3
Software DMA
request bit If software trigger is selected, a
DMA request is generated by
setting this bit to “1” (When read,
the value of this bit is always “0”)
DSR
b6 b5 b4 b3 b2 b1 b0
AA
A
AA
A
AA
A
AA
AA
A
A
AA
AA
A
A
Bit name
AA
A
0 0 0 0 0 0 0 : Falling edge of INT0 pin
0 0 0 0 0 0 1 : Software trigger
0 0 0 0 0 1 0 : Timer A0
0 0 0 0 0 1 1 : Timer A1
0 0 0 0 1 0 0 : Timer A2
0 0 0 0 1 0 1 : Must not be set
0 0 0 0 1 1 0 : Must not be set
0 0 0 0 1 1 1 : Must not be set
0 0 0 1 0 0 0 : Timer B1
0 0 0 1 0 0 1 : Timer B2
0 0 0 1 0 1 0 : UART0 transmit
0 0 0 1 0 1 1 : UART0 receive
0 0 0 1 1 0 0 : UART2 transmit
0 0 0 1 1 0 1 : UART2 receive
0 0 0 1 1 1 0 : A-D conversion
0 0 0 1 1 1 1 : UART1 transmit
1 0 0 0 1 1 0 : Two edges of INT0 pin
Must not be set except the above.
AA
A
AA
A
DSEL4
DSEL5
DMS
(DMS)
Figure 1.13.2. DMAC register (1)
Mitsubishi microcomputer
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M16C / 30 Grou
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTE
R
DMAC
69
DMA0 control register
Symbol Address When reset
DM0CON 002C16 00000X002
Bit name FunctionBit symbol
Transfer unit bit select bit
b7 b6 b5 b4 b3 b2 b1 b0
0 : 16 bits
1 : 8 bits
DMBIT
RW
DMASL
DMAS
DMAE
Repeat transfer mode
select bit 0 : Single transfer
1 : Repeat transfer
DMA request bit (Note 1) 0 : DMA not requested
1 : DMA requested
0 : Disabled
1 : Enabled
0 : Fixed
1 : Forward
DMA enable bit
Source address direction
select bit (Note 3)
Destination address
direction select bit (Note 3) 0 : Fixed
1 : Forward
DSD
DAD
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”.
Note 1: DMA request can be cleared by resetting the bit.
Note 2: This bit can only be set to “0”.
Note 3: Source address direction select bit and destination address direction select bit
cannot be set to “1” simultaneously.
(Note 2)
A
A
A
A
A
A
A
A
A
A
A
A
A
A
Figure 1.13.3. DMAC register (2)
Mitsubishi microcomputer
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M16C / 30 Grou
p
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTE
R
DMAC
70
b7 b0 b7 b0
(b8)(b15)
Function
RW
• Transfer counter
Set a value one less than the transfer count
Symbol Address When reset
TCR0 0029
16
, 0028
16
Indeterminate
DMA0 transfer counter
Transfer count
specification
0000
16
to FFFF
16
b7
(b23) b3 b0 b7 b0 b7 b0
(b8)(b16)(b15)(b19)
Function
RW
• Source pointer
Stores the source address
Symbol Address When reset
SAR0 0022
16
to 0020
16
Indeterminat
e
DMA0 source pointer
Transfer address
specification
00000
16
to FFFFF
16
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”.
Symbol Address When reset
DAR0 0026
16
to 0024
16
Indeterminat
e
b3 b0 b7 b0 b7 b0
(b8)(b15)(b16)(b19)
Function
RW
• Destination pointer
Stores the destination address
DMA0 destination pointer
Transfer address
specification
00000
16
to FFFFF
16
b7
(b23)
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”.
A
A
A
A
A
A
A
A
Figure 1.13.4. DMAC register (3)
Mitsubishi microcomputer
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTE
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DMAC
71
(1) Transfer cycle
The transfer cycle consists of the bus cycle in which data is read from memory or from the SFR area
(source read) and the bus cycle in which the data is written to memory or to the SFR area (destination
write). The number of read and write bus cycles depends on the source and destination addresses. In
memory expansion mode and microprocessor mode, the number of read and write bus cycles also de-
pends on the level of the BYTE pin. Also, the bus cycle itself is longer when software waits are inserted.
(a) Effect of source and destination addresses
When 16-bit data is transferred on a 16-bit data bus, and the source and destination both start at odd
addresses, there are one more source read cycle and destination write cycle than when the source
and destination both start at even addresses.
(b) Effect of BYTE pin level
When transferring 16-bit data over an 8-bit data bus (BYTE pin = “H”) in memory expansion mode and
microprocessor mode, the 16 bits of data are sent in two 8-bit blocks. Therefore, two bus cycles are
required for reading the data and two are required for writing the data. Also, in contrast to when the
CPU accesses internal memory, when the DMAC accesses internal memory (internal ROM, internal
RAM, and SFR), these areas are accessed using the data size selected by the BYTE pin.
(c) Effect of software wait
When the SFR area or a memory area with a software wait is accessed, the number of cycles is
increased for the wait by 1 bus cycle. The length of the cycle is determined by BCLK.
Figure 1.13.5 shows the example of the transfer cycles for a source read. For convenience, the destina-
tion write cycle is shown as one cycle and the source read cycles for the different conditions are shown.
In reality, the destination write cycle is subject to the same conditions as the source read cycle, with the
transfer cycle changing accordingly. When calculating the transfer cycle, remember to apply the respec-
tive conditions to both the destination write cycle and the source read cycle. For example (2) in Figure
1.13.5, if data is being transferred in 16-bit units on an 8-bit bus, two bus cycles are required for both the
source read cycle and the destination write cycle.
Mitsubishi microcomputer
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M16C / 30 Grou
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTE
R
DMAC
72
BCLK
Address
bus
RD signal
WR signal
Data
bus
CPU use
CPU use CPU use
CPU useSource
Source
Destination
Destination
Dummy
cycle
Dummy
cycle
(1) 8-bit transfers
16-bit transfers and the source address is even.
BCLK
Address
bus
RD signal
WR signal
Data
bus
CPU use
CPU use CPU use
CPU useSource
Source
Destination
Destination
Dummy
cycle
Dummy
cycle
(3) One wait is inserted into the source read under the conditions in (1)
BCLK
Address
bus
RD signal
WR signal
Data
bus
CPU use
CPU use CPU use
CPU useSource
Source
Destination
Destination
Dummy
cycle
Dummy
cycle
Source + 1
Source + 1
(2) 16-bit transfers and the source address is odd
Transferring 16-bit data on an 8-bit data bus (In this case, there are also two destination cycles).
BCLK
Address
bus
RD signal
WR signal
Data
bus
CPU use
CPU use CPU use
CPU useSource
Source
Destination
Destination
Dummy
cycle
Dummy
cycle
Source + 1
Source + 1
(4) One wait is inserted into the source read under the conditions in (2)
(When 16-bit data is transferred on an 8-bit data bus, there are two destination cycles).
Note: The same timing changes occur with the respective conditions at the destination as at the source.
Figure 1.13.5. Example of the transfer cycles for a source read
Mitsubishi microcomputer
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M16C / 30 Grou
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTE
R
DMAC
73
Single-chip mode Memory expansion mode
Transfer unit Bus width Access address Microprocessor mode
No. of read No. of write No. of read No. of write
cycles cycles cycles cycles
16-bit Even 1111
8-bit transfers (BYTE= “L”) Odd 1111
(DMBIT= “1”) 8-bit Even — — 1 1
(BYTE = “H”) Odd — — 1 1
16-bit Even 1111
16-bit transfers (BYTE = “L”) Odd 2222
(DMBIT= “0”) 8-bit Even — — 2 2
(BYTE = “H”) Odd — — 2 2
Table 1.13.2. No. of DMAC transfer cycles
Internal memory External memory
Internal ROM/RAM Internal ROM/RAM
SFR area Separate bus Separate bus Multiplex
No wait With wait No wait With wait bus
122123
Coefficient j, k
(2) DMAC transfer cycles
Any combination of even or odd transfer read and write addresses is possible. Table 1.13.2 shows the
number of DMAC transfer cycles.
The number of DMAC transfer cycles can be calculated as follows:
No. of transfer cycles per transfer unit = No. of read cycles x j + No. of write cycles x k
Mitsubishi microcomputer
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M16C / 30 Grou
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTE
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DMAC
74
DMA enable bit
Setting the DMA enable bit to “1” makes the DMAC active. The DMAC carries out the following operations
at the time data transfer starts immediately after DMAC is turned active.
(1) Reloads the value of one of the source pointer and the destination pointer - the one specified for the
forward direction - to the forward direction address pointer.
(2) Reloads the value of the transfer counter reload register to the transfer counter.
Thus overwriting “1” to the DMA enable bit with the DMAC being active carries out the operations given
above, so the DMAC operates again from the initial state at the instant “1” is overwritten to the DMA
enable bit.
DMA request bit
The DMAC can generate a DMA transfer request signal triggered by a factor chosen in advance out of
DMA request factors.
DMA request factors include the following.
* Factors effected by using the interrupt request signals from the built-in peripheral functions and software
DMA factors (internal factors) effected by a program.
* External factors effected by utilizing the input from external interrupt signals.
For the selection of DMA request factors, see the descriptions of the DMA0 factor selection register.
The DMA request bit turns to “1” if the DMA transfer request signal occurs regardless of the DMAC's state
(regardless of whether the DMA enable bit is set to “1” or “0”). It turns to “0” immediately before data
transfer starts.
In addition, it can be set to “0” by use of a program, but cannot be set to “1”.
There can be instances in which a change in DMA request factor selection bit causes the DMA request bit
to turn to “1”. So be sure to set the DMA request bit to “0” after the DMA request factor selection bit is
changed.
The DMA request bit turns to “1” if a DMA transfer request signal occurs, and turns to “0” immediately
before data transfer starts. If the DMAC is active, data transfer starts immediately, so the value of the
DMA request bit, if read by use of a program, turns out to be “0” in most cases. To examine whether the
DMAC is active, read the DMA enable bit.
Here follows the timing of changes in the DMA request bit.
(1) Internal factors
Except the DMA request factors triggered by software, the timing for the DMA request bit to turn to “1” due
to an internal factor is the same as the timing for the interrupt request bit of the interrupt control register to
turn to “1” due to several factors.
Turning the DMA request bit to “0” due to an internal factor is timed to be effected immediately before the
transfer starts.
(2) External factors ________
An external factor is a factor caused to occur by the leading edge of input from the INT0 pin.
________
Selecting the INT0 pins as external factors using the DMA request factor selection bit causes input from
these pins to become the DMA transfer request signals.
The timing for the DMA request bit to turn to “1” when an external factor is selected synchronizes with the
signal's edge applicable to the function specified by the DMA request factor selection bit (synchronizes
________
with the trailing edge of the input signal to INT0 pin, for example).
With an external factor selected, the DMA request bit is timed to turn to “0” immediately before data
transfer starts similarly to the state in which an internal factor is selected.
Timer
75
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTE
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Timer
There are five 16-bit timers. These timers can be classified by function into timers A (three) and timers B
(two). All these timers function independently. Figures 1.14.1 and 1.14.2 show the block diagram of timers.
• Timer mode
• One-shot timer mode
• PWM mode
• Timer mode
• One-shot timer mode
• PWM mode
• Timer mode
• One-shot timer mode
• PWM mode
• Event counter mode
• Event counter mode
• Event counter mode
TA0IN
TA1IN
TA2IN
Timer A0
Timer A1
Timer A2
f1 f8 f32 fC32
Timer A0 interrupt
Timer A1 interrupt
Timer A2 interrupt
Noise
filter
Noise
filter
Noise
filter
1/32 fC32
1/8
1/4
f1
f8
f32
XIN XCIN
Clock prescaler reset flag (bit 7
at address 038116) set to “1”
Reset
Clock prescaler
Timer B2 overflow
Note : The TA0
IN pin (P71) is shared with RxD2, so be careful.
Figure 1.14.1. Timer A block diagram
Timer
76
Mitsubishi microcomputer
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTE
R
Figure 1.14.2. Timer B block diagram
• Event counter mode
• Event counter mode
• Timer mode
• Pulse width measuring mode
• Timer mode
• Pulse width measuring mode
TB1
IN
TB2
IN
Timer B1
Timer B2
f
1
f
8
f
32
f
C32
Noise
filter
Noise
filter
1/32 f
C32
1/8
1/4
f
1
f
8
f
32
X
IN
X
CIN
Clock prescaler reset flag (bit 7
at address 0381
16
) set to “1” Reset
Clock prescaler
Timer A
Timer B1 interrupt
Timer B2 interrupt
Timer A
77
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTE
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Timer A
Figure 1.14.3 shows the block diagram of timer A. Figures 1.14.4 to 1.14.6 show the timer A-related
registers.
Except in event counter mode, timers A0 through A2 all have the same function. Use the timer Ai mode
register (i = 0 to 2) bits 0 and 1 to choose the desired mode.
Timer A has the four operation modes listed as follows:
• Timer mode: The timer counts an internal count source.
• Event counter mode: The timer counts pulses from an external source or a timer overflow.
• One-shot timer mode: The timer stops counting when the count reaches “000016”.
• Pulse width modulation (PWM) mode: The timer outputs pulses of a given width.
Figure 1.14.4. Timer A-related registers (1)
Count start flag
(Address 0380
16
)
Up count/down count
TAi Addresses TAj TAk
Timer A0 038716 038616 Must not be set Timer A1
Timer A1 038916 038816 Timer A0 Timer A2
Timer A2 038B16 038A16 Timer A1 Must not be set
Always down count except
in event counter mode
Reload register (16)
Counter (16)
Low-order
8 bits
AAA
AAA
High-order
8 bits
Clock source
selection
• Timer
(gate function)
• Timer
• One shot
• PWM
f1
f8
f32
TAi
IN
(i = 0 to 2)
TB2 overflow
• Event counter
fC32
Clock selection
TAj overflow
(j = i – 1. Note, however, must not be set when i = 0)
Pulse output
Toggle flip-flop
TAiOUT
(i = 0 to 2)
Data bus low-order bits
Data bus high-order bits
AA
AA
AA
Up/down flag
Down count
(Address 0384
16
)
TAk overflow
(k = i + 1. Note, however, must not be set when i = 2)
Polarity
selection
Clock selection
To external
trigger circuit
Timer Ai mode register
Symbol Address When reset
TAiMR(i=0 to 2) 0396
16
to 0398
16
00
16
Bit name FunctionBit symbol
WR
b7 b6 b5 b4 b3 b2 b1 b0
0 0 : Timer mode
0 1 : Event counter mode
1 0 : One-shot timer mode
1 1 : Pulse width modulation
(PWM) mode
b1 b0
TCK1
MR3
MR2
MR1
TMOD1
MR0
TMOD0
TCK0
Function varies with each operation mode
Count source select bit
(Function varies with each operation mode)
Operation mode select bit
A
AA
A
AA
A
AA
A
AA
A
AA
A
A
AA
AA
A
AA
A
A
AA
AA
Figure 1.14.3. Block diagram of timer A
Mitsubishi microcomputer
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M16C / 30 Grou
p
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTE
R
Timer A
78
Figure 1.14.5. Timer A-related registers (2)
Symbol Address When reset
TA0 038716,038616 Indeterminate
TA1 038916,038816 Indeterminate
TA2 038B16,038A16 Indeterminate
b7 b0 b7 b0
(b15) (b8)
Timer Ai register (Note 1)
WR
• Timer mode 000016 to FFFF16
Counts an internal count source
Function Values that can be set
• Event counter mode 000016 to FFFF16
Counts pulses from an external source or timer overflow
• One-shot timer mode 000016 to FFFF16
Counts a one shot width (Note 2,4)
• Pulse width modulation mode (16-bit PWM)
Functions as a 16-bit pulse width modulator
• Pulse width modulation mode (8-bit PWM)
Timer low-order address functions as an 8-bit
prescaler and high-order address functions as an 8-bit
pulse width modulator
000016 to FFFE16
(Note 3,4)
A
A
A
A
A
A
A
A
Note 1: Read and write data in 16-bit units.
Note 2: When the timer Ai register is set to “000016”, the counter does not
operate and the timer Ai interrupt request is not generated. When the
pulse is set to output, the pulse does not output from the TAiOUT pin.
Note 3: When the timer Ai register is set to “000016”, the pulse width modulator
does not operate and the output level of the TAiOUT pin remains “L”
level, therefore the timer Ai interrupt request is not generated. This also
occurs in the 8-bit pulse width modulator mode when the significant 8
high-order bits in the timer Ai register are set to “0016”.
Note 4: Use MOV instruction to write to this register.
0016 to FE16
(High-order address)
0016 to FF16
(Low-order address)
(Note 3,4)
Symbol Address When reset
TABSR 038016 0016
Count start flag
Bit name FunctionBit symbol WR
b7 b6 b5 b4 b3 b2 b1 b0
AAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAA
Timer B2 count start flag
Timer B1 count start flag
Timer A2 count start flag
Timer A1 count start flag
Timer A0 count start flag 0 : Stops counting
1 : Starts counting
TB2S
TB1S
TA2S
TA1S
TA0S
A
A
A
A
A
A
A
A
A
A
A
A
A
A
0 : Stops counting
1 : Starts counting
Reserved bit Must always be set to “0”
000
Timer A2 up/down flag
Timer A1 up/down flag
Timer A0 up/down flag
Timer A2 two-phase pulse
signal processing select bit
Symbol Address When reset
UDF 038416 0016
TA2P
Up/down flag (Note 1)
Bit name FunctionBit symbol WR
b7 b6 b5 b4 b3 b2 b1 b0
TA2UD
TA1UD
TA0UD 0 : Down count
1 : Up count
This specification becomes valid
when the up/down flag content is
selected for up/down switching
cause
0 : two-phase pulse signal
processing disabled
1 : two-phase pulse signal
processing enabled (Note 2)
When not using the two-phase
pulse signal processing function,
set the select bit to “0”
A
A
A
A
A
A
A
A
A
A
Note 1: Use MOV instruction to write to this register.
Note 2: Set the TAiIN and TAiOUT
p
ins corres
p
ondent
p
ort direction re
g
isters to “0”.
00 00
Reserved bit Must always be set to “0”
Reserved bit Must always be set to “0”
Timer A
79
Mitsubishi microcomputer
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTE
R
Symbol Address When reset
CPSRF 0381
16
0XXXXXXX
2
Clock prescaler reset flag
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA
Clock prescaler reset flag 0 : No effect
1 : Prescaler is reset
(When read, the value is “0”)
CPSR
WR
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be
indeterminate.
A
AA
TA1OS
TA2OS
TA0OS
One-shot start flag
Symbol Address When reset
ONSF 0382
16
00X00000
2
Timer A0 one-shot start flag
Timer A1 one-shot start flag
Timer A2 one-shot start flag
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
Nothing is assigned.
In an attempt to write to this bit, write “0”. The value, if read, turns out to be indeterminate.
TA0TGL
TA0TGH
0 0 :
Input on TA0
IN
is selected (Note)
0 1 : TB2 overflow is selected
1 0 : Must not be set
1 1 : TA1 overflow is selected
Timer A0 event/trigger
select bit
b7 b6
Note: Set the corresponding port direction register to “0”.
WR
1 : Timer start
When read, the value is “0”
A
A
A
A
A
A
A
A
A
A
A
A
A
A
Reserved bit Must always be set to “0”
00
TA1TGL
Symbol Address When reset
TRGSR 0383
16
00
16
Timer A1 event/trigger
select bit 0 0 :
Input on TA1
IN
is selected (Note)
0 1 : TB2 overflow is selected
1 0 : TA0 overflow is selected
1 1 : TA2 overflow is selected
Trigger select register
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
0 0 :
Input on TA2
IN
is selected (Note)
0 1 : TB2 overflow is selected
1 0 : TA1 overflow is selected
1 1 : Must not be set
Timer A2 event/trigger
select bit
WR
TA1TGH
TA2TGL
TA2TGH
b1 b0
b3 b2
Note: Set the corresponding port direction register to “0”.
A
AA
A
AA
A
AA
A
A
AA
AA
A
A
AA
AA
A
A
AA
AA
Reserved bit Must always be set to “0”
0000
Figure 1.14.6. Timer A-related registers (3)
Mitsubishi microcomputer
s
M16C / 30 Grou
p
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTE
R
Timer A
80
Item Specification
Count source f1, f8, f32, fC32
Count operation • Down count
•
When the timer underflows, it reloads the reload register contents before continuing counting
Divide ratio 1/(n+1) n : Set value
Count start condition Count start flag is set (= 1)
Count stop condition Count start flag is reset (= 0)
Interrupt request generation timing
When the timer underflows
TAiIN pin function Programmable I/O port or gate input
TAiOUT pin function Programmable I/O port or pulse output
Read from timer Count value can be read out by reading timer Ai register
Write to timer • When counting stopped
When a value is written to timer Ai register, it is written to both reload register and counter
• When counting in progress
When a value is written to timer Ai register, it is written to only reload register
(Transferred to counter at next reload time)
Select function • Gate function
Counting can be started and stopped by the TAiIN pin’s input signal
• Pulse output function
Each time the timer underflows, the TAiOUT pin’s polarity is reversed
(1) Timer mode
In this mode, the timer counts an internally generated count source. (See Table 1.14.1.) Figure 1.14.7
shows the timer Ai mode register in timer mode.
Table 1.14.1. Specifications of timer mode
Note 1: The settings of the corresponding port register and port direction register
are invalid.
Note 2: The bit can be “0” or “1”.
Note 3: Set the corresponding port direction register to “0”.
Timer Ai mode register Symbol Address When reset
TAiMR(i=0 to 2) 0396
16
to 0398
16
00
16
Bit name FunctionBit symbol WR
b7 b6 b5 b4 b3 b2 b1 b0
Operation mode
select bit 0 0 : Timer mode
b1 b0
TMOD1
TMOD0
MR0 Pulse output function
select bit 0 : Pulse is not output
(TA
iOUT
pin is a normal port pin)
1 : Pulse is output (Note 1)
(TA
iOUT
pin is a pulse output pin)
Gate function select bit 0 X
(Note 2): Gate function not available
(TAi
IN
pin is a normal port pin)
1 0 : Timer counts only when TA
iIN
pin is
held “L” (Note 3)
1 1 : Timer counts only when TA
iIN
pin is
held “H” (Note 3)
b4 b3
MR2
MR1
MR3 0 (Must always be “0” in timer mode)
0 0 : f
1
0 1 : f
8
1 0 : f
32
1 1 : f
C32
b7 b6
TCK1
TCK0 Count source select bit
00
0
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
Figure 1.14.7. Timer Ai mode register in timer mode
Timer A
81
Mitsubishi microcomputer
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p
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTE
R
Item Specification
Count source
•
External signals input to TAi
IN
pin (effective edge can be selected by software)
• TB2 overflow, TAj overflow
Count operation • Up count or down count can be selected by external signal or software
• When the timer overflows or underflows, it reloads the reload register con
tents before continuing counting (Note)
Divide ratio 1/ (FFFF16 - n + 1) for up count
1/ (n + 1) for down count n : Set value
Count start condition Count start flag is set (= 1)
Count stop condition Count start flag is reset (= 0)
Interrupt request generation timing
The timer overflows or underflows
TAiIN pin function Programmable I/O port or count source input
TAiOUT pin function Programmable I/O port, pulse output, or up/down count select input
Read from timer Count value can be read out by reading timer Ai register
Write to timer • When counting stopped
When a value is written to timer Ai register, it is written to both reload register and counter
• When counting in progress
When a value is written to timer Ai register, it is written to only reload register
(Transferred to counter at next reload time)
Select function • Free-run count function
Even when the timer overflows or underflows, the reload register content is not reloaded to it
• Pulse output function
Each time the timer overflows or underflows, the TAiOUT pin’s polarity is reversed
Note: This does not apply when the free-run function is selected.
(2) Event counter mode
In this mode, the timer counts an external signal or an internal timer’s overflow. Timers A0 and A1 can
count a single-phase external signal. Timer A2 can count a single-phase and a two-phase external
signal. Table 1.14.2 lists timer specifications when counting a single-phase external signal. Figure
1.14.8 shows the timer Ai mode register in event counter mode.
Table 1.14.3 lists timer specifications when counting a two-phase external signal. Figure 1.14.9 shows
the timer Ai mode register in event counter mode.
Table 1.14.2. Timer specifications in event counter mode (when not processing two-phase pulse signal)
Figure 1.14.8. Timer Ai mode register in event counter mode
Note 1: In event counter mode, the count source is selected by the event / trigger select bit
(addresses 038216 and 038316).
Note 2: The settings of the corresponding port register and port direction register are invalid.
Note 3: Valid only when counting an external signal.
Note 4: When an “L” signal is input to the TAiOUT pin, the downcount is activated. When “H”,
the upcount is activated. Set the corresponding port direction register to “0”.
Symbol Address When reset
TAiMR(i = 0 to 2) 0396
16
to 0398
16
00
16
WR
b7 b6 b5 b4 b3 b2 b1 b0
Operation mode select bit 0 1 : Event counter mode
(Note 1)
b1 b0
TMOD0
MR0 Pulse output function
select bit 0 : Pulse is not output
(TA
iOUT
pin is a normal port pin)
1 : Pulse is output (Note 2)
(TA
iOUT
pin is a pulse output pin)
Count polarity
select bit (Note 3)
MR2
MR1
MR3 0 (Must always be “0” in event counter mode)
TCK0 Count operation type
select bit
010
0 : Counts external signal's falling edge
1 : Counts external signal's rising edge
Up/down switching
cause select bit 0 : Up/down flag's content
1 : TA
iOUT
pin's input signal (Note 4)
0 : Reload type
1 : Free-run type
Bit symbol Bit name Function RW
TCK1 Invalid when not using two-phase pulse signal processing
Can be “0” or “1”
TMOD1
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
Timer Ai mode register
(When not using two-phase pulse signal processing)
Mitsubishi microcomputer
s
M16C / 30 Grou
p
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTE
R
Timer A
82
Item Specification
Count source • Two-phase pulse signals input to TA2IN or TA2OUT pin
Count operation • Up count or down count can be selected by two-phase pulse signal
• When the timer overflows or underflows, the reload register content is
reloaded and the timer starts over again (Note)
Divide ratio 1/ (FFFF16 - n + 1) for up count
1/ (n + 1) for down count n : Set value
Count start condition Count start flag is set (= 1)
Count stop condition Count start flag is reset (= 0)
Interrupt request generation timing
Timer overflows or underflows
TA2IN pin function
Two-phase pulse input (Set the TA2IN pin correspondent port direction register to “0”.)
TA2OUT pin function
Two-phase pulse input (Set the TA2
OUT
pin correspondent port direction register to “0”.)
Read from timer Count value can be read out by reading timer A2 register
Write to timer • When counting stopped
When a value is written to timer A2 register, it is written to both reload
register and counter
• When counting in progress
When a value is written to timer A2 register, it is written to only reload
register. (Transferred to counter at next reload time.)
Select function • Normal processing operation
The timer counts up rising edges or counts down falling edges on the TA2IN
pin when input signal on the TA2OUT pin is “H”.
Note: This does not apply when the free-run function is selected.
Table 1.14.3. Timer specifications in event counter mode (when processing two-phase pulse signal with timer A2)
TA2OUT
Up
count Up
count Up
count Down
count Down
count Down
count
TA2IN
Timer A
83
Mitsubishi microcomputer
s
M16C / 30 Grou
p
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTE
R
Note : When performing two-phase pulse signal processing, make sure the two-phase pulse
signal processing operation select bit (address 0384
16
) is set to “1”. Also, always be
sure to set the event/trigger select bit (address 0383
16
) to “00”.
Timer Ai mode register
(When using two-phase pulse signal processing) (Note)
Symbol Address When reset
TA2MR 0398
16
00
16
b6 b5 b4 b3 b2 b1 b0
Operation mode select bit 0 1 : Event counter mode
b1 b0
TMOD1
TMOD0
MR0 0 (Must always be “0” when using two-phase pulse signal
processing)
0 (Must always be “0” when using two-phase pulse signal
processing)
MR2
MR1
MR3 0 (Must always be “0” when using two-phase pulse signal
processing)
TCK0
010
1 (Must always be “1” when using two-phase pulse signal
processing)
Bit name Function WR
Count operation type
select bit 0 : Reload type
1 : Free-run type
001
AA
AA
A
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
AA
A
A
TCK1 0 (Must always be “0” when using two-phase pulse signal
processing)
0
Figure 1.14.9. Timer Ai mode register in event counter mode
Mitsubishi microcomputer
s
M16C / 30 Grou
p
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTE
R
Timer A
84
Item Specification
Count source f1, f8, f32, fC32
Count operation • The timer counts down
• When the count reaches 000016, the timer stops counting after reloading a new count
• If a trigger occurs when counting, the timer reloads a new count and restarts counting
Divide ratio 1/n n : Set value
Count start condition • An external trigger is input
• The timer overflows
• The one-shot start flag is set (= 1)
Count stop condition • A new count is reloaded after the count has reached 000016
• The count start flag is reset (= 0)
Interrupt request generation timing
The count reaches 000016
TAiIN pin function Programmable I/O port or trigger input
TAiOUT pin function Programmable I/O port or pulse output
Read from timer When timer Ai register is read, it indicates an indeterminate value
Write to timer • When counting stopped
When a value is written to timer Ai register, it is written to both reload
register and counter
• When counting in progress
When a value is written to timer Ai register, it is written to only reload register
(Transferred to counter at next reload time)
Table 1.14.4. Timer specifications in one-shot timer mode
Figure 1.14.10. Timer Ai mode register in one-shot timer mode
(3) One-shot timer mode
In this mode, the timer operates only once. (See Table 1.14.4.) When a trigger occurs, the timer starts up
and continues operating for a given period. Figure 1.14.10 shows the timer Ai mode register in one-shot
timer mode.
Bit name
Timer Ai mode register
Symbol Address When reset
TAiMR(i = 0 to 2) 0396
16
to 0398
16
00
16
Function
Bit symbol
b7 b6 b5 b4 b3 b2 b1 b0
Operation mode select bit 1 0 : One-shot timer mode
b1 b0
TMOD1
TMOD0
MR0 Pulse output function
select bit 0 : Pulse is not output
(TA
iOUT
pin is a normal port pin)
1 : Pulse is output (Note 1)
(TAi
OUT
pin is a pulse output pin)
MR2
MR1
MR3 0 (Must always be “0” in one-shot timer mode)
0 0 : f
1
0 1 : f
8
1 0 : f
32
1 1 : f
C32
b7 b6
TCK1
TCK0 Count source select bit
100
0 : One-shot start flag is valid
1 : Selected by event/trigger select
bits
Trigger select bit
External trigger select
bit (Note 2) 0 : Falling edge of TAi
IN
pin's input signal (Note 3)
1 : Rising edge of TAi
IN
pin's input signal (Note 3)
Note 1: The settings of the corresponding port register and port direction register are invalid.
Note 2: Valid only when the TAiIN pin is selected by the event/trigger select bit
(addresses 038216 and 038316). If timer overflow is selected, this bit can be “1” or “0”.
Note 3: Set the corres
p
ondin
g
p
ort direction re
g
ister to “0”.
WR
AA
A
AA
AA
A
A
AA
A
AA
AA
A
A
AA
A
AA
A
AA
A
AA
A
Timer A
85
Mitsubishi microcomputer
s
M16C / 30 Grou
p
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTE
R
(4) Pulse width modulation (PWM) mode
In this mode, the timer outputs pulses of a given width in succession. (See Table 1.14.5.) In this mode, the
counter functions as either a 16-bit pulse width modulator or an 8-bit pulse width modulator. Figure
1.14.11 shows the timer Ai mode register in pulse width modulation mode. Figure 1.14.12 shows the
example of how a 16-bit pulse width modulator operates. Figure 1.14.13 shows the example of how an 8-
bit pulse width modulator operates.
Figure 1.14.11. Timer Ai mode register in pulse width modulation mode
Table 1.14.5. Timer specifications in pulse width modulation mode
Bit name
Timer Ai mode register
Symbol Address When reset
TAiMR(i=0 to 2) 0396
16
to 0398
16
00
16
FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
Operation mode
select bit 1 1 : PWM mode
b1 b0
TMOD1
TMOD0
MR0
MR2
MR1
MR3
0 0 : f
1
0 1 : f
8
1 0 : f
32
1 1 : f
C32
b7 b6
TCK1
TCK0 Count source select bit
WR
111
1 (Must always be “1” in PWM mode)
16/8-bit PWM mode
select bit 0: Functions as a 16-bit pulse width modulator
1: Functions as an 8-bit pulse width modulator
Trigger select bit
External trigger select
bit (Note 1) 0: Falling edge of TAi
IN
pin's input signal (Note 2)
1: Rising edge of TAi
IN
pin's input signal (Note 2)
0: Count start flag is valid
1: Selected by event/trigger select bits
Note 1: Valid only when the TAiIN pin is selected by the event/trigger select bit
(addresses 038216 and 038316). If timer overflow is selected, this bit can be “1” or “0”.
Note 2: Set the corresponding port direction register to “0”.
A
A
AA
AA
A
AA
A
AA
A
AA
A
AA
A
A
AA
AA
A
AA
A
AA
Item Specification
Count source f1, f8, f32, fC32
Count operation • T
he timer counts down (operating as an 8-bit or a 16-bit pulse width modulator)
•
The timer reloads a new count at a rising edge of PWM pulse and continues counting
• The timer is not affected by a trigger that occurs when counting
16-bit PWM • High level width n / fi n : Set value
• Cycle time (216-1) / fi fixed
8-bit PWM
•
High level width n (m+1) / fi n : values set to timer Ai register’s high-order address
•
Cycle time (28
-
1) (m+1) / fi
m : values set to timer Ai register’s low-order address
Count start condition • External trigger is input
• The timer overflows
• The count start flag is set (= 1)
Count stop condition • The count start flag is reset (= 0)
Interrupt request generation timing
PWM pulse goes “L”
TAiIN pin function Programmable I/O port or trigger input
TAiOUT pin function Pulse output
Read from timer When timer Ai register is read, it indicates an indeterminate value
Write to timer • When counting stopped
When a value is written to timer Ai register, it is written to both reload
register and counter
• When counting in progress
When a value is written to timer Ai register, it is written to only reload register
(Transferred to counter at next reload time)
Mitsubishi microcomputer
s
M16C / 30 Grou
p
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTE
R
Timer A
86
1 / f
i
X
(2 – 1)
16
Count source
TA
iIN
pin
input signal
PWM pulse output
from TA
iOUT
pin
Condition : Reload register = 0003
16
, when external trigger
(rising edge of TA
iIN
pin input signal) is selected
Trigger is not generated by this signal
“H”
“H”
“L”
“L”
Timer Ai interrupt
request bit
“1”
“0”
Cleared to “0” when interrupt request is accepted, or cleared by software
f
i
: Frequency of count source
(f
1
, f
8
, f
32
, f
C32
)
Note: n = 0000
16
to FFFE
16
.
1 / f
i
X
n
Count source (Note1)
TA
iIN
pin input signal
Underflow signal of
8-bit prescaler (Note2)
PWM pulse output
from TA
iOUT
pin
“H”
“H”
“H”
“L”
“L”
“L”
“1”
“0”
Timer Ai interrupt
request bit
Cleared to “0” when interrupt request is accepted, or cleaerd by software
f
i
: Frequency of count source
(f
1
, f
8
, f
32
, f
C32
)
Note 1: The 8-bit prescaler counts the count source.
Note 2: The 8-bit pulse width modulator counts the 8-bit prescaler's underflow signal.
Note 3: m = 00
16
to FF
16
; n = 00
16
to FE
16
.
AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA
Condition : Reload register high-order 8 bits = 0216
Reload register low-order 8 bits = 0216
External trigger (falling edge of TAiIN pin input signal) is selected
1 / fi X (m + 1) X (2 – 1)
8
1 / fi X (m + 1) X n
1 / fi X (m + 1)
Figure 1.14.12. Example of how a 16-bit pulse width modulator operates
Figure 1.14.13. Example of how an 8-bit pulse width modulator operates
Timer B
87
Mitsubishi microcomputer
s
M16C / 30 Grou
p
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTE
R
Timer B
Figure 1.14.14 shows the block diagram of timer B. Figures 1.14.15 and 1.14.16 show the timer B-related
registers.
Use the timer Bi mode register (i = 1, 2) bits 0 and 1 to choose the desired mode.
Timer B has three operation modes listed as follows:
• Timer mode: The timer counts an internal count source.
• Event counter mode: The timer counts pulses from an external source or a timer overflow.
• Pulse period/pulse width measuring mode: The timer measures an external signal's pulse period or
pulse width.
Figure 1.14.14. Block diagram of timer B
Timer Bi mode register
Symbol Address When reset
TBiMR(i = 1, 2) 039C16, 039D16 00XX00002
Bit name FunctionBit symbol WR
b7 b6 b5 b4 b3 b2 b1 b0
0 0 : Timer mode
0 1 : Event counter mode
1 0 : Pulse period/pulse width
measurement mode
1 1 : Must not be set.
b1 b0
TCK1
MR3
MR1
TMOD1
MR0
TMOD0
TCK0
Function varies with each operation mode
Count source select bit
(Function varies with each operation mode)
Operation mode select bit
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
Function varies with each operation mode
Nothing is assigned.
In an attempt to write to these bits, write “0”.
The value, if read, turns out to be indeterminate.
Clock source selection
(address 0380
16
)
• Event counter
• Timer
• Pulse period/pulse width measurement Reload register (16)
Low-order 8 bits High-order 8 bits
Data bus low-order bits
Data bus high-order bits
f
1
f
8
f
32
TBj overflow
(j = i – 1. Note, however,
must not be set when i = 1)
Can be selected in only
event counter mode
Count start flag
f
C32
Polarity switching
and edge pulse
TBi
IN
(i = 1, 2)
Counter reset circuit
Counter (16)
TBi Address TBj
Timer B1 0393
16
0392
16
Must not be set
Timer B2 0395
16
0394
16
Timer B1
Clock selection
Figure 1.14.15. Timer B-related registers (1)
Mitsubishi microcomputer
s
M16C / 30 Grou
p
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTE
R
Timer B
88
Symbol Address When reset
TB1 0393
16
, 0392
16
Indeterminate
TB2 0395
16
, 0394
16
Indeterminate
b7 b0 b7 b0
(b15) (b8)
Timer Bi register (Note)
WR
• Pulse period / pulse width measurement mode
Measures a pulse period or width
• Timer mode 0000
16
to FFFF
16
Counts the timer's period
Function
Values that can be set
• Event counter mode 0000
16
to FFFF
16
Counts external pulses input or a timer overflow
Note: Read and write data in 16-bit units.
A
A
A
A
A
Symbol Address When reset
CPSRF 0381
16
0XXXXXXX
2
Clock prescaler reset flag
Bit name Function
Bit symbol WR
b7 b6 b5 b4 b3 b2 b1 b0
AAAAAAAAAAAAAAA
A
AAAAAAAAAAAAA
A
AAAAAAAAAAAAAAA
Clock prescaler reset flag 0 : No effect
1 : Prescaler is reset
(When read, the value is “0”)
CPSR
A
A
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns
out to be indeterminate.
Symbol Address When reset
TABSR 0380
16
00
16
Count start flag
Bit name
Bit symbol WR
b7 b6 b5 b4 b3 b2 b1 b0
AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA
Timer B2 count start flag
Timer B1 count start flag
Timer A2 count start flag
Timer A1 count start flag
Timer A0 count start flag 0 : Stops counting
1 : Starts counting
TB2S
TB1S
TA2S
TA1S
TA0S
Function
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
0 : Stops counting
1 : Starts counting
Reverved bit Must always be set to “0”
000
Figure 1.14.16. Timer B-related registers (2)
Timer B
89
Mitsubishi microcomputer
s
M16C / 30 Grou
p
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTE
R
Item Specification
Count source f1, f8, f32, fC32
Count operation • Counts down
• When the timer underflows, it reloads the reload register contents before
continuing counting
Divide ratio 1/(n+1) n : Set value
Count start condition Count start flag is set (= 1)
Count stop condition Count start flag is reset (= 0)
Interrupt request generation timing
The timer underflows
TBiIN pin function Programmable I/O port
Read from timer Count value is read out by reading timer Bi register
Write to timer • When counting stopped
When a value is written to timer Bi register, it is written to both reload register and counter
• When counting in progress
When a value is written to timer Bi register, it is written to only reload register
(Transferred to counter at next reload time)
(1) Timer mode
In this mode, the timer counts an internally generated count source. (See Table 1.14.6.) Figure 1.14.17
shows the timer Bi mode register in timer mode.
Table 1.14.6. Timer specifications in timer mode
Timer Bi mode register Symbol Address When reset
TBiMR(i=1, 2) 039C
16, 039D16 00XX00002
Bit name Function
Bit symbol WR
b7 b6 b5 b4 b3 b2 b1 b0
AA
AA
A
A
Operation mode select bit 0 0 : Timer mode
b1 b0
TMOD1
TMOD0
MR0 Invalid in timer mode
Can be “0” or “1”
MR1
MR3
0 0 : f1
0 1 : f8
1 0 : f32
1 1 : fC32
TCK1
TCK0 Count source select bit
0
Invalid in timer mode.
In an attempt to write to this bit, write “0”. The value, if read in
timer mode, turns out to be indeterminate.
0
Nothing is assiigned.
In an attempt to write to this bit, write “0”. The value, if read,
turns out to be indeterminate.
b7 b6
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
Figure 1.14.17. Timer Bi mode register in timer mode
Mitsubishi microcomputer
s
M16C / 30 Grou
p
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTE
R
Timer B
90
Item Specification
Count source • External signals input to TBiIN pin
• Effective edge of count source can be a rising edge, a falling edge, or falling
and rising edges as selected by software
Count operation • Counts down
• When the timer underflows, it reloads the reload register contents before
continuing counting
Divide ratio 1/(n+1) n : Set value
Count start condition Count start flag is set (= 1)
Count stop condition Count start flag is reset (= 0)
Interrupt request generation timing
The timer underflows
TBiIN pin function Count source input
Read from timer Count value can be read out by reading timer Bi register
Write to timer • When counting stopped
When a value is written to timer Bi register, it is written to both reload register and counter
• When counting in progress
When a value is written to timer Bi register, it is written to only reload register
(Transferred to counter at next reload time)
(2) Event counter mode
In this mode, the timer counts an external signal or an internal timer's overflow. (See Table 1.14.7.)
Figure 1.14.18 shows the timer Bi mode register in event counter mode.
Table 1.14.7. Timer specifications in event counter mode
Figure 1.14.18. Timer Bi mode register in event counter mode
Timer Bi mode register Symbol Address When reset
TBiMR(i=1, 2) 039C
16
, 039D
16
00XX0000
2
Bit name FunctionBit symbol WR
b7 b6 b5 b4 b3 b2 b1 b0
AA
AA
Operation mode select bit 0 1 : Event counter mode
b1 b0
TMOD1
TMOD0
MR0 Count polarity select
bit (Note 1)
MR1
MR3 Invalid in event counter mode.
In an attempt to write to this bit, write “0”. The value, if read in
event counter mode, turns out to be indeterminate.
TCK1
TCK0
01
0 0 : Counts external signal's
falling edges
0 1 : Counts external signal's
rising edges
1 0 : Counts external signal's
falling and rising edges
1 1 : Must not be set.
b3 b2
Nothing is assigned.
In an attempt to write to this bit, write “0”. The value, if read,
turns out to be indeterminate.
Note 1: Valid only when input from the TBi
IN
pin is selected as the event clock.
If timer's overflow is selected, this bit can be “0” or “1”.
Note 2: Set the corresponding port direction register to “0”.
Invalid in event counter mode.
Can be “0” or “1”.
Event clock select 0 : Input from TBi
IN
pin (Note 2)
1 : TBj overflow
(j = i – 1; however, must not be set,
when i = 1)
A
A
A
A
A
A
A
A
A
A
A
A
A
Timer B
91
Mitsubishi microcomputer
s
M16C / 30 Grou
p
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTE
R
Item Specification
Count source f1, f8, f32, fC32
Count operation • Up count
• Counter value “000016” is transferred to reload register at measurement
pulse's effective edge and the timer continues counting
Count start condition Count start flag is set (= 1)
Count stop condition Count start flag is reset (= 0)
Interrupt request generation timing
• When measurement pulse's effective edge is input (Note 1)
• When an overflow occurs. (Simultaneously, the timer Bi overflow flag
changes to “1”. Assume that the count start flag condition is “1” and then the
timer Bi overflow flag becomes “1”. If the timer Bi mode register has a write-
access after next count cycle of the timer from the above condition, the timer
Bi overflow flag becomes “0”.)
TBiIN pin function Measurement pulse input
Read from timer When timer Bi register is read, it indicates the reload register’s content
(measurement result) (Note 2)
Write to timer Cannot be written to
(3) Pulse period/pulse width measurement mode
In this mode, the timer measures the pulse period or pulse width of an external signal. (See Table 1.14.8.)
Figure 1.14.19 shows the timer Bi mode register in pulse period/pulse width measurement mode. Figure
1.14.20 shows the operation timing when measuring a pulse period. Figure 1.14.21 shows the operation
timing when measuring a pulse width.
Table 1.14.8. Timer specifications in pulse period/pulse width measurement mode
Figure 1.14.19. Timer Bi mode register in pulse period/pulse width measurement mode
Note 1:
An interrupt request is not generated when the first effective edge is input after the timer has started counting.
Note 2: The value read out from the timer Bi register is indeterminate until the second effective edge is input
after the timer has started counting.
Timer Bi mode register Symbol Address When reset
TBiMR(i=1, 2) 039C16, 039D16 00XX00002
Bit nameBit symbol
WR
b7 b6 b5 b4 b3 b2 b1 b0
Operation mode
select bit 1 0 : Pulse period / pulse width
measurement mode
b1 b0
TMOD1
TMOD0
MR0 Measurement mode
select bit
MR1
MR3
TCK1
TCK0
01
0 0 : Pulse period measurement (Interval between
measurement pulse's falling edge to falling edge)
0 1 : Pulse period measurement (Interval between
measurement pulse's rising edge to rising edge)
1 0 : Pulse width measurement (Interval between
measurement pulse's falling edge to rising edge,
and between rising edge to falling edge)
1 1 : Must not be set.
Function
b3 b2
Nothing is assigned.
In an attempt to write to this bit, write “0”. The value, if read, turns out to be
indeterminate.
Count source
select bit
Timer Bi overflow
flag (Note) 0 : Timer did not overflow
1 : Timer has overflowed
0 0 : f1
0 1 : f8
1 0 : f32
1 1 : fC32
b7 b6
Note: It is indeterminate when reset. Assume that the count start flag condition is “1” and then the timer Bi
overflow flag becomes “1”. If the timer Bi mode register has a write access after next count cycle of
the timer from the above condition, the timer Bi overflow flag becomes “0”. This flag cannot be set
to “1” by software.
AA
AA
A
A
AA
A
AA
A
AA
A
AA
A
AA
AA
A
A
AA
Mitsubishi microcomputer
s
M16C / 30 Grou
p
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTE
R
Timer B
92
Figure 1.14.21. Operation timing when measuring a pulse width
Measurement pulse
“H”
Count source
Count start flag
Timer Bi interrupt
request bit
Timing at which counter
reaches “000016”
“1”
“1”
Transfer
(measured value) Transfer
(measured value)
“L”
“0”
“0”
Timer Bi overflow flag
“1”
“0”
Note 1: Counter is initialized at completion of measurement.
Note 2: Timer has overflowed.
(Note 1)(Note 1)(Note 1)
Transfer
(measured
value)
(Note 1)
Cleared to “0” when interrupt request is accepted, or cleared by software.
(Note 2)
Transfer
(indeterminate
value)
Reload register counter
transfer timing
Figure 1.14.20. Operation timing when measuring a pulse period
Count source
Measurement pulse
Count start flag
Timer Bi interrupt
request bit
Timing at which counter
reaches “0000
16
”
“H”
“1”
Transfer
(indeterminate value)
“L”
“0”
“0”
Timer Bi overflow flag
“1”
“0”
Note 1: Counter is initialized at completion of measurement.
Note 2: Timer has overflowed.
(Note 1)(Note 1)
When measuring measurement pulse time interval from falling edge to falling edge
(Note 2)
Cleared to “0” when interrupt request is accepted, or cleared by software.
Transfer
(measured value)
“1”
Reload register counter
transfer timing
Serial I/O
93
Mitsubishi microcomputer
s
M16C / 30 Grou
p
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTE
R
Serial I/O
Serial I/O is configured as three channels: UART0, UART1, UART2.
UART0, UART1 and UART2 each have an exclusive timer to generate a transfer clock, so they operate
independently of each other.
Figure 1.16.1 shows the block diagram of UART0, UART1 and UART2. Figures 1.16.2 and 1.16.3 show
the block diagram of the transmit/receive unit.
UARTi (i = 0 to 2) has two operation modes: a clock synchronous serial I/O mode and a clock asynchronous
serial I/O mode (UART mode). The contents of the serial I/O mode select bits (bits 0 to 2 at addresses
03A0
16
, 03A8
16
and 0378
16
) determine whether UARTi is used as a clock synchronous serial I/O or as a
UART. Although a few functions are different, UART0, UART1 and UART2 have almost the same functions.
UART2, in particular, is used for the SIM interface with some extra settings added in clock-asynchronous
serial I/O mode (Note). It also has the bus collision detection function that generates an interrupt request if
the TxD pin and the RxD pin are different in level.
Table 1.16.1 shows the comparison of functions of UART0 through UART2, and Figures 1.16.4 to 1.16.9
show the registers related to UARTi.
Note: SIM : Subscriber Identity Module
Note 1: Only when clock synchronous serial I/O mode.
Note 2: Only when clock synchronous serial I/O mode and 8-bit UART mode.
Note 3: Only when UART mode.
Note 4: Using for SIM interface.
UART0 UART1 UART2Function
CLK polarity selection
Continuous receive mode selection
LSB first / MSB first selection
Impossible
Transfer clock output from multiple
pins selection Impossible
ImpossibleSerial data logic switch Impossible
Sleep mode selection Impossible
ImpossibleTxD, RxD I/O polarity switch Impossible Possible
CMOS outputTxD, RxD port output format CMOS output N-channel open-drain
output
ImpossibleParity error signal output Impossible
ImpossibleBus collision detection Impossible Possible
Possible (Note 1)
Possible (Note 1)
Possible (Note 1)
Possible (Note 3)
Possible (Note 1)
Possible (Note 1)
Possible (Note 1)
Possible (Note 1)
Possible (Note 3)
Possible (Note 1)
Possible (Note 2)
Possible (Note 1)
Possible (Note 4)
Possible (Note 4)
Table 1.16.1. Comparison of functions of UART0 through UART2
Serial I/O
94
Mitsubishi microcomputer
s
M16C / 30 Grou
p
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTE
R
Figure 1.16.1. Block diagram of UARTi (i = 0 to 2)
n0 : Values set to UART0 bit rate generator (U0BRG)
n1 : Values set to UART1 bit rate generator (U1BRG)
n2 : Values set to UART2 bit rate generator (U2BRG)
RxD
2
Reception
control circuit
Transmission
control circuit
1 / (n
2
+1)
1/16
1/16
1/2
Bit rate generator
(address 0379
16
)
Clock synchronous type
(when internal clock is selected)
UART reception
Clock synchronous type
UART transmission
Clock synchronous type
Clock synchronous type
(when internal clock is selected)
Clock synchronous type
(when external clock is
selected)
Receive
clock
Transmit
clock
CLK
2
CTS
2
/ RTS
2
f
1
f
8
f
32
Vcc
RTS
2
CTS
2
TxD
2
(UART2)
RxD polarity
reversing circuit
TxD
polarity
reversing
circuit
RxD
0
1 / (n
0
+1)
1/2
Bit rate generator
(address 03A1
16
)
Clock synchronous type
(when internal clock is selected)
UART reception
Clock synchronous type
UART transmission
Clock synchronous type
Clock synchronous type
(when internal clock is selected)
Clock synchronous type
(when external clock is
selected)
Receive
clock
Transmit
clock
CLK
0
Clock source selection
CTS
0
/ RTS
0
f
1
f
8
f
32
Reception
control circuit
Transmission
control circuit
Internal
External
Vcc
RTS
0
CTS
0
TxD
0
Transmit/
receive
unit
RxD
1
1 / (n
1
+1)
1/16
1/16
1/2
Bit rate generator
(address 03A9
16
)
Clock synchronous type
(when internal clock is selected)
UART reception
Clock synchronous type
UART transmission
Clock synchronous type
Clock synchronous type
(when internal clock is selected)
Clock synchronous type
(when external clock is
selected)
Receive
clock
Transmit
clock
CLK
1
Clock source selection
f
1
f
8
f
32
Reception
control circuit
Transmission
control circuit
Internal
External
RTS
1
CTS
1
TxD
1
(UART1)
(UART0)
CLK
polarity
reversing
circuit
CLK
polarity
reversing
circuit
CTS/RTS disabled
Clock output pin
select switch
CTS
1
/ RTS
1
/
CLKS
1
CTS/RTS disabled
CTS/RTS selected
CTS/RTS disabled
V
CC
CTS/RTS disabled
CTS/RTS selected
CTS/RTS disabled
CTS/RTS disabled
CTS/RTS
selected
CLK
polarity
reversing
circuit
Internal
External
Clock source selection
Transmit/
receive
unit
Transmit/
receive
unit
1/16
1/16
Serial I/O
95
Mitsubishi microcomputer
s
M16C / 30 Grou
p
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTE
R
Figure 1.16.2. Block diagram of UARTi (i = 0, 1) transmit/receive unit
SP SP PAR
2SP
1SP
UART
UART (7 bits)
UART (8 bits)
UART (7 bits)
UART (9 bits)
Clock
synchronous
type
Clock synchronous
type
TxDi
UARTi transmit register
PAR
enabled
PAR
disabled
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
SP: Stop bit
PAR: Parity bit
UARTi transmit
buffer register
MSB/LSB conversion circuit
UART (8 bits)
UART (9 bits)
Clock synchronous
type
UARTi receive
buffer register
UARTi receive register
2SP
1SP
PAR
enabled
PAR
disabled
UART
UART (7 bits)
UART (9 bits)
Clock
synchronous
type
Clock
synchronous type
UART (7 bits)
UART (8 bits)
RxDi
Clock
synchronous type
UART (8 bits)
UART (9 bits)
Address 03A6
16
Address 03A7
16
Address 03AE
16
Address 03AF
16
Address 03A2
16
Address 03A3
16
Address 03AA
16
Address 03AB
16
Data bus low-order bits
MSB/LSB conversion circuit
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
8
0000000
SP SP PAR
“0”
Data bus high-order bits
Serial I/O
96
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s
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p
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTE
R
SP SP
PAR
2SP
1SP
UART
UART
(7 bits)
UART
(8 bits)
UART(7 bits)
UART
(9 bits)
Clock
synchronous
type
Clock
synchronous type
Data bus low-order bits
TxD2
UART2 transmit register
PAR
disabled
PAR
enabled
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0UART2 transmit
buffer register
UART
(8 bits)
UART
(9 bits)
Clock
synchronous type
UART2 receive
buffer register
UART2 receive register
2SP
1SP
UART
(7 bits)
UART
(8 bits) UART(7 bits)
UART
(9 bits)
Clock
synchronous type
Clock
synchronous type
RxD2
UART
(8 bits)
UART
(9 bits)
Address 037E
16
Address 037F
16
Address 037A
16
Address 037B
16
Data bus high-order bits
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
8
0000000
SP SP
PAR
“0”
Reverse
No reverse
Error signal
output circuit
RxD data
reverse circuit
Error signal output
enable
Error signal output
disable
Reverse
No reverse
Logic reverse circuit + MSB/LSB conversion circuit
Logic reverse circuit + MSB/LSB conversion circuit
PAR
enabled
PAR
disabled
UART
Clock
synchronous
type
TxD data
reverse circuit
SP: Stop bit
PAR: Parity bit
Figure 1.16.3. Block diagram of UART2 transmit/receive unit
Serial I/O
97
Mitsubishi microcomputer
s
M16C / 30 Grou
p
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTE
R
Figure 1.16.4. Serial I/O-related registers (1)
b7
UARTi bit rate generator (Note 1, 2)
b0
Symbol Address When reset
U0BRG 03A116 Indeterminate
U1BRG 03A916 Indeterminate
U2BRG 037916 Indeterminate
Function
Assuming that set value = n, BRGi divides the count source by
n + 1 0016 to FF16
Values that can be set WR
AA
b7 b0
(b15) (b8) b7 b0
UARTi transmit buffer register (Note)
Function
Transmit data
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate.
Symbol Address When reset
U0TB 03A316, 03A216 Indeterminate
U1TB 03AB16, 03AA16 Indeterminate
U2TB 037B16, 037A16 Indeterminate
WR
AA
(b15)
Symbol Address When reset
U0RB 03A716, 03A616 Indeterminate
U1RB 03AF16, 03AE16 Indeterminate
U2RB 037F16, 037E16 Indeterminate
b7 b0
(b8) b7 b0
UARTi receive buffer register
Function
(During UART mode)
Function
(During clock synchronous
serial I/O mode)
Bit name
Bit
symbol
0 : No framing error
1 : Framing error found
0 : No parity error
1 : Parity error found
0 : No error
1 : Error found
Note 1: Bits 15 through 12 are set to “0” when the serial I/O mode select bit (bits 2 to 0 at addresses 03A016,
03A816 and 037816) are set to “0002” or the receive enable bit is set to “0”.
(Bit 15 is set to “0” when bits 14 to 12 all are set to “0”.) Bits 14 and 13 are also set to “0” when the
lower byte of the UARTi receive buffer register (addresses 03A616, 03AE16 and 037E16) is read out.
Note 2: Arbitration lost detecting flag is allocated to U2RB and noting but “0” may be written. Nothing is
assigned in bit 11 of U0RB and U1RB. When write, set “0”. The value, if read, turns out to be “0”.
Invalid
Invalid
Invalid
OER
FER
PER
SUM
Overrun error flag (Note 1)
Framing error flag (Note 1)
Parity error flag (Note 1)
Error sum flag (Note 1)
0 : No overrun error
1 : Overrun error found
0 : No overrun error
1 : Overrun error found
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”.
Receive data
WR
Receive data
A
A
A
A
A
A
ABT Arbitration lost detecting
flag (Note 2) Invalid0 : Not detected
1 : Detected
A
AA
Note 1: Write a value to this register while transmit/receive halts.
Note 2: Use MOV instruction to write to this register.
Note: Use MOV instruction to write to this register.
Serial I/O
98
Mitsubishi microcomputer
s
M16C / 30 Grou
p
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTE
R
UARTi transmit/receive mode register
Symbol Address When reset
UiMR(i=0,1) 03A0
16
, 03A8
16
00
16
b7 b6 b5 b4 b3 b2 b1 b0
Bit name
Bit
symbol WR
Must always be “001”
0 0 0 : Serial I/O invalid
0 1 0 : Must not be set.
0 1 1 : Must not be set.
1 1 1 : Must not be set.
b2 b1 b0
CKDIR
SMD1
SMD0 Serial I/O mode select bit
SMD2
Internal/external clock
select bit
STPS
PRY
PRYE
SLEP
Parity enable bit
0 : Internal clock
1 : External clock (Note)
Stop bit length select bit
Odd/even parity select bit
Sleep select bit
0 : One stop bit
1 : Two stop bits
0 : Parity disabled
1 : Parity enabled
0 : Sleep mode deselected
1 : Sleep mode selected
1 0 0 : Transfer data 7 bits long
1 0 1 : Transfer data 8 bits long
1 1 0 : Transfer data 9 bits long
0 0 0 : Serial I/O invalid
0 1 0 : Must not be set.
0 1 1 : Must not be set.
1 1 1 : Must not be set.
b2 b1 b0
0 : Internal clock
1 : External clock (Note)
Invalid
Valid when bit 6 = “1”
0 : Odd parity
1 : Even parity
Invalid
Invalid
Must always be “0”
Function
(During UART mode)
Function
(During clock synchronous
serial I/O mode)
UART2 transmit/receive mode register
Symbol Address When reset
U2MR 0378
16
00
16
b7 b6 b5 b4 b3 b2 b1 b0
Bit name
Bit
symbol WR
Must always be “001”
0 0 0 : Serial I/O invalid
0 1 0 : (Note 1)
0 1 1 : Must not be set.
1 1 1 : Must not be set.
b2 b1 b0
CKDIR
SMD1
SMD0 Serial I/O mode select bit
SMD2
Internal/external clock
select bit
STPS
PRY
PRYE
IOPOL
Parity enable bit
0 : Internal clock
1 : External clock (Note 2)
Stop bit length select bit
Odd/even parity select bit
TxD, RxD I/O polarity
reverse bit
0 : One stop bit
1 : Two stop bits
0 : Parity disabled
1 : Parity enabled
0 : No reverse
1 : Reverse
Usually set to “0”
1 0 0 : Transfer data 7 bits long
1 0 1 : Transfer data 8 bits long
1 1 0 : Transfer data 9 bits long
0 0 0 : Serial I/O invalid
0 1 0 : Must not be set.
0 1 1 : Must not be set.
1 1 1 : Must not be set.
b2 b1 b0
Invalid
Valid when bit 6 = “1”
0 : Odd parity
1 : Even parity
Invalid
Invalid
0 : No reverse
1 : Reverse
Usually set to “0”
Function
(During UART mode)
Function
(During clock synchronous
serial I/O mode)
A
AA
A
AA
A
AA
A
AA
A
AA
A
A
AA
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
A
AA
AA
A
AA
Note 1: Bit 2 to bit 0 are set to “010
2
” when I
2
C mode is used.
Note 2: Set the corresponding port direction register to “0”.
Must always be “0”
Note : Set the corresponding port direction register to “0”.
Figure 1.16.5. Serial I/O-related registers (2)
Serial I/O
99
Mitsubishi microcomputer
s
M16C / 30 Grou
p
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTE
R
UARTi transmit/receive control register 0
Symbol Address When reset
UiC0(i=0,1) 03A4
16
, 03AC
16
08
16
b7 b6 b5 b4 b3 b2 b1 b0
Function
(During UART mode) WR
Function
(During clock synchronous
serial I/O mode)
TXEPT
CLK1
CLK0
CRS
CRD
NCH
CKPOL
BRG count source
select bit
Transmit register empty
flag
0 : Transmit data is output at
falling edge of transfer clock
and receive data is input at
rising edge
1 : Transmit data is output at
rising edge of transfer clock
and receive data is input at
falling edge
CLK polarity select bit
CTS/RTS function
select bit
CTS/RTS disable bit
Data output select bit
0 0 : f
1
is selected
0 1 : f
8
is selected
1 0 : f
32
is selected
1 1 : Must not be set.
b1 b0
0 : LSB first
1 : MSB first
0 : Data present in transmit
register (during transmission)
1 : No data present in transmit
register (transmission
completed)
0 : CTS/RTS function enabled
1 : CTS/RTS function disabled
(P6
0
and P6
4
function as
programmable I/O port)
0 : T
X
Di pin is CMOS output
1 : T
X
Di pin is N-channel
open-drain output
UFORM Transfer format select bit
0 0 : f
1
is selected
0 1 : f
8
is selected
1 0 : f
32
is selected
1 1 : Must not be set.
b1 b0
Valid when bit 4 = “0”
0 : CTS function is selected (Note 1)
1 : RTS function is selected (Note 2)
Valid when bit 4 = “0”
0 : CTS function is selected (Note 1)
1 : RTS function is selected (Note 2)
0 : Data present in transmit register
(during transmission)
1 : No data present in transmit
register (transmission completed)
0: T
X
Di pin is CMOS output
1: T
X
Di pin is N-channel
open-drain output
Must always be “0”
Bit name
Bit
symbol
Must always be “0”
Note 1: Set the corresponding port direction register to “0”.
Note 2: The settings of the corresponding port register and port direction register are invalid.
0 : CTS/RTS function enabled
1 : CTS/RTS function disabled
(P6
0
and P6
4
function as
programmable I/O port)
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
UART2 transmit/receive control register 0
Symbol Address When reset
U2C0 037C
16
08
16
b7 b6 b5 b4 b3 b2 b1 b0
Function
(During UART mode) WR
Function
(During clock synchronous
serial I/O mode)
TXEPT
CLK1
CLK0
CRS
CRD
CKPOL
BRG count source
select bit
Transmit register empty
flag
0 : Transmit data is output at
falling edge of transfer clock
and receive data is input at
rising edge
1 : Transmit data is output at
rising edge of transfer clock
and receive data is input at
falling edge
CLK polarity select bit
CTS/RTS function
select bit
CTS/RTS disable bit
0 0 : f
1
is selected
0 1 : f
8
is selected
1 0 : f
32
is selected
1 1 : Must not be set.
b1 b0
0 : LSB first
1 : MSB first
0 : Data present in transmit
register (during transmission)
1 : No data present in transmit
register (transmission
completed)
0 : CTS/RTS function enabled
1 : CTS/RTS function disabled
(P7
3
functions
programmable I/O port)
0 : TXDi pin is CMOS output
1 : TXDi pin is N-channel
open-drain output
UFORM Transfer format select bit
(Note 3)
0 0 : f
1
is selected
0 1 : f
8
is selected
1 0 : f
32
is selected
1 1 : Must not be set.
b1 b0
Valid when bit 4 = “0”
0 : CTS function is selected (Note 1)
1 : RTS function is selected (Note 2)
Valid when bit 4 = “0”
0 : CTS function is selected (Note 1)
1 : RTS function is selected (Note 2)
0 : Data present in transmit register
(during transmission)
1 : No data present in transmit
register (transmission completed)
0: TXDi pin is CMOS output
1: TXDi pin is N-channel
open-drain output
Must always be “0”
Bit name
Bit
symbol
Note 1: Set the corresponding port direction register to “0”.
Note 2: The settings of the corresponding port register and port direction register are invalid.
Note 3: Only clock synchronous serial I/O mode and 8-bit UART mode are valid.
0 : CTS/RTS function enabled
1 : CTS/RTS function disabled
(P7
3
functions programmable
I/O port)
Nothing is assigned.
In an attempt to write to this bit, write “0”. The value, if read, turns out to be “0”.
0 : LSB first
1 : MSB first
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
Figure 1.16.6. Serial I/O-related registers (3)
Serial I/O
100
Mitsubishi microcomputer
s
M16C / 30 Grou
p
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTE
R
Figure 1.16.7. Serial I/O-related registers (4)
UARTi transmit/receive control register 1
Symbol Address When reset
UiC1(i=0,1) 03A516
,
03AD16 0216
b7 b6 b5 b4 b3 b2 b1 b0
Bit name
Bit
symbol WR
Function
(During UART mode)
Function
(During clock synchronous
serial I/O mode)
TE
TI
RE
RI
Transmit enable bit
Receive enable bit
Receive complete flag
Transmit buffer
empty flag
0 : Transmission disabled
1 : Transmission enabled
0 : Data present in
transmit buffer register
1 : No data present in
transmit buffer register
0 : Reception disabled
1 : Reception enabled
0 : Transmission disabled
1 : Transmission enabled
0 : Data present in
transmit buffer register
1 : No data present in
transmit buffer register
0 : Reception disabled
1 : Reception enabled
0 : No data present in
receive buffer register
1 : Data present in
receive buffer register
0 : No data present in
receive buffer register
1 : Data present in
receive buffer register
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”.
UART2 transmit/receive control register 1
Symbol Address When reset
U2C1 037D16 0216
b7 b6 b5 b4 b3 b2 b1 b0
Bit name
Bit
symbol WR
Function
(During UART mode)
Function
(During clock synchronous
serial I/O mode)
TE
TI
RE
RI
Transmit enable bit
Receive enable bit
Receive complete flag
Transmit buffer
empty flag
0 : Transmission disabled
1 : Transmission enabled
0 : Data present in
transmit buffer register
1 : No data present in
transmit buffer register
0 : Reception disabled
1 : Reception enabled
0 : Transmission disabled
1 : Transmission enabled
0 : Data present in
transmit buffer register
1 : No data present in
transmit buffer register
0 : Reception disabled
1 : Reception enabled
0 : No data present in
receive buffer register
1 : Data present in
receive buffer register
0 : No data present in
receive buffer register
1 : Data present in
receive buffer register
U2IRS UART2 transmit interrupt
cause select bit 0 : Transmit buffer empty
(TI = 1)
1 : Transmit is completed
(TXEPT = 1)
0 : Transmit buffer empty
(TI = 1)
1 : Transmit is completed
(TXEPT = 1)
U2RRM UART2 continuous
receive mode enable bit 0 : Continuous receive
mode disabled
1 : Continuous receive
mode enabled
Must always be "0"
Data logic select bit 0 : No reverse
1 : Reverse 0 : No reverse
1 : Reverse
U2LCH
U2ERE Error signal output
enable bit Must always be "0" 0 : Output disabled
1 : Output enabled
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
Serial I/O
101
Mitsubishi microcomputer
s
M16C / 30 Grou
p
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTE
R
Note: When using multiple pins to output the transfer clock, the following requirements must be met:
• UART1 internal/external clock select bit (bit 3 at address 03A8
16
) = “0”.
UART transmit/receive control register 2
Symbol Address When reset
UCON 03B0
16
X0000000
2
b7 b6 b5 b4 b3 b2 b1 b0
Bit
name
Bit
symbol WR
Function
(During UART mode)
Function
(During clock synchronous
serial I/O mode)
CLKMD0
CLKMD1
Reserved bit
UART0 transmit
interrupt cause select bit
UART0 continuous
receive mode enable bit 0 : Continuous receive
mode disabled
1 : Continuous receive
mode enable
UART1 continuous
receive mode enable bit
CLK/CLKS select bit 0
UART1 transmit
interrupt cause select bit
0 :
Transmit buffer empty (Tl = 1)
1 : Transmission completed
(TXEPT = 1)
0 :
Transmit buffer empty (Tl = 1)
1 : Transmission completed
(TXEPT = 1)
0 : Normal mode
(CLK output is CLK1 only)
1 : Transfer clock output
from multiple pins
function selected
0 : Continuous receive
mode disabled
1 : Continuous receive
mode enabled
Nothing is assigned.
In an attempt to write to this bit, write “0”. The value, if read, turns out to be indeterminate.
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed
(TXEPT = 1)
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed
(TXEPT = 1)
Must always be “0”
U0IRS
U1IRS
U0RRM
U1RRM
Invalid
CLK/CLKS select
bit 1 (Note)
Valid when bit 5 = “1”
0 : Clock output to CLK1
1 : Clock output to CLKS1
A
AA
A
AA
A
AA
A
A
AA
AA
A
AA
A
AA
A
AA
UART2 special mode register
Symbol Address When reset
U2SMR 0377
16
00
16
b7 b6 b5 b4 b3 b2 b1 b0
Bit
name
Bit
symbol WR
Function
(During UART mode)
Function
(During clock synchronous
serial I/O mode)
ABSCS
ACSE
SSS
I
2
C mode select bit
Bus busy flag
0 : STOP condition detected
1 : START condition detected
SCLL sync output
enable bit
Bus collision detect
sampling
clock select bit
Arbitration lost detecting
flag control bit
0 : Normal mode
1 : I
2
C mode
0 : Update per bit
1 : Update per byte
IICM
ABC
BBS
LSYN
0 : Ordinary
1 : Falling edge of R
X
D
2
0 : Disabled
1 : Enabled
Transmit start condition
select bit
Must always be “0”
0 : Rising edge of transfer
clock
1 : Underflow signal of timer A0
Auto clear function
select bit of transmit
enable bit
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
0 : No auto clear function
1 : Auto clear at occurrence of
bus collision
Must always be “0”
Must always be “0”
Must always be “0”
Must always be “0”
Must always be “0”
Must always be “0”
Note 1: Nothing but “0” may be written.
Note 2: When not in I
2
C mode, do not set this bit by writing a “1”. During normal mode, set it to “0”. When this
bit = “0”, UART2 special mode register 3 (U2SMR3 at address 0375
16
) bits 7 to 5 (DL2 to DL0 = SDA
digital delay setup bits) are initialized to “000”, with the analog delay circuit selected. Also, when SDDS
= “0”, the U2SMR3 register cannot be read or written to.
Note 3: When analog delay is selected, only the analog delay value is effective; when digital delay is selected,
only the digital delay value is effective.
(Note1)
A
A
A
A
SDDS SDA digital delay select
bit (Note 2, Note 3) Must always be “0”
0 : Analog delay output
is selected
1 : Digital delay output
is selected
(must always be “0” when
not using I C mode)
2
Must always be set to
“0”
0
Must always be “0”
Must always be “0”
Figure 1.16.8. Serial I/O-related registers (5)
Serial I/O
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTE
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Figure 1.16.9. Serial I/O-related registers (6)
UART2 special mode register 2 (I C bus exclusive use register)
Symbol Address When reset
U2SMR2 037616 0016
b7 b6 b5 b4 b3 b2 b1 b0
Bit name
Bit
symbol WR
Function
(I2C bus exclusive use)
STAC
SWC2
SDHI
I C mode select bit 2
SCL wait output bit 0 : Disabled
1 : Enabled
SDA output stop bit
UART2 initialization bit
Clock-synchronous bit
Refer to Table 1.16.11
0 : Disabled
1 : Enabled
IICM2
CSC
SWC
ALS 0 : Disabled
1 : Enabled
SDA output disable bit
SCL wait output bit 2
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
0: Enabled
1: Disabled (high impedance)
0 : Disabled
1 : Enabled
0: UART2 clock
1: 0 output
2
SHTC Start/stop condition
control bit 1: Set this bit to “1” in I2C mode
(refer to Table 1.16.12)
A
A
2
UART2 special mode register 3 (I C bus exclusive use register)
Symbol Address When reset
U2SMR3 037516 Indeterminate
(However, when SDDS = “1”, the initial value is “0016”)
b7 b6 b5 b4 b3 b2 b1 b0
Bit name
Bit
symbol WR
Function
(I C bus exclusive use register)
DL2
SDA digital delay setup
bit
(Note 1, Note 2, Note 3,
Note 4)
DL0
DL1
A
A
A
A
A
A
0 0 0 : Analog delay is selected
0 0 1 : 1 to 2 cycle(s) of 1/f(XIN)
0 1 0 : 2 to 3 cycles of 1/f(XIN)
0 1 1 : 3 to 4 cycles of 1/f(XIN)
1 0 0 : 4 to 5 cycles of 1/f(XIN)
1 0 1 : 5 to 6 cycles of 1/f(XIN)
1 1 0 : 6 to 7 cycles of 1/f(XIN)
1 1 1 : 7 to 8 cycles of 1/f(XIN)
2
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be
indeterminate. However, when SDDS = “1”, the value “0” is read out (Note 1)
2
b7 b6 b5
Note 1: This bit can be read or written to when UART2 special mode register (U2SMR at address 037716) bit
7 (SDDS: SDA digital delay select bit) = “1”. When the initial value of UART2 special mode register 3
(U2SMR3) is read after setting SDDS = “1”, the value is “0016”. When writing to UART2 special mode
register 3 (U2SMR3) after setting SDDS = “1”, be sure to write 0's to bits 0–4. When SDDS = “0”,
this register cannot be written to; when read, the value is indeterminate.
Note 2: These bits are initialized to “000” when SDDS = “0”, with the analog delay circuit selected. After a reset,
these bits are set to “000”, with the analog delay circuit selected. However, because these bits can be
read only when SDDS = “1”, the value read from these bits when SDDS = “0” is indeterminate.
Note 3: When analog delay is selected, only the analog delay value is effective; when digital delay is selected,
only the digital delay value is effective.
Note 4: The amount of delay varies with the load on SCL and SDA pins. Also, when using an external clock, the
amount of delay increases by about 100 ns, so be sure to take this into account when using the device.
Digital delay
is selected
Clock synchronous serial I/O mode
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(1) Clock synchronous serial I/O mode
The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. Tables 1.16.2
and 1.16.3 list the specifications of the clock synchronous serial I/O mode. Figure 1.16.10 shows the
UARTi transmit/receive mode register.
Table 1.16.2. Specifications of clock synchronous serial I/O mode (1)
Item Specification
Transfer data format • Transfer data length: 8 bits
Transfer clock • When internal clock is selected (bit 3 at addresses 03A016, 03A816, 037816
= “0”) : fi/ 2(n+1) (Note 1) fi = f1, f8, f32
• When external clock is selected (bit 3 at addresses 03A016, 03A816, 037816
= “1”) : Input from CLKi pin
Transmission/reception control
_______ _______ _______ _______
• CTS function, RTS function, CTS and RTS function invalid: selectable
Transmission start condition
• To start transmission, the following requirements must be met:
_ Transmit enable bit (bit 0 at addresses 03A516, 03AD16, 037D16) = “1”
_
Transmit buffer empty flag (bit 1 at addresses 03A5
16
, 03AD
16
, 037D
16
) = “0”
_______ _______
_ When CTS function selected, CTS input level = “L”
•
Furthermore, if external clock is selected, the following requirements must also be met:
_ CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16, 037C16) = “0”:
CLKi input level = “H”
_ CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16, 037C16) = “1”:
CLKi input level = “L”
Reception start condition • To start reception, the following requirements must be met:
_ Receive enable bit (bit 2 at addresses 03A516, 03AD16, 037D16) = “1”
_ Transmit enable bit (bit 0 at addresses 03A516, 03AD16, 037D16) = “1”
_
Transmit buffer empty flag (bit 1 at addresses 03A5
16
, 03AD
16
, 037D
16
) = “0”
• Furthermore, if external clock is selected, the following requirements must
also be met:
_ CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16, 037C16) = “0”:
CLKi input level = “H”
_ CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16, 037C16) = “1”:
CLKi input level = “L”
• When transmitting
_ Transmit interrupt cause select bit (bits 0, 1 at address 03B016, bit 4 at
address 037D16) = “0”: Interrupts requested when data transfer from UARTi
transfer buffer register to UARTi transmit register is completed
_ Transmit interrupt cause select bit (bits 0, 1 at address 03B016, bit 4 at
address 037D16) = “1”: Interrupts requested when data transmission from
UARTi transfer register is completed
• When receiving
_ Interrupts requested when data transfer from UARTi receive register to
UARTi receive buffer register is completed
Error detection • Overrun error (Note 2)
This error occurs when the next data is ready before contents of UARTi
receive buffer register are read out
Interrupt request
generation timing
Note 1: “n” denotes the value 0016 to FF16 that is set to the UART bit rate generator.
Note 2: If an overrun error occurs, the UARTi receive buffer will have the next data written in. Note also that
the UARTi receive interrupt request bit does not change.
Clock synchronous serial I/O mode
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Item Specification
Select function • CLK polarity selection
Whether transmit data is output/input timing at the rising edge or falling edge
of the transfer clock can be selected
• LSB first/MSB first selection
Whether transmission/reception begins with bit 0 or bit 7 can be selected
• Continuous receive mode selection
Reception is enabled simultaneously by a read from the receive buffer register
• Transfer clock output from multiple pins selection (UART1)
UART1 transfer clock can be chosen by software to be output from one of
the two pins set
• Switching serial data logic (UART2)
Whether to reverse data in writing to the transmission buffer register or
reading the reception buffer register can be selected.
• TxD, RxD I/O polarity reverse (UART2)
This function is reversing TxD port output and RxD port input. All I/O data
level is reversed.
Table 1.16.3. Specifications of clock synchronous serial I/O mode (2)
Clock synchronous serial I/O mode
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Figure 1.16.10. UARTi transmit/receive mode register in clock synchronous serial I/O mode
Symbol Address When reset
UiMR(i=0,1) 03A0
16
, 03A8
16
00
16
CKDIR
UARTi transmit/receive mode registers
Internal/external clock
select bit
STPS
PRY
PRYE
SLEP
0 : Internal clock
1 : External clock (Note)
Bit name FunctionBit symbol WR
b7 b6 b5 b4 b3 b2 b1 b0
0 (Must always be “0” in clock synchronous serial I/O mode)
010
SMD0
SMD1
SMD2
Serial I/O mode select bit 0 0 1 : Clock synchronous serial
I/O mode
b2 b1 b0
0
Invalid in clock synchronous serial I/O mode
Symbol Address When reset
U2MR 0378
16
00
16
CKDIR
UART2 transmit/receive mode register
Internal/external clock
select bit
STPS
PRY
PRYE
IOPOL
0 : Internal clock
1 : External clock (Note 2)
Bit name FunctionBit symbol WR
b7 b6 b5 b4 b3 b2 b1 b0
010
SMD0
SMD1
SMD2
Serial I/O mode select bit 0 0 1 : Clock synchronous serial
I/O mode
b2 b1 b0
0
Invalid in clock synchronous serial I/O mode
TxD, RxD I/O polarity
reverse bit (Note 1) 0 : No reverse
1 : Reverse
Note 1: Usually set to “0”.
Note 2: Set the corresponding port direction register to “0”.
A
AA
A
A
AA
AA
A
AA
A
AA
A
A
AA
AA
A
AA
A
A
AA
AA
A
AA
A
AA
A
A
AA
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
A
AA
AA
Note : Set the corresponding port direction register to “0”.
Clock synchronous serial I/O mode
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Table 1.16.4 lists the functions of the input/output pins during clock synchronous serial I/O mode. This
table shows the pin functions when the transfer clock output from multiple pins function is not selected.
Note that for a period from when the UARTi operation mode is selected to when transfer starts, the TxDi
pin outputs an “H”. (If the N-channel open-drain is selected, this pin is in floating state.)
Table 1.16.4. Input/output pin functions in clock synchronous serial I/O mode
Pin name Function Method of selection
TxDi
(P6
3
, P6
7
, P7
0
)Serial data output
Serial data input
Transfer clock output
Transfer clock input
Programmable I/O port
(Outputs dummy data when performing reception only)
RxDi
(P6
2
, P6
6
, P7
1
)
CLKi
(P6
1
, P6
5
, P7
2
)Internal/external clock select bit (bit 3 at address 03A0
16
, 03A8
16
, 0378
16
) = “0”
Internal/external clock select bit (bit 3 at address 03A0
16
, 03A8
16
, 0378
16
) = “1”
Port P6
1
, P6
5
and P7
2
direction register (bits 1 and 5 at address 03EE
16
,
bit 2 at address 03EF
16
) = “0”
Port P6
2
, P6
6
and P7
1
direction register (bits 2 and 6 at address 03EE
16
,
bit 1 at address 03EF
16
)= “0”
(Can be used as an input port when performing transmission only)
CTS/RTS disable bit (bit 4 at address 03A4
16
, 03AC
16
, 037C
16
) =“0”
CTS/RTS function select bit (bit 2 at address 03A4
16
, 03AC
16
, 037C
16
) = “0”
Port P6
0
, P6
4
and P7
3
direction register (bits 0 and 4 at address 03EE
16
,
bit 3 at address 03EF
16
) = “0”
CTS/RTS disable bit (bit 4 at address 03A4
16
, 03AC
16
, 037C
16)
= “0”
CTS/RTS function select bit (bit 2 at address 03A4
16
, 03AC
16
, 037C
16
) = “1”
CTS/RTS disable bit (bit 4 at address 03A4
16
, 03AC
16
, 037C
16
) = “1”
CTS input
RTS output
CTSi/RTSi
(P6
0
, P6
4
, P7
3
)
(when transfer clock output from multiple pins is not selected)
Clock synchronous serial I/O mode
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Figure 1.16.11. Typical transmit/receive timings in clock synchronous serial I/O mode
• Example of transmit timing (when internal clock is selected)
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
Tc
T
CLK
Stopped pulsing because transfer enable bit = “0”
Data is set in UARTi transmit buffer register
Tc = TCLK = 2(n + 1) / fi
fi: frequency of BRGi count source (f
1
, f
8
, f
32
)
n: value set to BRGi
Transfer clock
Transmit enable
bit (TE)
Transmit buffer
empty flag (Tl)
CLKi
TxDi
Transmit
register empty
flag (TXEPT)
“H”
“L”
“0”
“1”
“0”
“1”
“0”
“1”
CTSi
The above timing applies to the following settings:
• Internal clock is selected.
• CTS function is selected.
• CLK polarity select bit = “0”.
• Transmit interrupt cause select bit = “0”.
Transmit interrupt
request bit (IR)
“0”
“1”
Stopped pulsing because CTS = “H”
Transferred from UARTi transmit buffer register to UARTi transmit register
Shown in ( ) are bit symbols. Cleared to “0” when interrupt request is accepted, or cleared by software
1 / f
EXT
Dummy data is set in UARTi transmit buffer register
Transmit enable
bit (TE)
Transmit buffer
empty flag (Tl)
CLKi
RxDi
Receive complete
flag (Rl)
RTSi
“H”
“L”
“0”
“1”
“0”
“1”
“0”
“1”
Receive enable
bit (RE)
“0”
“1”
Receive data is taken in
Transferred from UARTi transmit buffer register to UARTi transmit register
Read out from UARTi receive buffer register
The above timing applies to the following settings:
• External clock is selected.
• RTS function is selected.
• CLK polarity select bit = “0”.
f
EXT
: frequency of external clock
Transferred from UARTi receive register
to UARTi receive buffer register
Receive interrupt
request bit (IR)
“0”
“1”
D0D1D2D3D4D5D6D7D0D1D2D3D4D5
Shown in ( ) are bit symbols.
Meet the following conditions are met when the CLK
input before data reception = “H”
• Transmit enable bit “1”
• Receive enable bit “1”
• Dummy data write to UARTi transmit buffer register
Cleared to “0” when interrupt request is accepted, or cleared by software
• Example of receive timing (when external clock is selected)
Clock synchronous serial I/O mode
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(a) Polarity select function
As shown in Figure 1.16.12, the CLK polarity select bit (bit 6 at addresses 03A416, 03AC16, 037C16)
allows selection of the polarity of the transfer clock.
• When CLK polarity select bit = “1”
Note 2: The CLKi pin level when not
transferring data is “L”.
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
0
D
0
T
X
D
i
R
X
D
i
CLK
i
• When CLK polarity select bit = “0”
Note 1: The CLKi pin level when not
transferring data is “H”.
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
0
T
X
D
i
R
X
D
i
CLK
i
Figure 1.16.12. Polarity of transfer clock
(b) LSB first/MSB first select function
As shown in Figure 1.16.13, when the transfer format select bit (bit 7 at addresses 03A416, 03AC16,
037C16) = “0”, the transfer format is “LSB first”; when the bit = “1”, the transfer format is “MSB first”.
Figure 1.16.13. Transfer format
LSB first
• When transfer format select bit = “0”
D0
D0
D1D2D3D4D5D6D7
D1D2D3D4D5D6D7
TXDi
RXDi
CLKi
• When transfer format select bit = “1”
D6D5D4D3D2D1D0
D7
D7D6D5D4D3D2D1D0
TXDi
RXDi
CLKi
MSB first
Note: This applies when the CLK polarity select bit = “0”.
Clock synchronous serial I/O mode
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(c) Transfer clock output from multiple pins function (UART1)
This function allows the setting two transfer clock output pins and choosing one of the two to output a
clock by using the CLK and CLKS select bit (bits 4 and 5 at address 03B016). (See Figure 1.16.14.)
The multiple pins function is valid only when the internal clock is selected for UART1.
Figure 1.16.14. The transfer clock output from the multiple pins function usage
Microcomputer
TXD1 (P67)
CLKS1 (P64)
CLK1 (P65)IN
CLK
IN
CLK
Note: This applies when the internal clock is selected and transmission
is performed only in clock synchronous serial I/O mode.
(d) Continuous receive mode
If the continuous receive mode enable bit (bits 2 and 3 at address 03B016, bit 5 at address 037D16) is
set to “1”, the unit is placed in continuous receive mode. In this mode, when the receive buffer register
is read out, the unit simultaneously goes to a receive enable state without having to set dummy data to
the transmit buffer register back again.
(e) Serial data logic switch function (UART2)
When the data logic select bit (bit6 at address 037D
16
) = “1”, and writing to transmit buffer register or
reading from receive buffer register, data is reversed. Figure 1.16.15 shows the example of serial data
logic switch timing.
Figure
1.16.15.
Serial data logic switch timing
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
Transfer clock
TxD
2
(no reverse)
TxD
2
(reverse)
“H”
“L”
“H”
“L”
“H”
“L”
•When LSB first
Clock asynchronous serial I/O (UART) mode
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Item Specification
Transfer data format • Character bit (transfer data): 7 bits, 8 bits, or 9 bits as selected
• Start bit: 1 bit
• Parity bit: Odd, even, or nothing as selected
• Stop bit: 1 bit or 2 bits as selected
Transfer clock •
When internal clock is selected (bit 3 at addresses 03A016, 03A816, 037816 = “0”) :
fi/16(n+1) (Note 1) fi = f1, f8, f32
•
When external clock is selected (bit 3 at addresses 03A016, 03A816 =“1”) :
fEXT/16(n+1) (Note 1) (Note 2) (Do not set external clock for UART2)
Transmission/reception control
_______ _______ _______ _______
• CTS function, RTS function, CTS and RTS function invalid: selectable
Transmission start condition
• To start transmission, the following requirements must be met:
- Transmit enable bit (bit 0 at addresses 03A516, 03AD16, 037D16) = “1”
-
Transmit buffer empty flag (bit 1 at addresses 03A5
16
, 03AD
16
, 037D
16
) = “0”
_______ _______
- When CTS function selected, CTS input level = “L”
Reception start condition • To start reception, the following requirements must be met:
- Receive enable bit (bit 2 at addresses 03A516, 03AD16, 037D16) = “1”
- Start bit detection
Interrupt request • When transmitting
generation timing - Transmit interrupt cause select bits (bits 0,1 at address 03B016, bit4 at
address 037D16) = “0”: Interrupts requested when data transfer from UARTi
transfer buffer register to UARTi transmit register is completed
- Transmit interrupt cause select bits (bits 0, 1 at address 03B016, bit4 at
address 037D16) = “1”: Interrupts requested when data transmission from
UARTi transfer register is completed
• When receiving
- Interrupts requested when data transfer from UARTi receive register to
UARTi receive buffer register is completed
Error detection • Overrun error (Note 3)
This error occurs when the next data is ready before contents of UARTi
receive buffer register are read out
• Framing error
This error occurs when the number of stop bits set is not detected
• Parity error
This error occurs when if parity is enabled, the number of 1’s in parity and
character bits does not match the number of 1’s set
• Error sum flag
This flag is set (= 1) when any of the overrun, framing, and parity errors is
encountered
(2) Clock asynchronous serial I/O (UART) mode
The UART mode allows transmitting and receiving data after setting the desired transfer rate and transfer
data format. Tables 1.16.5 and 1.16.6 list the specifications of the UART mode. Figure 1.16.16 shows
the UARTi transmit/receive mode register.
Table 1.16.5. Specifications of UART Mode (1)
Note 1: ‘n’ denotes the value 0016 to FF16 that is set to the UARTi bit rate generator.
Note 2: fEXT is input from the CLKi pin.
Note 3: If an overrun error occurs, the UARTi receive buffer will have the next data written in. Note also that
the UARTi receive interrupt request bit does not change.
Clock asynchronous serial I/O (UART) mode
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Table 1.16.6. Specifications of UART Mode (2)
Item Specification
Select function • Sleep mode selection (UART0, UART1)
This mode is used to transfer data to and from one of multiple slave micro-
computers
• Serial data logic switch (UART2)
This function is reversing logic value of transferring data. Start bit, parity bit
and stop bit are not reversed.
•TXD, RXD I/O polarity switch (UART2)
This function is reversing TXD port output and RXD port input. All I/O data
level is reversed.
Clock asynchronous serial I/O (UART) mode
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Figure 1.16.16. UARTi transmit/receive mode register in UART mode
Symbol Address When reset
UiMR(i=0,1) 03A0
16
, 03A8
16
00
16
CKDIR
UARTi transmit / receive mode registers
Internal / external clock
select bit
STPS
PRY
PRYE
SLEP
0 : Internal clock
1 : External clock (Note)
Bit name FunctionBit symbol
WR
b7 b6 b5 b4 b3 b2 b1 b0
SMD0
SMD1
SMD2
Serial I/O mode select bit
b2 b1 b0
0 : One stop bit
1 : Two stop bits
0 : Parity disabled
1 : Parity enabled
0 : Sleep mode deselected
1 : Sleep mode selected
1 0 0 : Transfer data 7 bits long
1 0 1 : Transfer data 8 bits long
1 1 0 : Transfer data 9 bits long
Valid when bit 6 = “1”
0 : Odd parity
1 : Even parity
Stop bit length select bit
Odd / even parity
select bit
Parity enable bit
Sleep select bit
Symbol Address When reset
U2MR 0378
16
00
16
CKDIR
UART2 transmit / receive mode register
Internal / external clock
select bit
STPS
PRY
PRYE
IOPOL
Must always be “0”
Bit name FunctionBit symbol
WR
b7 b6 b5 b4 b3 b2 b1 b0
SMD0
SMD1
SMD2
Serial I/O mode select bit
b2 b1 b0
0 : One stop bit
1 : Two stop bits
0 : Parity disabled
1 : Parity enabled
0 : No reverse
1 : Reverse
1 0 0 : Transfer data 7 bits long
1 0 1 : Transfer data 8 bits long
1 1 0 : Transfer data 9 bits long
Valid when bit 6 = “1”
0 : Odd parity
1 : Even parity
Stop bit length select bit
Odd / even parity
select bit
Parity enable bit
TxD, RxD I/O polarity
reverse bit (Note)
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
Note: Usually set to “0”.
Note : Set the corresponding port direction register to “0”.
Clock asynchronous serial I/O (UART) mode
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Table 1.16.7 lists the functions of the input/output pins during UART mode. Note that for a period from
when the UARTi operation mode is selected to when transfer starts, the TxDi pin outputs an “H”. (If the N-
channel open-drain is selected, this pin is in floating state.)
Table 1.16.7. Input/output pin functions in UART mode
Pin name Function Method of selection
TxDi
(P6
3
, P6
7
, P7
0
)Serial data output
Serial data input
Programmable I/O port
Transfer clock input
Programmable I/O port
RxDi
(P6
2
, P6
6
, P7
1
)
CLKi
(P6
1
, P6
5
, P7
2
)Internal/external clock select bit (bit 3 at address 03A0
16
, 03A8
16
, 0378
16
) = “0”
Internal/external clock select bit (bit 3 at address 03A0
16
, 03A8
16
) = “1”
Port P6
1
, P6
5
direction register (bits 1 and 5 at address 03EE
16
) = “0”
(Do not set external clock for UART2)
Port P6
2
, P6
6
and P7
1
direction register (bits 2 and 6 at address 03EE
16
,
bit 1 at address 03EF
16
)= “0”
(Can be used as an input port when performing transmission only)
CTS/RTS disable bit (bit 4 at address 03A4
16
, 03AC
16
, 037C
16
) =“0”
CTS/RTS function select bit (bit 2 at address 03A4
16
, 03AC
16
, 037C
16
) = “0”
Port P6
0
, P6
4
and P7
3
direction register (bits 0 and 4 at address 03EE
16
,
bit 3 at address 03EF
16
) = “0”
CTS/RTS disable bit (bit 4 at address 03A4
16
, 03AC
16
, 037C
16)
= “0”
CTS/RTS function select bit (bit 2 at address 03A4
16
, 03AC
16
, 037C
16
) = “1”
CTS/RTS disable bit (bit 4 at address 03A4
16
, 03AC
16
, 037C
16
) = “1”
CTS input
RTS output
CTSi/RTSi
(P6
0
, P6
4
, P7
3
)
Clock asynchronous serial I/O (UART) mode
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Transmit enable
bit(TE)
Transmit buffer
empty flag(TI)
Transmit register
empty flag (TXEPT)
Start
bit Parity
bit
TxDi
CTSi
The above timing applies to the following settings :
• Parity is enabled.
• One stop bit.
• CTS function is selected.
• Transmit interrupt cause select bit = “1”.
“1”
“0”
“1”
“L”
“H”
“0”
“1”
Tc = 16 (n + 1) / fi or 16 (n + 1) / f
EXT
fi : frequency of BRGi count source (f
1
, f
8
, f
32
)
f
EXT
: frequency of BRGi count source (external clock)
n : value set to BRGi
Transmit interrupt
request bit (IR)
“0”
“1”
Cleared to “0” when interrupt request is accepted, or cleared by software
Transmit enable
bit(TE)
Transmit buffer
empty flag(TI)
TxDi
Transmit register
empty flag (TXEPT)
“0”
“1”
“0”
“1”
“0”
“1”
The above timing applies to the following settings :
• Parity is disabled.
• Two stop bits.
• CTS function is disabled.
• Transmit interrupt cause select bit = “0”.
Transfer clock
Tc
Tc = 16 (n + 1) / fi or 16 (n + 1) / f
EXT
fi : frequency of BRGi count source (f
1
, f
8
, f
32
)
f
EXT
: frequency of BRGi count source (external clock)
n : value set to BRGi
Transmit interrupt
request bit (IR)
“0”
“1”
Shown in ( ) are bit symbols.
Shown in ( ) are bit symbols.
Tc
Transfer clock
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
ST PD
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
SP ST PSP D
0
D
1
ST
Stopped pulsing because transmit enable bit = “0”
Stop
bit
Transferred from UARTi transmit buffer register to UARTi transmit register
Start
bit
The transfer clock stops momentarily as CTS is “H” when the stop bit is checked.
The transfer clock starts as the transfer starts immediately CTS changes to “L”.
Data is set in UARTi transmit buffer register
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
ST SP
D
8
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
ST D
8
D
0
D
1
ST
SPSP
Transferred from UARTi transmit buffer register to UARTi transmit register
Stop
bit Stop
bit
Data is set in UARTi transmit buffer register.
“0”
SP
Cleared to “0” when interrupt request is accepted, or cleared by software
• Example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit)
• Example of transmit timing when transfer data is 9 bits long (parity disabled, two stop bits)
Figure 1.16.17. Typical transmit timings in UART mode(UART0,UART1)
Clock asynchronous serial I/O (UART) mode
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Figure 1.16.18. Typical transmit timings in UART mode(UART2)
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
ST P
Start
bit Parity
bit
Cleared to “0” when interrupt request is accepted, or cleared by software
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
ST P
Tc
SP
Stop
bit
Data is set in UART2 transmit buffer register
Transferred from UART2 transmit buffer register to UARTi transmit register
SP
Transmit enable
bit(TE)
Transmit buffer
empty flag(TI)
Transmit register
empty flag (TXEPT)
“0”
“1”
“0”
“1”
“0”
“1”
Transmit interrupt
request bit (IR)
“0”
“1”
Transfer clock
TxD2
The above timing applies to the following settings :
• Parity is enabled.
• One stop bit.
• Transmit interrupt cause select bit = “1”.
Tc = 16 (n + 1) / fi
fi : frequency of BRG2 count source (f
1
, f
8
, f
32
)
n : value set to BRG2
Shown in ( ) are bit symbols.
Note
Note: The transmit is started with overflow timing of BRG after having written in a value at the transmit buffer in the above timing.
• Example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit)
Clock asynchronous serial I/O (UART) mode
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(b) Function for switching serial data logic (UART2)
When the data logic select bit (bit 6 of address 037D16) is assigned “1”, data is inverted in writing to the
transmission buffer register or reading the reception buffer register. Figure 1.16.20 shows the ex-
ample of timing for switching serial data logic.
Figure 1.16.20. Timing for switching serial data logic
ST : Start bit
P : Even parity
SP : Stop bit
D0 D1 D2 D3 D4 D5 D6 D7 P SPST
SPST D3 D4 D5 D6 D7 PD0 D1 D2
Transfer clock
TxD
2
(no reverse)
TxD
2
(reverse)
“H”
“L”
“H”
“L”
“H”
“L”
• When LSB first, parity enabled, one stop bit
• Example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit)
Figure 1.16.19. Typical receive timing in UART mode
(a) Sleep mode (UART0, UART1)
This mode is used to transfer data between specific microcomputers among multiple microcomputers
connected using UARTi. The sleep mode is selected when the sleep select bit (bit 7 at addresses
03A016, 03A816) is set to “1” during reception. In this mode, the unit performs receive operation when
the MSB of the received data = “1” and does not perform receive operation when the MSB = “0”.
D0
Start bit
Sampled “L” Receive data taken in
BRGi count
source
Receive enable bit
RxDi
Transfer clock
Receive
complete flag
RTSi
Stop bit
“1”
“0”
“0”
“1”
“H”
“L”
The above timing applies to the following settings :
•Parity is disabled.
•One stop bit.
•RTS function is selected.
Receive interrupt
request bit “0”
“1”
Transferred from UARTi receive register to
UARTi receive buffer register
Reception triggered when transfer clock
is generated by falling edge of start bit
D7
D1
Cleared to “0” when interrupt request is accepted, or cleared by software
Clock asynchronous serial I/O (UART) mode
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(c) TxD, RxD I/O polarity reverse function (UART2)
This function is to reverse TXD pin output and RXD pin input. The level of any data to be input or output
(including the start bit, stop bit(s), and parity bit) is reversed. Set this function to “0” (not to reverse) for
usual use.
(d) Bus collision detection function (UART2)
This function is to sample the output level of the TXD pin and the input level of the RXD pin at the rising
edge of the transfer clock; if their values are different, then an interrupt request occurs. Figure 1.16.21
shows the example of detection timing of a bus collision (in UART mode).
Figure 1.16.21. Detection timing of a bus collision (in UART mode)
ST : Start bit
SP : Stop bit
ST
ST
SP
SP
Transfer clock
TxD
2
RxD
2
Bus collision detection
interrupt request signal
“H”
“L”
“H”
“L”
“H”
“L”
“1”
“0”
Bus collision detection
interrupt request bit “1”
“0”
Clock asynchronous serial I/O (UART) mode
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Item Specification
Transfer data format • Transfer data 8-bit UART mode
(bit 2 through bit 0 of address 037816 = “1012”)
• One stop bit (bit 4 of address 037816 = “0”)
• With the direct format chosen
Set parity to “even”
(bit 5 and bit 6 of address 037816 = “1” and “1” respectively)
Set data logic to “direct” (bit 6 of address 037D16 = “0”).
Set transfer format to LSB (bit 7 of address 037C16 = “0”).
• With the inverse format chosen
Set parity to “odd”
(bit 5 and bit 6 of address 037816 = “0” and “1” respectively)
Set data logic to “inverse” (bit 6 of address 037D16 = “1”)
Set transfer format to MSB (bit 7 of address 037C16 = “1”)
Transfer clock •
With the internal clock chosen (bit 3 of address 037816 = “0”) : fi / 16 (n + 1) (Note 1) : fi=f1, f8, f32
(Do not set external clock)
Transmission / reception control
_______ _______
• Disable the CTS and RTS function (bit 4 of address 037C16 = “1”)
Other settings • The sleep mode select function is not available for UART2
•
Set transmission interrupt factor to “transmission completed” (bit 4 of address 037D
16
= “1”)
Transmission start condition
• To start transmission, the following requirements must be met:
- Transmit enable bit (bit 0 of address 037D16) = “1”
- Transmit buffer empty flag (bit 1 of address 037D16) = “0”
R
eceptio
n start condition
• To start reception, the following requirements must be met:
- Reception enable bit (bit 2 of address 037D16) = “1”
- Detection of a start bit
• When transmitting
When data transmission from the UART2 transmit register is completed
(bit 4 of address 037D16 = “1”)
• When receiving
When data transfer from the UART2 receive register to the UART2 receive
buffer register is completed
Error detection •
Overrun error (see the specifications of clock-asynchronous serial I/O) (Note 2)
• Framing error (see the specifications of clock-asynchronous serial I/O)
• Parity error (see the specifications of clock-asynchronous serial I/O)
- On the reception side, an “L” level is output from the TXD2 pin by use of the parity error
signal output function (bit 7 of address 037D16 = “1”) when a parity error is detected
- On the transmission side, a parity error is detected by the level of input to
the RXD2 pin when a transmission interrupt occurs
• The error sum flag (see the specifications of clock-asynchronous serial I/O)
(3) Clock-asynchronous serial I/O mode (used for the SIM interface)
The SIM interface is used for connecting the microcomputer with a memory card or the like; adding some
extra settings in UART2 clock-asynchronous serial I/O mode allows the user to effect this function. Table
1.16.8 shows the specifications of clock-asynchronous serial I/O mode (used for the SIM interface).
Interrupt request
generation timing
Note 1: ‘n’ denotes the value 0016 to FF16 that is set to the UART2 bit rate generator.
Note 2: If an overrun error occurs, the UART2 receive buffer will have the next data written in. Note also
that the UART2 receive interrupt request bit does not change.
Table 1.16.8.
Specifications of clock-asynchronous serial I/O mode (used for the SIM interface)
Clock asynchronous serial I/O (UART) mode
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Figure 1.16.22. Typical transmit/receive timing in UART mode (used for the SIM interface)
Transmit enable
bit(TE)
Transmit buffer
empty flag(TI)
Transmit register
empty flag (TXEPT)
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
ST P
Start
bit Parity
bit
The above timing applies to the following settings :
• Parity is enabled.
• One stop bit.
• Transmit interrupt cause select bit = “1”.
“0”
“1”
“0”
“1”
“0”
“1”
Tc = 16 (n + 1) / fi
fi : frequency of BRG2 count source (f1, f8, f32)
n : value set to BRG2
Transmit interrupt
request bit (IR) “0”
“1”
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
ST P
Shown in ( ) are bit symbols.
Tc
Transfer clock
SP
Stop
bit
Data is set in UART2 transmit buffer register
SP
An “L” level returns from TxD
2
due to
the occurrence of a parity error.
The level is detected by the
interrupt routine.
The level is
detected by the
interrupt routine.
Receive enable
bit (RE)
Receive complete
flag (RI)
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
ST P
Start
bit Parity
bit
RxD2
The above timing applies to the following settings :
• Parity is enabled.
• One stop bit.
• Transmit interrupt cause select bit = “0”.
“0”
“1”
“0”
“1”
Tc = 16 (n + 1) / fi
fi : frequency of BRG2 count source (f1, f8, f32)
n : value set to BRG2
Receive interrupt
request bit (IR) “0”
“1”
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
ST PSP
Shown in ( ) are bit symbols.
Tc
Transfer clock
SP
Stop
bit
An “L” level returns from TxD
2
due to
the occurrence of a parity error.
TxD2
Read to receive buffer Read to receive buffer
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
ST P
Signal conductor level
(Note 2) D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
ST PSP
SP
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
ST PD
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
ST P SP
SP
TxD2
RxD2
Signal conductor level
(Note 2)
Note 2: Equal in waveform because TxD2 and RxD2 are connected.
Transferred from UART2 transmit buffer register to UART2 transmit register
Cleared to “0” when interrupt request is accepted, or cleared by software
Cleared to “0” when interrupt request is accepted, or cleared by software
Note 1: The transmit is started with overflow timing of BRG after having written in a value at the transmit buffer in the above timing.
Note 1
Clock asynchronous serial I/O (UART) mode
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(a) Function for outputting a parity error signal
During reception, with the error signal output enable bit (bit 7 of address 037D16) assigned “1”, you
can output an “L” level from the TXD2 pin when a parity error is detected. And during transmission,
comparing with the case in which the error signal output enable bit (bit 7 of address 037D16) is as-
signed “0”, the transmission completion interrupt occurs in the half cycle later of the transfer clock.
Therefore parity error signals can be detected by a transmission completion interrupt program. Figure
1.16.23 shows the output timing of the parity error signal.
Figure 1.16.23. Output timing of the parity error signal
ST : Start bit
P : Even Parity
SP : Stop bit
D0 D1 D2 D3 D4 D5 D6 D7 P SPST
Hi-Z
Transfer
clock
RxD
2
TxD
2
Receive
complete flag
“H”
“L”
“H”
“L”
“H”
“L”
“1”
• LSB first
“0”
(b) Direct format/inverse format
Connecting the SIM card allows you to switch between direct format and inverse format. If you choose
the direct format, D0 data is output from TxD2. If you choose the inverse format, D7 data is inverted
and output from TxD2.
Figure 1.16.24 shows the SIM interface format.
Figure 1.16.24. SIM interface format
P : Even parity
D0 D1 D2 D3 D4 D5 D6 D7 P
Transfer
clcck
TxD2
(direct)
TxD2
(inverse) D7 D6 D5 D4 D3 D2 D1 D0 P
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Figure 1.16.25 shows the example of connecting the SIM interface. Connect TXD2 and RXD2 and apply
pull-up.
Figure 1.16.25. Connecting the SIM interface
Microcomputer
SIM card
TxD2
RxD2
UART2 Special Mode Register
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UART2 Special Mode Register
The UART2 special mode register (address 037716) is used to control UART2 in various ways.
Figure 1.16.26 shows the UART2 special mode register.
Bit 0 of the UART2 special mode register (037716) is used as the I2C mode select bit.
Setting “1” in the I2C mode select bit (bit 0) goes the circuit to achieve the I2C bus (simplified I2C bus)
interface effective.
Table 1.16.9 shows the relation between the I2C mode select bit and respective control workings.
Since this function uses clock-synchronous serial I/O mode, set this bit to “0” in UART mode.
Figure 1.16.26. UART2 special mode register
UART2 special mode register
Symbol Address When reset
U2SMR 037716 0016
b7 b6 b5 b4 b3 b2 b1 b0
Bit
name
Bit
symbol WR
Function
(During UART mode)
Function
(During clock synchronous
serial I/O mode)
ABSCS
ACSE
SSS
I2C mode select bit
Bus busy flag
0 : STOP condition detected
1 : START condition detected
SCL L sync output
enable bit
Bus collision detect
sampling clock select bit
Arbitration lost detecting
flag control bit
0 : Normal mode
1 : I2C mode
0 : Update per bit
1 : Update per byte
IICM
ABC
BBS
LSYN
0 : Ordinary
1 : Falling edge of RxD2
0 : Disabled
1 : Enabled
Transmit start condition
select bit
Must always be “0”
0 : Rising edge of transfer
clock
1 : Underflow signal of timer A0
Auto clear function
select bit of transmit
enable bit
A
A
AA
AA
A
AA
A
A
AA
AA
A
AA
A
AA
A
AA
A
AA
0 : No auto clear function
1 : Auto clear at occurrence of
bus collision
Must always be “0”
Must always be “0”
Must always be “0”
Must always be “0”
Must always be “0”
Must always be “0”
Note 1: Nothing but “0” may be written.
Note 2: When not in I2C mode, do not set this bit by writing a “1”. During normal mode, set it to “0”. When this
bit = “0”, UART2 special mode register 3 (U2SMR3 at address 037516) bits 7 to 5 (DL2 to DL0 = SDA
digital delay setup bits) are initialized to “000”, with the analog delay circuit selected. Also, when SDDS
= “0”, the U2SMR3 register cannot be read or written to.
Note 3: When analog delay is selected, only the analog delay value is effective; when digital delay is selected,
only the digital delay value is effective.
(Note1)
AA
A
SDDS SDA digital delay select
bit (Note 2, Note 3) Must always be “0”
0 : Analog delay output
is selected
1 : Digital delay output
is selected
(must always be “0” when
not using I C mode)
2
UART2 special mode register 3 (I C bus exclusive use register)
Symbol Address When reset
U2SMR3 0375
16
Indeterminate
(However, when SDDS = “1”, the initial value is “00
16
”)
b7 b6 b5 b4 b3 b2 b1 b0
Bit name
Bit
symbol WR
Function
(I C bus exclusive use register)
DL2
SDA digital delay setup
bit
(Note 1, Note 2, Note 3,
Note 4)
DL0
DL1
AA
A
AA
AA
A
A
AA
A
0 0 0 : Analog delay is selected
0 0 1 : 1 to 2 cycle(s) of 1/f(X
IN
)
0 1 0 : 2 to 3 cycles of 1/f(X
IN
)
0 1 1 : 3 to 4 cycles of 1/f(X
IN
)
1 0 0 : 4 to 5 cycles of 1/f(X
IN
)
1 0 1 : 5 to 6 cycles of 1/f(X
IN
)
1 1 0 : 6 to 7 cycles of 1/f(X
IN
)
1 1 1 : 7 to 8 cycles of 1/f(X
IN
)
2
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be
indeterminate. However, when SDDS = “1”, the value “0” is read out (Note 1)
2
b7 b6 b5
Note 1: This bit can be read or written to when UART2 special mode register (U2SMR at address 037716) bit
7 (SDDS: SDA digital delay select bit) = “1”. When the initial value of UART2 special mode register 3
(U2SMR3) is read after setting SDDS = “1”, the value is “00
16
”. When writing to UART2 special mode
register 3 (U2SMR3) after setting SDDS = “1”, be sure to write 0's to bits 0–4. When SDDS = “0”,
this register cannot be written to; when read, the value is indeterminate.
Note 2: These bits are initialized to “000” when SDDS = “0”, with the analog delay circuit selected. After a reset,
these bits are set to “000”, with the analog delay circuit selected. However, because these bits can be
read only when SDDS = “1”, the value read from these bits when SDDS = “0” is indeterminate.
Note 3: When analog delay is selected, only the analog delay value is effective; when digital delay is selected,
only the digital delay value is effective.
Note 4: The amount of delay varies with the load on SCL and SDA pins. Also, when using an external clock, the
amount of delay increases by about 100 ns, so be sure to take this into account when using the device.
Digital delay
is selected
UART2 Special Mode Register
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Function Normal mode I
2
C mode (Note 1)
Factor of interrupt number 15 (Note 2) UART2 transmission No acknowledgment detection (NACK)
Factor of interrupt number 16 (Note 2) UART2 reception
Start condition detection or stop
condition detection
UART2 transmission output delay Not delayed Delayed
P7
0
at the time when UART2 is in use TxD
2
(output) SDA (input/output) (Note 3)
P7
1
at the time when UART2 is in use RxD
2
(input) SCL (input/output)
P7
2
at the time when UART2 is in use CLK
2
P7
2
1
2
3
4
5
6
7
Note 1: Make the settings given below when I
2
C mode is in use.
Set 0 1 0 in bits 2, 1, 0 of the UART2 transmission/reception mode register.
Disable the RTS/CTS function. Choose the MSB First function.
Note 2: Follow the steps given below to switch from a factor to another.
1. Disable the interrupt of the corresponding number.
2. Switch from a factor to another.
3. Reset the interrupt request flag of the corresponding number.
4. Set an interrupt level of the corresponding number.
Note 3: Set an initial value of SDA transmission output when serial I/O is invalid.
Factor of interrupt number 10 (Note 2) Bus collision detection
Acknowledgment detection (ACK)
Noise filter width 15ns 50ns
Reading P7
1
Reading the terminal when 0 is
assigned to the direction register Reading the terminal regardless of the
value of the direction register
8
9
Initial value of UART2 output H level (when 0 is assigned to
the CLK polarity select bit) The value set in latch P7
0
when the port is
selected
10
Table 1.16.9. Features in I2C mode
P7
0
/TxD
2
/SDA
P7
1
/RxD
2
/SCL
CLK
control
P7
2
/CLK
2
Falling edge
detection
UART2 reception/ACK interrupt
request
To DMA0
To DMA0
2
P70 through P72 conforming to the simplified I C bus
I/O
Timer
UART2
Timer
UART2
IICM=1 (SDDS=0) or
DL=000 (SDDS=1) IICM=0
or IICM2=1
IICM=1
and IICM2=0
SDHI
Noize
Filter
Timer
UART2
UART2
I/O
D
TQ
D
TQ
D
TQ
NACK
ACK
UART2
UART2
IICM=1
IICM=0
IICM=0
IICM=1
IICM=1
IICM=0
S
RQ
IICM=1
IICM=0
I/O
R
Q
ALS
IICM=0 or
DL≠000 (SDDS=1)
SDDS=0
or DL=000
SDDS=1 and
DL≠000
SWC2
Falling edge of 9 bit
SWC
IICM=1
and IICM2=0
IICM=0
or IICM2=1
Selector
Selector
Selector
Noize
Filter
Noize
Filter
*
With IICM set to 1, the port terminal is to be readable
even if 1 is assigned to P7
1
of the direction register.
Port reading
External clock
Internal clock
9th pulse
Bus collision
detection
Bus collision/start, stop condition
detection interrupt request
UART2 transmission/
NACK interrupt request
Start condition
detection
Stop condition
detection
L-synchronous
output enabling
bit
(Port P71 output data latch)
Data bus
Reception register
Bus busy
Transmission
register
Arbitration
Analog
delay
Digital delay
(Divider)
Figure 1.16.27. Functional block diagram for I2C mode
UART2 Special Mode Register
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An attempt to read Port P71 (SCL) results in getting the terminal’s level regardless of the content of the
port direction register. The initial value of SDA transmission output goes to the value set in port P70. The
interrupt factors of the bus collision detection interrupt, UART2 transmission interrupt, and of UART2
reception interrupt turn to the start/stop condition detection interrupt, acknowledgment non-detection in-
terrupt, and acknowledgment detection interrupt respectively.
The start condition detection interrupt refers to the interrupt that occurs when the falling edge of the SDA
terminal (P70) is detected with the SCL terminal (P71) staying “H”. The stop condition detection interrupt
refers to the interrupt that occurs when the rising edge of the SDA terminal (P70) is detected with the SCL
terminal (P71) staying “H”. The bus busy flag (bit 2 of the UART2 special mode register) is set to “1” by the
start condition detection, and set to “0” by the stop condition detection.
The acknowledgment non-detection interrupt refers to the interrupt that occurs when the SDA terminal
level is detected still staying “H” at the rising edge of the 9th transmission clock. The acknowledgment
detection interrupt refers to the interrupt that occurs when SDA terminal’s level is detected already went
to “L” at the 9th transmission clock.
Bit 1 of the UART2 special mode register (037716) is used as the arbitration lost detecting flag control bit.
Arbitration means the act of detecting the nonconformity between transmission data and SDA terminal
data at the timing of the SCL rising edge. This detecting flag is located at bit 11 of the UART2 reception
buffer register (037F16, 037E16), and “1” is set in this flag when nonconformity is detected. Use the
arbitration lost detecting flag control bit to choose which way to use to update the flag, bit by bit or byte by
byte. When setting this bit to “1” and updated the flag byte by byte if nonconformity is detected, the
arbitration lost detecting flag is set to “1” at the falling edge of the 9th transmission clock.
If update the flag byte by byte, must judge and clear (“0”) the arbitration lost detecting flag after complet-
ing the first byte acknowledge detect and before starting the next one byte transmission.
Bit 3 of the UART2 special mode register is used as SCL- and L-synchronous output enable bit. Setting
this bit to “1” goes the P71 data register to “0” in synchronization with the SCL terminal level going to “L”.
Figure 1.16.27 shows the functional block diagram for I2C mode. Setting “1” in the I2C mode select bit
(IICM) causes ports P70, P71, and P72 to work as data transmission-reception terminal SDA, clock input-
output terminal SCL, and port P72 respectively. A delay circuit is added to the SDA transmission output,
so the SDA output changes after SCL fully goes to “L”. The SDA digital delay select bit (bit 7 at address
037716) can be used to select between analog delay and digital delay. When digital delay is selected, the
amount of delay can be selected in the range of 2 cycles to 8 cycles of f1 using UART2 special mode
register 3 (at address 037516). Delay circuit select conditions are shown in Table 1.16.10.
Table 1.16.10. Delay circuit select conditions
Digital delay is
selected
001
111
000
(000)
1
0
1
11
Analog delay is
selected
No delay
00(000)
IICM SDDS DL
Register value Contents
When digital delay is selected, no analog delay is added. Only
digital delay is effective.
When DL is set to “000”, analog delay is selected no matter what
value is set in SDDS.
When SDDS is set to “0”, DL is initialized, so that DL =“000”.
When IICM = “0”, no delay circuit is selected. When IICM = “0”,
however, always make sure SDDS = “0”.
to
UART2 Special Mode Register
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1. Bus collision detect sampling clock select bit (Bit 4 of the UART2 special mode register)
0: Rising edges of the transfer clock
CLK
Timer A0
1: Timer A0 overflow
2. Auto clear function select bit of transmt enable bit (Bit 5 of the UART2 special mode register)
CLK
TxD/RxD
Bus collision
detect interrupt
request bit
Transmit
enable bit
3. Transmit start condition select bit (Bit 6 of the UART2 special mode register)
CLK
TxD Enabling transmission
CLK
TxD
RxD
With "1: falling edge of RxD
2" selected
0: In normal state
TxD/RxD
Figure 1.16.28. Some other functions added
Some other functions added are explained here. Figure 1.16.28 shows their workings.
Bit 4 of the UART2 special mode register is used as the bus collision detect sampling clock select bit. The
bus collision detect interrupt occurs when the RXD2 level and TXD2 level do not match, but the nonconfor-
mity is detected in synchronization with the rising edge of the transfer clock signal if the bit is set to “0”. If
this bit is set to “1”, the nonconformity is detected at the timing of the overflow of timer A0 rather than at
the rising edge of the transfer clock.
Bit 5 of the UART2 special mode register is used as the auto clear function select bit of transmit enable
bit. Setting this bit to “1” automatically resets the transmit enable bit to “0” when “1” is set in the bus
collision detect interrupt request bit (nonconformity).
Bit 6 of the UART2 special mode register is used as the transmit start condition select bit. Setting this bit
to “1” starts the TxD transmission in synchronization with the falling edge of the RxD terminal.
UART2 Special Mode Register 2
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UART2 Special Mode Register 2
UART2 special mode register 2 (address 037616) is used to further control UART2 in I2C mode. Figure
1.16.29 shows the UART2 special mode register 2.
UART2 special mode register 2 (I C bus exclusive use register)
Symbol Address When reset
U2SMR2 037616 0016
b7 b6 b5 b4 b3 b2 b1 b0
Bit name
Bit
symbol WR
Function
STAC
SWC2
SDHI
I C mode select bit 2
SCL wait output bit 0 : Disabled
1 : Enabled
SDA output stop bit
UART2 initialization bit
Clock-synchronous bit
Refer to Table 1.16.11
0 : Disabled
1 : Enabled
IICM2
CSC
SWC
ALS 0 : Disabled
1 : Enabled
SDA output disable bit
SCL wait output bit 2
AA
AA
A
A
AA
AA
A
A
AA
A
AA
A
AA
A
AA
A
AA
A
0: Enabled
1: Disabled (high impedance)
0 : Disabled
1 : Enabled
0: UART2 clock
1: 0 output
2
SHTC Start/stop condition
control bit 1: Set this bit to “1” in I2C mode
(refer to Table 1.16.12)
AA
A
2
Figure 1.16.29. UART2 special mode register 2
UART2 Special Mode Register 2
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Bit 0 of the UART2 special mode register 2 (address 037616) is used as the I2C mode select bit 2. Table
1.16.11 shows the types of control to be changed by I2C mode select bit 2 when the I2C mode select bit
is set to “1”. Table 1.16.12 shows the timing characteristics of detecting the start condition and the stop
condition. Set the start/stop condition control bit (bit 7 of UART2 special mode register 2) to “1” in I2C
mode.
Function IICM2 = 1IICM2 = 0
Factor of interrupt number 15 No acknowledgment detection (NACK) UART2 transmission (the rising edge
of the final bit of the clock)
Factor of interrupt number 16 Acknowledgment detection (ACK) UART2 reception (the falling edge
of the final bit of the clock)
1
2
3Timing for transferring data from the
UART2 reception shift register to the
reception buffer.
The rising edge of the final bit of the
reception clock The falling edge of the final bit of the
reception clock
Timing for generating a UART2
reception/ACK interrupt request The rising edge of the final bit of the
reception clock The falling edge of the final bit of the
reception clock
4
3 to 6 cycles < duration for setting-up (Note 2)
3 to 6 cycles < duration for holding (Note 2)
Note 1 : When the start/stop condition control bit SHTC is “1” .
Note 2 : “Cycles” is in terms of the input oscillation frequency f(XIN) of the main clock.
Duration for
setting up Duration for
holding
SCL
SDA
(Start condition)
SDA
(Stop condition)
Table 1.16.11. Functions changed by I2C mode select bit 2
Table 1.16.12.
Timing characteristics of detecting the start condition and the stop condition (Note 1)
UART2 Special Mode Register 2
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P7
0
/TxD
2
/SDA
P7
1
/RxD
2
/SCL
CLK
control
P7
2
/CLK
2
Falling edge
detection
UART2 reception/ACK interrupt
request
To DMA0
To DMA0
2
P70 through P72 conforming to the simplified I C bus
I/O
Timer
UART2
Timer
UART2
IICM=1 (SDDS=0) or
DL=000 (SDDS=1) IICM=0
or IICM2=1
IICM=1
and IICM2=0
SDHI
Noize
Filter
Timer
UART2
UART2
I/O
D
TQ
D
TQ
D
TQ
NACK
ACK
UART2
UART2
IICM=1
IICM=0
IICM=0
IICM=1
IICM=1
IICM=0
S
RQ
IICM=1
IICM=0
I/O
R
Q
ALS
IICM=0 or
DL≠000 (SDDS=1)
SDDS=0
or DL=000
SDDS=1 and
DL≠000
SWC2
Falling edge of 9 bit
SWC
IICM=1
and IICM2=0
IICM=0
or IICM2=1
Selector
Selector
Selector
Noize
Filter
Noize
Filter
*
With IICM set to 1, the port terminal is to be readable
even if 1 is assigned to P7
1
of the direction register.
Port reading
External clock
Internal clock
9th pulse
Bus collision
detection
Bus collision/start, stop condition
detection interrupt request
UART2 transmission/
NACK interrupt request
Start condition
detection
Stop condition
detection
L-synchronous
output enabling
bit
(Port P7
1
output data latch)
Data bus
Reception register
Bus busy
Transmission
register
Arbitration
Analog
delay
Digital delay
(Divider)
Functions available in I2C mode are shown in Figure 1.16.30 — a functional block diagram.
Bit 3 of the UART2 special mode register 2 (address 037616) is used as the SDA output stop bit. Setting
this bit to “1” causes an arbitration loss to occur, and the SDA pin turns to high-impedance state at the
instant when the arbitration lost detecting flag is set to “1”.
Bit 1 of the UART2 special mode register 2 (address 037616) is used as the clock synchronization bit.
With this bit set to “1” at the time when the internal SCL is set to “H”, the internal SCL turns to “L” if the
falling edge is found in the SCL pin; and the baud rate generator reloads the set value, and start counting
within the “L” interval. When the internal SCL changes from “L” to “H” with the SCL pin set to “L”, stops
counting the baud rate generator, and starts counting it again when the SCL pin turns to “H”. Due to this
function, the UART2 transmission-reception clock becomes the logical product of the signal flowing
through the internal SCL and that flowing through the SCL pin. This function operates over the period
from the moment earlier by a half cycle than falling edge of the UART2 first clock to the rising edge of the
ninth bit. To use this function, choose the internal clock for the transfer clock.
Bit 2 of the UART2 special mode register 2 (037616) is used as the SCL wait output bit. Setting this bit to
“1” causes the SCL pin to be fixed to “L” at the falling edge of the ninth bit of the clock. Setting this bit to
“0” frees the output fixed to “L”.
Figure 1.16.30. Functional block diagram for I2C mode
UART2 Special Mode Register 2
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Bit 4 of the UART2 special mode register 2 (address 037616) is used as the UART2 initialization bit.
Setting this bit to “1”, and when the start condition is detected, the microcomputer operates as follows.
(1) The transmission shift register is initialized, and the content of the transmission register is transferred
to the transmission shift register. This starts transmission by dealing with the clock entered next as the
first bit. The UART2 output value, however, doesn’t change until the first bit data is output after the
entrance of the clock, and remains unchanged from the value at the moment when the microcomputer
detected the start condition.
(2) The reception shift register is initialized, and the microcomputer starts reception by dealing with the
clock entered next as the first bit.
(3) The SCL wait output bit turns to “1”. This turns the SCL pin to “L” at the falling edge of the ninth bit of
the clock.
Starting to transmit/receive signals to/from UART2 using this function doesn’t change the value of the
transmission buffer empty flag. To use this function, choose the external clock for the transfer clock.
Bit 5 of the UART2 special mode register 2 (037616) is used as the SCL wait output bit 2. Setting this bit
to “1” with the serial I/O specified allows the user to forcibly output an “1” from the SCL pin even if UART2
is in operation. Setting this bit to “0” frees the “L” output from the SCL pin, and the UART2 clock is input/
output.
Bit 6 of the UART2 special mode register 2 (037616) is used as the SDA output disable bit. Setting this bit
to “1” forces the SDA pin to turn to the high-impedance state. Refrain from changing the value of this bit
at the rising edge of the UART2 transfer clock. There can be instances in which arbitration lost detecting
flag is turned on.
A-D Converter
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Item Performance
Method of A-D conversion Successive approximation (capacitive coupling amplifier)
Analog input voltage (Note 1)
0V to AVCC (VCC)
Operating clock φAD (Note 2)
VCC = 5V fAD/divide-by-2 of fAD/divide-by-4 of fAD, fAD=f(XIN)
VCC = 3V divide-by-2 of fAD/divide-by-4 of fAD, fAD=f(XIN)
Resolution 8-bit or 10-bit (selectable)
Absolute precision VCC = 5V • Without sample and hold function
±3LSB
• With sample and hold function (8-bit resolution)
±2LSB
• With sample and hold function (10-bit resolution)
AN0 to AN7 input : ±3LSB
ANEX0 and ANEX1 input (including mode in which external
operation amp is connected) : ±7LSB
VCC = 3V • Without sample and hold function (8-bit resolution)
±2LSB
Operating modes One-shot mode
Analog input pins 8pins (AN0 to AN7) + 2pins (ANEX0 and ANEX1)
A-D conversion start condition
• Software trigger
A-D conversion starts when the A-D conversion start flag changes to “1”
• External trigger (can be retriggered)
A-D conversion starts when the A-D conversion start flag is “1” and the
___________
ADTRG/P97 input changes from “H” to “L”
Conversion speed per pin • Without sample and hold function
8-bit resolution: 49
φ
AD cycles
,
10-bit resolution: 59
φ
AD cycles
• With sample and hold function
8-bit resolution: 28
φ
AD cycles
,
10-bit resolution: 33
φ
AD cycles
A-D Converter
The A-D converter consists of one 10-bit successive approximation A-D converter circuit with a capacitive coupling
amplifier. Pins P10
0
to P10
7
, P9
5
, and P9
6
also function as the analog signal input pins. The direction registers of
these pins for A-D conversion must therefore be set to input. The Vref connect bit (bit 5 at address 03D7
16
) can be
used to isolate the resistance ladder of the A-D converter from the reference voltage input pin (V
REF
) when the A-D
converter is not used. Doing so stops any current flowing into the resistance ladder from V
REF
, reducing the power
dissipation. When using the A-D converter, start A-D conversion only after setting bit 5 of 03D7
16
to connect V
REF
.
The result of A-D conversion is stored in the A-D registers of the selected pins. When set to 10-bit precision, the low
8 bits are stored in the even addresses and the high 2 bits in the odd addresses. When set to 8-bit precision, the low
8 bits are stored in the even addresses.
Table 1.17.1 shows the performance of the A-D converter. Figure 1.17.1 shows the block diagram of the
A-D converter, and Figures 1.17.2 and 1.17.3 show the A-D converter-related registers.
Note 1: Does not depend on use of sample and hold function.
Note 2:
Divide the frequency if f(X
IN
) exceeds 10MH
Z
, and make φ
AD
frequency equal to or less than 10MHz.
Without sample and hold function, set the
φ
AD frequency to 250kHZ min.
With the sample and hold function, set the
φ
AD frequency to 1MHZ min.
Table 1.17.1. Performance of A-D converter
A-D Converter
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Figure 1.17.1. Block diagram of A-D converter
1/2
φAD
1/2
f
AD
A-D conversion rate
selection
(03C1
16
, 03C0
16
)
(03C3
16
, 03C2
16
)
(03C5
16
, 03C4
16
)
(03C7
16
, 03C6
16
)
(03C9
16
, 03C8
16
)
(03CB
16
, 03CA
16
)
(03CD
16
, 03CC
16
)
(03CF
16
, 03CE
16
)
CKS1=1
CKS0=0
0 0 : Normal operation
0 1 : ANEX0
1 0 : ANEX1
1 1 : External op-amp mode
A-D register 0(16)
A-D register 1(16)
A-D register 2(16)
A-D register 3(16)
A-D register 4(16)
A-D register 5(16)
A-D register 6(16)
A-D register 7(16)
Resistor ladder
ANEX1
ANEX0
Successive conversion register
OPA1,OPA0=0,1
OPA0=1
OPA1=1
OPA1,OPA0=1,1
AN
0
AN
1
AN
2
AN
3
AN
5
AN
6
AN
7
A-D control register 0 (address 03D6
16
)
A-D control register 1 (address 03D7
16
)
V
ref
V
IN
Data bus high-order
Data bus low-order
V
REF
AN
4
OPA1,OPA0=0,0
VCUT=0
AV
SS VCUT=1
CKS0=1
CKS1=0
CH2,CH1,CH0=000
CH2,CH1,CH0=001
CH2,CH1,CH0=010
CH2,CH1,CH0=011
CH2,CH1,CH0=100
CH2,CH1,CH0=101
CH2,CH1,CH0=110
CH2,CH1,CH0=111
Decoder
Comparator
OPA1, OPA0
Addresses
A-D Converter
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Figure 1.17.2. A-D converter-related registers (1)
A-D control register 0 (Note)
Symbol Address When reset
ADCON0 03D616 00000XXX2
b7 b6 b5 b4 b3 b2 b1 b0
Analog input pin select bit 0 0 0 : AN0 is selected
0 0 1 : AN1 is selected
0 1 0 : AN2 is selected
0 1 1 : AN3 is selected
1 0 0 : AN4 is selected
1 0 1 : AN5 is selected
1 1 0 : AN6 is selected
1 1 1 : AN7 is selected
CH0
Bit symbol Bit name Function
CH1
CH2
A-D operation mode
select bit 0 0 0 : One-shot mode
Must not be set except “00”
MD0
MD1
Trigger select bit 0 : Software trigger
1 : ADTRG trigger
TRG
ADST A-D conversion start flag 0 : A-D conversion disabled
1 : A-D conversion started
Frequency select bit 0 0 : fAD/4 is selected
1 : fAD/2 is selected
CKS0
WR
A-D control register 1 (Note)
Symbol Address When reset
ADCON1 03D716 0016
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
WR
b2 b1 b0
b4 b3
Note: If the A-D control register is rewritten during A-D conversion, the conversion result is
indeterminate.
Note: If the A-D control register is rewritten during A-D conversion, the conversion result is
indeterminate.
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
BITS 8/10-bit mode select bit 0 : 8-bit mode
1 : 10-bit mode
VCUT
OPA0
Vref connect bit
OPA1
0 : Vref not connected
1 : Vref connected
External op-amp
connection mode bit 0 0 : ANEX0 and ANEX1 are not used
0 1 : ANEX0 input is A-D converted
1 0 : ANEX1 input is A-D converted
1 1 : External op-amp connection mode
b7 b6
Frequency select bit 1 0 : fAD/2 or fAD/4 is selected
1 : fAD is selected
CKS1
A
A
A
A
A
A
A
A
A
A
Reserved bit Must always be set to “0”
000
A-D Converter
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Figure 1.17.3. A-D converter-related registers (2)
A-D control register 2 (Note)
Symbol Address When reset
ADCON2 03D416 0000XXX02
b7 b6 b5 b4 b3 b2 b1 b0
A-D conversion method
select bit 0 : Without sample and hold
1 : With sample and hold
Bit symbol Bit name Function R W
Note: If the A-D control register is rewritten during A-D conversion, the conversion
result is indeterminate.
A
A
A
A
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to
be “0”.
A-D register i
Symbol Address When reset
ADi(i=0 to 7)
03C0
16
to 03CF
16
Indeterminate
Eight low-order bits of A-D conversion result
Function R W
(b15) b7b7 b0 b0
(b8)
• During 10-bit mode
Two high-order bits of A-D conversion result
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if
read, turns out to be “0”.
• During 8-bit mode
When read, the content is indeterminate
A
A
A
A
SMP
Reserved bit Must always be set to
“0”
A
A
A
A
000
A-D Converter
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(1) One-shot mode
In one-shot mode, the pin selected using the analog input pin select bit is used for one-shot A-D conver-
sion. Table 1.17.2 shows the specifications of one-shot mode. Figure 1.17.4 shows the A-D control regis-
ter in one-shot mode.
Table 1.17.2. One-shot mode specifications
Figure 1.17.4. A-D conversion register in one-shot mode
A-D control register 0 (Note)
Symbol Address When reset
ADCON0 03D616 00000XXX2
b7 b6 b5 b4 b3 b2 b1 b0
Analog input pin select
bit
Bit symbol Bit name Function
CH1
CH2
A-D operation mode
select bit 0
MD0
MD1 Trigger select bit 0 : Software trigger
1 : ADTRG trigger
TRG
ADST A-D conversion start flag 0 : A-D conversion disabled
1 : A-D conversion started
Frequency select bit 0 0: fAD/4 is selected
1: fAD/2 is selected
CKS0
WR
00
A-D control register 1 (Note)
Symbol Address When reset
ADCON1 03D716 0016
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
Reserved bit Must always be set to “0”
WR
0
0 0 0 : AN0 is selected
0 0 1 : AN1 is selected
0 1 0 : AN2 is selected
0 1 1 : AN3 is selected
1 0 0 : AN4 is selected
1 0 1 : AN5 is selected
1 1 0 : AN6 is selected
1 1 1 : AN7 is selected
b2 b1 b0
0 0 : One-shot mode
b4 b3
CH0
1
Note : If the A-D control register is rewritten during A-D conversion, the conversion
result is indeterminate.
Note: If the A-D control register is rewritten during A-D conversion, the conversion
result is indeterminate.
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
BITS 8/10-bit mode select bit 0 : 8-bit mode
1 : 10-bit mode
VCUT
OPA0
Vref connect bit
OPA1
1 : Vref connected
External op-amp
connection mode bit 0 0 : ANEX0 and ANEX1 are not used
0 1 : ANEX0 input is A-D converted
1 0 : ANEX1 input is A-D converted
1 1 : External op-amp connection mode
b7 b6
Frequency select bit1 0 : fAD/2 or fAD/4 is selected
1 : fAD is selected
CKS1
A
A
A
A
A
A
A
A
A
A
00
Item Specification
Function
The pin selected by the analog input pin select bit is used for one A-D conversion
Start condition Writing “1” to A-D conversion start flag
Stop condition
•
End of A-D conversion (A-D conversion start flag changes to “0”, except
when external trigger is selected)
• Writing “0” to A-D conversion start flag
Interrupt request generation timing
End of A-D conversion
Input pin One of AN0 to AN7, as selected
Reading of result of A-D converter
Read A-D register corresponding to selected pin
A-D Converter
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTE
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(a) Sample and hold
Sample and hold is selected by setting bit 0 of the A-D control register 2 (address 03D416) to “1”. When
sample and hold is selected, the rate of conversion of each pin increases. As a result, a 28
φ
AD cycle is
achieved with 8-bit resolution and 33
φ
AD with 10-bit resolution. Sample and hold can be selected in all
modes. However, in all modes, be sure to specify before starting A-D conversion whether sample and
hold is to be used.
(b) Extended analog input pins
In one-shot mode and repeat mode, the input via the extended analog input pins ANEX0 and ANEX1 can
also be converted from analog to digital.
When bit 6 of the A-D control register 1 (address 03D716) is “1” and bit 7 is “0”, input via ANEX0 is
converted from analog to digital. The result of conversion is stored in A-D register 0.
When bit 6 of the A-D control register 1 (address 03D716) is “0” and bit 7 is “1”, input via ANEX1 is
converted from analog to digital. The result of conversion is stored in A-D register 1.
(c) External operation amp connection mode
In this mode, multiple external analog inputs via the extended analog input pins, ANEX0 and ANEX1, can
be amplified together by just one operation amp and used as the input for A-D conversion.
When bit 6 of the A-D control register 1 (address 03D716) is “1” and bit 7 is “1”, input via AN0 to AN7 is
output from ANEX0. The input from ANEX1 is converted from analog to digital and the result stored in the
corresponding A-D register. The speed of A-D conversion depends on the response of the external op-
eration amp. Do not connect the ANEX0 and ANEX1 pins directly. Figure 1.17.5 is an example of how to
connect the pins in external operation amp mode.
Analog
input
External o
p
-am
p
AN0
AN7
AN1
AN2
AN3
AN4
AN5
AN6
ANEX1
ANEX0
Resistor ladder
Successive conversion register
Comparator
Figure 1.17.5. Example of external op-amp connection mode
Programmable I/O Port
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTE
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Programmable I/O Ports
There are 87 programmable I/O ports: P0 to P10 (excluding P85). Each port can be set independently for
input or output using the direction register. A pull-up resistance for each block of 4 ports can be set. P85 is
an input-only port and has no built-in pull-up resistance.
Figures 1.20.1 to 1.20.4 show the programmable I/O ports. Figure 1.20.5 shows the I/O pins.
Each pin functions as a programmable I/O port and as the I/O for the built-in peripheral devices.
To use the pins as the inputs for the built-in peripheral devices, set the direction register of each pin to input
mode. When the pins are used as the outputs for the built-in peripheral devices (other than the D-A con-
verter), they function as outputs regardless of the contents of the direction registers. When pins are to be
used as the outputs for the D-A converter, do not set the direction registers to output mode. See the
descriptions of the respective functions for how to set up the built-in peripheral devices.
(1) Direction registers
Figure 1.20.6 shows the direction registers.
These registers are used to choose the direction of the programmable I/O ports. Each bit in these regis-
ters corresponds one for one to each I/O pin.
In memory expansion and microprocessor mode, the contents of corresponding direction register of pins
_______ _______ _____ ________ ______ ________ _______ _______ __________ _________
A0 to A19, D0 to D15, CS0 to CS3, RD, WRL/WR, WRH/BHE, ALE, RDY, HOLD, HLDA and BCLK cannot
be modified.
Note: There is no direction register bit for P85.
(2) Port registers
Figure 1.20.7 shows the port registers.
These registers are used to write and read data for input and output to and from an external device. A
port register consists of a port latch to hold output data and a circuit to read the status of a pin. Each bit
in port registers corresponds one for one to each I/O pin.
In memory expansion and microprocessor mode, the contents of corresponding port register of pins A0 to
_______ ________ _____ ________ ______ ________ ________ _______ __________ _________
A19, D0 to D15, CS0 to CS3, RD, WRL/WR, WRH/BHE, ALE, RDY, HOLD, HLDA and BCLK cannot be
modified.
(3) Pull-up control registers
Figure 1.20.8 shows the pull-up control registers.
The pull-up control register can be set to apply a pull-up resistance to each block of 4 ports. When ports
are set to have a pull-up resistance, the pull-up resistance is connected only when the direction register is
set for input.
However, in memory expansion mode and microprocessor mode, the pull-up control register of P0 to P3,
P40 to P43, and P5 is invalid. The contents of register can be changed, but the pull-up resistance is not
connected.
(4) Port control register
Figure 1.20.9 shows the port control register.
The bit 0 of port control register is used to read port P1 as follows:
0 : When port P1 is input port, port input level is read.
When port P1 is output port , the contents of port P1 register is read.
1 : The contents of port P1 register is read always.
This register is valid in the following:
• External bus width is 8 bits in microprocessor mode or memory expansion mode.
• Port P1 can be used as a port in multiplexed bus for the entire space.
Programmable I/O Port
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTE
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Figure 1.20.1. Programmable I/O ports (1)
P0
0
to P0
7
, P2
0
to P2
7
,
P3
0
to P3
7
, P4
0
to P4
7
,
P5
0
to P5
4
, P5
6
P1
0
to P1
4
P1
5
to P1
7
P5
7
, P6
0
, P6
1
, P6
4
, P6
5
,
P7
2
, P7
3
, P7
4
Data bus
Direction register
Pull-up selection
Port latch
Data bus
Direction register
Pull-up selection
Port latch
Port P1 control register
Direction register
Port latch
Port P1 control register
Pull-up selection
Data bus
Input to respective peripheral functions
Direction register
Port latch
Pull-up selection
Data bus
Input to respective peripheral functions
"1"
Output
(Note)
(Note)
(Note)
(Note)
Note: symbolizes a parasitic diode.
Do not apply a voltage higher than Vcc to each port.
Programmable I/O Port
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTE
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Figure 1.20.2. Programmable I/O ports (2)
P8
2
to P8
4
Data bus
Direction register
Pull-up selection
Port latch
Input to respective peripheral functions
(Note1)
P6
3
, P6
7
"1"
Output
Data bus
Direction register
Pull-up selection
Port latch (Note1)
P8
5
Data bus
NMI interrupt input (Note1)
Data bus
Direction register
Pull-up selection
Port latch
Input to respective peripheral functions
(Note 2)
(Note1)
P7
6
, P7
7
, P8
0
, P8
1
,
P9
0
, P9
3
, P9
4
(inside dotted-line not included)
P5
5
, P6
2
, P6
6
, P7
5
,
P9
1
, P9
2
, P9
7
(inside dotted-line included)
Note 1: symbolizes a parasitic diode.
Do not apply a voltage higher than Vcc to each port.
Note 2: In a part of port, the input to a respective peripheral functions
does not exist, but schmitt circuit exists.
Programmable I/O Port
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTE
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Figure 1.20.3. Programmable I/O ports (3)
Note 1: symbolizes a parasitic diode.
Do not apply a voltage higher than Vcc to each port.
P9
6
, P10
0
to P10
3
(inside dotted-line not included)
P9
5
, P10
4
to P10
7
(inside dotted-line included)
Data bus
Direction register
Pull-up selection
Port latch
Analog input
Input to respective peripheral functions
(Note 1)
P7
0
, P7
1
"1"
Output
Direction register
Port latch
Input to respective peripheral functions
(Note 2)
Data bus
Note 2: symbolizes a parasitic diode.
Programmable I/O Port
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTE
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Figure 1.20.5. I/O pins
Figure 1.20.4. Programmable I/O ports (4)
P8
7
P8
6
fc
Rf
Rd
Data bus
Direction register
Pull-up selection
Port latch
"1"
Output
Direction register
Pull-up selection
Port latch
Data bus
Note : symbolizes a parasitic diode.
Do not apply a voltage higher than Vcc to each port.
(Note)
(Note)
BYTE BYTE signal input
CNV
SS
CNV
SS
signal input
RESET RESET signal input
Note : symbolizes a parasitic diode.
Do not apply a voltage higher than Vcc to each pin.
(Note)
(Note)
(Note)
Programmable I/O Port
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTE
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Figure 1.20.6. Direction register
Port Pi direction register (Note 1, 2)
Symbol Address When reset
PDi (i = 0 to 10, except 8) 03E2
16
, 03E3
16
, 03E6
16
, 03E7
16
, 03EA
16
00
16
03EB
16
, 03EE
16
, 03EF
16
, 03F3
16
, 03F6
16
00
16
Bit name FunctionBit symbol WR
b7 b6 b5 b4 b3 b2 b1 b0
PDi_0 Port Pi
0
direction register
PDi_1 Port Pi
1
direction register
PDi_2 Port Pi
2
direction register
PDi_3 Port Pi
3
direction register
PDi_4 Port Pi
4
direction register
PDi_5 Port Pi
5
direction register
PDi_6 Port Pi
6
direction register
PDi_7 Port Pi
7
direction register
0 : Input mode
(Functions as an input port)
1 : Output mode
(Functions as an output port)
(i = 0 to 10 except 8)
Port P8 direction register
Symbol Address When reset
PD8
03F216 00X00000
2
Bit name FunctionBit symbol WR
b7 b6 b5 b4 b3 b2 b1 b0
PD8_0 Port P8
0
direction register
PD8_1 Port P8
1
direction register
PD8_2 Port P8
2
direction register
PD8_3 Port P8
3
direction register
PD8_4 Port P8
4
direction register
Nothing is assigned.
In an attempt to write to this bit, write “0”. The value, if read, turns out to be
indeterminate.
PD8_6 Port P8
6
direction register
PD8_7 Port P8
7
direction register
0 : Input mode
(Functions as an input port)
1 : Output mode
(Functions as an output port)
0 : Input mode
(Functions as an input port)
1 : Output mode
(Functions as an output port)
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
Note 2: In memory expansion and microprocessor mode, the contents of
corresponding port Pi direction register of pins A
0
to A
19
, D
0
to D
15
,
CS
0
to CS
3
, RD, WRL/WR, WRH/BHE, ALE, RDY, HOLD, HLDA and
BCLK cannot be modified.
Note 1: Set bit 2 of protect register (address 000A
16
) to “1” before rewriting to
the port P9 direction register.
Programmable I/O Port
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTE
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Port Pi register (Note 2) Symbol Address When reset
Pi (i = 0 to 10, except 8) 03E0
16
, 03E1
16
, 03E4
16
, 03E5
16
, 03E8
16
Indeterminate
03E9
16
, 03EC
16
, 03ED
16
, 03F1
16
, 03F4
16
Indeterminate
Bit name FunctionBit symbol WR
b7 b6 b5 b4 b3 b2 b1 b0
Pi_0 Port Pi
0
register
Pi_1 Port Pi
1
register
Pi_2 Port Pi
2
register
Pi_3 Port Pi
3
register
Pi_4 Port Pi
4
register
Pi_5 Port Pi
5
register
Pi_6 Port Pi
6
register
Pi_7 Port Pi
7
register
Data is input and output to and from
each pin by reading and writing to
and from each corresponding bit
0 : “L” level data
1 : “H” level data (Note 1)
(i = 0 to 10 except 8)
Port P8 register
Symbol Address When reset
P8 03F0
16
Indeterminate
Bit name FunctionBit symbol WR
b7 b6 b5 b4 b3 b2 b1 b0
P8_0 Port P8
0
register
P8_1 Port P8
1
register
P8_2 Port P8
2
register
P8_3 Port P8
3
register
P8_4 Port P8
4
register
P8_5 Port P8
5
register
P8_6 Port P8
6
register
P8_7 Port P8
7
register
Data is input and output to and from
each pin by reading and writing to
and from each corresponding bit
(except for P8
5
)
0 : “L” level data
1 : “H” level data
AA
AA
A
A
AA
A
AA
A
AA
A
AA
A
AA
AA
A
A
AA
AA
A
A
AA
A
AA
AA
A
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
AA
A
A
AA
A
AA
A
AA
Note 1:
Since P7
0
and P7
1
are N-channel open drain ports, the data is high-impedance.
Note 2: In memory expansion and microprocessor mode, the contents of
corresponding port Pi register of pins A
0
to A
19
, D
0
to D
15
, CS
0
to CS
3
,
RD, WRL/WR, WRH/BHE, ALE, RDY, HOLD, HLDA and BCLK cannot
be modified.
Figure 1.20.7. Port register
Programmable I/O Port
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Figure 1.20.8. Pull-up control register
Pull-up control register 0 (Note)
Symbol Address When reset
PUR0 03FC
16
00
16
Bit name Function Bit symbol WR
b7 b6 b5 b4 b3 b2 b1 b0
PU00 P0
0
to P0
3
pull-up
PU01 P0
4
to P0
7
pull-up
PU02 P1
0
to P1
3
pull-up
PU03 P1
4
to P1
7
pull-up
PU04 P2
0
to P2
3
pull-up
PU05 P2
4
to P2
7
pull-up
PU06 P3
0
to P3
3
pull-up
PU07 P3
4
to P3
7
pull-up
The corresponding port is pulled
high with a pull-up resistor
0 : Not pulled high
1 : Pulled high
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
Pull-up control register 1
Symbol Address When reset
PUR1 03FD
16
00
16
(Note 2)
Bit name Function Bit symbol
WR
b7 b6 b5 b4 b3 b2 b1 b0
PU10 P4
0
to P4
3
pull-up (Note 3)
PU11 P4
4
to P4
7
pull-up
PU12 P5
0
to P5
3
pull-up (Note 3)
PU13 P5
4
to P5
7
pull-up (Note 3)
PU14 P6
0
to P6
3
pull-up
PU15 P6
4
to P6
7
pull-up
PU16 P7
2
to P7
3
pull-up (Note 1)
PU17 P7
4
to P7
7
pull-up
The corresponding port is pulled
high with a pull-up resistor
0 : Not pulled high
1 : Pulled high
Note 1: Since P7
0
and P7
1
are N-channel open drain ports, pull-up is not available for them.
Note 2: When the V
CC
level is being impressed to the CNV
SS
terminal, this register becomes
to 02
16
when reset (PU11 becomes to “1”).
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
Pull-up control register 2
Symbol Address When reset
PUR2 03FE
16
00
16
Bit name FunctionBit symbol WR
b7 b6 b5 b4 b3 b2 b1 b0
PU20 P8
0
to P8
3
pull-up
PU21 P8
4
to P8
7
pull-up
(Except P8
5
)
PU22 P9
0
to P9
3
pull-up
PU23 P9
4
to P9
7
pull-up
PU24 P10
0
to P10
3
pull-up
PU25 P10
4
to P10
7
pull-up
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”.
The corresponding port is pulled
high with a pull-up resistor
0 : Not pulled high
1 : Pulled high
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
Note 3: In memory expansion and microprocessor mode, the content of these bits can be
changed, but the pull-up resistance is not connected.
Note : In memory expansion and microprocessor mode, the content of this register
can be changed, but the pull-up resistance is not connected.
Programmable I/O Port
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTE
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Figure 1.20.9. Port control register
Port control register
Symbpl Address When reset
PCR 03FF
16
00
16
Bit name FunctionBit symbol
WR
b7 b6 b5 b4 b3 b2 b1 b0
PCR0 Port P1 control register 0 : When input port, read port
input level. When output port,
read the contents of port P1
register.
1 : Read the contents of port P1
register though input/output
port.
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns
out to be “0”.
A
A
Programmable I/O Port
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTE
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Pin name Connection
Ports P0 to P10
(excluding P85)
XOUT (Note)
AVSS, VREF, BYTE
AVCC
After setting for input mode, connect every pin to VSS via a resistor
(pull-down); or after setting for output mode, leave these pins open.
Open
Connect to VCC
Connect to VSS
Note: With external clock input to XIN pin.
NMI Connect via resistor to VCC (pull-up)
Table 1.20.1. Example connection of unused pins in single-chip mode
Pin name Connection
Ports P6 to P10
(excluding P85)
AVSS, VREF
AVCC
After setting for input mode, connect every pin to VSS via a resistor
(pull-down); or after setting for output mode, leave these pins open.
Open
Connect to VCC
Connect to VSS
Note 1: With external clock input to XIN pin.
Note 2: When the BCLK output disable bit (bit 7 at address 000416) is set to “1”, connect to VCC via a resistor (pull-up).
HOLD, RDY, NMI Connect via resistor to VCC (pull-up)
BHE, ALE, HLDA,
XOUT (Note 1), BCLK (Note 2)
P45 / CS1 to P47 / CS3 Set ports to input mode, set output enable bits of CS1 through CS3 to
0, and connect to Vcc via resistors (pull-up).
Figure 1.20.10. Example connection of unused pins
Port P0 to P10 (except for P8
5
)
(Input mode)
·
·
·
(Input mode)
(Output mode)
NMI
X
OUT
AV
CC
BYTE
AV
SS
V
REF
Microcomputer
V
CC
V
SS
In single-chip mode
Port P6 to P10 (except for P8
5
)
(Input mode)
·
·
·
(Input mode)
(Output mode)
NMI
X
OUT
AV
CC
AV
SS
V
REF
Open
Microcomputer
V
CC
V
SS
In memory expansion mode or
in microprocessor mode
HOLD
RDY
ALE
BCLK (Note)
BHE
HLDA
Open
Open Open
·
·
··
·
·
Port P4
5
/ CS1
to P4
7
/ CS3
Note : When the BCLK output disable bit (bit 7 at address 0004
16
) is set to “1”, connect to V
CC
via a resistor (pull-up).
Table 1.20.2. Example connection of unused pins in memory expansion mode and microprocessor mode
Electrical characteristics
146
Mitsubishi microcomputer
s
M16C / 30 Grou
p
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTE
R
Table 1.23.1. Absolute maximum ratings
Note : Specify a product of -40°C to 85°C to use it.
VREF, XIN
XOUT
VO
-0.3 to Vcc+0.3
-0.3 to Vcc+0.3
PdTopr=25
-0.3 to 6.5
-0.3 to 6.5 V
V
V
VI
AVcc
Vcc
Tstg
Topr
mW
V
-65 to 150
300
-20 to 85 / -40 to 85 (Note)
P30 to P37, P40 to P47, P50 to P57,
P60 to P67, P72 to P77, P80 to P87,
P00 to P07, P10 to P17, P20 to P27,
P30 to P37,P40 to P47, P50 to P57,
P60 to P67,P72 to P77, P80 to P84,
P00 to P07, P10 to P17, P20 to P27,
RESET,
P90 to P97, P100 to P107,
P86, P87, P90 to P97, P100 to P107,
P70, P71
P70, P71
-0.3 to 6.5
-0.3 to 6.5
V
V
CNVSS, BYTE,
VCC=AVCC
VCC=AVCC
C
C
C
Symbol Parameter Condition Rated value Unit
Supply voltage
Analog supply voltage
Input
voltage
Output
voltage
Power dissipation
Operating ambient temperature
Storage temperature
Electrical characteristics
Electrical characteristics
147
Mitsubishi microcomputer
s
M16C / 30 Grou
p
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTE
R
Note 1: The mean output current is the mean value within 100ms.
Note 2: The total IOL (peak) for ports P0, P1, P2, P86, P87, P9, and P10 must be 80mA max. The total IOH (peak) for ports P0, P1,
P2, P86, P87, P9, and P10 must be 80mA max. The total IOL (peak) for ports P3, P4, P5, P6, P7, and P80 to P84 must be
80mA max. The total IOH (peak) for ports P3, P4, P5, P6, P72 to P77, and P80 to P84 must be 80mA max.
Note 3: Specify a product of -40°C to 85°C to use it.
Note 4: Relationship between main clock oscillation frequency and supply voltage.
Table 1.23.2.
Recommended operating conditions (referenced to V
CC
= 2.7V to 5.5V at Topr = – 20
o
C
to 85
o
C / – 40
o
C to 85
o
C (Note 3) unless otherwise specified)
Main clock input oscillation frequency (No wait)
AAAAAAA
AAAAAAA
AAAAAAA
AAAAAAA
AAAAAAA
AAAAAAA
AAAAAAA
AAAAAAA
16.0
5.0
0.0 2.7 4.2 5.5
Operating maximum
frequency
[MH
Z
]
Supply voltage
[V]
(BCLK: no division)
7.33 X V
CC
- 14.791MH
Z
Main clock input oscillation frequency (With wait)
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
16.0
10.0
0.0 2.7 4.2 5.5
Operating maximum
frequency
[MH
Z
]
Supply voltage
[V]
(BCLK: no division)
4 X V
CC
- 0.8MH
Z
2.7 5.5
Vcc 5.0
VccAVcc V
V0
0
V
IH
I
OH (avg)
mA
mA
Vss
AVss
0.8Vcc
V
V
V
V
V
V
V
0.8Vcc
0.5Vcc
Vcc
Vcc
Vcc
0.2Vcc
0.2Vcc
0
0
0
(data input function during memory expansion and microprocessor modes)
0.16Vcc
I
OH (peak)
P7
2
to P7
7
, P8
0
to P8
7
, P9
0
to P9
7
, P10
0
to P10
7
,
-5.0
-10.0
P0
0
to P0
7
, P1
0
to P1
7
, P2
0
to P2
7
, P3
0
(during single-chip mode)
P0
0
to P0
7
, P1
0
to P1
7
, P2
0
to P2
7
, P3
0
P0
0
to P0
7
, P1
0
to P1
7
,
P2
0
to P2
7
, P3
0
to P3
7
,
P4
0
to P4
7
, P5
0
to P5
7
,
P6
0
to P6
7
, P7
2
to P7
7
,
P8
0
to P8
4
, P8
6
, P8
7
, P9
0
to P9
7
, P10
0
to P10
7
P3
1
to P3
7
, P4
0
to P4
7
, P5
0
to P5
7,
P6
0
to P6
7
,
10.0
5.0
mA
f
(X
IN
)
I
OL (peak)
mA
I
OL (avg)
f
(Xc
IN
) kHz5032.768
V
X
IN
, RESET, CNV
SS
, BYTE
P7
0
to P7
7
, P8
0
to P8
7
, P9
0
to P9
7
, P10
0
to P10
7
,
P3
1
to P3
7
, P4
0
to P4
7
, P5
0
to P5
7,
P6
0
to P6
7
,
X
IN
, RESET, CNV
SS
, BYTE
(data input function during memory expansion and microprocessor modes)
P0
0
to P0
7
, P1
0
to P1
7
, P2
0
to P2
7
, P3
0
(during single-chip mode)
P0
0
to P0
7
, P1
0
to P1
7
, P2
0
to P2
7
, P3
0
P0
0
to P0
7
, P1
0
to P1
7
,
P2
0
to P2
7
, P3
0
to P3
7
,
P4
0
to P4
7
, P5
0
to P5
7
,
P6
0
to P6
7
, P7
2
to P7
7
,
P8
0
to P8
4
, P8
6
, P8
7
, P9
0
to P9
7
, P10
0
to P10
7
P0
0
to P0
7
, P1
0
to P1
7
,
P2
0
to P2
7
, P3
0
to P3
7
,
P4
0
to P4
7
, P5
0
to P5
7
,
P6
0
to P6
7
, P7
0
to P7
7
,
P8
0
to P8
4
, P8
6
, P8
7
, P9
0
to P9
7
, P10
0
to P10
7
P0
0
to P0
7
, P1
0
to P1
7
,
P2
0
to P2
7
, P3
0
to P3
7
,
P4
0
to P4
7
, P5
0
to P5
7
,
P6
0
to P6
7
, P7
0
to P7
7
,
P8
0
to P8
4
, P8
6
, P8
7
, P9
0
to P9
7
, P10
0
to P10
7
P7
0
,0.8Vcc 6.5 V
P7
1
V
IL
7.33 X Vcc
-14.791
4 X Vcc
-0.8
Vcc=4.2V to 5.5V
Vcc=2.7V to 4.2V
Vcc=4.2V to 5.5V
Vcc=2.7V to 4.2V
0
0
0
0
MHz
MHz
MHz
MHz
16
16
Symbol Parameter Unit
Standard
Min Typ. Max.
Supply voltage
Analog supply voltage
Supply voltage
Analog supply voltage
HIGH input
voltage
LOW input
voltage
HIGH peak output
current
HIGH average output
current
LOW peak output
current
LOW average
output current
Main clock input oscillation
frequency (Note 4)
Subclock oscillation frequency
With wait
No wait
Electrical characteristics
148
Mitsubishi microcomputer
s
M16C / 30 Grou
p
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTE
R
Table 1.23.3. A-D conversion characteristics (referenced to VCC = AVCC = VREF = 2.7V to 5.5V, Vss = AVSS =
0V at
Topr = – 20oC to 85oC / – 40oC to 85oC (Note 4)
unless otherwise specified)
µs
Standard
Min. Typ. Max.
Resolution
Absolute
accuracy
Bits
LSB
VREF = VCC ±3
10
Symbol Parameter Measuring condition Unit
V
REF
= V
CC
= 5V
R
LADDER
tCONV
Ladder resistance
Conversion time(10bit), Sample & hold function available
Reference voltage
Analog input voltage
kΩ
V
VIA
VREF
V0
2.7
10
VCC
VREF
40
3.3
2.8
tCONV
tSAMP
Sampling time
0.3
VREF = VCC
Sample & hold function not available
Sample & hold function available(10bit)
AN
0
to AN
7
input
ANEX0, ANEX1 input,
External op-amp connection mode
V
REF
=V
CC
= 5V
LSB
LSB
±7
Sample & hold function available(8bit)
V
REF
= V
CC
= 5V ±2 LSB
µs
µs
±3
Note 1: Do f(XIN) in range of main clock input oscillation frequency prescribed with recommended operating
conditions of table 1.23.2. Divide the f AD if f(XIN) exceeds 10MHz, and make AD operation clock frequency
(ØAD) equal to or lower than 10MHz. And divide the f AD if VCC is less than 4.2V, and make AD operation
clock frequency (ØAD) equal to or lower than f AD/2.
Note 2: A case without sample & hold function turn AD operation clock frequency (ØAD) into 250 kHz or more in
addition to a limit of Note 1.
A case with sample & hold function turn AD operation clock frequency (ØAD) into 1MHz or more in addition
to a limit of Note 1.
Note 3: Connect AVCC pin to VCC pin and apply the same electric potential.
Note 4: Specify a product of -40°C to 85°C to use it.
Sample & hold function not available(8bit)
V
REF
= V
CC
= 3V, Ø
AD
= f
AD
/2 ±2 LSB
Conversion time(8bit), Sample & hold function available
V
REF
= V
CC
= 5V, Ø
AD
=10MHz
V
REF
= V
CC
= 5V, Ø
AD
=10MHz 9.8
t
CONV µs
Conversion time(8bit), Sample & hold function not available
V
REF
= V
CC
= 3V, Ø
AD
= f
AD
/2 = 5MHz
Electrical characteristics (Vcc = 5V)
149
Mitsubishi microcomputer
s
M16C / 30 Grou
p
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTE
R
VCC = 5V
Table 1.23.6.
Electrical characteristics (referenced to V
CC
= 4.2V to 5.5V, V
SS
= 0V at
Topr = – 20oC
to 85oC / – 40oC to 85oC (Note 2)
, f(X
IN
) = 16MH
Z
unless otherwise specified)
V
OH
V
OH
V
OH
V
OL
V
OL
V
OL
V
V4
.
7
V
X
O
U
T
3
.
0
3
.
0
V2.0
0
.
4
5V
V
X
OUT
2.0
2.0
3
.
0I
OH
= -5mA, V
CC
=5.0V
I
OH
= -1mA, V
CC
=5.0V
I
OH
= -200µA, V
CC
=5.0V
I
OH
= -0.5mA, V
CC
=5.0V
I
OL
= 5mA, V
CC
=5.0V
I
OL
= 1mA, V
CC
=5.0V
I
OL
= 200µA, V
CC
=5.0V
I
OL
= 0.5mA, V
CC
=5.0V
P0
0
to P0
7
, P1
0
to P1
7
, P2
0
to P2
7
,
P
0
0
t
o
P
0
7
,
P
1
0
t
o
P
1
7
,
P
2
0
t
o
P
2
7
,
P3
0
to P3
7
, P4
0
to P4
7
, P5
0
to P5
7
,
P3
0
to P3
7
, P4
0
to P4
7
, P5
0
to P5
7
,
P6
0
to P6
7
, P7
2
to P7
7
, P8
0
to P8
4
,
P0
0
to P0
7
, P1
0
to P1
7
, P2
0
to P2
7
,
P3
0
to P3
7
, P4
0
to P4
7
, P5
0
to P5
7
,
P6
0
to P6
7
, P7
2
to P7
7
, P8
0
to P8
4
,
HIGHPOWER
LOWPOWER
P8
6
, P8
7
, P9
0
to P9
7
, P10
0
to P10
7
H
I
G
H
P
O
W
E
R
LOWPOWER
P6
0
to P6
7
, P7
0
to P7
7
, P8
0
to P8
4
,
P8
6
, P8
7
, P9
0
to P9
7
, P10
0
to P10
7
P8
6
, P8
7
, P9
0
to P9
7
, P10
0
to P10
7
HIGHPOWER
LOWPOWER
X
C
O
U
T
3
.
0
1.6 V
P0
0
to P0
7
, P1
0
to P1
7
, P2
0
to P2
7
,
P
3
0
t
o
P
3
7
,
P
4
0
t
o
P
4
7
,
P
5
0
t
o
P
5
7
,
P
6
0
t
o
P
6
7
,
P
7
0
t
o
P
7
7
,
P
8
0
t
o
P
8
4
,
P8
6
, P8
7
, P9
0
to P9
7
, P10
0
to P10
7
V
T+-
V
T-
0
.
21.
0V
V
X
COUT
0
0
H
I
G
H
P
O
W
E
R
LOWPOWER
S
y
m
b
o
lP
a
r
a
m
e
t
e
rU
n
i
t
S
t
a
n
d
a
r
d
M
i
nT
y
p
.M
a
x
.
H
I
G
H
o
u
t
p
u
t
v
o
l
t
a
g
e
HIGH output
voltage
HIGH output
voltage
HIGH output
voltage
L
O
W
o
u
t
p
u
t
v
o
l
t
a
g
e
L
O
W
o
u
t
p
u
t
v
o
l
t
a
g
e
L
O
W
o
u
t
p
u
t
v
o
l
t
a
g
e
L
O
W
o
u
t
p
u
t
v
o
l
t
a
g
e
H
y
s
t
e
r
e
s
i
s
W
i
t
h
n
o
l
o
a
d
a
p
p
l
i
e
d
,
V
C
C
=
5
.
0
V
W
i
t
h
n
o
l
o
a
d
a
p
p
l
i
e
d
,
V
C
C
=
5
.
0
V
With no load applied, V
CC
=5.0V
W
i
t
h
n
o
l
o
a
d
a
p
p
l
i
e
d
,
V
C
C
=
5
.
0
V
I
IH
I
I
L
V
RAM
I
c
c
V
T+-
V
T-
0.2 1.8 V
5
.
0µ
A
2
.
0V
m
A
RESET
P
0
0
t
o
P
0
7
,
P
1
0
t
o
P
1
7
,
P
2
0
t
o
P
2
7
,
P
3
0
t
o
P
3
7
,
P
4
0
t
o
P
4
7
,
P
5
0
t
o
P
5
7
,
P
6
0
t
o
P
6
7
,
P
7
0
t
o
P
7
7
,
P
8
0
t
o
P
8
7
,
P
9
0
t
o
P
9
7
,
P
1
0
0
t
o
P
1
0
7
,
X
I
N
,
R
E
S
E
T
,
C
N
V
s
s
,
B
Y
T
E
V
I
= 5V , V
CC
=5.0V
V
I
= 0V , V
CC
=5.0V -5.0
3
0
.
05
0
.
0
f
(
X
I
N
)
=
1
6
M
H
z
P
0
0
t
o
P
0
7
,
P
1
0
t
o
P
1
7
,
P
2
0
t
o
P
2
7
,
P
3
0
t
o
P
3
7
,
P
4
0
t
o
P
4
7
,
P
5
0
t
o
P
5
7
,
P
6
0
t
o
P
6
7
,
P
7
0
t
o
P
7
7
,
P
8
0
t
o
P
8
7
,
P
9
0
t
o
P
9
7
,
P
1
0
0
t
o
P
1
0
7
,
X
I
N
,
R
E
S
E
T
,
C
N
V
s
s
,
B
Y
T
E
f
(
X
C
I
N
)
=
3
2
k
H
z
R
fXIN
R
fXCIN
X
IN
X
CIN
6.0
1.0
R
P
U
L
L
U
P
5
0
.
0
P0
0
to P0
7
, P1
0
to P1
7
, P2
0
to P2
7
,
P3
0
to P3
7
, P4
0
to P4
7
, P5
0
to P5
7
,
P6
0
to P6
7
, P7
2
to P7
7
, P8
0
to P8
4
,
P8
6
, P8
7
, P9
0
to P9
7
, P10
0
to P10
7
V
I
= 0V , V
CC
=5.0V 30.0 167.0
H
y
s
t
e
r
e
s
i
s
H
I
G
H
i
n
p
u
t
c
u
r
r
e
n
t
L
O
W
i
n
p
u
t
c
u
r
r
e
n
t
Pull-up
resistance
Feedback resistance
F
e
e
d
b
a
c
k
r
e
s
i
s
t
a
n
c
e
RAM retention voltage
P
o
w
e
r
s
u
p
p
l
y
c
u
r
r
e
n
t
µA
When clock is stopped
In single-chip
mode, the
output pins are
open and other
pins are V
SS
S
quare wave, no
di
v
i
s
i
on
S
q
u
a
r
e
w
a
v
e
Measuring condition
kΩ
MΩ
MΩ
µA
90.0
CLK
0
to CLK
4
,TA2
OUT
,
TB1
IN
, TB2
IN
, INT
0
to INT
2
, NMI,
A
D
T
R
G
,
C
T
S
0
t
o
C
T
S
2
,
S
C
L
,
S
D
A
,
HOLD, RDY, T A0
IN
to TA2
IN
,
KI
0
to KI
3
, RxD
0
to RxD
2
1
.
0µA
20.0
4
.
0µ
A
f
(
X
C
I
N
)
=
3
2
k
H
z
T
o
p
r
=
8
5°C
w
h
e
n
c
l
o
c
k
i
s
s
t
o
p
p
e
d
Topr = 25°C
when clock is st opp ed
W
h
e
n
a
W
A
I
T
i
n
s
t
r
u
c
t
i
o
n
i
s
e
x
e
c
u
t
e
d
(
N
o
t
e
1
)
N
o
t
e
1
:
W
i
t
h
o
n
e
t
i
m
e
r
o
p
e
r
a
t
e
d
u
s
i
n
g
f
C
3
2
.
N
o
t
e
2
:
S
p
e
c
i
f
y
a
p
r
o
d
u
c
t
o
f
-
4
0
°
C
t
o
8
5
°
C
t
o
u
s
e
i
t
.
1
0
(Topr
= 25°C)
V
CC
=5.0V
V
C
C
=
5
.
0
V
Electrical characteristics (Vcc = 5V)
150
Mitsubishi microcomputer
s
M16C / 30 Grou
p
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTE
R
Timing requirements (referenced to V
CC
= 5V, V
SS
= 0V at Topr = – 20
o
C to 85
o
C / – 40
o
C to 85
o
C (*)
unless otherwise specified)
* : Specify a product of -40°C to 85°C to use it.
f(BCLK) X 2
(Note)
(Note)
(Note)
40
30
0
0
40
0
Note: Calculated according to the BCLK frequency as follows: 40
Max.
External clock rise time ns
t
r
Min.
External clock input cycle time
External clock input HIGH pulse width
External clock input LOW pulse width
External clock fall time
ns
ns
ns
ns
t
c
t
w(H
)
t
w(L)
t
f
ParameterSymbol Unit
Standard
15
62.5
25
25 15
Min.
Data input setup time ns
t
su(DB-RD)
t
su(RDY-BCLK )
ParameterSymbol Unit
Max.
Standard
ns
RDY input setup time
Data input hold time ns
t
h(RD-DB)
t
h(BCLK -RDY)
ns
RDY input hold time
ns
HOLD input setup time
t
su(HOLD-BCLK )
ns
HOLD input hold time
t
h(BCLK-HOLD )
Data input access time (no wait) ns
t
ac1(RD-DB)
ns
ns
t
ac2(RD-DB)
t
ac3(RD-DB)
Data input access time (with wait)
Data input access time (when accessing multiplex bus area)
ns
t
d(BCLK-HLDA )
HLDA output delay time
t
ac1(RD – DB) = f(BCLK) X 2 – 45
10
9
[ns]
t
ac2(RD – DB) = f(BCLK) X 2 – 45
3 X 10
9
[ns]
t
ac3(RD – DB) = – 45
3 X 10
9
[ns]
VCC = 5V
Table 1.23.8. Memory expansion and microprocessor modes
Table 1.23.7. External clock input
Electrical characteristics (Vcc = 5V)
151
Mitsubishi microcomputer
s
M16C / 30 Grou
p
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTE
R
Standard
Max.
ns
TAi
IN
input LOW pulse width
t
w(TAL)
Min. ns
ns
Unit
Standard
Max.
Min. ns
ns
ns
Unit
Standard
Max.
Min. ns
ns
ns
Unit
Standard
Max.
Min. ns
ns
Unit
Standard
Max.
Min. ns
ns
ns
Unit
ns
ns
TAi
IN
input HIGH pulse width
t
w(TAH)
ParameterSymbol
TAi
IN
input cycle time
TAi
IN
input HIGH pulse width
TAi
IN
input LOW pulse width
t
c(TA)
t
w(TAH)
t
w(TAL)
Symbol Parameter
TAi
IN
input cycle time
TAi
IN
input HIGH pulse width
TAi
IN
input LOW pulse width
t
c(TA)
t
w(TAH)
t
w(TAL)
Symbol Parameter
t
w(TAH)
t
w(TAL)
Symbol Parameter
TAi
IN
input HIGH pulse width
TAi
IN
input LOW pulse width
Symbol Parameter
t
c(TA)
TAi
IN
input cycle time
TAi
OUT
input cycle time
TAi
OUT
input HIGH pulse width
TAi
OUT
input LOW pulse width
TAi
OUT
input setup time
TAi
OUT
input hold time
t
c(UP)
t
w(UPH)
t
w(UPL)
t
su(UP-T
IN
)
t
h(T
IN-
UP)
40
100
40
400
200
200
200
100
100
100
100
2000
1000
1000
400
400
Timing requirements (referenced to V
CC
= 5V, V
SS
= 0V at Topr = – 20
o
C to 85
o
C / – 40
o
C to 85
o
C (*)
unless otherwise specified)
* : Specify a product of -40°C to 85°C to use it.
Table 1.23.10. Timer A input (gating input in timer mode)
Table 1.23.11. Timer A input (external trigger input in one-shot timer mode)
Table 1.23.12. Timer A input (external trigger input in pulse width modulation mode)
Table 1.23.13. Timer A input (up/down input in event counter mode)
VCC = 5V
Table 1.23.9. Timer A input (counter input in event counter mode)
Electrical characteristics (Vcc = 5V)
152
Mitsubishi microcomputer
s
M16C / 30 Grou
p
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTE
R
Timing requirements (referenced to V
CC
= 5V, V
SS
= 0V at Topr = – 20
o
C to 85
o
C / – 40
o
C to 85
o
C (*)
unless otherwise specified)
* : Specify a product of -40°C to 85°C to use it.
ns
ns
ns
ns
ns
ns
ns
Standard
Max.Min.
TBi
IN
input cycle time (counted on one edge)
TBi
IN
input HIGH pulse width (counted on one edge)
TBi
IN
input LOW pulse width (counted on one edge)
ns
ns
ns
t
c(TB)
t
w(TBH)
t
w(TBL)
ParameterSymbol Unit
t
c(TB)
t
w(TBL)
t
w(TBH)
ns
ns
ns
TBi
IN
input HIGH pulse width (counted on both edges)
TBi
IN
input LOW pulse width (counted on both edges)
TBi
IN
input cycle time (counted on both edges)
Standard
Max.
Min. ns
ns
t
c(TB)
t
w(TBH)
Symbol Parameter Unit
t
w(TBL)
ns
TBi
IN
input HIGH pulse width
TBi
IN
input cycle time
TBi
IN
input LOW pulse width
Standard
Max.
Min. ns
ns
t
c(TB)
Symbol Parameter Unit
t
w(TBL)
ns
t
w(TBH)
TBi
IN
input cycle time
TBi
IN
input HIGH pulse width
TBi
IN
input LOW pulse width
Standard
Max.
Min. ns
ns
t
c(AD)
t
w(ADL)
Symbol Parameter Unit
AD
TRG
input cycle time (trigger able minimum)
AD
TRG
input LOW pulse width
Standard
Max.
Min. ns
ns
t
w(INH)
t
w(INL)
Symbol Parameter Unit
INTi input LOW pulse width
INTi input HIGH pulse width
Standard
Max.Min.
CLKi input cycle time
CLKi input HIGH pulse width
CLKi input LOW pulse width
t
c(CK)
t
w(CKH)
t
w(CKL)
ParameterSymbol Unit
t
d(C-Q)
t
su(D-C)
t
h(C-Q)
TxDi hold time
RxDi input setup time
TxDi output delay time
t
h(C-D)
RxDi input hold time
100
40
40
80
80
200
400
200
200
400
200
200
1000
125
250
250
200
100
100
0
30
90
80
VCC = 5V
Table 1.23.17. A-D trigger input
_______
Table 1.23.19. External interrupt INTi inputs
Table 1.23.15. Timer B input (pulse period measurement mode)
Table 1.23.16. Timer B input (pulse width measurement mode)
Table 1.23.18. Serial I/O
Table 1.23.14. Timer B input (counter input in event counter mode)
Electrical characteristics (Vcc = 5V)
153
Mitsubishi microcomputer
s
M16C / 30 Grou
p
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTE
R
Symbol Standard
Measuring condition
Max.Min.
Parameter Unit
t
d(BCLK-AD)
Address output delay time 25 ns
t
h(BCLK-AD)
Address output hold time (BCLK standard) 4 ns
t
h(BCLK-CS)
Chip select output hold time (BCLK standard) 4 ns
t
d(BCLK-ALE)
ALE signal output delay time 25 ns
t
h(BCLK-ALE)
ALE signal output hold time – 4 ns
t
d(BCLK-RD)
RD signal output delay time 25 ns
t
h(BCLK-RD)
RD signal output hold time 0 ns
t
d(BCLK-WR)
WR signal output delay time 25 ns
t
h(BCLK-WR)
WR signal output hold time 0 ns
t
d(BCLK-DB)
Data output delay time (BCLK standard) 40 ns
t
h(BCLK-DB)
Data output hold time (BCLK standard) 4ns
t
h(WR-DB)
Data output hold time (WR standard)(Note2) 0 ns
t
d(DB-WR)
Data output delay time (WR standard) ns
(Note1)
Note 1: Calculated according to the BCLK frequency as follows:
td(DB – WR) = f(BCLK) X 2
10
9
– 40 [ns]
t
d(BCLK-CS)
Chip select output delay time 25 ns
t
h(RD-AD)
Address output hold time (RD standard) 0ns
t
h(WR-AD)
Address output hold time (WR standard) 0ns
Note 2: This is standard value shows the timing when the output is off,
and doesn't show hold time of data bus.
Hold time of data bus is different by capacitor volume and pull-up
(pull-down) resistance value.
Hold time of data bus is expressed in
t = –CR X ln (1 – VOL / VCC)
by a circuit of the right figure.
For example, when VOL = 0.2VCC, C = 30pF, R = 1kΩ, hold time
of output “L” level is
t = – 30pF X 1kΩ X ln (1 – 0.2VCC / VCC)
= 6.7ns.
DBi
R
C
Note 3: Specify a product of -40°C to 85°C to use it.
Switching characteristics (referenced to VCC = 5V, VSS = 0V at Topr = – 20oC to 85oC / – 40oC to
85oC (Note 3), CM15 = “1” unless otherwise specified)
VCC = 5V
Figure 1.23.1
Table 1.23.20. Memory expansion mode and microprocessor mode (no wait)
Figure 1.23.1. Port P0 to P10 measurement circuit
P6
P7
P8
P10
P9
P0
P1
P2
P3
P4
P5
30pF
Electrical characteristics (Vcc = 5V)
154
Mitsubishi microcomputer
s
M16C / 30 Grou
p
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTE
R
Switching characteristics (referenced to VCC = 5V, VSS = 0V at Topr = – 20oC to 85oC / – 40oC to
85oC (Note 3), CM15 = “1” unless otherwise specified)
VCC = 5V
Figure 1.23.1
Table 1.23.21. Memory expansion mode and microprocessor mode
(with wait, accessing external memory)
Symbol Standard
Measuring condition Max.Min.
Parameter Unit
td(BCLK-AD) Address output delay time 25 ns
th(BCLK-AD) Address output hold time (BCLK standard) 4 ns
th(BCLK-CS) Chip select output hold time (BCLK standard) 4 ns
td(BCLK-ALE) ALE signal output delay time 25 ns
th(BCLK-ALE) ALE signal output hold time – 4 ns
td(BCLK-RD) RD signal output delay time 25 ns
th(BCLK-RD) RD signal output hold time 0 ns
td(BCLK-WR) WR signal output delay time 25 ns
th(BCLK-WR) WR signal output hold time 0 ns
td(BCLK-DB) Data output delay time (BCLK standard) 40 ns
th(BCLK-DB) Data output hold time (BCLK standard) 4ns
th(WR-DB) Data output hold time (WR standard)(Note2) 0 ns
td(DB-WR) Data output delay time (WR standard) ns
(Note1)
Note 1: Calculated according to the BCLK frequency as follows:
td(DB – WR) = f(BCLK)
10 9– 40 [ns]
td(BCLK-CS) Chip select output delay time 25 ns
th(RD-AD) Address output hold time (RD standard) 0ns
th(WR-AD) Address output hold time (WR standard) 0ns
Note 2: This is standard value shows the timing when the output is off,
and doesn't show hold time of data bus.
Hold time of data bus is different by capacitor volume and pull-up
(pull-down) resistance value.
Hold time of data bus is expressed in
t = –CR X ln (1 – VOL / VCC)
by a circuit of the right figure.
For example, when VOL = 0.2VCC, C = 30pF, R = 1kΩ, hold time
of output “L” level is
t = – 30pF X 1kΩ X ln (1 – 0.2VCC / VCC)
= 6.7ns.
DBi
R
C
Note 3: Specify a product of -40°C to 85°C to use it.
Electrical characteristics (Vcc = 5V)
155
Mitsubishi microcomputer
s
M16C / 30 Grou
p
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTE
R
Switching characteristics (referenced to VCC = 5V, VSS = 0V at Topr = – 20oC to 85oC / – 40oC to
85oC (Note 2), CM15 = “1” unless otherwise specified)
VCC = 5V
Table 1.23.22. Memory expansion mode and microprocessor mode
(with wait, accessing external memory, multiplex bus area selected)
Symbol Standard
Measuring condition
Max.Min.
Parameter Unit
t
d(BCLK-AD)
Address output delay time 25 ns
t
h(BCLK-AD)
Address output hold time (BCLK standard) 4 ns
t
d(BCLK-CS)
Chip select output delay time 25 ns
t
h(BCLK-CS)
Chip select output hold time (BCLK standard) 4 ns
nst
h(RD-AD)
Address output hold time (RD standard)
(Note1)
t
d(BCLK-RD)
RD signal output delay time 25 ns
t
h(BCLK-RD)
RD signal output hold time 0 ns
nst
h(WR-AD)
Address output hold time (WR standard)
(Note1)
t
d(BCLK-WR)
WR signal output delay time 25 ns
t
d(BCLK-DB)
Data output delay time (BCLK standard) 40 ns
t
h(BCLK-DB)
Data output hold time (BCLK standard) 4 ns
t
d(DB-WR)
Data output delay time (WR standard)
(Note1)
ns
t
d(BCLK-ALE)
ALE signal output delay time (BCLK standard) 25 ns
t
h(BCLK-ALE)
ALE signal output hold time (BCLK standard) – 4 ns
t
h(ALE-AD)
ALE signal output hold time (Adderss standard) 30 ns
t
h(BCLK-WR)
WR signal output hold time 0 ns
nst
h(RD-CS)
Chip select output hold time (RD standard)
(Note1)
t
h(WR-CS)
Chip select output hold time (WR standard)
(Note1)
ns
t
d(AD-RD)
Post-address RD signal output delay time ns0
t
d(AD-WR)
Post-address WR signal output delay time ns0
t
dZ(RD-AD)
Address output floating start time ns8
t
h(WR-DB)
Data output hold time (WR standard) ns
(Note1)
Note 1: Calculated according to the BCLK frequency as follows:
th(RD – AD) = f(BCLK) X 2
10
9
[ns]
th(WR – AD) = f(BCLK) X 2
10
9
[ns]
th(RD – CS) = f(BCLK) X 2
10
9
[ns]
th(WR – CS) = f(BCLK) X 2
10
9
[ns]
td(DB – WR) = f(BCLK) X 2
10
9
– 40 [ns]
X 3
td(AD – ALE) = f(BCLK) X 2
10
9
– 25 [ns]
th(WR – DB) = f(BCLK) X 2
10
9
[ns]
t
d(AD-ALE)
ALE signal output delay time (Address standard) ns
(Note1)
Note 2: Specify a product of -40°C to 85°C to use it.
Figure 1.23.1
Timing (Vcc = 5V)
156
Mitsubishi microcomputer
s
M16C / 30 Grou
p
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTE
R
VCC = 5V
tsu(D–C)
TAi
IN
input
TAi
OUT
input
During event counter mode
TBi
IN
input
CLKi
TxDi
RxDi
tc(TA)
tw(TAH)
tw(TAL)
tc(UP)
tw(UPH)
tw(UPL)
tc(TB)
tw(TBH)
tw(TBL)
tc(AD)
tw(ADL)
tc(CK)
tw(CKH)
tw(CKL)
tw(INL)
tw(INH)
td(C–Q) th(C–D)
th(C–Q)
th(T
IN
–UP) tsu(UP–T
IN
)
TAi
IN
input
(When count on falling
edge is selected)
TAi
IN
input
(When count on rising
edge is selected)
TAi
OUT
input
(Up/down input)
INTi input
AD
TRG
input
Figure 1.23.2. VCC = 5V timing diagram (1)
Timing (Vcc = 5V)
157
Mitsubishi microcomputer
s
M16C / 30 Grou
p
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTE
R
VCC = 5V
Measuring conditions :
• V
CC
=5V
• Input timing voltage : Determined with V
IL
=1.0V, V
IH
=4.0V
• Output timing voltage : Determined with V
OL
=2.5V, V
OH
=2.5V
Memory Expansion Mode and Microprocessor Mode
BCLK
HOLD input
HLDA output
P0, P1, P2,
P3, P4,
P5
0
to P5
2
(Valid with or without wait)
Note: The above pins are set to high-impedance regardless of the input level of the
BYTE pin and bit (PM06) of processor mode register 0 selects the function of
ports P4
0
to P4
3
.
t
h(BCLK–HOLD)
t
su(HOLD–BCLK)
(Valid only with wait)
t
d(BCLK–HLDA)
t
d(BCLK–HLDA)
Hi–Z
RDY input
tsu(RDY–BCLK) th(BCLK–RDY)
BCLK
RD
(Multiplexed bus)
(Multiplexed bus)
WR, WRL, WRH
WR, WRL, WRH
(Separate bus)
RD
(Separate bus)
Figure 1.23.3. VCC = 5V timing diagram (2)
Timing (Vcc = 5V)
158
Mitsubishi microcomputer
s
M16C / 30 Grou
p
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTE
R
BCLK
CSi
ALE –4ns.min
RD 25ns.max 0ns.min
4ns.min
4ns.min
Hi–Z
DB
0ns.min
ADi
BHE
Read timing
BCLK
CSi
ALE
25ns.max 0ns.min
4ns.min
4ns.min
Hi-Z
DB
40ns.max 4ns.min
(tcyc/2–40)ns.min
ADi
BHE
Write timing
td(BCLK–AD)
td(BCLK–ALE) th(BCLK–ALE)
tSU(DB–RD)
th(BCLK-AD)
td(BCLK–WR)
th(BCLK–DB)
td(BCLK–RD)
td(BCLK–ALE)
40ns.min
tac1(RD–DB)
Memory Expansion Mode and Microprocessor Mode
(With no wait)
WR,WRL,
WRH
td(BCLK–CS)
25ns.max
tcyc
th(BCLK–CS)
th(RD–CS)
0ns.min
25ns.max th(BCLK–AD)
th(RD–AD)
0ns.min
th(BCLK–RD)
25ns.max
th(RD–DB)
td(BCLK–CS)
25ns.max th(BCLK–CS)
tcyc th(WR–CS)
0ns.min
td(BCLK–AD)
25ns.max
25ns.max
th(BCLK–ALE)
–4ns.min th(WR–AD) 0ns.min
th(BCLK–WR)
td(BCLK–DB)
td(DB–WR) th(WR–DB)
0ns.min
VCC = 5V
Figure 1.23.4. VCC = 5V timing diagram (3)
Timing (Vcc = 5V)
159
Mitsubishi microcomputer
s
M16C / 30 Grou
p
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTE
R
BCLK
CSi
ALE
RD
4ns.min
Hi–Z
DB
40ns.min 0ns.min
ADi
BHE
Read timing
BCLK
CSi
ALE
4ns.min
t
h(WR–AD)
ADi
BHE
(tcyc–40)ns.min 0ns.min
DBi
Write timing
t
d(BCLK–RD)
0ns.min
0ns.min
t
h(RD–AD)
Memory Expansion Mode and Microprocessor Mode
(When accessing external memory area with wait)
Measuring conditions :
• V
CC
=5V
• Input timing voltage : Determined with: V
IL
=0.8V, V
IH
=2.5V
• Output timing voltage : Determined with: V
OL
=0.8V, V
OH
=2.0V
WR,WRL,
WRH
t
d(BCLK–CS)
25ns.max
tcyc
t
h(BCLK–CS)
4ns.min
t
h(RD–CS)
0ns.min
t
h(BCLK–AD)
t
d(BCLK–AD)
25ns.max
t
d(BCLK–ALE) 25ns.max
t
h(BCLK–ALE)
–4ns.min
t
h(BCLK–RD)
0ns.min
25ns.max
t
ac2(RD–DB)
t
h(RD–DB)
t
SU(DB–RD)
t
d(BCLK–CS)
25ns.max
tcyc
t
h(BCLK–CS)
4ns.min
t
h(WR–CS)
0ns.min
t
h(BCLK–AD)
t
d(BCLK–AD)
25ns.max
t
d(BCLK–ALE)
25ns.max
t
h(BCLK–ALE)
–4ns.min
t
h(BCLK–WR)
0ns.min
t
d(BCLK–WR)
25ns.max
t
h(BCLK–DB)
4ns.min
t
d(BCLK–DB)
40ns.max
t
d(DB–WR)
t
h(WR–DB)
VCC = 5V
Figure 1.23.5. VCC = 5V timing diagram (4)
Timing (Vcc = 5V)
160
Mitsubishi microcomputer
s
M16C / 30 Grou
p
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTE
R
Memory Expansion Mode and Microprocessor Mode
(When accessing external memory area with wait, and select multiplexed bus)
BCLK
CSi
ALE
RD
4ns.min
tcyc
ADi
BHE
ADi
/DBi
t
d(AD–ALE)
Read timing
0ns.min
BCLK
CSi
ALE
–4ns.min
4ns.min
4ns.min
tcyc
ADi
BHE
ADi
/DBi
Write timing
Address
Measuring conditions :
• V
CC
=5V
• Input timing voltage : Determined with
V
IL
=0.8V, V
IH
=2.5V
• Output timing voltage : Determined with V
OL
=0.8V, V
OH
=2.0V
(tcyc/2)ns.min
AddressData input
(tcyc/2)ns.min
t
d(BCLK–ALE)
(tcyc/2)ns.min
t
h(WR–CS)
Address
(tcyc x 3/2–40)ns.min
t
d(BCLK–ALE) (tcyc/2)ns.min
(tcyc/2-25)ns.min
Address
25ns.max
t
SU(DB–RD)
tac3(RD–DB)
(tcyc/2)ns.min
t
h(ALE–AD)
30ns.min
t
d(AD–RD)
0ns.min
t
dz(RD–AD)
8ns.max
t
d(AD–WR)
0ns.min
Data output
WR,WRL,
WRH
t
d(BCLK–CS)
25ns.max
t
h(RD–CS)
t
h(BCLK–CS)
4ns.min
t
h(BCLK–AD)
t
h(RD–DB)
0ns.min
40ns.min
25ns.max
t
d(BCLK–AD)
–4ns.min
t
h(BCLK–ALE)
t
d(BCLK–RD)
25ns.max
t
h(RD–AD)
t
h(BCLK–RD)
0ns.min
t
d(BCLK–CS)
25ns.max
t
h(BCLK–CS)
t
h(BCLK–DB)
4ns.min
t
h(WR–DB)
t
d(DB–WR)
t
h(BCLK–AD)
t
d(AD–ALE)
(tcyc/2–25)ns.min
t
d(BCLK–AD)
25ns.max
25ns.max
t
h(BCLK–ALE)
25ns.max
t
d(BCLK–WR)
t
h(BCLK–WR)
t
h(WR–AD)
t
d(BCLK–DB)
40ns.max
VCC = 5V
Figure 1.23.6. VCC = 5V timing diagram (5)
Electrical characteristics (Vcc = 3V)
161
Mitsubishi microcomputer
s
M16C / 30 Grou
p
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTE
R
S
y
m
b
o
l
V
O
H
H
I
G
H
o
u
t
p
u
t
v
o
l
t
a
g
e
V
O
H
V
O
L
L
O
W
o
u
t
p
u
t
v
o
l
t
a
g
e
LOW output voltage
V
OL
H
I
G
H
o
u
t
p
u
t
v
o
l
t
a
g
e
Standard
Typ. U
n
i
t
Measuring condition
V
V
X
O
U
T
2
.
5
2
.
5
V0.5
V
X
O
U
T
0.5
0.5
M
i
nM
a
x
.
2
.
5
P
a
r
a
m
e
t
e
r
I
O
H
=
-
1
m
A
,
V
C
C
=
3
.
0
V
I
O
H
=
-
0
.
1
m
A
,
V
C
C
=
3
.
0
V
I
O
H
=
-
5
0
µ
A
,
V
C
C
=
3
.
0
V
I
O
L
=
1
m
A
,
V
C
C
=
3
.
0
V
I
OL
= 0.1mA, V
CC
=3.0V
I
OL
= 50µA, V
CC
=3.0V
P
0
0
t
o
P
0
7
,
P
1
0
t
o
P
1
7
,
P
2
0
t
o
P
2
7
,
P
0
0
t
o
P
0
7
,
P
1
0
t
o
P
1
7
,
P
2
0
t
o
P
2
7
,
P
3
0
t
o
P
3
7
,
P
4
0
t
o
P
4
7
,
P
5
0
t
o
P
5
7
,
P
3
0
t
o
P
3
7
,
P
4
0
t
o
P
4
7
,
P
5
0
t
o
P
5
7
,
P
6
0
t
o
P
6
7
,
P
7
2
t
o
P
7
7
,
P
8
0
t
o
P
8
4
,
H
I
G
H
P
O
W
E
R
L
O
W
P
O
W
E
R
P
8
6
,
P
8
7
,
P
9
0
t
o
P
9
7
,
P
1
0
0
t
o
P
1
0
7
HIGHPOWER
LOWPOWER
P
6
0
t
o
P
6
7
,
P
7
0
t
o
P
7
7
,
P
8
0
t
o
P
8
4
,
P
8
6
,
P
8
7
,
P
9
0
t
o
P
9
7
,
P
1
0
0
t
o
P
1
0
7
H
I
G
H
P
O
W
E
R
L
O
W
P
O
W
E
R
H
I
G
H
o
u
t
p
u
t
v
o
l
t
a
g
eX
C
O
U
T
W
i
t
h
n
o
l
o
a
d
a
p
p
l
i
e
d
,
V
C
C
=
3
.
0
V
W
i
t
h
n
o
l
o
a
d
a
p
p
l
i
e
d
,
V
C
C
=
3
.
0
V3.0
1
.
6V
Hysteresis
Hysteresis
HIGH input
current
I
IH
LOW input
current
I
I
L
V
R
A
M
RAM retention voltage
I
c
cP
o
w
e
r
s
u
p
p
l
y
c
u
r
r
e
n
t
V
T+-
V
T-
V
T
+
-
V
T
-
0
.
20
.
8V
0.2 1.8 V
P0
0
to P0
7
, P1
0
to P1
7
, P2
0
to P2
7
,
P3
0
to P3
7
, P4
0
to P4
7
,P5
0
to P5
7
,
P6
0
to P6
7
, P7
0
to P7
7
, P8
0
to P8
7
,
P9
0
to P9
7
, P10
0
to P10
7,
4.0 µA
µ
A
When clock is stopped 2.0 V
RESET
X
I
N
,
R
E
S
E
T
,
C
N
V
s
s
,
B
Y
T
E
V
I
= 3V , V
CC
=3.0V
V
I
=
0
V
,
V
C
C
=
3
.
0
V-
4
.
0
P0
0
to P0
7
, P1
0
to P1
7
, P2
0
to P2
7
,
P3
0
to P3
7
, P4
0
to P4
7
, P5
0
to P5
7
,
P6
0
to P6
7
, P7
0
to P7
7
, P8
0
to P8
7
,
P9
0
to P9
7
, P10
0
to P10
7,
X
IN
, RESET, CNVss, BYTE
S
quare wave
f(X
CIN
) = 32kHz 4
0
.
0µ
A
R
f
X
I
N
R
f
X
C
I
N
F
e
e
d
b
a
c
k
r
e
s
i
s
t
a
n
c
eX
I
N
F
e
e
d
b
a
c
k
r
e
s
i
s
t
a
n
c
eX
C
I
N
1
0
.
0
3
.
0
M
M
S
quare wave, no
di
v
i
s
i
on
f(X
IN
) = 10MHz mA
8.5 21.25
R
PULLUP
120.0
k
P0
0
to P0
7
, P1
0
to P1
7
, P2
0
to P2
7
,
P3
0
to P3
7
, P4
0
to P4
7
, P5
0
to P5
7
,
P6
0
to P6
7
, P7
2
to P7
7
, P8
0
to P8
4
,
P8
6
, P8
7
, P9
0
to P9
7
,P10
0
to P10
7
L
O
W
o
u
t
p
u
t
v
o
l
t
a
g
e VX
C
O
U
T
0
0
With no load applied, V
CC
=3.0V
With no load applied, V
CC
=3.0V
HIGHPOWER
LOWPOWER
V
I
=
0
V
,
V
C
C
=
3
.
0
V66.0 500.0
I
n
s
i
n
g
l
e
-
c
h
i
p
m
o
d
e
,
t
h
e
o
u
t
p
u
t
p
i
n
s
a
r
e
o
p
e
n
a
n
d
o
t
h
e
r
p
i
n
s
a
r
e
V
S
S
P
u
l
l
-
u
p
r
e
s
i
s
t
a
n
c
e
Ω
Ω
Ω
CLK
0
to CLK
4
,TA2
OUT
,
TB1
IN
, TB2
IN
, INT
0
to INT
2
, NMI,
A
D
T
R
G
,
C
T
S
0
t
o
C
T
S
2
,
S
C
L
,
S
D
A
H
O
L
D
,
R
D
Y
,
T
A
0
I
N
t
o
T
A
2
I
N
,
KI
0
to KI
3
, RxD
0
to RxD
2
1
.
0µA
2
0
.
0
0
.
9µ
A
2
.
8µ
A
f(X
CIN
) = 32kHz
f
(
X
C
I
N
)
=
3
2
k
H
z
Topr = 85°C
when clock is stopped
Topr = 25°C
when clock is stopped
Wh
en a
WAITi
nstruct
i
on
is executed.
Oscillation capa c ity H igh
(Note 2 )
W
h
e
n
a
W
A
I
T
i
n
s
t
r
u
c
t
i
o
n
i
s
e
x
e
c
u
t
e
d
.
O
s
c
i
l
l
a
t
i
o
n
c
a
p
a
c
i
t
y
L
o
w
(
N
o
t
e
2
)
N
o
t
e
1
:
S
p
e
c
i
f
y
a
p
r
o
d
u
c
t
o
f
-
4
0
°
C
t
o
8
5
°
C
t
o
u
s
e
i
t
.
N
o
t
e
2
:
W
i
t
h
o
n
e
t
i
m
e
r
o
p
e
r
a
t
e
d
u
s
i
n
g
f
C
3
2
.
10
1
0
(Topr
= 25°C)
(Topr
= 25°C)
V
C
C
=
3
.
0
V
V
C
C
=
3
.
0
V
VCC = 3V
Table 1.23.23. Electrical characteristics (referenced to V
CC
= 2.7 to 3.3V, V
SS
= 0V at Topr = – 20
o
C
to 85
o
C / – 40
o
C to 85
o
C (Note 1), f(X
IN
) = 10MH
Z
with wait unless otherwise specified)
Electrical characteristics (Vcc = 3V)
162
Mitsubishi microcomputer
s
M16C / 30 Grou
p
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTE
R
9
10
Min.
Data input setup time ns
t
su(DB-RD)
tsu(RDY-BCLK )
ParameterSymbol Unit
Max.
Standard
RDY input setup time ns
Data input hold time ns
t
h(RD-DB)
th(BCLK -RDY) ns
RDY input hold time
ns
HOLD input setup time
t
su(HOLD-BCLK )
ns
HOLD input hold time
t
h(BCLK-HOLD )
Data input access time (no wait) ns
t
ac1(RD-DB) ns
ns
tac2(RD-DB)
tac3(RD-DB)
Data input access time (with wait)
Data input access time (when accessing multiplex bus area)
ns
HLDA output delay time
t
d(BCLK-HLDA)
80
60
0
0
80
0
(Note)
(Note)
(Note)
Note: Calculated according to the BCLK frequency as follows: 100
Max.Min.
ParameterSymbol Unit
Standard
nstr
External clock rise time 18
nst
f
External clock fall time 18
tac1(RD – DB) = f(BCLK) X 2 – 90 [ns]
tac2(RD – DB) = f(BCLK) X 2 – 90
3 X 10
9
[ns]
tac3(RD – DB) = f(BCLK) X 2 – 90
3 X 10
9
[ns]
t
c
External clock input cycle time ns100
t
w(H)
External clock input HIGH pulse width ns40
t
w(L)
External clock input LOW pulse width ns40
VCC = 3V
Table 1.23.25. Memory expansion and microprocessor modes
Timing requirements (referenced to V
CC
= 3V, V
SS
= 0V at Topr = – 20
o
C to 85
o
C / – 40
o
C to 85
o
C (*)
unless otherwise specified)
* : Specify a product of -40°C to 85°C to use it.
Table 1.23.24. External clock input
Electrical characteristics (Vcc = 3V)
163
Mitsubishi microcomputer
s
M16C / 30 Grou
p
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTE
R
VCC = 3V
Timing requirements (referenced to V
CC
= 3V, V
SS
= 0V at Topr = – 20
o
C to 85
o
C / – 40
o
C to 85
o
C (*)
unless otherwise specified)
* : Specify a product of -40°C to 85°C to use it.
Standard
Max.Min. UnitParameterSymbol
nst
w(TAL)
TAi
IN
input LOW pulse width 60
nst
c(TA)
TAi
IN
input cycle time 150 nst
w(TAH)
TAi
IN
input HIGH pulse width 60
Standard
Max.Min. UnitParameterSymbol
nst
c(TA)
TAi
IN
input cycle time 600 nst
w(TAH)
TAi
IN
input HIGH pulse width 300 nst
w(TAL)
TAi
IN
input LOW pulse width 300
Standard
Max.Min. UnitParameterSymbol
nst
c(TA)
TAi
IN
input cycle time 300 nst
w(TAH)
TAi
IN
input HIGH pulse width 150 nst
w(TAL)
TAi
IN
input LOW pulse width 150
Standard
Max.Min. UnitParameterSymbol
nst
w(TAH)
TAi
IN
input HIGH pulse width 150 nst
w(TAL)
TAi
IN
input LOW pulse width 150
Standard
Max.Min. UnitParameterSymbol
nst
c(UP)
TAi
OUT
input cycle time 3000 nst
w(UPH)
TAi
OUT
input HIGH pulse width 1500 nst
w(UPL)
TAi
OUT
input LOW pulse width 1500 nst
su(UP-TIN)
TAi
OUT
input setup time 600 nst
h(TIN-UP)
TAi
OUT
input hold time 600
Table 1.23.27. Timer A input (gating input in timer mode)
Table 1.23.28. Timer A input (external trigger input in one-shot timer mode)
Table 1.23.29. Timer A input (external trigger input in pulse width modulation mode)
Table 1.23.30. Timer A input (up/down input in event counter mode)
Table 1.23.26. Timer A input (counter input in event counter mode)
Electrical characteristics (Vcc = 3V)
164
Mitsubishi microcomputer
s
M16C / 30 Grou
p
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTE
R
Timing requirements (referenced to V
CC
= 3V, V
SS
= 0V at Topr = – 20
o
C to 85
o
C / – 40
o
C to 85
o
C (*)
unless otherwise specified)
* : Specify a product of -40°C to 85°C to use it.
VCC = 3V
Standard
Max.Min.
ParameterSymbol Unit
nst
c(TB)
TBi
IN
input cycle time (counted on one edge) 150 nst
w(TBH)
TBi
IN
input HIGH pulse width (counted on one edge) 60 nst
w(TBL)
TBi
IN
input LOW pulse width (counted on one edge) 60
t
w(TBH)
nsTBi
IN
input HIGH pulse width (counted on both edges) 160
t
w(TBL)
nsTBi
IN
input LOW pulse width (counted on both edges) 160
t
c(TB)
nsTBi
IN
input cycle time (counted on both edges) 300
Standard
Max.Min.
ParameterSymbol Unit
nst
c(TB)
TBi
IN
input cycle time 600 nst
w(TBH)
TBi
IN
input HIGH pulse width 300
t
w(TBL)
nsTBi
IN
input LOW pulse width 300
Standard
Max.Min.
ParameterSymbol Unit
nst
c(TB)
TBi
IN
input cycle time 600 nst
w(TBH)
TBi
IN
input HIGH pulse width 300
t
w(TBL)
nsTBi
IN
input LOW pulse width 300
Standard
Max.Min.
ParameterSymbol Unit
nst
c(AD)
AD
TRG
input cycle time (trigger able minimum) 1500 nst
w(ADL)
AD
TRG
input LOW pulse width 200
Standard
Max.Min.
ParameterSymbol Unit
nst
w(INH)
INTi input HIGH pulse width 380 nst
w(INL)
INTi input LOW pulse width 380
Standard
Max.Min.
ParameterSymbol Unit
nst
c(CK)
CLKi input cycle time 300 nst
w(CKH)
CLKi input HIGH pulse width 150 nst
w(CKL)
CLKi input LOW pulse width 150
t
h(C-Q)
nsTxDi hold time 0
t
su(D-C)
nsRxDi input setup time 50
t
h(C-D)
nsRxDi input hold time 90
t
d(C-Q)
nsTxDi output delay time 160
Table 1.23.31. Timer B input (counter input in event counter mode)
Table 1.23.32. Timer B input (pulse period measurement mode)
Table 1.23.33. Timer B input (pulse width measurement mode)
Table 1.23.34. A-D trigger input
Table 1.23.35. Serial I/O
_______
Table 1.23.36. External interrupt INTi inputs
Electrical characteristics (Vcc = 3V)
165
Mitsubishi microcomputer
s
M16C / 30 Grou
p
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTE
R
t
d(BCLK-AD)
Address output delay time 60 ns
t
d(BCLK-CS)
Chip select output delay time 60 ns
t
h(BCLK-AD)
Address output hold time (BCLK standard) 4 ns
t
h(BCLK-CS)
Chip select output hold time (BCLK standard) 4 ns
t
d(BCLK-ALE)
ALE signal output delay time 60 ns
t
h(BCLK-ALE)
ALE signal output hold time — 4ns
t
d(BCLK-RD)
RD signal output delay time 60 ns
t
h(BCLK-RD)
RD signal output hold time 0 ns
t
h(RD-AD)
Address output hold time (RD standard) 0ns
t
d(BCLK-WR)
WR signal output delay time 60 ns
t
h(BCLK-WR)
WR signal output hold time 0 ns
t
h(WR-AD)
Address output hold time (WR standard) 0ns
t
d(BCLK-DB)
Data output delay time (BCLK standard) 80 ns
t
h(BCLK-DB)
Data output hold time (BCLK standard) 4ns
t
d(DB-WR)
Data output delay time (WR standard) (Note1) ns
t
h(WR-DB)
Data output hold time (WR standard)(Note2) 0 ns
Note 1: Calculated according to the BCLK frequency as follows:
td(DB – WR) = f(BCLK) X 2
10
9
– 80 [ns]
Symbol Standard
Measuring condition Max.Min.
Parameter Unit
Note 2: This is standard value shows the timing when the output is off,
and doesn't show hold time of data bus.
Hold time of data bus is different by capacitor volume and pull-up
(pull-down) resistance value.
Hold time of data bus is expressed in
t = –CR X ln (1 – VOL / VCC)
by a circuit of the right figure.
For example, when VOL = 0.2VCC, C = 30pF, R = 1kΩ, hold time
of output “L” level is
t = – 30pF X 1kΩ X ln (1 – 0.2VCC / VCC)
= 6.7ns.
DBi
R
C
Note 3: Specify a product of -40°C to 85°C to use it.
Switching characteristics (referenced to VCC = 3V, VSS = 0V at Topr = – 20oC to 85oC / – 40oC to
85oC (Note 3), CM15=“1” unless otherwise specified)
VCC = 3V
Figure 1.23.7
Table 1.23.37. Memory expansion and microprocessor modes (with no wait)
Figure 1.23.7. Port P0 to P10 measurement circuit
P6
P7
P8
P10
P9
P0
P1
P2
P3
P4
P5
30pF
Electrical characteristics (Vcc = 3V)
166
Mitsubishi microcomputer
s
M16C / 30 Grou
p
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTE
R
Switching characteristics (referenced to VCC = 3V, VSS = 0V at Topr = – 20oC to 85oC / – 40oC to
85oC (Note 3), CM15=“1” unless otherwise specified)
VCC = 3V
Figure 1.23.7
Table 1.23.38. Memory expansion and microprocessor modes
(when accessing external memory area with wait)
td(BCLK-AD) Address output delay time 60 ns
td(BCLK-CS) Chip select output delay time 60 ns
th(BCLK-AD) Address output hold time (BCLK standard) 4 ns
th(BCLK-CS) Chip select output hold time (BCLK standard) 4 ns
td(BCLK-ALE) ALE signal output delay time 60 ns
th(BCLK-ALE) ALE signal output hold time – 4 ns
td(BCLK-RD) RD signal output delay time 60 ns
th(BCLK-RD) RD signal output hold time 0 ns
th(RD-AD) Address output hold time (RD standard) 0ns
td(BCLK-WR) WR signal output delay time 60 ns
th(BCLK-WR) WR signal output hold time 0 ns
th(WR-AD) Address output hold time (WR standard) 0ns
td(BCLK-DB) Data output delay time (BCLK standard) 80 ns
th(BCLK-DB) Data output hold time (BCLK standard) 4ns
td(DB-WR) Data output delay time (WR standard) (Note1) ns
th(WR-DB) Data output hold time (WR standard)(Note2) 0 ns
Note 1: Calculated according to the BCLK frequency as follows:
td(DB – WR) = f(BCLK)
109– 80 [ns]
Symbol
Standard
Measuring condition
Max.Min.
Parameter Unit
Note 2: This is standard value shows the timing when the output is off,
and doesn't show hold time of data bus.
Hold time of data bus is different by capacitor volume and pull-up
(pull-down) resistance value.
Hold time of data bus is expressed in
t = –CR X ln (1 – VOL / VCC)
by a circuit of the right figure.
For example, when VOL = 0.2VCC, C = 30pF, R = 1kΩ, hold time
of output “L” level is
t = – 30pF X 1kΩ X ln (1 – 0.2VCC / VCC)
= 6.7ns.
DBi
R
C
Note 3: Specify a product of -40°C to 85°C to use it.
Electrical characteristics (Vcc = 3V)
167
Mitsubishi microcomputer
s
M16C / 30 Grou
p
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTE
R
VCC = 3V
Switching characteristics (referenced to VCC = 3V, VSS = 0V at Topr = – 20oC to 85oC / – 40oC to
85oC (Note 2), CM15=“1” unless otherwise specified)
Table 1.23.39. Memory expansion and microprocessor modes
(when accessing external memory area with wait, and select multiplexed bus)
Symbol
Standard
Measuring condition Max.Min.
Parameter Unit
t
d(BCLK-AD)
Address output delay time 60 ns
t
h(BCLK-AD)
Address output hold time (BCLK standard) 4 ns
t
d(BCLK-CS)
Chip select output delay time 60 ns
t
h(BCLK-CS)
Chip select output hold time (BCLK standard) 4 ns
nst
h(RD-AD)
Address output hold time (RD standard) (Note1)
t
d(BCLK-RD)
RD signal output delay time 60 ns
t
h(BCLK-RD)
RD signal output hold time 0 ns
nst
h(WR-AD)
Address output hold time (WR standard) (Note1)
t
d(BCLK-WR)
WR signal output delay time 60 ns
t
d(BCLK-DB)
Data output delay time (BCLK standard) 80 ns
t
h(BCLK-DB)
Data output hold time (BCLK standard) 4 ns
t
d(DB-WR)
Data output delay time (WR standard) (Note1) ns
t
h(BCLK-ALE)
ALE signal output hold time (BCLK standard) – 4 ns
t
d(AD-ALE)
ALE signal output delay time (Address standard) (Note1) ns
t
h(ALE-AD)
ALE signal output hold time(Address standard) 50 ns
t
h(BCLK-WR)
WR signal output hold time 0 ns
nst
h(RD-CS)
Chip select output hold time (RD standard) (Note1)
t
h(WR-CS)
Chip select output hold time (WR standard) (Note1) ns
t
d(AD-RD)
Post-address RD signal output delay time ns0
t
d(AD-WR)
Post-address WR signal output delay time ns0
t
dZ(RD-AD)
Address output floating start time ns8
t
d(BCLK-ALE)
ALE signal output delay time (BCLK standard) ns60
Note 1: Calculated according to the BCLK frequency as follows:
th(RD – AD) = f(BCLK) X 2
10
9
[ns]
th(WR – AD) = f(BCLK) X 2
10
9
[ns]
th(RD – CS) = f(BCLK) X 2
10
9
[ns]
th(WR – CS) = f(BCLK) X 2
10
9
[ns]
td(DB – WR) = f(BCLK) X 2
10
9
– 80 [ns]
X 3
td(AD – ALE) = f(BCLK) X 2
10
9
– 45 [ns]
th(WR – DB) = f(BCLK) X 2
10
9
[ns]
t
h(WR-DB)
Data output hold time (WR standard) ns(Note1)
Note 2: Specify a product of -40°C to 85°C to use it.
Figure 1.23.7
Timing (Vcc = 3V)
168
Mitsubishi microcomputer
s
M16C / 30 Grou
p
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTE
R
VCC = 3V
t
su(D–C)
TAiIN input
TAiOUT input
During event counter mode
TBiIN input
CLKi
TxDi
RxDi
t
c(TA)
t
w(TAH)
t
w(TAL)
t
c(UP)
t
w(UPH)
t
w(UPL)
t
c(TB)
t
w(TBH)
t
w(TBL)
t
c(AD)
t
w(ADL)
t
c(CK)
t
w(CKH)
t
w(CKL)
t
w(INL)
t
w(INH)
t
d(C–Q)
t
h(C–D)
t
h(C–Q)
t
h(TIN–UP)
t
su(UP–TIN)
TAiIN input
(When count on falling
edge is selected)
TAiIN input
(When count on rising
edge is selected)
TAiOUT input
(Up/down input)
INTi input
ADTRG input
Figure 1.23.8. VCC = 3V timing diagram (1)
Timing (Vcc = 3V)
169
Mitsubishi microcomputer
s
M16C / 30 Grou
p
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTE
R
VCC = 3V
Measuring conditions :
• VCC=3V
• Input timing voltage : Determined with VIL=0.6V, VIH=2.4V
• Output timing voltage : Determined with VOL=1.5V, VOH=1.5V
Memory Expansion Mode and Microprocessor Mode
BCLK
HOLD input
HLDA output
P0, P1, P2,
P3, P4,
P50 to P52
(Valid with or without wait)
Note: The above pins are set to high-impedance regardless of the input level of the
BYTE pin and bit (PM06) of processor mode register 0 selects the function of
ports P40 to P43.
t
h(BCLK–HOLD)
t
su(HOLD–BCLK)
(Valid only with wait)
t
d(BCLK–HLDA)
t
d(BCLK–HLDA)
Hi–Z
RDY input
tsu(RDY–BCLK) th(BCLK–RDY)
BCLK
RD
(Multiplexed bus)
(Multiplexed bus)
WR, WRL, WRH
WR, WRL, WRH
(Separate bus)
RD
(Separate bus)
Figure 1.23.9. VCC = 3V timing diagram (2)
Timing (Vcc = 3V)
170
Mitsubishi microcomputer
s
M16C / 30 Grou
p
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTE
R
Read timing
Write timing
BCLK
CSi
ALE
RD
60ns.max
4ns.min
4ns.min
Hi–Z
DB
0ns.min
ADi
BHE
tcyc
80ns.min
BCLK
CSi
ALE
–4ns.min
60ns.max 0ns.min
4ns.min
Hi–Z
DB
4ns.min
ADi
BHE
tcyc
t
h(BCLK–ALE)
t
h(BCLK–DB)
t
d(BCLK–ALE)
t
d(BCLK–WR)
0ns.min
t
h(WR–AD)
Memory Expansion Mode and Microprocessor Mode
(With no wait)
WR,WRL,
WRH
t
d(BCLK–CS)
60ns.max
t
h(BCLK–CS)
t
h(RD–CS)
t
d(BCLK–AD)
60ns.max
t
h(BCLK–AD)
60ns.max
t
d(BCLK–ALE) –4ns.min
t
h(RD–AD) 0ns.min
t
d(BCLK–RD)
t
h(BCLK–RD)
t
ac1(RD–DB)
t
h(RD–DB)
0ns.min
t
SU(DB–RD)
t
d(BCLK–CS)
t
h(BCLK–CS)
4ns.min
60ns.max
0ns.min
t
h(WR–CS)
t
d(BCLK–AD)
60ns.max
t
h(BCLK–AD)
60ns.max
t
h(BCLK–ALE)
t
h(BCLK–WR)
t
d(BCLK–DB)
t
h(WR–DB)
t
d(DB–WR)
(
tc
y
c/2–80
)
ns.min 0ns.min
80ns.max
0ns.min
VCC = 3V
Figure 1.23.10. VCC = 3V timing diagram (3)
Timing (Vcc = 3V)
171
Mitsubishi microcomputer
s
M16C / 30 Grou
p
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTE
R
Read timing
Write timing
BCLK
CSi
ALE
RD
4ns.min
4ns.min
Hi–Z
DB
80ns.min
0ns.min
ADi
BHE
td(BCLK–WR)
60ns.max th(BCLK–WR)
0ns.min
BCLK
CSi
td(BCLK–CS)
60ns.max
td(BCLK–AD)
ALE
th(BCLK–ALE)
th(BCLK–CS)
4ns.min
tcyc 0ns.min
th(WR–CS)
0ns.min
th(WR–AD)
ADi
BHE
td(BCLK–DB) 4ns.min
th(BCLK–DB)
td(DB–WR)
(tcyc–80)ns.min 0ns.min
th(WR–DB)
DBi
th(RD–AD)
0ns.min
td(BCLK–ALE)
60ns.max
tSU(DB–RD)
Memory Expansion Mode and Microprocessor Mode
(When accessing external memory area with wait)
Measuring conditions :
• V
CC=3V
• Input timing voltage : Determined with VIL=0.48V, VIH=1.5V
• Output timing voltage : Determined with VOL=1.5V, VOH=1.5V
WR,WRL,
WRH
td(BCLK–CS)
60ns.max
th(RD–CS)
tcyc
td(BCLK–AD)
60ns.max th(BCLK–AD)
–4ns.min
th(BCLK–ALE)
60ns.max
td(BCLK–RD) th(BCLK–RD) 0ns.min
tac2(RD–DB)
th(RD–DB) 0ns.min
th(BCLK–AD)
60ns.max
td(BCLK–ALE) 60ns.max –4ns.min
80ns.max
th(BCLK–CS)
4ns.min
VCC = 3V
Figure 1.23.11. VCC = 3V timing diagram (4)
Timing (Vcc = 3V)
172
Mitsubishi microcomputer
s
M16C / 30 Grou
p
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTE
R
Memory Expansion Mode and Microprocessor Mode
(When accessing external memory area with wait, and select multiplexed bus)
Measuring conditions :
• VCC=3V
• Input timing voltage : Determined with VIL=0.48V,VIH=1.5V
• Output timing voltage : Determined with VOL=1.5V,VOH=1.5V
Read timing
Write timing
0ns.min
BCLK
CSi
ALE 60ns.max –4ns.min
th(BCLK–CS)
4ns.min
tcyc
ADi
BHE
80ns.max th(BCLK–DB)
4ns.min
td(DB–WR)
(tcyc x 3/2–80)ns.min
ADi
/DBi Address Data output
(tcyc/2)ns.min
Address
(tcyc/2–60)ns.min
td(BCLK–ALE)
td(BCLK–WR)
4ns.min
BCLK
CSi
td(BCLK–CS)
60ns.max
ALE
RD
4ns.min
th(BCLK–CS)
4ns.min
tcyc
ADi
BHE
ADi
/DBi th(RD–DB)
0ns.min
Address
(tcyc/2)ns.min
Data input
Address
tac3(RD–DB)
tdz(RD–AD)
8ns.max
td(AD–RD)
0ns.min
td(AD–WR)
WR,WRL,
WRH
th(RD–CS)
td(AD–ALE) (tcyc/2–45)ns.min
tSU(DB–RD)
80ns.min
th(ALE–AD)
50ns.min
td(BCLK–AD)
60ns.max
60ns.max
td(BCLK–ALE) th(BCLK–ALE)
–4ns.min (tcyc/2)ns.min
th(RD–AD)
th(BCLK–AD)
th(BCLK–RD)
0ns.min
td(BCLK–RD)
60ns.max
td(BCLK–CS)
60ns.max th(WR–CS)
(tcyc/2)ns.min
td(BCLK–DB)
td(AD–ALE)
td(BCLK–AD)
60ns.max
th(WR–DB)
(tcyc/2)ns.min
th(BCLK–AD)
th(WR–AD)
th(BCLK–WR)
th(BCLK–ALE) 0ns.min
60ns.max
VCC = 3V
Figure 1.23.12. VCC = 3V timing diagram (5)
173
Package Outline
Mitsubishi microcomputer
s
M16C / 30 Grou
p
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTE
R
LQFP100-P-1414-0.50 Weight(g)
–0.63
JEDEC Code
EIAJ Package Code Lead Material
Cu Alloy
100P6Q-A
Plastic 100pin 14✕14mm body LQFP
–
0.1
–
––
0.2
–
–
––
–
–––
–
Symbol Min Nom Max
A
A
2
b
c
D
E
H
E
L
L
1
y
b
2
Dimension in Millimeters
H
D
A
1
0.225 ––
I
2
0.9 ––
M
D
14.4 ––
M
E
14.4
10°0°0.1
1.0 0.70.50.3 16.216.015.8 16.216.015.8 0.5 14.114.013.9 14.114.013.9 0.1750.1250.105 0.280.180.13 1.4
01.7
e
e
E
H
E
1
76
75
51
5026
25
H
D
D
A
F
y
100
Lp 0.45
–
–
0.6
0.25
–
0.75
–
0.08
x
A3
b
x
M
A
1
A
2
L
1
L
Detail F
Lp
A3
c
M
D
l
2
b
2
M
E
e
Recommended Mount Pad
MMP
QFP100-P-1420-0.65 1.58
Weight(g)
–
JEDEC Code
EIAJ Package Code Lead Material
Alloy 42
100P6S-A
Plastic 100pin 14✕20mm body QFP
–
0.1
–
––
0.2
–
–
––
–
–––
–
Symbol Min Nom Max
A
A
2
b
c
D
E
H
E
L
L
1
y
b
2
Dimension in Millimeters
H
D
A
1
0.35 ––
I
2
1.3 ––
M
D
14.6 ––
M
E
20.6
10°0°0.1
1.4 0.80.60.4 23.122.822.5 17.116.816.5 0.65 20.220.019.8 14.214.013.8 0.20.150.13 0.40.30.25 2.8
03.05
e
e
e
E
c
H
E
1
30
31
81
50
80
51
H
D
D
M
D
M
E
A
F
A
1
A
2
L
1
L
y
b
2
I
2
Recommended Mount Pad
Detail F
100
x––0.13
bx
M
MMP
Package Outline
SFR difference between M16C/62A and M16C/30
174
Mitsubishi microcomputer
s
M16C / 30 Grou
p
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTE
R
SFR difference between M16C/62A and M16C/30
Address Symbol M16C/62A M16C/30
0005 PM1 Processor mode register 1
bit0:Reserved bit
bit1:Nothing is assigned
bit2:Nothing is assigned
PM13:Internal reserved area expansion bit
bit4:Reserved bit
bit5:Reserved bit
bit6:Reserved bit
PM17:Wait bit
Processor mode register 1
bit0:Reserved bit
bit1:Nothing is assigned
bit2:Nothing is assigned
bit3:Reserved bit
bit4:Reserved bit
bit5:Reserved bit
bit6:Reserved bit
PM17:Wait bit
000A PRCR Protect register
PRC0:Enables writing to system clock control registers 0
and 1
PRC1:Enables writing to processor mode registers 0 and 1
PRC2:Enables writing to port P9 direction register
and SI/O control register
bit3-bit7:Nothing is assigned
Protect register
PRC0:Enables writing to system clock control registers 0
and 1
PRC1:Enables writing to processor mode registers 0 and 1
PRC2:Enables writing to port P9 direction register
bit3-bit7:Nothing is assigned
0030 SAR1 DMA1 source pointer Reserved register
0031 SAR1 DMA1 source pointer Reserved register
0032 SAR1 DMA1 source pointer Reserved register
0034 DAR1 DMA1 destination pointer Reserved register
0035 DAR1 DMA1 destination pointer Reserved register
0036 DAR1 DMA1 destination pointer Reserved register
0038 TCR1 DMA1 transfer counter Reserved register
0039 TCR1 DMA1 transfer counter Reserved register
003C DM1CON DMA1 control register Reserved register
0044 INT3IC INT3 interrupt control register Reserved register
0045 TB5IC Timer B5 interrupt control register Reserved register
0046 TB4IC Timer B4 interrupt control register Reserved register
0047 TB3IC Timer B3 interrupt control register Reserved register
0048 S4IC/INT5IC SI/O4,INT5 interrupt control register Reserved register
0049 S3IC/INT4IC SI/O3,INT4 interrupt control register Reserved register
004C DM1IC DMA1 interrupt control register Reserved register
0058 TA3IC Timer A3 interrupt control register Reserved register
0059 TA4IC Timer A4 interrupt control register Reserved register
005A TB0IC Timer B0 interrupt control register Reserved register
0340 TBSR Timer B3, 4, 5 count start flag Reserved register
0342 TA11 Timer A1-1 register Reserved register
0343 TA11 Timer A1-1 register Reserved register
0344 TA21 Timer A2-1 register Reserved register
0345 TA21 Timer A2-1 register Reserved register
0346 TA41 Timer A4-1 register Reserved register
0347 TA41 Timer A4-1 register Reserved register
0348 INVC0 Three-phase PWM control register 0 Reserved register
0349 INVC1 Three-phase PWM control register 1 Reserved register
034A IDB0 Three-phase output buffer register 0 Reserved register
034B IDB1 Three-phase output buffer register 1 Reserved register
034C DTT Dead time timer Reserved register
034D ICTB2 Timer B2 interrupt occurrence frequency set
counter Reserved register
Mitsubishi microcomputer
s
M16C / 30 Grou
p
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTE
R
SFR difference between M16C/62A and M16C/30
175
SFR difference between M16C/62A and M16C/30
Address Symbol M16C/62A M16C/30
035F IFSR
Interrupt cause select register
IFSR0:INT0 interrupt polarity switching bit
IFSR1:INT1 interrupt polarity switching bit
IFSR2:INT2 interrupt polarity switching bit
IFSR3:INT3 interrupt polarity switching bit
IFSR4:INT4 interrupt polarity switching bit
IFSR5:INT5 interrupt polarity switching bit
IFSR6:Interrupt request cause select bit
IFSR7:Interrupt request cause select bit
Interrupt cause select register
IFSR0:INT0 interrupt polarity switching bit
IFSR1:INT1 interrupt polarity switching bit
IFSR2:INT2 interrupt polarity switching bit
bit3:Reserved bit
bit4:Reserved bit
bit5:Reserved bit
bit6:Reserved bit
bit7:Reserved bit
0360 S3TRR SI/O3 transmit/receive register Reserved register
0362 S3C SI/O3 control register Reserved register
0363 S3BRG SI/O3 bit rate generator Reserved register
0364 S4TRR SI/O4 transmit/receive register Reserved register
0366 S4C SI/O4 control register Reserved register
0367 S4BRG SI/O4 bit rate generator Reserved register
0380 TABSR Count start flag
TA0S:Timer A0 count start flag
TA1S:Timer A1 count start flag
TA2S:Timer A2 count start flag
TA3S:Timer A3 count start flag
TA4S:Timer A4 count start flag
TB0S:Timer B0 count start flag
TB1S:Timer B1 count start flag
TB2S:Timer B2 count start flag
Count start flag
TA0S:Timer A0 count start flag
TA1S:Timer A1 count start flag
TA2S:Timer A2 count start flag
bit3:Reserved bit
bit4:Reserved bit
bit5:Reserved bit
TB1S:Timer B1 count start flag
TB2S:Timer B2 count start flag
0382 ONSF One-shot start flag
TA0OS:Timer A0 one-shot start flag
TA1OS:Timer A1 one-shot start flag
TA2OS:Timer A2 one-shot start flag
TA3OS:Timer A3 one-shot start flag
TA4OS:Timer A4 one-shot start flag
bit5:Nothing is assigned
TA0TGL:Timer A0 event/trigger select bit
TA0TGH: "00","01","10"and"11" can be chosen.
One-shot start flag
TA0OS:Timer A0 one-shot start flag
TA1OS:Timer A1 one-shot start flag
TA2OS:Timer A2 one-shot start flag
bit3:Reserved bit
bit4:Reserved bit
bit5:Nothing is assigned
TA0TGL:Timer A0 event/trigger select bit
TA0TGH: "00","01"and"11" can be chosen.
"10" can't be chosen.
0383 TRGSR
Trigger select register
TA1TGL:Timer A1 event/trigger select bit
TA1TGH: "00","01","10"and"11" can be chosen.
TA2TGL:Timer A2 event/trigger select bit
TA2TGH: "00","01","10"and"11" can be chosen.
TA3TGL:Timer A3 event/trigger select bit
TA3TGH: "00","01","10"and"11" can be chosen.
TA4TGL:Timer A4 event/trigger select bit
TA4TGH: "00","01","10"and"11" can be chosen.
Trigger select register
TA1TGL:Timer A1 event/trigger select bit
TA1TGH: "00","01","10"and"11" can be chosen.
TA2TGL:Timer A2 event/trigger select bit
TA2TGH: "00","01"and"10" can be chosen.
"11" can't be chosen.
bit4:Reserved bit
bit5:Reserved bit
bit6:Reserved bit
bit7:Reserved bit
0384 UDF Up-down flag
TA0UD:Timer A0 up/down flag
TA1UD:Timer A1 up/down flag
TA2UD:Timer A2 up/down flag
TA3UD:Timer A3 up/down flag
TA4UD:Timer A4 up/down flag
TA2P:Timer A2 two-phase pulse signal processing select bit
TA3P:Timer A3 two-phase pulse signal processing
select bit
TA4P:Timer A4 two-phase pulse signal processing
select bit
Up-down flag
TA0UD:Timer A0 up/down flag
TA1UD:Timer A1 up/down flag
TA2UD:Timer A2 up/down flag
bit3:Reserved bit
bit4:Reserved bit
TA2P:Timer A2 two-phase pulse signal processing select bit
bit6:Reserved bit
bit7:Reserved bit
SFR difference between M16C/62A and M16C/30
176
Mitsubishi microcomputer
s
M16C / 30 Grou
p
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTE
R
SFR difference between M16C/62A and M16C/30
Address Symbol M16C/62A M16C/30
039C TB1MR Timer B1 mode register
Event counter mode
TMOD0:Operation mode select bit
TMOD1:
MR0:Count polarity select bit
MR1:
MR2:Nothing is assigned
MR3:Invalid
TCK1:Event clock select "0" and "1" can be
chosen.
Timer B1 mode register
Event counter mode
TMOD0:Operation mode select bit
TMOD1:
MR0:Count polarity select bit
MR1:
MR2:Nothing is assigned
MR3:Invalid
TCK1:Event clock select "0 " can be chosen. "1"
can't be chosen.
03B6 FMR1 Flash memory control register 1 Reserved register
03B7 FMR0 Flash memory control register 0 Reserved register
03B8 DM0SL
DMA0 request cause select register
DMA0 request factors
Falling edge of INT0 pin
Software trigger
Timer A0
Timer A1
Timer A2
Timer A3
Timer A4
two edges of INT0 pin
Timer B0
Timer B1
Timer B2
Timer B3
Timer B4
Timer B5
UART0 transmit
UART0 receive
UART2 transmit
UART2 receive
UART1 transmit
A-D conversion
DMA0 request cause select register
DMA0 request factors
Falling edge of INT0 pin
Software trigger
Timer A0
Timer A1
Timer A2
two edges of INT0 pin
Timer B1
Timer B2
UART0 transmit
UART0 receive
UART2 transmit
UART2 receive
UART1 transmit
A-D conversion
03BA DM1SL DMA1 request cause select register Reserved register
03BC CRCD CRC data register Reserved register
03BD CRCIN CRC data register Reserved register
03BE CRCIN CRC input register Reserved register
03D6 ADCON0 A-D control register 0
CH0:Analog input pin select bit
CH1:
CH2:
MD0:A-D operation mode select bit 0
MD1: "00","01","10"and"11" can be chosen
TRG:Trigger select bit
ADST:A-D conversion start flag
CKS0:Frequency select bit 0
A-D control register 0
CH0:Analog input pin select bit
CH1:
CH2:
MD0:A-D operation mode select bit 0
MD1: "00 " can be chosen. "01","10"and"11" can't
be chosen.
TRG:Trigger select bit
ADST:A-D conversion start flag
CKS0:Frequency select bit 0
03D7 ADCON1 A-D control register 1
SCAN0:A-D sweep pin select bit
SCAN1:
MD2:A-D operation mode select bit 1
BITS:8/10-bit mode select bit
CKS1:Frequency select bit 1
VCUT:Vref connect bit
OPA0:External op-amp connection mode bit
OPA1:
A-D control register 1
bit0:Reserved bit
bit1:Reserved bit
bit2:Reserved bit
BITS:8/10-bit mode select bit
CKS1:Frequency select bit 1
VCUT:Vref connect bit
OPA0:External op-amp connection mode bit
OPA1:
© 2002 MITSUBISHI ELECTRIC CORP.
Printed in Japan (ROD) II
New publication, effective June. 2002.
Specifications subject to change without notice.
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