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TCA9517

GND

VCCA

3SDAA

2SCLA

7SCLB

6SDAB

I2C or SMBus Master

(e.g. Processor)

5EN

VCCB

I2C Slave Devices

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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

TCA9517

SCPS242D –DECEMBER 2012–REVISED JULY 2017

TCA9517 Level-Shifting I

C Bus Repeater

1 Features

1• Two-Channel Bidirectional Buffer

• I2C Bus and SMBus Compatible

• Operating Supply Voltage Range of 0.9 V to 5.5 V

on A-side

• Operating Supply Voltage Range of 2.7 V to 5.5 V

on B-side

• Voltage-Level Translation From 0.9 V - 5.5 V to

2.7 V - 5.5 V

• Footprint and Functional Replacement for

PCA9515B

• Active-High Repeater-Enable Input

• Open-Drain I2C I/O

• 5.5-V Tolerant I2C and Enable Input Support

Mixed-Mode Signal Operation

• Accommodates Standard Mode and Fast Mode

I2C Devices and Multiple Masters

• High-Impedance I2C Pins When Powered-Off

• Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

• ESD Protection Exceeds JESD 22

– 5500 V Human-Body Model (A114-A)

– 200 V Machine Model (A115-A)

– 1000 V Charged-Device Model (C101)

2 Applications

• Servers

• Routers (Telecom Switching Equipment)

• Industrial Equipment

• Products with Many I2C Slaves and/or Long PCB

Traces

3 Description

The TCA9517 is a bidirectional buffer with level

shifting capabilities for I2C and SMBus systems. It

provides bidirectional voltage-level translation (up-

translation/down-translation) between low voltages

(down to 0.9 V) and higher voltages (2.7 V to 5.5 V)

in mixed-mode applications. This device enables I2C

and SMBus systems to be extended without

degradation of performance, even during level

shifting.

The TCA9517 buffers both the serial data (SDA) and

the serial clock (SCL) signals on the I2C bus, thus

allowing two buses of up to 400-pF bus capacitance

to be connected in an I2C application.

The TCA9517 has two types of drivers: A-side drivers

and B-side drivers. All inputs and I/Os are over-

voltage tolerant to 5.5 V, even when the device is

unpowered (VCCB and/or VCCA = 0 V).

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)

TCA9517 VSSOP (8) 3.00 mm × 3.00 mm

SOIC (8) 4.90 mm x 3.91 mm

(1) For all available packages, see the orderable addendum at

the end of the datasheet.

Simplified Schematic

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Table of Contents

1 Features.................................................................. 1

2 Applications ........................................................... 1

3 Description............................................................. 1

4 Revision History..................................................... 2

5 Description (continued)......................................... 3

6 Pin Configuration and Functions......................... 4

7 Specifications......................................................... 4

7.1 Absolute Maximum Ratings ..................................... 4

7.2 ESD Ratings.............................................................. 5

7.3 Recommended Operating Conditions....................... 5

7.4 Thermal Information.................................................. 5

7.5 Electrical Characteristics........................................... 6

7.6 Timing Requirements................................................ 6

7.7 I2C Interface Switching Characteristics..................... 7

7.8 Typical Characteristics.............................................. 8

8 Parameter Measurement Information .................. 9

9 Detailed Description............................................ 10

9.1 Overview................................................................. 10

9.2 Functional Block Diagram....................................... 10

9.3 Feature Description................................................. 11

9.4 Device Functional Modes........................................ 11

10 Application and Implementation........................ 12

10.1 Application Information.......................................... 12

10.2 Typical Application ............................................... 12

11 Power Supply Recommendations ..................... 15

12 Layout................................................................... 16

12.1 Layout Guidelines ................................................. 16

12.2 Layout Example .................................................... 16

13 Device and Documentation Support................. 17

13.1 Community Resource............................................ 17

13.2 Trademarks........................................................... 17

13.3 Electrostatic Discharge Caution............................ 17

13.4 Glossary................................................................ 17

14 Mechanical, Packaging, and Orderable

Information........................................................... 17

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision C (June 2015) to Revision D Page

• Deleted VCCA < VCCB from the Design Requirements list ..................................................................................................... 12

Changes from Revision B (May 2013) to Revision C Page

• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional

Modes,Application and Implementation section, Power Supply Recommendations section, Layout section, Device

and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1

• Removed Ordering Information table. .................................................................................................................................... 3

Changes from Revision A (April 2013) to Revision B Page

• Updated the TOP-SIDE MARKING column of the ORDERING INFORMATION TABLE...................................................... 1

Changes from Original (December 2012) to Revision A Page

• Added D package to document.............................................................................................................................................. 1

• Updated the TOP-SIDE MARKING column of the ORDERING INFORMATION TABLE...................................................... 1

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5 Description (continued)

The type of buffer design on the B-side prevents it from being used in series with devices which use static

voltage offset. This is because these devices do not recognize buffered low signals as a valid low and do not

propagate it as a buffered low again.

The B-side drivers operate from 2.7 V to 5.5 V. The output low level for this internal buffer is approximately 0.5 V,

but the input voltage must be 70 mV or more below the output low level when the output internally is driven low.

The higher-voltage low signal is called a buffered low. When the B-side I/O is driven low internally, the low is not

recognized as a low by the input. This feature prevents a lockup condition from occurring when the input low

condition is released.

The A-side drivers operate from 0.9 V to 5.5 V and drive more current. They do not require the buffered low

feature (or the static offset voltage). This means that a low signal on the B-side translates to a nearly 0 V low on

the A-side, which accommodates smaller voltage swings of lower-voltage logic. The output pulldown on the A-

side drives a hard low, and the input level is set at 0.3 × VCCA to accommodate the need for a lower low level in

systems where the low-voltage-side supply voltage is as low as 0.9 V.

The A-side of two or more TCA9517 s can be connected together, allowing many topographies (See Figure 8

and Figure 9 ), with the A-side as the common bus. Also, the A-side can be connected directly to any other buffer

with static- or dynamic-offset voltage. Multiple TCA9517 s can be connected in series, A-side to B-side, with no

buildup in offset voltage and with only time-of-flight delays to consider. The TCA9517 cannot be connected B-

side to B-side, because of the buffered low voltage from the B-side. The B-side cannot be connected to a device

with rise time accelerators.

VCCA is only used to provide the 0.3 × VCCA reference to the A-side input comparators and for the power-good-

detect circuit. The TCA9517 logic and all I/Os are powered by the VCCB pin.

As with the standard I2C system, pullup resistors are required to provide the logic-high levels on the buffered

bus. The TCA9517 has standard open-drain configuration of the I2C bus. The size of these pullup resistors

depends on the system, but each side of the repeater must have a pullup resistor. The device is designed to

work with Standard mode and Fast mode I2C devices in addition to SMBus devices. Standard mode I2C devices

only specify 3 mA in a generic I2C system, where Standard mode devices and multiple masters are possible.

Under certain conditions, higher termination currents can be used.

VCCA

SCLA

SDAA

GND

VCCB

SCLB

SDAB

VCCA VCCB

GND EN

SDAA SDAB

SCLA SCLB

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6 Pin Configuration and Functions

D Packages

8-Pin SOIC

Top View

DGK Package

8-Pin VSSOP

Top View

Pin Functions

PIN TYPE DESCRIPTION

NO. NAME

1 VCCA Supply A-side supply voltage (0.9 V to 5.5 V)

2 SCLA Input/Output Serial clock bus, A-side. Connect to VCCA through a pull-up resistor. If unused, connect directly to

ground.

3 SDAA Input/Output Serial data bus, A-side. Connect to VCCA through a pull-up resistor. If unused, connect directly to

ground.

4 GND Ground Ground

5 EN Input Active-high repeater enable input

6 SDAB Input/Output Serial data bus, B-side. Connect to VCCB through a pull-up resistor. If unused, connect directly to

ground.

7 SCLB Input/Output Serial clock bus, B-side. Connect to VCCB through a pull-up resistor. If unused, connect directly to

ground.

8 VCCB Supply B-side and device supply voltage (2.7 V to 5.5 V)

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)

MIN MAX UNIT

VCCB Supply voltage range –0.5 7 V

VCCA Supply voltage range –0.5 7 V

VIEnable input voltage range(2) –0.5 7 V

VI/O I2C bus voltage range(2) –0.5 7 V

IIK Input clamp current VI< 0 –50 mA

IOK Output clamp current VO< 0 –50

IOContinuous output current ±50 mA

Continuous current through VCC or GND ±100 mA

Tstg Storage temperature range –65 150 °C

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(1) JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process.

7.2 ESD Ratings VALUE UNIT

V(ESD) Electrostatic discharge

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±5500

Charged-device model (CDM), per JEDEC specification JESD22-

C101(2) ±1000

Machine model (A115-A) ±200

(1) Low-level supply voltage

(2) VIL specification is for the first low level seen by the SDAB and SCLB lines. VILc is for the second and subsequent low levels seen by the

SDAB and SCLB lines. See VILC and Pullup Resistor Sizing for VILC application information

7.3 Recommended Operating Conditions MIN MAX UNIT

VCCA Supply voltage, A-side bus 0.9(1) 5.5 V

VCCB Supply voltage, B-side bus 2.7 5.5 V

VIH High-level input voltage SDAA, SCLA 0.7 × VCCA 5.5 VSDAB, SCLB 0.7 × VCCB 5.5

EN 0.7 × VCCB 5.5

VIL Low-level input voltage SDAA, SCLA 0.3 × VCCA VSDAB, SCLB(2) 0.3 × VCCB

EN 0.3 × VCCB

IOL Low-level output current 6 mA

TAOperating free-air temperature –40 85 °C

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

7.4 Thermal Information

THERMAL METRIC(1) TCA9517

UNITDGK (VSSOP) D (SOIC)

8 PINS 8 PINS

RθJA Junction-to-ambient thermal resistance 187.6 133.6 °C/W

RθJC(top) Junction-to-case (top) thermal resistance 59.3 87.6 °C/W

RθJB Junction-to-board thermal resistance 108.6 74.2 °C/W

ψJT Junction-to-top characterization parameter 3.4 36.9 °C/W

ψJB Junction-to-board characterization parameter 106.9 73.7 °C/W

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7.5 Electrical Characteristics

VCCB = 2.7 V to 5.5 V, GND = 0 V, TA= –40°C to 85°C (unless otherwise noted)

PARAMETER TEST CONDITIONS VCCB MIN TYP MAX UNIT

VIK Input clamp voltage II= –18 mA 2.7 V to 5.5 V –1.2 V

VOL Low-level output

voltage SDAB, SCLB IOL = 100 μA or 6 mA,

VILA = VILB = 0 V 2.7 V to 5.5 V 0.45 0.52 0.6 V

SDAA, SCLA IOL = 6 mA 0.1 0.2

VOL – VILc Low-level input voltage

below low-level output

voltage SDAB, SCLB ensured by design 2.7 V to 5.5 V 70 mV

VILC SDA and SCL low-level

input voltage contention SDAB, SCLB 2.7 V to 5.5 V 0.4 V

ICC Quiescent supply current for VCCA

Both channels low,

SDAA = SCLA = GND and

SDAB = SCLB = open, or

SDAA = SCLA = open and

SDAB = SCLB = GND

1 mA

ICC Quiescent supply current

Both channels high,

SDAA = SCLA = VCCA and

SDAB = SCLB = VCCB and

EN = VCCB

5.5 V

1.5 5

Both channels low,

SDAA = SCLA = GND and

SDAB = SCLB = open 1.5 5

In contention,

SDAA = SCLA = GND and

SDAB = SCLB = GND 3 5

IIInput leakage current

SDAB, SCLB VI= VCCB

2.7 V to 5.5 V

±1

μA

VI= 0.2 V 10

SDAA, SCLA VI= VCCB ±1

VI= 0.2 V 10

EN VI= VCCB ±1

VI= 0.2 V –10 –30

IOH High-level output

leakage current SDAB, SCLB VO= 3.6 V 2.7 V to 5.5 V 10 μA

SDAA, SCLA 10

CIInput capacitance EN VI= 3 V or 0 V 3.3 V 6 10 pF

SCLA, SCLB VI= 3 V or 0 V 3.3 V 8 13

0 V 7 11

CIO Input/output

capacitance SDAA, SDAB VI= 3 V or 0 V 3.3 V 8 13 pF

0 V 7 11

(1) EN should change state only when the global bus and the repeater port are in an idle state.

7.6 Timing Requirements

over recommended operating free-air temperature range (unless otherwise noted) MIN MAX UNIT

tsu Setup time, EN high before Start condition(1) 100 ns

thHold time, EN high after Stop condition(1) 100 ns

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(1) Times are specified with loads of 1.35-kΩpull-up resistance and 50-pF load capacitance on the B-side and 167-Ωpull-up and 57-pF

load capacitance on the A side. Different load resistance and capacitance alter the RC time constant, thereby changing the propagation

delay and transition times.

(2) pull-up voltages are VCCA on the A side and VCCB on the B-side.

(3) Typical values were measured with VCCA = VCCB = 3.3 V at TA= 25°C, unless otherwise noted.

(4) The tPLH delay data from B to A side is measured at 0.4 V on the B-side to 0.5 VCCA on the A side when VCCA is less than 2 V, and

1.5 V on the A side if VCCA is greater than 2 V.

(5) The proportional delay data from A to B-side is measured at 0.3 VCCA on the A side to 1.5 V on the B-side.

(6) Typical value measured with VCCA = 2.7 V at TA= 25°C

7.7 I2C Interface Switching Characteristics

VCCB = 2.7 V to 5.5 V, GND = 0 V, TA= –40°C to 85°C (unless otherwise noted)(1) (2)

PARAMETER FROM

(INPUT) TO

(OUTPUT) TEST CONDITIONS MIN TYP(3) MAX UNIT

tPLZ Propagation delay

SDAB, SCLB(4)

(see Figure 6)SDAA, SCLA(4)

(see Figure 6)80 141 250 ns

SDAA, SCLA(5)

(see Figure 5)SDAB, SCLB(5)

(see Figure 5)25 74 110

tPZL Propagation delay SDAB, SCLB SDAA, SCLA

VCCA ≤2.7 V

(see Figure 4)30 76(6) 110

VCCA ≥3 V

(see Figure 4)10 86 230

SDAA, SCLA(5)

(see Figure 5)SDAB, SCLB(5)

(see Figure 5)60 107 230

tTLH Transition time B-side to A side 80% 20%

VCCA ≤2.7 V

(see Figure 5)10 12 15

VCCA ≥3 V

(see Figure 5)40 42 45

A side to B-side

(see Figure 4)110 125 140

tTHL Transition time B-side to A side 80% 20%

VCCA ≤2.7 V

(see Figure 5)1 52(6) 105

VCCA ≥3 V

(see Figure 5)20 67 175

A side to B-side

(see Figure 4)30 48 90

Port A IOL (mA)

Port A VOL (V)

0 1 2 3 4 5 6

0.025

0.05

0.075

0.1

0.125

0.15

D001

-40C

25C

85C

Port B IOL (mA)

Port B VOL (V)

0 1 2 3 4 5 6

0.49

0.5

0.51

0.52

0.53

0.54

D002

-40C

25C

85C

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7.8 Typical Characteristics

VCCA = 0.9 V, VCCB = 2.7 V

Figure 1. Port A VOL vs IOL Figure 2. Port B VOL vs IOL

tPLH

INPUT

SDAB, SCLB

OUTPUT

SCLA, SDAA

50% is V is less than 2 V

1.5 V if V is greater than 2 V

CCA

0.4 V

3 V

0.1 V

1.5 V1.5 V

INPUT

OUTPUT

1.2 V

VOL

tPZL tPLZ

80%

20%

0.6 V 0.6 V

80%

20%

tTHL tTLH

0.3 VCCA

INPUT

OUTPUT

3 V

80%

20%

1.5 V 1.5 V

80%

20%

0.3 VCCA

VCCA

tPZL tPLZ

t /t

PLZ PZL

TEST S1

CL= 57 pF

(see Note C)

GND

PULSE

GENERATOR DUT

(see Note B)

TEST CIRCUIT FOR OPEN-DRAIN OUTPUT

(see Note A)

LVCC

VCC

VIN VOUT

VCC

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8 Parameter Measurement Information

A. RL= 167 Ω(0.9 V to 2.7 V) and RL= 450 Ω(3.0 V to 5.5 V) on the A side and 1.35 kΩon the B-side

B. RTtermination resistance should be equal to ZOUT of pulse generators.

C. CLincludes probe and jig capacitance.

D. All input pulses are supplied by generators having the following characteristics: PRR ≤10 MHz, ZO= 50 Ω,

slew rate ≥1 V/ns.

E. The outputs are measured one at a time, with one transition per measurement.

F. tPLH and tPHL are the same as tpd.

G. tPLZ and tPHZ are the same as tdis.

H. tPZL and tPZH are the same as ten.

Figure 3. Test Circuit

Figure 4. Waveform 1 – Propagation Delay and

Transition Times for B-side to A-side Figure 5. Waveform 2 – Propagation Delay and

Transition Times for A-side to B-side

Figure 6. Waveform 3 – Propagation Delay for B-side to A-side

SDAB

SCLBSCLA

SDAA

VCCB

Pullup

Resistor

GND

1 8

VCCA VCCB

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9 Detailed Description

9.1 Overview

The TCA9517 is a bidirectional buffer with level shifting capabilities for I2C and SMBus systems. It provides

bidirectional voltage-level translation (up-translation/down-translation) between low voltages (down to 0.9 V) and

higher voltages (2.7 V to 5.5 V) in mixed-mode applications. This device enables I2C and SMBus systems to be

extended without degradation of performance, even during level shifting.

The TCA9517 buffers both the serial data (SDA) and the serial clock (SCL) signals on the I2C bus, thus allowing

two buses of up to 400-pF bus capacitance to be connected in an I2C application.

The TCA9517 has two types of drivers: A-side drivers and B-side drivers. All inputs and I/Os are over-voltage

tolerant to 5.5 V, even when the device is unpowered (VCCB and/or VCCA = 0 V).

9.2 Functional Block Diagram

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9.3 Feature Description

9.3.1 Two-Channel Bidirectional Buffer

The TCA9517 is a two-channel bidirectional buffer with level-shifting capabilities

9.3.2 Active-High Repeater-Enable Input

The TCA9517 has an active-high enable (EN) input with an internal pull-up to VCCB, which allows the user to

select when the repeater is active. This can be used to isolate a badly behaved slave on power-up reset. The EN

input should change state only when the global bus and repeater port are in an idle state, to prevent system

failures.

9.3.3 VOL B-Side Offset Voltage

The B-side drivers operate from 2.7 V to 5.5 V. The output low level for this internal buffer is approximately 0.5 V,

but the input voltage must be 70 mV or more below the output low level when the output internally is driven low.

The higher-voltage low signal is called a buffered low. When the B-side I/O is driven low internally, the low is not

recognized as a low by the input. This feature prevents a lockup condition from occurring when the input low

condition is released. This type of design prevents 2 B-side ports from being connected to each other.

9.3.4 Standard Mode and Fast Mode Support

The TCA9517 supports standard mode as well as fast mode I2C. The maximum system operating frequency will

depend on system design and the delays added by the repeater.

9.3.5 Clock Stretching Support

The TCA9517 can support clock stretching, but care needs to be taken to minimize the overshoot voltage

presented during the hand-off between the slave and master. This is best done by increasing the pull-up resistor

value.

9.4 Device Functional Modes

Table 1. Function Table

INPUT

EN FUNCTION

L Outputs disabled

HSDAA = SDAB

SCLA = SCLB

BUS B

TCA9517

SDA SDAB SDA

SCL SCLB SCL

BUS A

3.3 V

SDAA

SCLA

VCCA

VCCB

10 kW

1.2 V

SLAVE

400 kHz

BUS

MASTER

400 kHz

10 kW10 kW10 kW

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10 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

10.1 Application Information

A typical application is shown in Figure 7. In this example, the system master is running on a 3.3 V I2C bus, and

the slave is connected to a 1.2 V I2C bus. Both buses run at 400 kHz. Master devices can be placed on either

bus.

The TCA9517 is 5-V tolerant, so it does not require any additional circuitry to translate between 0.9 V to 5.5 V

bus voltages and 2.7 V to 5.5 V bus voltages.

When the A side of the TCA9517 is pulled low by a driver on the I2C bus, a comparator detects the falling edge

when it goes below 0.3 × VCCA and causes the internal driver on the B-side to turn on, causing the B-side to pull

down to about 0.5 V. When the B-side of the TCA9517 falls, first a CMOS hysteresis-type input detects the falling

edge and causes the internal driver on the A side to turn on and pull the A-side pin down to ground. In order to

illustrate what would be seen in a typical application, refer to Figure 9 and Figure 10. If the bus master in

Figure 7 were to write to the slave through the TCA9517 , waveforms shown in Figure 9 would be observed on

the A bus. This looks like a normal I2C transmission, except that the high level may be as low as 0.9 V, and the

turn on and turn off of the acknowledge signals are slightly delayed.

On the B-side bus of the TCA9517 , the clock and data lines would have a positive offset from ground equal to

the VOL of the TCA9517 . After the eighth clock pulse, the data line is pulled to the VOL of the slave device, which

is very close to ground in this example. At the end of the acknowledge, the level rises only to the low level set by

the driver in the TCA9517 for a short delay, while the A-bus side rises above 0.3 × VCCA and then continues high.

10.2 Typical Application

Figure 7. Typical Application Schematic

10.2.1 Design Requirements

For the level translating application, the following should be true:

• VCCA = 0.9 V to 5.5 V

• VCCB = 2.7 to 5.5 V

• B-side ports must not be connected together

TCA9517

SDA SDA

SCL SCLA SCL

VCCA VCCB

SDAB

SCLB

10 kW10 kW10 kW10 kW

TCA9517

SDAA SDA

SCLA SCL

SDAB

SCLB

10 kW10 kW

TCA9517

SDAA SDA

SCLA SCL

SDAB

SCLB

10 kW10 kW

BUS

MASTER

SLAVE

400 kHz

SLAVE

400 kHz

SLAVE

400 kHz

SDAA

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Typical Application (continued)

10.2.2 Detailed Design Procedure

10.2.2.1 Clock Stretching Support

The TCA9517 can support clock stretching, but care needs to be taken to minimize the overshoot voltage

presented during the hand-off between the slave and master. This is best done by increasing the pull-up resistor

value.

10.2.2.2 VILC and Pullup Resistor Sizing

For the TCA9517 to function correctly, all devices on the B-side must be able to pull the B-side below the voltage

input low contention level (VILC). This means that the VOL of any device on the B-side must be below

0.4 V.

VOL of a device can be adjusted by changing the IOL through the device which is set by the pull-up resistance

value. The pull-up resistance on the B-side must be carefully selected to ensure that logic levels will be

transferred correctly to the A-side.

Figure 8. Typical Star Application

Multiple A sides of TCA9517 s can be connected in a star configuration, allowing all nodes to communicate with

each other.

9th CLOCK PULSE — ACKNOWLEDGE

V OF SLAVE

SCL

SDA

V OF TCA9517

9th CLOCK PULSE — ACKNOWLEDGE

SCL

SDA

TCA9517

SDA SDAA

SCL SCLA

SDAB

SCLB

10 kW10 kW

VCCB

TCA9517

SDAA

SCLA

SDAB

SCLB

10 kW

TCA9517

SDAA

SCLA

SDAB

SCLB

10 kW

SDA

SCL

10 kW

SLAVE

400 kHz

BUS

MASTER

10 kW10 kW10 kW

TCA9517

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Typical Application (continued)

Figure 9. Typical Series Application

To further extend the I2C bus for long traces/cables, multiple TCA9517 s can be connected in series as long as

the A-side is connected to the B-side. I2C bus slave devices can be connected to any of the bus segments. The

number of devices that can be connected in series is limited by repeater delay/time-of-flight considerations on the

maximum bus speed requirements.

Figure 10. Bus A (0.9 V to 5.5 V Bus) Waveform

Figure 11. Bus B (2.7 V to 5.5 V Bus) Waveform

Magnitude (V)

0.5

1.5

2.5

D003

Port A

Port B

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Typical Application (continued)

10.2.3 Application Curve

Figure 12. Voltage Translation at 400 kHz, VCCA = 0.9 V, VCCB = 2.7 V

11 Power Supply Recommendations

VCCB and VCCA can be applied in any sequence at power up. The TCA9517 includes a power-up circuit that

keeps the output drivers turned off until VCCB is above 2.5 V and the VCCA is above 0.8 V. After power up and

with the EN high, a low level on the A-side (below 0.3 × VCCA) turns the corresponding B-side driver (either SDA

or SCL) on and drives the B-side down to approximately 0.5 V. When the A-side rises above 0.3 × VCCA, the B-

side pull-down driver is turned off and the external pull-up resistor pulls the pin high. When the B-side falls first

and goes below 0.3 × VCCB, the A-side driver is turned on and the A-side pulls down to 0 V. The B-side pull-down

is not enabled unless the B-side voltage goes below 0.4 V. If the B-side low voltage does not go below 0.5 V, the

A-side driver turns off when the B-side voltage is above 0.7 × VCCB. If the B-side low voltage goes below 0.4 V,

the B-side pull-down driver is enabled, and the B-side is able to rise to only 0.5 V until the A-side rises above 0.3

× VCCA.

TI recommends using a decoupling capacitor and placing it close to the VCCA and VCCB pins of a value of

about 100 nF.

To VCCB Plane

0402 Cap

To VCCA Plane

SCLB

SDAB

VCCB

SCLA

SDAA

GND

VCCA

0402 Cap

= Via to GND Plane

TCA9517

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Product Folder Links: TCA9517

12 Layout

12.1 Layout Guidelines

There are no special layout procedures required for the TCA9517 .

It is recommended that the decoupling capacitors be placed as close to the VCC pins as possible.

12.2 Layout Example

Figure 13 shows an example layout of the DGK package.

Figure 13. TCA9517A Layout Example

TCA9517

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13 Device and Documentation Support

13.1 Community Resource

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

13.2 Trademarks

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

13.3 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

13.4 Glossary

SLYZ022 —TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

14 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

PACKAGE OPTION ADDENDUM

www.ti.com 14-Jul-2017

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

TCA9517DGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS

& no Sb/Br) CU NIPDAUAG Level-1-260C-UNLIM -40 to 85 AYK

TCA9517DR ACTIVE SOIC D 8 2500 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 PW517

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish

value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

PACKAGE OPTION ADDENDUM

www.ti.com 14-Jul-2017

Addendum-Page 2

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

TCA9517DGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1

TCA9517DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 14-Jul-2017

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

TCA9517DGKR VSSOP DGK 8 2500 364.0 364.0 27.0

TCA9517DR SOIC D 8 2500 340.5 338.1 20.6

PACKAGE MATERIALS INFORMATION

www.ti.com 14-Jul-2017

Pack Materials-Page 2

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