Input
Mux
3rdOrder
DS
Modulator
REFP REFN
PGA
Burnout
Detect
Burnout
Detect
DVDD
DGND
ADS1246
AVSS
AIN0
AIN1
SCLK
DIN
DRDY
DOUT/DRDY
CS
START
RESET
AVDD
InternalOscillator
Adjustable
Digital
Filter
Serial
Interface
and
Control
CLK
Input
Mux
3rdOrder
DS
Modulator
REFP1 REFN1 VREFOUT VREFCOM
REFP0/
GPIO0
REFN0/
GPIO1
Burnout
Detect
Burnout
Detect
DVDD
DGND
IEXC1AVSS
AIN0/IEXC
AIN1/IEXC
AIN2/IEXC/GPIO2
AIN3/IEXC/GPIO3
AIN4/IEXC/GPIO4
AIN5/IEXC/GPIO5
AIN6/IEXC/GPIO6
AIN7/IEXC/GPIO7
ADS1248 Only
SCLK
DIN
DRDY
DOUT/DRDY
CS
START
RESET
AVDD
IEXC2
InternalOscillator
Voltage
Reference
Serial
Interface
and
Control
VBIAS
GPIO
CLK
ADS1248 Only
ADS1247
ADS1248
PGA
System
Monitor
Adjustable
Digital
Filter
Dual
Current
DACs
VREFMux
ADS1248 Only
VBIAS
ADS1246
ADS1247
ADS1248
www.ti.com
SBAS426G AUGUST 2008REVISED OCTOBER 2011
24-Bit Analog-to-Digital Converters for Temperature Sensors
Check for Samples: ADS1246,ADS1247,ADS1248
1FEATURES DESCRIPTION
The ADS1246, ADS1247, and ADS1248 are
2324 Bits, No Missing Codes highly-integrated, precision, 24-bit analog-to-digital
Data Output Rates Up to 2kSPS converters (ADCs). The ADS1246/7/8 feature an
Single-Cycle Settling for All Data Rates onboard, low-noise, programmable gain amplifier
(PGA), a precision delta-sigma (ΔΣ) ADC with a
Simultaneous 50/60Hz Rejection at 20SPS single-cycle settling digital filter, and an internal
4 Differential/7 Single-Ended Inputs (ADS1248) oscillator. The ADS1247 and ADS1248 also provide a
2 Differential/3 Single-Ended Inputs (ADS1247) built-in, very low drift voltage reference with 10mA
output capacity, and two matched programmable
Low-Noise PGA: 48nV at PGA = 128 current digital-to-analog converters (DACs). The
Matched Current Source DACs ADS1246/7/8 provide a complete front-end solution
Very Low Drift Internal Voltage Reference: for temperature sensor applications including thermal
10ppm/°C (max) couples, thermistors, and RTDs.
Sensor Burnout Detection An input multiplexer supports four differential inputs
4/8 General-Purpose I/Os (ADS1247/8) for the ADS1248, two for the ADS1247, and one for
the ADS1246. In addition, the multiplexer has a
Internal Temperature Sensor sensor burnout detect, voltage bias for
Power Supply and VREF Monitoring thermocouples, system monitoring, and
(ADS1247/8) general-purpose digital I/Os (ADS1247 and
Self and System Calibration ADS1248). The onboard, low-noise PGA provides
selectable gains of 1 to 128. The ΔΣ modulator and
SPI-Compatible Serial Interface adjustable digital filter settle in only one cycle, for fast
Analog Supply Unipolar (+2.7V to channel cycling when using the input multiplexer, and
+5.25V)/Bipolar (±2.5V) Operation support data rates up to 2kSPS. For data rates of
Digital Supply: +2.7V to +5.25V 20SPS or less, both 50Hz and 60Hz interference are
rejected by the filter.
Operating Temperature 40°C to +125°CThe ADS1246 is offered in a small TSSOP-16
APPLICATIONS package, the ADS1247 is available in a TSSOP-20
package, and the ADS1248 in a TSSOP-28 package.
Temperature Measurement All three devices are rated over the extended
RTDs, Thermocouples, and Thermistors specified temperature range of 40°C to +105°C.
Pressure Measurement
Industrial Process Control
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2SPI is a trademark of Motorola, Inc.
3All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright ©20082011, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
ADS1246
ADS1247
ADS1248
SBAS426G AUGUST 2008REVISED OCTOBER 2011
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION(1)
DUAL SENSOR
EXCITATION CURRENT PACKAGE-
PRODUCT NUMBER OF INPUTS VOLTAGE REFERENCE SOURCES LEAD
1 Differential
ADS1246 or External NO TSSOP-16
1 Single-Ended
2 Differential
ADS1247 or Internal or External YES TSSOP-20
3 Single-Ended
4 Differential
ADS1248 or Internal or External YES TSSOP-28
7 Single-Ended
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this data sheet, or see the TI
website at www.ti.com
ABSOLUTE MAXIMUM RATINGS(1)
Over operating free-air temperature range (unless otherwise noted). ADS1246, ADS1247, ADS1248
PARAMETER MIN MAX UNIT
AVDD to AVSS 0.3 +5.5 V
AVSS to DGND 2.8 +0.3 V
DVDD to DGND 0.3 +5.5 V
100, momentary mA
Input current 10, continuous mA
Analog input voltage to AVSS AVSS 0.3 AVDD + 0.3 V
Digital input voltage to DGND 0.3 DVDD + 0.3 V
Maximum junction temperature +150 °C
Operating temperature range 40 +125 °C
Storage temperature range 60 +150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2Copyright ©20082011, Texas Instruments Incorporated
(V )(Gain)
IN
2
AVSS 0.1V+ +
AVDD 0.1V- - (V )(Gain)
IN
2
ADS1246
ADS1247
ADS1248
www.ti.com
SBAS426G AUGUST 2008REVISED OCTOBER 2011
ELECTRICAL CHARACTERISTICS
Minimum/maximum specifications apply from 40°C to +105°C. Typical specifications are at +25°C. All specifications at
AVDD = +5V, DVDD = +3.3V, AVSS = 0V, VREF = +2.048V, and oscillator frequency = 4.096MHz, unless otherwise noted.
ADS1246, ADS1247, ADS1248
PARAMETER CONDITIONS MIN TYP MAX UNIT
ANALOG INPUTS
Full-scale input voltage ±VREF/PGA(1) V
(VIN = ADCINP ADCINN)
Common-mode input range V
Differential input current 100 pA
Absolute input current See Table 7
PGA gain settings 1, 2, 4, 8, 16, 32, 64, 128
Burnout current source 0.5, 2, or 10 μA
Bias voltage (AVDD + AVSS)/2 V
Bias voltage output impedance 400
SYSTEM PERFORMANCE
Resolution No missing codes 24 Bits
Data rate 5, 10, 20, 40, 80, 160, 320, 640, 1000, 2000 SPS
Differential input, end point fit, PGA = 1
Integral nonlinearity (INL) 6 15 ppm
VCM = 2.5V
Offset error After calibration(2) 15 15 μV
Offset drift See Figure 11 to Figure 14 nV/°C
T = +25°C, all PGAs,
Gain error 0.02 ±0.005 0.02 %
data rate = 40, 80, or 160SPS
Gain drift See Figure 19 to Figure 22 ppm/°C
ADC conversion time Single-cycle settling
Noise See Table 1 to Table 4
Normal-mode rejection See Table 9
At dc, PGA = 1 80 90 dB
Common-mode rejection At dc, PGA = 32 90 125 dB
AVDD/DVDD at dc, PGA = 32,
Power-supply rejection 100 135 dB
data rate = 80SPS
VOLTAGE REFERENCE INPUT
Voltage reference input 0.5 (AVDD AVSS) 1 V
(VREF = VREFP VREFN)
Negative reference input (REFN) AVSS 0.1 REFP 0.5 V
Positive reference input (REFP) REFN + 0.5 AVDD + 0.1 V
Reference input current 30 nA
ON-CHIP VOLTAGE REFERENCE
Output voltage 2.038 2.048 2.058 V
Output current(3) ±10 mA
Load regulation 50 μV/mA
TA= +25°C to +105°C 2 10 ppm/°C
Drift(4) TA=40°C to +105°C 6 15 ppm/°C
Startup time See Table 10 μs
(1) For VREF >2.7V, the analog input differential voltage should not exceed 2.7V/PGA.
(2) Offset calibration on the order of noise.
(3) Do not exceed this loading on the internal voltage reference.
(4) Specified by the combination of design and final production test.
Copyright ©20082011, Texas Instruments Incorporated 3
ADS1246
ADS1247
ADS1248
SBAS426G AUGUST 2008REVISED OCTOBER 2011
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
Minimum/maximum specifications apply from 40°C to +105°C. Typical specifications are at +25°C. All specifications at
AVDD = +5V, DVDD = +3.3V, AVSS = 0V, VREF = +2.048V, and oscillator frequency = 4.096MHz, unless otherwise noted.
ADS1246, ADS1247, ADS1248
PARAMETER CONDITIONS MIN TYP MAX UNIT
CURRENT SOURCES (IDACS)
Output current 50, 100, 250, 500, 750, 1000, 1500 μA
Voltage compliance All currents AVDD 0.7 V
Initial error All currents, each IDAC 6±1 6 % of FS
Initial mismatch All currents, between IDACs ±0.15 % of FS
Temperature drift Each IDAC 100 ppm/°C
Temperature drift matching Between IDACs 10 ppm/°C
SYSTEM MONITORS
Voltage TA= +25°C 118 mV
Temperature
sensor reading Drift 405 μV/°C
GENERAL-PURPOSE INPUT/OUTPUT (GPIO)
VIH 0.7AVDD AVDD V
VIL AVSS 0.3AVDD V
Logic levels VOH IOH = 1mA 0.8AVDD V
VOL IOL = 1mA 0.2 AVDD V
DIGITAL INPUT/OUTPUT (other than GPIO)
VIH 0.7DVDD DVDD V
VIL DGND 0.3DVDD V
Logic levels VOH IOH = 1mA 0.8DVDD V
VOL IOL = 1mA DGND 0.2 DVDD V
Input leakage DGND <VIN <DVDD ±10 μA
Frequency 1 4.5 MHz
Clock input
(CLK) Duty cycle 25 75 %
Internal oscillator frequency 3.89 4.096 4.3 MHz
POWER SUPPLY
DVDD 2.7 5.25 V
AVSS 2.5 0 V
AVDD AVSS + 2.7 AVSS + 5.25 V
Normal mode, DVDD = 5V, 230 μA
data rate = 20SPS, internal oscillator
DVDD current Normal mode, DVDD = 3.3V, 210 μA
data rate = 20SPS, internal oscillator
Sleep mode 0.2 µA
Converting, AVDD = 5V, 225 µA
data rate = 20SPS, external reference
Converting, AVDD = 3.3V, 200 µA
data rate = 20SPS, external reference
AVDD current Sleep mode 0.1 µA
Additional current with internal reference 180 μA
enabled
AVDD = DVDD = 5V,
data rate = 20SPS, internal oscillator, 2.3 mW
external reference
Power dissipation AVDD = DVDD = 3.3V,
data rate = 20SPS, internal oscillator, 1.4 mW
external reference
TEMPERATURE RANGE
Specified 40 +105 °C
Operating 40 +125 °C
Storage 60 +150 °C
4Copyright ©20082011, Texas Instruments Incorporated
ADS1246
ADS1247
ADS1248
www.ti.com
SBAS426G AUGUST 2008REVISED OCTOBER 2011
THERMAL INFORMATION ADS1246,
ADS1247,
ADS1248
THERMAL METRIC(1) UNITS
TSSOP (IPW)
28
θJA Junction-to-ambient thermal resistance(2) 54.6
θJC(top) Junction-to-case(top) thermal resistance (3) 11.3
θJB Junction-to-board thermal resistance (4) 13.0 °C/W
ψJT Junction-to-top characterization parameter (5) 0.5
ψJB Junction-to-board characterization parameter (6) 12.7
θJC(bottom) Junction-to-case(bottom) thermal resistance (7) n/a
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific
JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Copyright ©20082011, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Link(s): ADS1246 ADS1247 ADS1248
DVDD
DGND
CLK
RESET
REFP0/GPIO0
REFN0/GPIO1
REFP1
REFN1
VREFOUT
VREFCOM
AIN0/IEXC
AIN1/IEXC
AIN4/IEXC/GPIO4
AIN5/IEXC/GPIO5
SCLK
DIN
DOUT/DRDY
DRDY
CS
START
AVDD
AVSS
IEXC1
IEXC2
AIN3/IEXC/GPIO3
AIN2/IEXC/GPIO2
AIN7/IEXC/GPIO7
AIN6/IEXC/GPIO6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
ADS1248
ADS1246
ADS1247
ADS1248
SBAS426G AUGUST 2008REVISED OCTOBER 2011
www.ti.com
PIN CONFIGURATIONS
PW PACKAGE
TSSOP-28
(TOP VIEW)
6Submit Documentation Feedback Copyright ©20082011, Texas Instruments Incorporated
Product Folder Link(s): ADS1246 ADS1247 ADS1248
ADS1246
ADS1247
ADS1248
www.ti.com
SBAS426G AUGUST 2008REVISED OCTOBER 2011
ADS1248 (TSSOP-28) PIN DESCRIPTIONS
NAME PIN NO. FUNCTION DESCRIPTION
DVDD 1 Digital Digital power supply
DGND 2 Digital Digital ground
CLK 3 Digital input External clock input. Tie this pin to DGND to activate the internal oscillator.
RESET 4 Digital input Chip reset (active low). Returns all register values to reset values.
Analog input
REFP0/GPIO0 5 Positive external reference input 0, or general-purpose digital input/output pin 0
Digital in/out
Analog input
REFN0/GPIO1 6 Negative external reference 0 input, or general-purpose digital input/output pin 1
Digital in/out
REFP1 7 Analog input Positive external reference 1 input
REFN1 8 Analog input Negative external reference 1 input
VREFOUT 9 Analog output Positive internal reference voltage output
Negative internal reference voltage output. Connect this pin to AVSS when using a unipolar
VREFCOM 10 Analog output supply, or to the midvoltage of the power supply when using a bipolar supply.
AIN0/IEXC 11 Analog input Analog input 0, optional excitation current output
AIN1/IEXC 12 Analog input Analog input 1, optional excitation current output
Analog input
AIN4/IEXC/GPIO4 13 Analog input 4, optional excitation current output, or general-purpose digital input/output pin 4
Digital in/out
Analog input
AIN5/IEXC/GPIO5 14 Analog input 5, optional excitation current output, or general-purpose digital input/output pin 5
Digital in/out
Analog input
AIN6/IEXC/GPIO6 15 Analog input 6, optional excitation current output, or general-purpose digital input/output pin 6
Digital in/out
Analog input
AIN7/IEXC/GPIO7 16 Analog input 7, optional excitation current output, or general-purpose digital input/output pin 7
Digital in/out
Analog input
AIN2/IEXC/GPIO2 17 Analog input 2, optional excitation current output, or general-purpose digital input/output pin 2
Digital in/out
Analog input
AIN3/IEXC/GPIO3 18 Analog input 3, optional excitation current output, or general-purpose digital input/output pin 3
Digital in/out
IOUT2 19 Analog output Excitation current output 2
IOUT1 20 Analog output Excitation current output 1
AVSS 21 Analog Negative analog power supply
AVDD 22 Analog Positive analog power supply
START 23 Digital input Conversion start. See text for complete description.
CS 24 Digital input Chip select (active low)
DRDY 25 Digital output Data ready (active low)
Serial Data Out Output, or
DOUT/DRDY 26 Digital output Data Out combined with Data Ready (active low when DRDY function enabled)
DIN 27 Digital input Serial data input
SCLK 28 Digital input Serial clock input
Copyright ©20082011, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Link(s): ADS1246 ADS1247 ADS1248
DVDD
DGND
CLK
RESET
REFP0/GPIO0
REFN0/GPIO1
VREFOUT
VREFCOM
AIN0/IEXC
AIN1/IEXC
SCLK
DIN
DOUT/DRDY
DRDY
CS
START
AVDD
AVSS
AIN3/IEXC/GPIO3
AIN2/IEXC/GPIO2
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
ADS1247
ADS1246
ADS1247
ADS1248
SBAS426G AUGUST 2008REVISED OCTOBER 2011
www.ti.com
PW PACKAGE
TSSOP-20
(TOP VIEW)
ADS1247 (TSSOP-20) PIN DESCRIPTIONS
NAME PIN NO. FUNCTION DESCRIPTION
DVDD 1 Digital Digital power supply
DGND 2 Digital Digital ground
CLK 3 Digital input External clock input. Tie this pin to DGND to activate the internal oscillator.
RESET 4 Digital input Chip reset (active low). Returns all register values to reset values.
Analog input
REFP0/GPIO0 5 Positive external reference input, or general-purpose digital input/output pin 0
Digital in/out
Analog input
REFN0/GPIO1 6 Negative external reference input, or general-purpose digital input/output pin 1
Digital in/out
VREFOUT 7 Analog output Positive internal reference voltage output
Negative internal reference voltage output. Connect this pin to AVSS when using a unipolar
VREFCOM 8 Analog output supply, or to the midvoltage of the power supply when using a bipolar supply.
AIN0/IEXC 9 Analog input Analog input 0, optional excitation current output
AIN1/IEXC 10 Analog input Analog input 1, optional excitation current output
Analog input
AIN2/IEXC/GPIO2 11 Analog input 2, optional excitation current output, or general-purpose digital input/output pin 2
Digital in/out
Analog input Analog input 3, with or without excitation current output, or general-purpose digital input/output
AIN3/IEXC/GPIO3 12 Digital in/out pin 3
AVSS 13 Analog Negative analog power supply
AVDD 14 Analog Positive analog power supply
START 15 Digital input Conversion start. See text for description of use.
CS 16 Digital input Chip select (active low)
DRDY 17 Digital output Data ready (active low)
Serial data out output, or
DOUT/DRDY 18 Digital output Data out combined with Data Ready (active low when DRDY function enabled)
DIN 19 Digital input Serial data input
SCLK 20 Digital input Serial clock input
8Submit Documentation Feedback Copyright ©20082011, Texas Instruments Incorporated
Product Folder Link(s): ADS1246 ADS1247 ADS1248
DVDD
DGND
CLK
RESET
REFP
REFN
AINP
AINN
SCLK
DIN
DOUT/DRDY
DRDY
CS
START
AVDD
AVSS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
ADS1246
ADS1246
ADS1247
ADS1248
www.ti.com
SBAS426G AUGUST 2008REVISED OCTOBER 2011
PW PACKAGE
TSSOP-16
(TOP VIEW)
ADS1246 (TSSOP-16) PIN DESCRIPTIONS
NAME PIN NO. FUNCTION DESCRIPTION
DVDD 1 Digital Digital power supply
DGND 2 Digital Digital ground
CLK 3 Digital input External clock input. Tie this pin to DGND to activate the internal oscillator.
RESET 4 Digital input Chip reset (active low). Returns all register values to reset values.
REFP 5 Analog input Positive external reference input
REFN 6 Analog input Negative external reference input
AINP 7 Analog input Positive analog input
AINN 8 Analog input Negative analog input
AVSS 9 Analog Negative analog power supply
AVDD 10 Analog Positive analog power supply
START 11 Digital input Conversion start. See text for description of use.
CS 12 Digital input Chip select (active low)
DRDY 13 Digital output Data ready (active low)
Serial data out output, or
DOUT/DRDY 14 Digital output Data out combined with Data Ready (active low when DRDY function enabled)
DIN 15 Digital input Serial data input
SCLK 16 Digital input Serial clock input
Copyright ©20082011, Texas Instruments Incorporated Submit Documentation Feedback 9
Product Folder Link(s): ADS1246 ADS1247 ADS1248
SCLK
DOUT[7] DOUT[6] DOUT[5] DOUT[4] DOUT[1] DOUT[0]
DIN[0] DIN[7] DIN[6] DIN[5] DIN[4] DIN[1] DIN[0]
CS
DOUT/ (1)
DRDY
DIN
tCSSC
tDIST tDIHD
tSCLK tSCCS
tCSDO
tDOPD
tSPWL
tSPWH
tDOHD
tCSPW
SCLK(3)
1 2 3 87654
DRDY
tSTD
tDTS
tPWH
ADS1246
ADS1247
ADS1248
SBAS426G AUGUST 2008REVISED OCTOBER 2011
www.ti.com
TIMING DIAGRAMS
Figure 1. Serial Interface Timing
Timing Characteristics for Figure 1(1)
At TA= -40°C to +105°C and DVDD = 2.7V to 5.5V.
SYMBOL DESCRIPTION MIN MAX UNIT
tCSSC CS low to first SCLK high (set up time) 10 ns
tSCCS SCLK low to CS high (hold time) 7 tOSC (2)
tDIST DIN set up time 5 ns
tDIHD DIN hold time 5 ns
tDOPD SCLK rising edge to new data valid 50(3) ns
tDOHD DOUT hold time 0 ns
488 ns
tSCLK SCLK period 64 Conversions
tSPWH SCLK pulse width high 0.25 0.75 tSCLK
tSPWL SCLK pulse width low 0.25 0.75 tSCLK
tCSDO CS high to DOUT high impedance 10 ns
tCSPW Chip Select high pulse width 5 tOSC
(1) DRDY MODE bit = 0.
(2) tOSC = 1/fCLK. The default clock frequency fCLK = 4.096MHz.
(3) For DVDD >3.6V, tDOPD = 180ns.
(1) This timing diagram is applicable only when the CS pin is low. SCLK need not be low during tSTD when CS is high.
(2) SCLK should only be sent in multiples of eight during partial retrieval of output data.
Figure 2. SPI Interface Timing to Allow Conversion Result Loading
Timing Characteristics for Figure 2
At TA= -40°C to +105°C and DVDD = 2.7V to 5.5V.
SYMBOL DESCRIPTION MIN MAX UNIT
tPWH DRDY pulse width high 3 tOSC
tSTD SCLK low prior to DRDY low 5 tOSC
tDTS DRDY falling edge to SCLK rising edge 1/fCLK ns
10 Submit Documentation Feedback Copyright ©20082011, Texas Instruments Incorporated
Product Folder Link(s): ADS1246 ADS1247 ADS1248
tSTART
START
ADS1246
ADS1247
ADS1248
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SBAS426G AUGUST 2008REVISED OCTOBER 2011
Figure 3. Minimum START Pulse Width
Timing Characteristics for Figure 3
At TA= -40°C to +105°C and DVDD = 2.7V to 5.5V.
SYMBOL DESCRIPTION MIN MAX UNIT
tSTART START pulse width high 3 tOSC
Figure 4. Reset Pulse Width and SPI Communication After Reset
Timing Characteristics for Figure 4
At TA= -40°C to +105°C and DVDD = 2.7V to 5.5V.
SYMBOL DESCRIPTION MIN MAX UNIT
tRESET RESET pulse width low 4 tOSC
tRHSC RESET high to SPI communication start 0.6(1) ms
(1) Applicable only when fOSC = 4.096MHz and scales proportionately with fOSC frequency.
Copyright ©20082011, Texas Instruments Incorporated Submit Documentation Feedback 11
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ADS1246
ADS1247
ADS1248
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NOISE PERFORMANCE
The ADS1246/7/8 noise performance can be optimized by adjusting the data rate and PGA setting. As the
averaging is increased by reducing the data rate, the noise drops correspondingly. Increasing the PGA value
reduces the input-referred noise, particularly useful when measuring low-level signals. Table 1 to Table 6
summarize noise performance of the ADS1246/7/8. The data are representative of typical noise performance at
T = +25°C. The data shown are the result of averaging the readings from multiple devices and were measured
with the inputs shorted together. A minimum of 128 consecutive readings were used to calculate the RMS and
peak-to-peak noise for each reading.
Table 1,Table 3, and Table 5 list the input-referred noise in units of μVRMS and μVPP for the conditions shown.
Table 2,Table 4, and Table 6 list the corresponding data in units of ENOB (effective number of bits) where:
ENOB = ln(Full-Scale Range/Noise)/ln(2) (1)
Table 3 to Table 6 use the internal reference available on the ADS1247 and ADS1248. The data though are also
representative of the ADS1246 noise performance when using a low-noise external reference such as the
REF5020.
Table 1. Noise in μVRMS and (μVPP)
at AVDD = 5V, AVSS = 0V, and External Reference = 2.5V
DATA PGA SETTING
RATE
(SPS) 1 2 4 8 16 32 64 128
5 1.1 (4.99) 0.68 (3.8) 0.37 (1.9) 0.19 (0.98) 0.1 (0.44) 0.07 (0.31) 0.05 (0.27) 0.05 (0.21)
10 1.53 (8.82) 0.82 (3.71) 0.5 (2.69) 0.27 (1.33) 0.15 (0.67) 0.08 (0.5) 0.06 (0.36) 0.07 (0.34)
20 2.32 (13.37) 1.23 (6.69) 0.71 (3.83) 0.34 (1.9) 0.18 (1.01) 0.12 (0.71) 0.10 (0.51) 0.09 (0.54)
40 2.72 (17.35) 1.33 (7.65) 0.68 (3.83) 0.38 (2.21) 0.22 (1.13) 0.14 (0.77) 0.15 (0.78) 0.14 (0.76)
80 3.56 (22.67) 1.87 (12.3) 0.81 (5.27) 0.5 (3.49) 0.3 (1.99) 0.19 (1.24) 0.19 (1.16) 0.18 (1.04)
160 5.26 (42.03) 2.52 (17.57) 1.32 (9.22) 0.67 (5.25) 0.41 (2.89) 0.26 (1.91) 0.27 (1.74) 0.26 (1.74)
320 9.39 (74.91) 4.68 (39.48) 2.69 (18.95) 1.24 (9.94) 0.68 (5.25) 0.45 (3.08) 0.38 (2.71) 0.36 (2.46)
640 13.21 (119.66) 6.93 (59.31) 3.59 (28.55) 1.53 (10.68) 0.95 (8.7) 0.63 (4.94) 0.53 (3.74) 0.5 (3.55)
1000 32.34 (443.91) 16.11 (185.67) 11.54 (92.23) 4.65 (37.55) 2.02 (23.14) 1.15 (12.29) 0.77 (7.42) 0.64 (4.98)
2000 32.29 (372.54) 15.99 (182.27) 8.02 (91.73) 4.08 (45.89) 2.19 (24.14) 1.36 (12.32) 1.08 (8.03) 1 (6.93)
Table 2. Effective Number of Bits From RMS Noise and (Peak-to-Peak Noise)
at AVDD = 5V, AVSS = 0V, and External Reference = 2.5V
DATA PGA SETTING
RATE
(SPS) 1 2 4 8 16 32 64 128
5 21.8 (19.6) 21.5 (19) 21.4 (19) 21.4 (19) 21.3 (19.2) 20.9 (18.7) 20.2 (17.8) 19.4 (17.2)
10 21.4 (18.8) 21.3 (19.1) 21 (18.5) 20.8 (18.6) 20.7 (18.6) 20.6 (18) 19.9 (17.5) 18.9 (16.5)
20 20.8 (18.2) 20.7 (18.2) 20.5 (18) 20.5 (18) 20.4 (18) 20 (17.5) 19.3 (16.9) 18.4 (15.9)
40 20.5 (17.8) 20.6 (18) 20.5 (18) 20.4 (17.8) 20.2 (17.8) 19.8 (17.4) 18.7 (16.3) 17.8 (15.4)
80 20.1 (17.5) 20.1 (17.3) 20.3 (17.6) 20 (17.2) 19.7 (17) 19.4 (16.7) 18.4 (15.7) 17.5 (14.9)
160 19.6 (16.6) 19.6 (16.8) 19.6 (16.8) 19.5 (16.6) 19.3 (16.4) 18.9 (16) 17.9 (15.2) 16.9 (14.2)
320 18.7 (15.7) 18.7 (15.7) 18.5 (15.7) 18.7 (15.7) 18.5 (15.6) 18.1 (15.3) 17.4 (14.5) 16.5 (13.7)
640 18.2 (15.1) 18.2 (15.1) 18.1 (15.1) 18.4 (15.5) 18 (14.8) 17.6 (14.7) 16.9 (14.1) 16 (13.1)
1000 17 (13.2) 17 (13.4) 16.4 (13.4) 16.7 (13.7) 17 (13.4) 16.8 (13.3) 16.4 (13.1) 15.6 (12.6)
2000 17 (13.4) 17 (13.5) 17 (13.4) 16.9 (13.4) 16.8 (13.4) 16.5 (13.3) 15.9 (13) 15 (12.2)
12 Submit Documentation Feedback Copyright ©20082011, Texas Instruments Incorporated
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SBAS426G AUGUST 2008REVISED OCTOBER 2011
Table 3. Noise in μVRMS and (μVPP)
at AVDD = 5V, AVSS = 0V, and Internal Reference = 2.048V
DATA PGA SETTING
RATE
(SPS) 1 2 4 8 16 32 64 128
5 1.35 (7.78) 0.7 (4.17) 0.35 (2.03) 0.17 (0.95) 0.1 (0.53) 0.06 (0.32) 0.05 (0.31) 0.05 (0.29)
10 1.8 (10.82) 0.88 (5.26) 0.5 (2.75) 0.24 (1.47) 0.13 (0.8) 0.09 (0.49) 0.07 (0.39) 0.07 (0.4)
20 2.62 (14.32) 1.22 (7.05) 0.66 (3.88) 0.35 (2.05) 0.19 (1.09) 0.12 (0.66) 0.1 (0.61) 0.1 (0.55)
40 2.64 (16.29) 1.34 (7.75) 0.69 (4.06) 0.35 (2.07) 0.21 (1.15) 0.15 (0.85) 0.14 (0.81) 0.13 (0.75)
80 3.69 (23.62) 1.82 (10.81) 0.89 (5.48) 0.51 (2.68) 0.3 (1.69) 0.21 (1.32) 0.2 (1.09) 0.18 (0.98)
160 5.7 (35.74) 2.63 (16.9) 1.34 (8.82) 0.68 (4.24) 0.4 (2.65) 0.3 (1.92) 0.28 (1.88) 0.26 (1.57)
320 9.67 (67.44) 4.95 (35.3) 2.59 (17.52) 1.29 (8.86) 0.72 (4.35) 0.49 (3.03) 0.4 (2.44) 0.37 (2.34)
640 13.66 (93.06) 7.04 (45.2) 3.63 (18.73) 1.84 (12.97) 1.02 (6.51) 0.68 (4.2) 0.58 (3.69) 0.53 (3.5)
1000 31.18 (284.59) 16 (129.77) 7.58 (61.3) 3.98 (33.04) 2.08 (16.82) 1.16 (9.08) 0.83 (5.42) 0.68 (4.65)
2000 31.42 (273.39) 15.45 (130.68) 8.07 (67.13) 4.06 (36.16) 2.29 (19.22) 1.38 (9.87) 1.06 (6.93) 1 (6.48)
Table 4. Effective Number of Bits From RMS Noise and (Peak-to-Peak Noise)
at AVDD = 5V, AVSS = 0V, and Internal Reference = 2.048V
DATA PGA SETTING
RATE
(SPS) 1 2 4 8 16 32 64 128
5 21.5 (19) 21.5 (18.9) 21.5 (18.9) 21.5 (19) 21.3 (18.9) 21 (18.6) 20.2 (17.7) 19.2 (16.8)
10 21.1 (18.5) 21.1 (18.6) 21 (18.5) 21 (18.4) 20.9 (18.3) 20.5 (18) 19.8 (17.3) 18.7 (16.3)
20 20.6 (18.1) 20.7 (18.1) 20.6 (18) 20.5 (17.9) 20.4 (17.8) 20.1 (17.6) 19.2 (16.7) 18.3 (15.8)
40 20.6 (17.9) 20.5 (18) 20.5 (17.9) 20.5 (17.9) 20.2 (17.8) 19.7 (17.2) 18.8 (16.3) 17.9 (15.4)
80 20.1 (17.4) 20.1 (17.5) 20.1 (17.5) 20 (17.5) 19.7 (17.2) 19.2 (16.6) 18.3 (15.8) 17.5 (15)
160 19.5 (16.8) 19.6 (16.9) 19.5 (16.8) 19.5 (16.9) 19.3 (16.6) 18.7 (16) 17.8 (15.1) 16.9 (14.3)
320 18.7 (15.9) 18.7 (15.8) 18.6 (15.8) 18.6 (15.8) 18.4 (15.8) 18 (15.4) 17.3 (14.7) 16.4 (13.7)
640 18.2 (15.4) 18.1 (15.5) 18.1 (15.7) 18.1 (15.3) 17.9 (15.3) 17.5 (14.9) 16.8 (14.1) 15.9 (13.2)
1000 17 (13.8) 17 (13.9) 17 (14) 17 (13.9) 16.9 (13.9) 16.8 (13.8) 16.2 (13.5) 15.5 (12.7)
2000 17 (13.9) 17 (13.9) 17 (13.9) 16.9 (13.8) 16.8 (13.7) 16.5 (13.7) 15.9 (13.2) 15 (12.3)
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Table 5. Noise in μVRMS and (μVPP)
at AVDD = 3V, AVSS = 0V, and Internal Reference = 2.048V
DATA PGA SETTING
RATE
(SPS) 1 2 4 8 16 32 64 128
5 2.5 (14.24) 1.32 (6.92) 0.67 (3.48) 0.32 (1.68) 0.17 (0.9) 0.09 (0.51) 0.08 (0.42) 0.07 (0.39)
10 3.09 (16.85) 1.69 (9.32) 0.82 (4.68) 0.42 (2.41) 0.23 (1.18) 0.11 (0.63) 0.11 (0.66) 0.1 (0.55)
20 4.55 (24.74) 2.19 (12.82) 1.07 (5.94) 0.55 (3.38) 0.28 (1.66) 0.16 (1) 0.15 (0.92) 0.14 (0.87)
40 5.06 (34.59) 2.39 (14.49) 1.27 (7.75) 0.66 (4.01) 0.36 (2.18) 0.21 (1.16) 0.21 (1.27) 0.15 (0.84)
80 6.63 (43.46) 3.28 (20.22) 1.79 (10.64) 0.89 (5.48) 0.47 (2.95) 0.29 (1.63) 0.28 (1.64) 0.21 (1.24)
160 9.75 (68.28) 4.89 (32.19) 2.36 (17.74) 1.26 (9.87) 0.65 (4.77) 0.4 (2.6) 0.4 (2.7) 0.3 (2.12)
320 19.22 (140.06) 9.8 (82.24) 4.81 (32.74) 2.47 (18.59) 1.27 (9.45) 0.71 (5.83) 0.5 (3.36) 0.43 (2.86)
640 27.07 (192.96) 13.54 (100.26) 6.88 (49.07) 3.4 (25.93) 1.76 (12.49) 1.02 (7.49) 0.71 (4.81) 0.6 (4.06)
1000 40.83 (388.28) 20.39 (185.96) 10.39 (89.38) 5.09 (43.28) 2.66 (22.78) 1.45 (11.01) 0.93 (6.74) 0.74 (4.86)
2000 42.06 (322.85) 21.15 (166.75) 10.66 (92.68) 5.61 (44.08) 2.92 (23.06) 1.68 (11.71) 1.19 (8.23) 1.05 (6.97)
Table 6. Effective Number of Bits From RMS and (Peak-to-Peak Noise)
at AVDD = 3V, AVSS = 0V, and Internal Reference = 2.048V
DATA PGA SETTING
RATE
(SPS) 1 2 4 8 16 32 64 128
5 20.6 (18.1) 20.6 (18.2) 20.5 (18.2) 20.6 (18.2) 20.5 (18.1) 20.4 (17.9) 19.6 (17.2) 18.8 (16.3)
10 20.3 (17.9) 20.2 (17.7) 20.3 (17.7) 20.2 (17.7) 20.1 (17.7) 20.1 (17.6) 19.1 (16.6) 18.3 (15.8)
20 19.8 (17.3) 19.8 (17.3) 19.9 (17.4) 19.8 (17.2) 19.8 (17.2) 19.6 (17) 18.7 (16.1) 17.8 (15.2)
40 19.6 (16.9) 19.7 (17.1) 19.6 (17.0) 19.6 (17) 19.5 (16.8) 19.2 (16.8) 18.2 (15.6) 17.7 (15.2)
80 19.2 (16.5) 19.3 (16.6) 19.1 (16.6) 19.1 (16.5) 19 (16.4) 18.7 (16.3) 17.8 (15.3) 17.2 (14.7)
160 18.7 (15.9) 18.7 (16) 18.7 (15.8) 18.6 (15.7) 18.6 (15.7) 18.3 (15.6) 17.3 (14.5) 16.7 (13.9)
320 17.7 (14.8) 17.7 (14.6) 17.7 (14.9) 17.7 (14.7) 17.6 (14.7) 17.5 (14.4) 17 (14.2) 16.2 (13.4)
640 17.2 (14.4) 17.2 (14.3) 17.2 (14.3) 17.2 (14.3) 17.1 (14.3) 16.9 (14.1) 16.5 (13.7) 15.7 (12.9)
1000 16.6 (13.4) 16.6 (13.4) 16.6 (13.5) 16.6 (13.5) 16.6 (13.5) 16.4 (13.5) 16.1 (13.2) 15.4 (12.7)
2000 16.6 (13.6) 16.6 (13.6) 16.6 (13.4) 16.5 (13.5) 16.4 (13.4) 16.2 (13.4) 15.7 (12.9) 14.9 (12.2)
14 Submit Documentation Feedback Copyright ©20082011, Texas Instruments Incorporated
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Counts
-53
-49
-45
-41
-37
-33
-29
-26
-22
-18
-14
-10
-6
-3
0
4
8
12
16
19
23
27
31
35
39
43
47
1800
1600
1400
1200
1000
800
600
400
200
0
AVDD=5V
PGA=1
DataRate=20SPS
12kSamples
=13s
(LSB)
Counts
-69
-63
-58
-52
-47
-41
-36
-30
-25
-20
-14
-9
-3
1
7
12
18
23
28
34
39
45
50
56
61
67
73
1800
1600
1400
1200
1000
800
600
400
200
0
AVDD=5V
PGA=32
DataRate=20SPS
12kSamples
=19s
(LSB)
Counts
-60
-50
-45
-40
-35
-30
-25
-20
-15
-10
-5
0
5
10
15
20
25
30
35
40
45
100
1600
1400
1200
1000
800
600
400
200
0
AVDD=3.3V
PGA=1
DataRate=20SPS
12kSamples
=18.5s
(LSB)
60
70
80
90
50
110
Counts
-80
-60
-45
-35
-25
-15
-5
5
15
25
35
1400
1200
1000
800
600
400
200
0
AVDD=3.3V
PGA=32
DataRate=20SPS
12kSamples
=22s
(LSB)
60
80
45
100
0.30
0.25
0.20
0.15
0.10
0.05
0
RMS Noise ( V)m
V (% of FSR)
IN
-100 -80 -60 -40 -20 10020 40 60 80
AVDD = 5V
PGA = 32
Data Rate = 5SPS
0
0.30
0.25
0.20
0.15
0.10
0.05
0
RMS Noise ( V)m
V (% of FSR)
IN
-100 -80 -60 -40 -20 10020 40 60 80
AVDD = 3.3V
PGA = 32
Data Rate = 5SPS
0
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SBAS426G AUGUST 2008REVISED OCTOBER 2011
TYPICAL CHARACTERISTICS
At TA= +25°C, AVDD = 5V, VREF = 2.5V, and AVSS = 0V, unless otherwise noted.
NOISE HISTOGRAM PLOT NOISE HISTOGRAM PLOT
Figure 5. Figure 6.
NOISE HISTOGRAM PLOT NOISE HISTOGRAM PLOT
Figure 7. Figure 8.
RMS NOISE vs INPUT SIGNAL RMS NOISE vs INPUT SIGNAL
Figure 9. Figure 10.
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4
3
2
1
0
-1
-2
-3
Temperature( C)°
Input-ReferredOffset( V)m
-40 -20 0 20 40 60 80 100 120
PGA=32
PGA=1
PGA=128
AVDD=5V
DataRate=20SPS
8
6
4
2
0
-2
-4
-6
-8
Temperature( C)°
Input-ReferredOffset( V)m
-40 -20 0 20 40 60 80 100 120
PGA=32
PGA=1
PGA=128
AVDD=5V
DataRate=160SPS
8
6
4
2
0
-2
-4
-6
-8
-10
-12
-14
Temperature( C)°
Input-ReferredOffset( V)m
-40 -20 0 20 40 60 80 100 120
PGA=32
PGA=1
PGA=128
AVDD=5V
DataRate=640SPS
15
10
5
0
-5
-10
-15
Temperature(°C)
Input-ReferredOffset(mV)
-40 -20 0 20 40 60 80 100 120
PGA=32
AVDD=5V
DataRate=2kSPS
PGA=1
PGA=128
4
3
2
1
0
1
2
3
-
-
-
Temperature( C)°
Input-ReferredOffset( V)m
-40 -20 0 20 40 60 80 100 120
AVDD=3.3V
DataRate=20SPS
PGA=1
PGA=32
PGA=128
5
4
3
2
1
0
1
2
3
4
5
6
-
-
-
-
-
-
Temperature( C)°
Input-ReferredOffset( V)m
-40 -20 0 20 40 60 80 100 120
AVDD=3.3V
DataRate=160SPS
PGA=1
PGA=32
PGA=128
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TYPICAL CHARACTERISTICS (continued)
At TA= +25°C, AVDD = 5V, VREF = 2.5V, and AVSS = 0V, unless otherwise noted.
OFFSET vs TEMPERATURE OFFSET vs TEMPERATURE
Figure 11. Figure 12.
OFFSET vs TEMPERATURE OFFSET vs TEMPERATURE
Figure 13. Figure 14.
OFFSET vs TEMPERATURE OFFSET vs TEMPERATURE
Figure 15. Figure 16.
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10
8
6
4
2
0
2
4
6
8
-
-
-
-
Temperature( C)°
Input-ReferredOffset( V)m
-40 -20 0 20 40 60 80 100 120
AVDD=3.3V
DataRate=640SPS
PGA=1
PGA=32
PGA=128
8
6
4
2
0
2
4
6
-
-
-
Temperature( C)°
Input-ReferredOffset( V)m
-40 -20 0 20 40 60 80 100 120
AVDD=3.3V
DataRate=2kSPS
PGA=1
PGA=32
PGA=128
0.05
0.04
0.03
0.02
0.01
0
-0.01
-0.02
-0.03
-0.04
-0.05
Temperature( C)°
GainError(%)
-40 -20 0 20 40 60 80 100 120
PGA=32
PGA=1
PGA=128
AVDD=5V
DataRate=20SPS
0.03
0.02
0.01
0
-0.01
-0.02
-0.03
-0.04
Temperature( C)°
GainError(%)
-40 -20 0 20 40 60 80 100 120
PGA=32
PGA=1
PGA=128
AVDD=5V
DataRate=160SPS
0.02
0.01
0
-0.01
-0.02
-0.03
-0.04
Temperature( C)°
GainError(%)
-40 -20 0 20 40 60 80 100 120
PGA=32
PGA=1
PGA=128
AVDD=5V
DataRate=2kSPS
0.03
0.02
0.01
0
-0.01
-0.02
-0.03
-0.04
Temperature( C)°
GainError(%)
-40 -20 0 20 40 60 80 100 120
PGA=32
PGA=1
PGA=128
DataRate=640SPS
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SBAS426G AUGUST 2008REVISED OCTOBER 2011
TYPICAL CHARACTERISTICS (continued)
At TA= +25°C, AVDD = 5V, VREF = 2.5V, and AVSS = 0V, unless otherwise noted.
OFFSET vs TEMPERATURE OFFSET vs TEMPERATURE
Figure 17. Figure 18.
GAIN vs TEMPERATURE GAIN vs TEMPERATURE
Figure 19. Figure 20.
GAIN vs TEMPERATURE GAIN vs TEMPERATURE
Figure 21. Figure 22.
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0.04
0.03
0.02
0.01
0
0.01
0.02
0.03
0.04
-
-
-
-
Temperature( C)°
GainError(%)
-40 -20 0 20 40 60 80 100 120
AVDD=3.3V
DataRate=20SPS
PGA=1
PGA=32
PGA=128
0.04
0.03
0.02
0.01
0
0.01
0.02
0.03
0.04
-
-
-
-
Temperature( C)°
GainError(%)
-40 -20 0 20 40 60 80 100 120
AVDD=3.3V
DataRate=160SPS
PGA=1
PGA=32
PGA=128
0.05
0.04
0.03
0.02
0.01
0
0.01
0.02
0.03
0.04
0.05
-
-
-
-
-
Temperature( C)°
GainError(%)
-40 -20 0 20 40 60 80 100 120
AVDD=3.3V
DataRate=640SPS
PGA=1
PGA=32
PGA=128
0.05
0.04
0.03
0.02
0.01
0
0.01
0.02
0.03
0.04
0.05
-
-
-
-
-
Temperature( C)°
GainError(%)
-40 -20 0 20 40 60 80 100 120
AVDD=3.3V
DataRate=2kSPS
PGA=1
PGA=32
PGA=128
600
550
500
450
400
350
300
250
200
150
100
DataRate(SPS)
AnalogCurrent( A)m
5 10 20 40 80 160 320 640 1000 2000
AVDD=5V
AVDD=3.3V
290
270
250
230
210
190
170
DataRate(SPS)
DigitalCurrent( A)m
5 10 20 40 80 160 320 640 1000 2000
DVDD=3.3V
DVDD=5V
ADS1246
ADS1247
ADS1248
SBAS426G AUGUST 2008REVISED OCTOBER 2011
www.ti.com
TYPICAL CHARACTERISTICS (continued)
At TA= +25°C, AVDD = 5V, VREF = 2.5V, and AVSS = 0V, unless otherwise noted.
GAIN vs TEMPERATURE GAIN vs TEMPERATURE
Figure 23. Figure 24.
GAIN vs TEMPERATURE GAIN vs TEMPERATURE
Figure 25. Figure 26.
ANALOG CURRENT vs DATA RATE DIGITAL CURRENT vs DATA RATE
Figure 27. Figure 28.
18 Submit Documentation Feedback Copyright ©20082011, Texas Instruments Incorporated
Product Folder Link(s): ADS1246 ADS1247 ADS1248
330
310
290
270
250
230
210
190
Temperature( C)°
DigitalCurrent( A)m
-40 -20 0 20 40 60 80 100 120
5/10/20SPS
40/80/160SPS
320/640/1kSPS
2kSPS
DVDD=5V
800
700
600
500
400
300
200
100
0
Temperature( C)°
AnalogCurrent( A)m
-40 -20 0 20 40 60 80 100 120
5/10/20SPS
40/80/160SPS
320/640/1kSPS
2kSPS
AVDD=5V
700
600
500
400
300
200
100
0
Temperature( C)°
AnalogCurrent( A)m
-40 -20 0 20 40 60 80 100 120
5/10/20SPS
40/80/160SPS
320/640/1kSPS
2kSPS
AVDD=3.3V
310
290
270
250
230
210
190
Temperature( C)°
DigitalCurrent( A)m
-40 -20 0 20 40 60 80 100 120
5/10/20SPS
40/80/160SPS
320/640/1kSPS
2kSPS
DVDD=3.3V
8
6
4
2
0
-2
-4
-6
-8
V (%ofFSR)
IN
INL(ppmofFSR)
-100 -50 0 50 100
PGA=1
DataRate=20SPS
- °40 C
- °10 C
+25 C°
+105 C°
8
6
4
2
0
-2
-4
-6
-8
-10
V (%ofFSR)
IN
INL(ppmofFSR)
-100 -50 0 50 100
PGA=32
DataRate=20SPS
- °40 C
+25 C°
+105 C°
- °10 C
ADS1246
ADS1247
ADS1248
www.ti.com
SBAS426G AUGUST 2008REVISED OCTOBER 2011
TYPICAL CHARACTERISTICS (continued)
At TA= +25°C, AVDD = 5V, VREF = 2.5V, and AVSS = 0V, unless otherwise noted.
ANALOG CURRENT vs TEMPERATURE DIGITAL CURRENT vs TEMPERATURE
Figure 29. Figure 30.
ANALOG CURRENT vs TEMPERATURE DIGITAL CURRENT vs TEMPERATURE
Figure 31. Figure 32.
INTEGRAL NONLINEARITY vs INPUT SIGNAL INTEGRAL NONLINEARITY vs INPUT SIGNAL
Figure 33. Figure 34.
Copyright ©20082011, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Link(s): ADS1246 ADS1247 ADS1248
8
6
4
2
0
-2
-4
-6
-8
V (%ofFSR)
IN
INL(ppmofFSR)
-100 -50 0 50 100
PGA=128
DataRate=20SPS
-40°C
+25 C°
+105 C°
-10°C
8
6
4
2
0
-2
-4
-6
-8
V (%ofFSR)
IN
INL(ppmofFSR)
-100 -50 0 50 100
PGA=1
DataRate=2kSPS
- °40 C
+25 C°
+105 C°
- °10 C
3.0
2.5
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
2.5
3.0
-
-
-
-
-
-
Temperature( C)°
DataRateError(%)
-40 -20 0 20 40 60 80 100 120
DVDD=5V
DVDD=3.3V
130
125
120
115
110
105
100
95
90
85
80
Temperature( C)°
CMRR(dB)
-40 -20 0 20 40 60 80 100 120
PGA=1
PGA=32
PGA=128
2.050
2.049
2.048
2.047
2.046
Temperature( C)°
OutputVoltage(V)
-40 -20 0 20 40 60 80 100 120
14Units
1.002
1.001
1.000
0.999
0.998
0.997
0.996
0.995
0.994
0.993
0.992
0.991
AVDD(V)
NormalizedOutputCurrent
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
750 Am
250 Am
1.5mA
500 Am
100 Am
1mA
50 Am
IDACCurrentSettings
ADS1246
ADS1247
ADS1248
SBAS426G AUGUST 2008REVISED OCTOBER 2011
www.ti.com
TYPICAL CHARACTERISTICS (continued)
At TA= +25°C, AVDD = 5V, VREF = 2.5V, and AVSS = 0V, unless otherwise noted.
INTEGRAL NONLINEARITY vs INPUT SIGNAL INTEGRAL NONLINEARITY vs INPUT SIGNAL
Figure 35. Figure 36.
DATA RATE ERROR vs TEMPERATURE
(Using Internal Oscillator) CMRR vs TEMPERATURE
Figure 37. Figure 38.
INTERNAL VREF vs TEMPERATURE IDAC LINE REGULATION
Figure 39. Figure 40.
20 Submit Documentation Feedback Copyright ©20082011, Texas Instruments Incorporated
Product Folder Link(s): ADS1246 ADS1247 ADS1248
8
7
6
5
4
3
2
1
0
Power-SupplyRejection( V/V)m
Gain
1 2 4 8 16 12832 64
5/10/20SPS
2000SPS
320/640/1000SPS
40/80/160SPS
0.004
0.003
0.002
0.001
0
-0.001
-0.002
-0.003
-0.004
Temperature( C)°
IEXC1 IEXC2(m-A)
-40 -20 0 20 40 60 80 100 120
1.5mASetting,10Units
Counts
2.0475
2.0476
2.0477
2.0478
2.0479
2.0480
2.0481
2.0482
2.0483
2.0484
2.0485
700
600
500
400
300
200
100
0
2280Units
InitialAccuracy(V)
Counts
-1.25
-1.00
-0.75
-0.50
-0.25
0
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
2.50
200
180
160
140
120
100
80
60
40
20
0
2280Units
InitialAccuracy(%)
−120
−100
−80
−60
−40
−20
0
0 200 400 600 800 1000
Time (hours)
Reference Drift (ppm)
32 Units
G000
Counts
-0.6
-0.5
-0.4
-0.3
-0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
350
300
250
200
150
100
50
0
2280Units
InitialAccuracy(%)
-0.2
ADS1246
ADS1247
ADS1248
www.ti.com
SBAS426G AUGUST 2008REVISED OCTOBER 2011
TYPICAL CHARACTERISTICS (continued)
At TA= +25°C, AVDD = 5V, VREF = 2.5V, and AVSS = 0V, unless otherwise noted.
IDAC DRIFT POWER-SUPPLY REJECTION vs GAIN
Figure 41. Figure 42.
INTERNAL VREF INITIAL ACCURACY HISTOGRAM IDAC INITIAL ACCURACY HISTOGRAM
Figure 43. Figure 44.
IDAC MISMATCH HISTOGRAM INTERNAL REFERENCE LONG TERM DRIFT
Figure 45. Figure 46.
Copyright ©20082011, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Link(s): ADS1246 ADS1247 ADS1248
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
1.1
0 1 2 3 4 5
Voltage (V)
Normalized IDAC Current
50µA
100µA
250µA
500µA
750µA
1mA
1.5mA
0.98
0.985
0.99
0.995
1
1.005
1.01
0 1 2 3 4 5
Voltage (V)
Normalized IDAC Current
ADS1246
ADS1247
ADS1248
SBAS426G AUGUST 2008REVISED OCTOBER 2011
www.ti.com
TYPICAL CHARACTERISTICS (continued)
At TA= +25°C, AVDD = 5V, VREF = 2.5V, and AVSS = 0V, unless otherwise noted.
IDAC VOLTAGE COMPLIANCE IDAC VOLTAGE COMPLIANCE
Figure 47. Figure 48.
22 Submit Documentation Feedback Copyright ©20082011, Texas Instruments Incorporated
Product Folder Link(s): ADS1246 ADS1247 ADS1248
Input
Mux
3rdOrder
DS
Modulator
REFP REFN
PGA
Burnout
Detect
Burnout
Detect
DVDD
DGND
ADS1246
AVSS
AIN0
AIN1
SCLK
DIN
DRDY
DOUT/DRDY
CS
START
RESET
AVDD
InternalOscillator
Adjustable
Digital
Filter
Serial
Interface
and
Control
CLK
VBIAS
Input
Mux
3rdOrder
DS
Modulator
REFP1 REFN1 VREFOUT VREFCOM
REFP0/
GPIO0
REFN0/
GPIO1
Burnout
Detect
Burnout
Detect
DVDD
DGND
IEXC1AVSS
AIN0/IEXC
AIN1/IEXC
AIN2/IEXC/GPIO2
AIN3/IEXC/GPIO3
AIN4/IEXC/GPIO4
AIN5/IEXC/GPIO5
AIN6/IEXC/GPIO6
AIN7/IEXC/GPIO7
ADS1248 Only
SCLK
DIN
DRDY
DOUT/DRDY
CS
START
RESET
AVDD
IEXC2
InternalOscillator
Voltage
Reference
Serial
Interface
and
Control
VBIAS
GPIO
CLK
ADS1248 Only
ADS1247
ADS1248
PGA
System
Monitor
Adjustable
Digital
Filter
Dual
Current
DACs
VREFMux
ADS1248 Only
ADS1246
ADS1247
ADS1248
www.ti.com
SBAS426G AUGUST 2008REVISED OCTOBER 2011
GENERAL DESCRIPTION
OVERVIEW The ADS1247 and ADS1248 also include a flexible
input multiplexer with system monitoring capability
The ADS1246, ADS1247 and ADS1248 are highly and general-purpose I/O settings, a very low-drift
integrated 24-bit data converters. They include a voltage reference, and two matched current sources
low-noise, high-impedance programmable gain for sensor excitation. Figure 49 and Figure 50 show
amplifier (PGA), a delta-sigma (ΔΣ) ADC with an the various functions incorporated in each device.
adjustable single-cycle settling digital filter, internal
oscillator, and a simple but flexible SPI-compatible
serial interface.
Figure 49. ADS1246 Diagram
Figure 50. ADS1247, ADS1248 Diagram
Copyright ©20082011, Texas Instruments Incorporated Submit Documentation Feedback 23
Product Folder Link(s): ADS1246 ADS1247 ADS1248
System Monitors
Temperature
Diode
VREFP
VREFN
VREFP1/4
VREFN1/4
VREFP0/4
VREFN0/4
AVDD/4
AVSS/4
DVDD/4
DGND/4
ADS1248 Only
ADS1247/48 Only
VBIAS
AIN0
AIN1
VBIAS
AIN2
VBIAS
AIN3
VBIAS
AIN4
VBIAS
AIN5
VBIAS
AIN6
VBIAS
AIN7
AVDD
IDAC1
IDAC2
AVDD
VBIAS
PGA
AINP
AVSS
AVDD
Burnout Current Source
(0.5 A, 2 A, 10m m mA)
Burnout Current Source
(0.5 A, 2 A, 10m m mA)
AINN
To
ADC
AVSS
AVSS
AVSS
AVSS
AVSS
AVSS
AVSS
AVSS
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD AVDD
ADS1246
ADS1247
ADS1248
SBAS426G AUGUST 2008REVISED OCTOBER 2011
www.ti.com
ADC INPUT AND MULTIPLEXER Any analog input pin can be selected as the positive
input or negative input through the MUX0 register.
The ADS1246/7/8 ADC measures the input signal The ADS1246/7/8 have a true fully differential mode,
through the onboard PGA. All analog inputs are meaning that the input signal range can be
connected to the internal AINPor AINNanalog inputs from 2.5V to +2.5V (when AVDD = 2.5V and
through the analog multiplexer. A block diagram of AVSS = 2.5V).
the analog input multiplexer is shown in Figure 51.Through the input multiplexer, the ambient
The input multiplexer connects to eight (ADS1248), temperature (internal temperature sensor), AVDD,
four (ADS1247), or two (ADS1246) analog inputs that DVDD, and external reference can all be selected for
can be configured as single-ended inputs, differential measurement. Refer to the System Monitor section
inputs, or in a combination of single-ended and for details.
differential inputs. The multiplexer also allows the
on-chip excitation current and/or bias voltage to be On the ADS1247 and ADS1248, the analog inputs
selected to a specific channel. can also be configured as general-purpose
inputs/outputs (GPIOs). See the General-Purpose
Digital I/O section for more details.
Figure 51. Analog Input Multiplexer Circuit
24 Submit Documentation Feedback Copyright ©20082011, Texas Instruments Incorporated
Product Folder Link(s): ADS1246 ADS1247 ADS1248
REFN1REFP1
ADC
ADS1248 Only
REFN0REFP0
REFNREFP
VREFCOMVREFOUT
ReferenceMultiplexer
Internal
Voltage
Reference
ADS1246
ADS1247
ADS1248
www.ti.com
SBAS426G AUGUST 2008REVISED OCTOBER 2011
ESD diodes protect the ADC inputs. To prevent these VOLTAGE REFERENCE INPUT
diodes from turning on, make sure the voltages on The voltage reference for the ADS1246/7/8 is the
the input pins do not go below AVSS by more than differential voltage between REFP and REFN:
100mV, and do not exceed AVDD by more than VREF = VREFP VREFN
100mV, as shown in Equation 2. Note that the same
caution is true if the inputs are configured to be In the case of the ADS1246, these pins are dedicated
GPIOs. inputs. For the ADS1247 and ADS1248, there is a
AVSS 100mV <(AINX) <AVDD + 100mV (2) multiplexer that selects the reference inputs, as
shown in Figure 52. The reference input uses a buffer
Settling Time for Channel Multiplexing to increase the input impedance.
The ADS1246/7/8 is a true single-cycle settling ΔΣ As with the analog inputs, REFP0 and REFN0 can be
converter. The first data available after the start of a configured as digital I/Os on the ADS1247/8.
conversion are fully settled and valid for use. The
time required to settle is roughly equal to the inverse
of the data rate. The exact time depends on the
specific data rate and the operation that resulted in
the start of a conversion; see Table 16 for specific
values.
ANALOG INPUT IMPEDANCE
The ADS1246/7/8 inputs are buffered through a
high-impedance PGA before they reach the ΔΣ
modulator. For the majority of applications, the input
current leakage is minimal and can be neglected.
However, because the PGA is chopper-stabilized for
noise and offset performance, the input impedance is
best described as small absolute input current. The
absolute current leakage for selected channels is Figure 52. Reference Input Multiplexer
approximately proportional to the selected modulator
clock. Table 7 shows the typical values for these The reference input circuit has ESD diodes to protect
currents with a differential voltage coefficient and the the inputs. To prevent the diodes from turning on,
corresponding input impedances over data rate. make sure the voltage on the reference input pin is
not less than AVSS 100mV, and does not exceed
AVDD + 100mV, as shown in Equation 3:
AVSS 100mV <(VREFP or VREFN)<AVDD + 100mV (3)
Table 7. Typical Values for Analog Input Current Over Data Rate(1)
CONDITION ABSOLUTE INPUT CURRENT EFFECTIVE INPUT IMPEDANCE
DR = 5SPS, 10SPS, 20SPS ±(0.5nA + 0.1nA/V) 5000MΩ
DR = 40SPS, 80SPS, 160SPS ±(2nA + 0.5nA/V) 1200MΩ
DR = 320SPS, 640SPS, 1kSPS ±(4nA + 1nA/V) 600MΩ
DR = 2kSPS ±(8nA + 2nA/V) 300MΩ
(1) Input current with VCM = 2.5V. TA= +25°C, AVDD = 5V, and AVSS = 0V.
Copyright ©20082011, Texas Instruments Incorporated Submit Documentation Feedback 25
Product Folder Link(s): ADS1246 ADS1247 ADS1248
()
(V )(Gain)
IN
2
AVSS+0.1V + £VCMI £
()
(V )(Gain)
IN
2
AVDD 0.1V- -
ADC
A1
454W
454W
7.5pF
A2
7.5pF
7.5pF
7.5pF
R
RC
AINP
AINN
ADS1246
ADS1247
ADS1248
SBAS426G AUGUST 2008REVISED OCTOBER 2011
www.ti.com
LOW-NOISE PGA MODULATOR
The ADS1246/7/8 feature a low-drift, low-noise, high A third-order modulator is used in the ADS1246/7/8.
input impedance programmable gain amplifier (PGA). The modulator converts the analog input voltage into
The PGA can be set to gain of 1, 2, 4, 8, 16, 32, 64, a pulse code modulated (PCM) data stream. To save
or 128 by register SYS0. A simplified diagram of the power, the modulator clock runs from 32kHz up to
PGA is shown in Figure 53. 512kHz for different data rates, as shown in Table 8.
The PGA consists of two chopper-stabilized Table 8. Modulator Clock Frequency for Different
amplifiers (A1 and A2) and a resistor feedback Data Rates
network that sets the gain of the PGA. The PGA input DATA RATE fMOD
is equipped with an electromagnetic interference (SPS) (kHz)
(EMI) filter, as shown in Figure 53. Note that as with 5, 10, 20 32
any PGA, it is necessary to ensure that the input
voltage stays within the specified common-mode 40, 80, 160 128
input range specified in the Electrical Characteristics.320, 640, 1000 256
The common-mode input (VCMI) must be within the 2000 512
range shown in Equation 4:
DIGITAL FILTER
(4) The ADS1246/7/8 use linear-phase finite impulse
response (FIR) digital filters that can be adjusted for
different output data rates. The digital filter always
settles in a single cycle.
Table 9 shows the exact data rates when an external
oscillator equal to 4.096MHz is used. Also shown is
the signal 3dB bandwidth, and the 50Hz and 60Hz
attenuation. For good 50Hz or 60Hz rejection, use a
data rate of 20SPS or slower.
The frequency responses of the digital filter are
shown in Figure 54 to Figure 64.Figure 57 shows a
detailed view of the filter frequency response from
48Hz to 62Hz for a 20SPS data rate. All filter plots
are generated with 4.096MHz external clock.
Figure 53. Simplified Diagram of the PGA
Table 9. Digital Filter Specifications(1)
ATTENUATION
NOMINAL ACTUAL 3dB
DATA RATE DATA RATE BANDWIDTH fIN = 50Hz ±0.3Hz fIN = 60Hz ±0.3Hz fIN = 50Hz ±1Hz fIN = 60Hz ±1Hz
5SPS 5.018SPS 2.26Hz 106dB 74dB 81dB 69dB
10SPS 10.037SPS 4.76Hz 106dB 74dB 80dB 69dB
20SPS 20.075SPS 14.8Hz 71dB 74dB 66dB 68dB
40SPS 40.15SPS 9.03Hz
80SPS 80.301SPS 19.8Hz
160SPS 160.6SPS 118Hz
320SPS 321.608SPS 154Hz
640SPS 643.21SPS 495Hz
1000SPS 1000SPS 732Hz
2000SPS 2000SPS 1465Hz
(1) Values shown for fOSC = 4.096MHz.
26 Submit Documentation Feedback Copyright ©20082011, Texas Instruments Incorporated
Product Folder Link(s): ADS1246 ADS1247 ADS1248
20
0
-20
-40
-60
-80
-100
-120
0 40 60
Frequency(Hz)
Magnitude(dB)
80 100 120 140 160 180 200
50 52 54 56 58 60
-60
-70
-80
-90
-100
-110
-120
48
Frequency(Hz)
Magnitude(dB)
62
20
0
-20
-40
-60
-80
-100
-120
0 40 60
Frequency(Hz)
Magnitude(dB)
80 100 120 140 160 180 200
200
0
-20
-40
-60
-80
-100
-120
0 400 600
Frequency(Hz)
Magnitude(dB)
800 1000 1200 1400 1600 1800 2000
20
0
-20
-40
-60
-80
-100
-120
0 40 60
Frequency(Hz)
Magnitude(dB)
80 100 120 140 160 180 200
200
0
-20
-40
-60
-80
-100
-120
0 400 600
Frequency(Hz)
Gain(dB)
800 1000 1200 1400 1600 1800 2000
ADS1246
ADS1247
ADS1248
www.ti.com
SBAS426G AUGUST 2008REVISED OCTOBER 2011
Figure 54. Filter Profile with Data Rate = 5SPS Figure 57. Detailed View of Filter Profile with Data
Rate = 20SPS between 48Hz and 62Hz
Figure 55. Filter Profile with Data Rate = 10SPS Figure 58. Filter Profile with Data Rate = 40SPS
Figure 56. Filter Profile with Data Rate = 20SPS Figure 59. Filter Profile with Data Rate = 80SPS
Copyright ©20082011, Texas Instruments Incorporated Submit Documentation Feedback 27
Product Folder Link(s): ADS1246 ADS1247 ADS1248
200
0
-20
-40
-60
-80
-100
-120
0 400 600
Frequency(Hz)
Magnitude(dB)
800 1000 1200 1400 1600 1800 2000
1
0
-20
-40
-60
-80
-100
-120
0 2 3
Frequency(kHz)
Magnitude(dB)
45678910
500
0
-20
-40
-60
-80
-100
-120
0 1000 1500
Frequency(Hz)
Magnitude(dB)
2000 2500 3000 3500 4000 4500 5000
2
0
-20
-40
-60
-80
-100
-120
0 4 6
Frequency(kHz)
Magnitude(dB)
8 10 12 14 16 18 20
500
0
-20
-40
-60
-80
-100
-120
0 1000 1500
Frequency(Hz)
Magnitude(dB)
2000 2500 3000 3500 4000 4500 5000
ADS1246
ADS1247
ADS1248
SBAS426G AUGUST 2008REVISED OCTOBER 2011
www.ti.com
Figure 60. Filter Profile with Data Rate = 160SPS Figure 63. Filter Profile with Data Rate = 1kSPS
Figure 61. Filter Profile with Data Rate = 320SPS Figure 64. Filter Profile with Data Rate = 2kSPS
CLOCK SOURCE
The ADS1246/7/8 can use either the internal
oscillator or an external clock. Connect the CLK pin to
DGND before power-on or reset to activate the
internal oscillator. Connecting an external clock to the
CLK pin at any time deactivates the internal oscillator,
with the device then operating on the external clock.
After the device switches to the external clock, it
cannot be switched back to the internal oscillator
without cycling the power supplies or resetting the
device.
Figure 62. Filter Profile with Data Rate = 640SPS
28 Submit Documentation Feedback Copyright ©20082011, Texas Instruments Incorporated
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INTERNAL VOLTAGE REFERENCE The two matched current sources can be connected
to dedicated current output pins IOUT1 and IOUT2
The ADS1247/8 includes an onboard voltage (ADS1248 only), or to any AIN pin (ADS1247/8); refer
reference with a low temperature coefficient. The to the ADS1247/48 Detailed Register Definitions
output of the voltage reference is 2.048V with the section for more information. It is possible to connect
capability of both sourcing and sinking up to 10mA of both current sources to the same pin. Note that the
current. internal reference must be turned on and properly
compensated when using the excitation current
The voltage reference must have a capacitor source DACs.
connected between VREFOUT and VREFCOM. The
value of the capacitance should be in the range of
1μF to 47μF. Large values provide more filtering of SENSOR DETECTION
the reference; however, the turn-on time increases The ADS1246/7/8 provide a selectable current
with capacitance, as shown in Table 10. For stability (0.5μA, 2μA, or 10μA) to help detect a possible
reasons, VREFCOM must have a path with an sensor malfunction.
impedance less than 10to ac ground nodes, such
as GND (for a 0V to 5V analog power supply), or When enabled, two burnout current sources flow
AVSS (for a ±2.5V analog power supply). In case this through the selected pair of analog inputs to the
impedance is higher than 10, a capacitor of at least sensor. One sources the current to the positive input
0.1μF should be connected between VREFCOM and channel, and the other sinks the same current from
an ac ground node (for example, GND). Note that the negative input channel.
because it takes time for the voltage reference to When the burnout current sources are enabled, a
settle to the final voltage, care must be taken when full-scale reading may indicate an open circuit in the
the device is turned off between conversions. Allow front-end sensor, or that the sensor is overloaded. It
adequate time for the internal reference to fully settle. may also indicate that the reference voltage is
absent. A near-zero reading may indicate a
Table 10. Internal Reference Settling Time short-circuit in the sensor.
VREFOUT SETTLING TIME TO REACH THE
CAPACITOR ERROR SETTLING ERROR BIAS VOLTAGE GENERATION
±0.5% 70μs
1μFA selectable bias voltage is provided for use with
±0.1% 110μsungrounded thermocouples. The bias voltage is
±0.5% 290μs(AVDD + AVSS)/2 and can applied to any analog
4.7μF±0.1% 375μsinput channel through internal input multiplexer. The
±0.5% 2.2ms bias voltage turn-on times for different sensor
47μFcapacitances are listed in Table 11.
±0.1% 2.4ms The internal bias generator, when selected on
The onboard reference is controlled by the registers; multiple channels, causes them to be internally
by default, it is off after startup (see the ADS1247/48 shorted. Because of this, it is important that care be
Detailed Register Definitions section for more details). taken to limit the amount of current that may flow
Therefore, the internal reference must first be turned through the device. It is recommended that under no
on and then connected via the internal reference circumstances more than 5mA be allowed to flow
multiplexer. Because the onboard reference is used through this path. This applies when the device is in
to generate the current reference for the excitation operation and when it is in shutdown mode.
current sources, it must be turned on before the
excitation currents become available. Table 11. Bias Voltage Settling Time
SENSOR CAPACITANCE SETTLING TIME
EXCITATION CURRENT SOURCE DACS 0.1μF 220μs
The ADS1247/8 provide two matched excitation 1μF 2.2ms
current sources for RTD applications. For three- or 10μF 22ms
four-wire RTD applications, the matched current
sources can be used to cancel the errors caused by 200μF 450ms
sensor lead resistance. The output current of the
current source DACs can be programmed to 50μA,
100μA, 250μA, 500μA, 750μA, 1000μA, or 1500μA.
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IOCFG
AINx/GPIOx
ToAnalogMux
DIOWRITE
IODIR
DIOREAD
REFx0/GPIOx
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Power-Supply Monitor
GENERAL-PURPOSE DIGITAL I/O The system monitor can measure the analog or
The ADS1248 has eight pins and the ADS1247 has digital power supply. When measuring the power
four pins that serve a dual purpose as either analog supply, the resulting conversion is approximately 1/4
inputs or general-purpose digital inputs/outputs of the actual power supply voltage.
(GPIOs). Conversion Result = (VSP/4)/VREF (5)
Figure 65 shows a diagram of how these functions
are combined onto a single pin. Note that when the Where VSP is the selected supply to be measured.
pin is configured as a GPIO, the corresponding logic
is powered from AVDD and AVSS. When the External Voltage Reference Monitor
ADS1247/8 are operated with bipolar analog The ADS1246/7/8 can be selected to measure the
supplies, the GPIO outputs bipolar voltages. Care external voltage reference. In this configuration, the
must be taken loading the GPIO pins when used as monitored external voltage reference is connected to
outputs because large currents can cause droop or the analog input. The result (conversion code) is
noise on the analog supplies. approximately 1/4 of the actual reference voltage.
Conversion Result = (VREX/4)/VREF (6)
Where VREX is the external reference to be
monitored.
NOTE: The internal reference voltage must be
enabled when measuring an external voltage
reference using the system monitor.
Ambient Temperature Monitor
On-chip diodes provide temperature-sensing
capability. When selecting the temperature monitor
function, the anodes of two diodes are connected to
Figure 65. Analog/Data Interface Pin the ADC. Typically, the difference in diode voltage is
118mV at +25°C with a temperature coefficient of
405μV/°C.
SYSTEM MONITOR Note that when the onboard temperature monitor is
The ADS1247 and ADS1248 provide a system selected, the PGA is automatically set to '1'.
monitor function. This function can measure the However, the PGA register bits in are not affected
analog power supply, digital power supply, external and the PGA returns to its set value when the
voltage reference, or ambient temperature. Note that temperature monitor is turned off.
the system monitor function provides a coarse result.
When the system monitor is enabled, the analog
inputs are disconnected.
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ADC S
OFC
Register
Final
Output
OutputData
Clippedto24Bits
´
+
-
FSCRegister
400000h
FinalOutputData=(Input OFC[2:0])- ´ FSC[2:0]
400000h
-1.251V > |Offset Scaling|
2V
Gain Scaling
ADS1246
ADS1247
ADS1248
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Offset Calibration Register: OFC[2:0]
CALIBRATION The offset calibration is a 24-bit word, composed of
The conversion data are scaled by offset and gain three 8-bit registers. The offset is in twos complement
registers before yielding the final output code. As format with a maximum positive value of 7FFFFFh
shown in Figure 66, the output of the digital filter is and a maximum negative value of 800000h. This
first subtracted by the offset register (OSC) and then value is subtracted from the conversion data. A
multiplied by the full-scale register (FSC). A digital register value of 000000h provides no offset
clipping circuit ensures that the output code does not correction. Note that while the offset calibration
exceed 24 bits. Equation 7 shows the scaling. register value can correct offsets ranging from FS to
+FS (as shown in Table 12), make sure to avoid
overloading the analog inputs.
Table 12. Final Output Code versus Offset
Calibration Register Setting
FINAL OUTPUT CODE WITH
OFFSET REGISTER VIN = 0
7FFFFFh 8000000h
Figure 66. Calibration Block Diagram 000001h FFFFFFh
000000h 000000h
FFFFFFh 000001h
(7) 8000000h 7FFFFFh
The values of the offset and full-scale registers are 1. Excludes effects of noise and inherent offset
set by writing to them directly, or they are set errors.
automatically by calibration commands.
The gain and offset calibration features are intended Full-Scale Calibration Register: FSC[2:0]
for correction of minor system level offset and gain The full-scale or gain calibration is a 24-bit word
errors. When entering manual values into the composed of three 8-bit registers. The full-scale
calibration registers, care must be taken to avoid calibration value is 24-bit, straight binary, normalized
scaling down the gain register to values far below a to 1.0 at code 400000h. Table 13 summarizes the
scaling factor of 1.0. Under extreme situations it scaling of the full-scale register. Note that while the
becomes possible to over-range the ADC. To avoid full-scale calibration register can correct gain errors
this, make sure to avoid encountering situations >1 (with gain scaling <1), make sure to avoid
where analog inputs are connected to voltages overloading the analog inputs. The default or reset
greater than the reference/PGA. value of FSC depends on the PGA setting. A different
Care must also be taken when increasing digital gain. factory-trimmed FSC Reset value is stored for each
When implementing custom digital gains less than PGA setting which provides outstanding gain
20% higher than nominal and offsets less than 40% accuracy over all the ADS1246/7/8 input ranges.
of full scale, no special care is required. When Note: The factory-trimmed FSC reset value loads
operating at digital gains greater than 20% higher automatically loaded whenever the PGA setting
than nominal and offsets greater than 40% of full changes.
scale, make sure that the offset and gain registers
follow the conditions of Equation 8.Table 13. Gain Correction Factor versus
Full-Scale Calibration Register Setting
FULL-SCALE REGISTER GAIN SCALING
(8) 800000h 2.0
400000h 1.0
200000h 0.5
000000h 0
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CalibrationTime= 50
fOSC
32
fMOD
16
fDATA
++
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Calibration Commands disconnected from the internal circuitry and a zero
differential signal is applied internally. With both offset
The ADS1246/7/8 provide commands for three types calibrations the offset calibration register (OFC) is
of calibration: system gain calibration, system offset updated afterwards. When either offset calibration
calibration and self offset calibration. Where absolute command is issued, the ADS1246/7/8 stop the
accuracy is needed, it is recommended that current conversion and start the calibration procedure
calibration be performed after power on, a change in immediately.
temperature, a change of PGA and in some cases a
change in channel. At the completion of calibration, Calibration Timing
the DRDY signal goes low indicating the calibration is
finished. The first data after calibration are always When calibration is initiated, the device performs 16
valid. If the START pin is taken low or a SLEEP consecutive data conversions and averages the
command is issued after any calibration command, results to calculate the calibration value. This
the devices goes to sleep after completing calibration. provides a more accurate calibration value. The time
required for calibration is shown in Table 14 and can
It is important to allow a pending system calibration to be calculated using Equation 9:
complete before issuing any other commands.
Issuing commands during a calibration can result in
corrupted data. If this occurs either resend the (9)
calibration command that was aborted or issue a
device reset. ADC POWER-UP
When DVDD is pulled up, the internal power-on reset
System Gain Calibration module generates a pulse that resets all digital
System gain calibration corrects for gain error in the circuitry. All the digital circuits are held in a reset
signal path. The system gain calibration is initiated by state for 216 system clocks to allow the analog circuits
sending the SYSGCAL command while applying a and the internal digital power supply to settle. SPI
full-scale input to the selected analog inputs. communication cannot occur until the internal reset is
Afterwards the full-scale calibration register (FSC) is released.
updated. When a system gain calibration command is
issued, the ADS1246/7/8 stop the current conversion ADC SLEEP MODE
and start the calibration procedure immediately. Power consumption can be dramatically reduced by
System Offset and Self Offset Calibration placing the ADS1246/7/8 into sleep mode. There are
two ways to put the device into sleep mode: the sleep
System offset calibration corrects both internal and command (SLEEP) and through the START pin.
external offset errors. The system offset calibration is
initiated by sending the SYSGOCAL command while During sleep mode, the internal reference status
applying a zero differential input (VIN = 0) to the depends on the setting of the VREFCON bits in the
selected analog inputs. The self offset calibration is MUX1 register; see the Register Descriptions section
initiated by sending the SELFOCAL command. for details.
During self offset calibration, the selected inputs are
Table 14. Calibration Time versus Data Rate
DATA RATE (SPS) CALIBRATION TIME (ms)(1)
5 3201.01
10 1601.01
20 801.012
40 400.26
80 200.26
160 100.14
320 50.14
640 25.14
1000 16.14
2000 8.07
(1) For fOSC = 4.096MHz.
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Converting
START
DOUT/DRDY
SCLK
DRDY
ADS1246/47/48
Status Shutdown
1 2 3 24
tCONV
tSTART
Converting Converting Converting Converting
START
DOUT/DRDY
ADS1246/47/48
Status
DataReady DataReady DataReady
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ADC CONTROL configuration registers. The device stays shut down
until the START pin is once again taken high to begin
ADC Conversion Control a new conversion. When the START pin is taken
back high again, the decimation filter is held in a
The START pin provides easy and precise control of reset state for 32 modulator clock cycles internally to
conversions. Pulse the START pin high to begin a allow the analog circuits to settle.
conversion, as shown in Figure 67 and Table 15. The
conversion completion is indicated by the The ADS1246/7/8 can be configured to convert
DOUT/DRDY pin going low. When the conversion continuously by holding the START pin high, as
completes, the ADS1246/7/8 automatically shuts shown in Figure 68.
down to save power. During shutdown, the
conversion result can be retrieved; however, START
must be taken high before communicating with the
Figure 67. Timing for Single Conversion Using START Pin
Table 15. START Pin Conversion Times for Figure 67
SYMBOL DESCRIPTION DATA RATE (SPS) VALUE UNIT
5 200.295 ms
10 100.644 ms
20 50.825 ms
40 25.169 ms
80 12.716 ms
Time from START pulse to DRDY and
tCONV DOUT/DRDY going low 160 6.489 ms
320 3.247 ms
640 1.692 ms
1000 1.138 ms
2000 0.575 ms
NOTE: SCLK held low in this example.
Figure 68. Timing for Conversion with START Pin High
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With the START pin held high, the ADC converts the an overload state can cause the chopper to become
selected input channels continuously. This unstable. This instability results in slow settling time.
configuration continues until the START pin is taken To prevent this slow settling, always change the PGA
low. The START pin can also be used to perform the setting or MUX setting to a non-overloaded state
synchronized measurement for the multi-channel before changing the data rate.
applications by pulsing the START pin. Single-Cycle Settling
RESET The ADS1246/7/8 are capable of single-cycle settling
When the RESET pin goes low, the device is across all gains and data rates. However, to achieve
immediately reset. All the registers are restored to single-cycle settling at 2kSPS, special care must be
default values. The device stays in reset mode as taken with respect to the interface. When operating at
long as the RESET pin stays low. When it goes high, 2kSPS, the SPI data SCLK period must not exceed
the ADC comes out of reset mode and is able to 520ns, and the time between the beginning of a byte
convert data. After the RESET pin goes high, and and the beginning of a subsequent byte must not
when the system clock frequency is 4.096MHz, the exceed 4.2µs. Additionally, when performing multiple
digital filter and the registers are held in a reset state individual write commands to the first four registers,
for 0.6ms when fOSC = 4.096MHz. Therefore, valid wait at least 64 oscillator clocks before initiating
SPI communication can only be resumed 0.6ms after another write command.
the RESET pin goes high; see Figure 4. When the
RESET pin goes low, the clock selection is reset to Digital Filter Reset Operation
the internal oscillator. Apart from the RESET command and the RESET pin,
Channel Cycling and Overload Recovery the digital filter is reset automatically when either a
write operation to the MUX0, VBIAS, MUX1, or SYS0
When cycling through channels, care must be taken registers is performed, when a SYNC command is
when configuring the ADS1246/7/8 to ensure that issued, or the START pin is taken high.
settling occurs within one cycle. For setups that
simply cycle through MUX channels, but do not The filter is reset two system clocks after the last bit
change PGA and data rate settings, simply changing of the SYNC command is sent. The reset pulse
the MUX0 register is sufficient. However, when created internally lasts for two multiplier clock cycles.
changing PGA and data rate settings it is important to If any write operation takes place in the MUX0
ensure that an overloaded condition cannot occur register, the filter is reset regardless of whether the
during the transmission. When configuration data are value changed or not. Internally, the filter pulse lasts
transferred to the ADS1246/7/8, new settings become for two system clock periods. If any write activity
active at the end of each byte sent. Therefore, a brief takes place in the VBIAS, MUX1, or SYS0 registers,
overload condition can occur during the transmission the filter is reset as well, regardless of whether the
of configuration data after the completion of the value changed or not. The reset pulse lasts for 32
MUX0 byte and before completion of the SYS0 byte. modulator clocks after the write operation. If there are
This temporary overload can result in intermittent multiple write operations, the resulting reset pulse
incorrect readings. To ensure that an overload does may be viewed as the ANDed result of the different
not occur, it may be necessary to split the active low pulses created individually by each action.
communication into two separate communications Table 16 shows the conversion time after a filter
allowing the change of the SYS0 register before the reset. Note that this time depends on the operation
change of the MUX0 register. initiating the reset. Also, the first conversion after a
In the event of an overloaded state, care must also filter reset has a slightly different time than the
be taken to ensure single cycle settling into the next second and subsequent conversions.
cycle. Because the ADS1246/7/8 implement a
chopper-stabilized PGA, changing data rates during
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Table 16. Data Conversion Time
FIRST DATA CONVERSION TIME AFTER FILTER RESET
HARDWARE RESET, RESET
COMMAND, START PIN HIGH,
WAKEUP COMMAND, VBIAS, SECOND AND SUBSEQUENT
SYNC COMMAND, MUX0 MUX1, or SYS0 REGISTER CONVERSION TIME AFTER
REGISTER WRITE WRITE FILTER RESET
NO. OF NO. OF NO. OF
NOMINAL EXACT DATA SYSTEM SYSTEM SYSTEM
DATA RATE RATE CLOCK CLOCK CLOCK
(SPS) (SPS) (ms)(1) CYCLES (ms)(1) CYCLES (ms) CYCLES
5 5.019 199.258 816160 200.26 820265 199.250 816128
10 10.038 99.633 408096 100.635 412201 99.625 408064
20 20.075 49.820 204064 50.822 208169 49.812 204032
40 40.151 24.92 102072 25.172 103106 24.906 102016
80 80.301 12.467 51064 12.719 52098 12.453 51008
160 160.602 6.240 25560 6.492 26594 6.226 25504
320 321.608 3.124 12796 3.25 13314 3.109 12736
640 643.216 1.569 6428 1.695 6946 1.554 6368
1000 1000 1.014 4156 1.141 4674 1 4096
2000 2000 0.514 2108 0.578 2370 0.5 2048
(1) For fOSC = 4.096MHz. command and the RDATA command. These
Data Format limitations are explained in detail in the SPI
Commands section of this data sheet. For the basic
The ADS1246/7/8 output 24 bits of data in binary serial interface timing characteristics, see Figure 1
twos complement format. The least significant bit and Figure 2 of this datasheet.
(LSB) has a weight of (VREF/PGA)/(223 1). The
positive full-scale input produces an output code of CS
7FFFFFh and the negative full-scale input produces The chip select pin (active low). The CS pin activates
an output code of 800000h. The output clips at these SPI communication. CS must be low before data
codes for signals exceeding full-scale. Table 17 transactions and must stay low for the entire SPI
summarizes the ideal output codes for different input communication period. When CS is high, the
signals. DOUT/DRDY pin enters a high-impedance state.
Therefore, reading and writing to the serial interface
Table 17. Ideal Output Code vs Input Signal are ignored and the serial interface is reset. DRDY
pin operation is independent of CS.
INPUT SIGNAL, VIN
(AINPAINN) IDEAL OUTPUT CODE Taking CS high deactivates only the SPI
+VREF/PGA 7FFFFFh communication with the device. Data conversion
(+VREF/PGA)/(223 1) 000001h continues and the DRDY signal can be monitored to
check if a new conversion result is ready. A master
0 000000h device monitoring the DRDY signal can select the
(VREF/PGA)/(223 1) FFFFFFh appropriate slave device by pulling the CS pin low.
(VREF/PGA) ×(223/223 1) 800000h The ADS1246/7/8 implement a timeout function for all
1. Excludes effects of noise, linearity, offset, and listed commands in the event that data is corrupted
gain errors. and chip select is permanently tied low. However, it is
important in systems where chip select is tied low
Digital Interface permanently that register writes always be fully
completed in 8 bit increments. The SCLK line should
The ADS1246/7/8 provide a standard SPI serial also be kept clean and situations should be avoided
communication interface plus a data ready signal where noise on the SCLK line could cause the device
(DRDY). Communication is full-duplex with the to interpret the transient as a false SCLK. In systems
exception of a few limitations in regards to the RREG where such events are likely to occur, it is
recommended that chip select be used to frame
communications to the device.
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SCLK
D[23]
1 2 22 1 2 823 243
D[22] D[21] D[2] D[1] D[0]
DOUT/ (1)
DRDY
DRDY
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SCLK DOUT/DRDY
The serial clock signal. SCLK provides the clock for This pin has two modes: data out (DOUT) only, or
serial communication. It is a Schmitt-trigger input, but data out (DOUT) combined with data ready (DRDY).
it is highly recommended that SCLK be kept as clean The DRDY MODE bit determines the function of this
as possible to prevent glitches from inadvertently pin. In either mode, the DOUT/DRDY pin goes to a
shifting the data. Data are shifted into DIN on the high-impedance state when CS is taken high.
falling edge of SCLK and shifted out of DOUT on the When the DRDY MODE bit is set to '0', this pin
rising edge of SCLK. functions as DOUT only. Data are clocked out at
DIN rising edge of SCLK, MSB first (see Figure 69).
The data input pin. DIN is used along with SCLK to When the DRDY MODE bit is set to '1', this pin
send data to the device. Data on DIN are shifted into functions as both DOUT and DRDY. Data are shifted
the device on the falling edge of SCLK. out from this pin, MSB first, at the rising edge of
The communication of this device is full-duplex in SCLK. This combined pin allows for the same control
nature. The device monitors commands shifted in but with fewer pins.
even when data are being shifted out. Data that are When the DRDY MODE bit is enabled and a new
present in the output shift register are shifted out conversion is complete, DOUT/DRDY goes low if it is
when sending in a command. Therefore, it is high. If it is already low, then DOUT/DRDY goes high
important to make sure that whatever is being sent on and then goes low (see Figure 70). Similar to the
the DIN pin is valid when shifting out data. When no DRDY pin, a falling edge on the DOUT/DRDY pin
command is to be sent to the device when reading signals that a new conversion result is ready. After
out data, the NOP command should be sent on DIN. DOUT/DRDY goes low, the data can be clocked out
DRDY by providing 24 SCLKs. In order to force
The data ready pin. The DRDY pin goes low to DOUT/DRDY high (so that DOUT/DRDY can be
indicate a new conversion is complete, and the polled for a '0' instead of waiting for a falling edge), a
conversion result is stored in the conversion result no operation command (NOP) or any other command
buffer. The SPI clock must be low in a short time that does not load the data output register can be
frame around the DRDY low transition (see Figure 2) sent after reading out the data. Because SCLKs can
so that the conversion result is loaded into both the only be sent in multiples of eight, a NOP can be sent
result buffer and the output shift register. Therefore, to force DOUT/DRDY high if no other command is
no commands should be issued during this time pending. The DOUT/DRDY pin goes high after the
frame if the conversion result is to be read out later. first rising edge of SCLK after reading the conversion
This constraint applies only when CS is asserted. result completely (see Figure 71). The same condition
When CS is not asserted, SPI communication with also applies after an RREG command. After all the
other devices on the SPI bus does not affect loading register bits have been read out, the rising edge of
of the conversion result. After the DRDY pin goes SCLK forces DOUT/DRDY high. Figure 72 illustrates
low, it is forced high on the first falling edge of SCLK an example where sending four NOP commands after
(so that the DRDY pin can be polled for '0' instead of an RREG command forces the DOUT/DRDY pin
waiting for a falling edge). If the DRDY pin is not high.
taken high after it falls low, a short high pulse is
created on it to indicate the next data are ready.
(1) CS tied low.
Figure 69. Data Retrieval with the DRDY MODE Bit = 0 (Disabled)
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SCLK
DIN
11
D[23] D[22]D[23]D[22] D[21]
NOP NOP
D[2] D[1] D[0] D[0]
22
3 22 23 24 24
DOUT/ (1)
DRDY
DRDY
SCLK
DIN
11
D[23] D[22]D[23]D[22] D[21]
NOP NOP NOP
D[2] D[1] D[0] D[0]
22
3 22 23 24 1 2 8 24
DOUT/ (1)
DRDY
DRDY
SCLK
DOUT/ (1)
DRDY
DIN NOP
1
reg[7] reg[1] reg[0]
2 1 2 7 87 8
NOP
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SBAS426G AUGUST 2008REVISED OCTOBER 2011
(1) CS tied low.
Figure 70. Data Retrieval with the DRDY MODE Bit = 1 (Enabled)
(1) DRDY MODE bit enabled, CS tied low.
Figure 71. DOUT/DRDY Forced High After Retrieving the Conversion Result
(1) DRDY MODE bit enabled, CS tied low.
Figure 72. DOUT/DRDY Forced High After Reading Register Data
The DRDY MODE bit modifies only the DOUT/DRDY SPI Communication During Sleep Mode
pin functionality. The DRDY pin functionality remains
unaffected. When the START pin is low or the device is in sleep
mode, only the RDATA, RDATAC, SDATAC,
SPI Reset WAKEUP, and NOP commands can be issued. The
RDATA command can be used to repeatedly read the
SPI communication can be reset in several ways. In last conversion result during sleep mode. Other
order to reset the SPI interface (without resetting the commands do not function because the internal clock
registers or the digital filter), the CS pin can be pulled is shut down to save power during sleep mode.
high. Taking the RESET pin low causes the SPI
interface to be reset along with all the other digital
functions. In this case, the registers and the
conversion are reset.
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REGISTER DESCRIPTIONS
ADS1246 REGISTER MAP
Table 18. ADS1246 Register Map
ADDRESS REGISTER BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
00h BCS BCS1 BCS0 0 0 0 0 0 1
01h VBIAS 0 0 0 0 0 0 VBIAS1 VBIAS0
02h MUX1 CLKSTAT 0 0 0 0 MUXCAL2 MUXCAL1 MUXCAL0
03h SYS0 0 PGA2 PGA1 PGA0 DR3 DR2 DR1 DR0
04h OFC0 OFC7 OFC6 OFC5 OFC4 OFC3 OFC2 OFC1 OFC0
05h OFC1 OFC15 OFC14 OFC13 OFC12 OFC11 OFC10 OFC9 OFC8
06h OFC2 OFC23 OFC22 OFC21 OFC20 OFC19 OFC18 OFC17 OFC16
07h FSC0 FSC7 FSC6 FSC5 FSC4 FSC3 FSC2 FSC1 FSC0
08h FSC1 FSC15 FSC14 FSC13 FSC12 FSC11 FSC10 FSC9 FSC8
09h FSC2 FSC23 FSC22 FSC21 FSC20 FSC19 FSC18 FSC17 FSC16
DRDY
0Ah ID ID3 ID2 ID1 ID0 0 0 0
MODE
ADS1246 DETAILED REGISTER DEFINITIONS
BCSBurnout Current Source Register. These bits control the settling of the sensor burnout detect current
source.
BCS - ADDRESS 00h RESET VALUE = 01h
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
BCS1 BCS0 0 0 0 0 0 1
Bits 7:6 BCS1:0
These bits select the magnitude of the sensor burnout detect current source.
00 = Burnout current source off (default)
01 = Burnout current source on, 0.5μA
10 = Burnout current source on, 2μA
11 = Burnout current source on, 10μA
Bits 5:0 These bits must always be set to '000001'.
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ADS1246 DETAILED REGISTER DEFINITIONS (continued)
VBIASBias Voltage Register. This register enables a bias voltage on the analog inputs.
VBIAS - ADDRESS 01h RESET VALUE = 00h
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
0 0 0 0 0 0 VBIAS1 VBIAS0
Bits 7:2 These bits must always be set to '000000'.
Bits 1:0 VBIAS1:0
These bits apply a bias voltage of midsupply (AVDD + AVSS)/2 to the selected analog input. Bit 0
is for AIN0, and bit 1 is for AIN1.
0 = Bias voltage not enabled (default)
1 = Bias voltage is applied to the analog input
MUXMultiplexer Control Register.
MUX - ADDRESS 02h RESET VALUE = x0h
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
CLKSTAT 0 0 0 0 MUXCAL2 MUXCAL1 MUXCAL0
Bit 7 CLKSTAT
This bit is read-only and indicates whether the internal or external oscillator is being used.
0 = Internal oscillator in use
1 = External oscillator in use
Bits 6:3 These bits must always be set to '0000'.
Bits 2:0 MUXCAL2:0
These bits are used to select a system monitor. The MUXCAL selection supercedes selections
from the VBIAS register.
000 = Normal operation (default)
001 = Offset calibration. The analog inputs are disconnected and AINP and AINN are internally
connected to midsupply (AVDD + AVSS)/2.
010 = Gain calibration. The analog inputs are connected to the voltage reference.
011 = Temperature measurement. The inputs are connected to a diode circuit that produces a
voltage proportional to the ambient temperature of the device..
Table 19 lists the ADC input connection and PGA settings for each MUXCAL setting. The PGA setting reverts to
the original SYS0 register setting when MUXCAL is taken back to normal operation or offset measurement.
Table 19. MUXCAL Settings
MUXCAL[2:0] PGA GAIN SETTING ADC INPUT
000 Set by SYS0 register Normal operation
001 Set by SYS0 register Offset calibration: inputs shorted to midsupply (AVDD + AVSS)/2
010 Forced to 1 Gain calibration: VREFP VREFN (full-scale)
011 Forced to 1 Temperature measurement diode
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ADS1246 DETAILED REGISTER DEFINITIONS (continued)
SYS0System Control Register 0.
SYS0 - ADDRESS 03h RESET VALUE = 00h
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
0 PGA2 PGA1 PGA0 DOR3 DOR2 DOR1 DOR0
Bit 7 These bits must always be set to '0'.
Bits 6:4 PGA2:0
These bits determine the gain of the PGA.
000 = 1 (default)
001 = 2
010 = 4
011 = 8
100 = 16
101 = 32
110 = 64
111 = 128
Bits 3:0 DOR3:0
These bits select the output data rate of the ADC. Bits with a value higher than 1001 select the
highest data rate of 2kSPS.
0000 = 5SPS (default)
0001 = 10SPS
0010 = 20SPS
0011 = 40SPS
0100 = 80SPS
0101 = 160SPS
0110 = 320SPS
0111 = 640SPS
1000 = 1000SPS
1001 to 1111 = 2000SPS
OFC23:0
These bits make up the offset calibration coefficient register of the ADS1248.
OFC0Offset Calibration Coefficient Register 0
OFC0 - ADDRESS 04h RESET VALUE = 00h
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
OFC7 OFC6 OFC5 OFC4 OFC3 OFC2 OFC1 OFC0
OFC1Offset Calibration Coefficient Register 1
OFC1 - ADDRESS 05h RESET VALUE = 00h
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
OFC15 OFC14 OFC13 OFC12 OFC11 OFC10 OFC9 OFC8
OFC2Offset Calibration Coefficient Register 2
OFC2 - ADDRESS 06h RESET VALUE = 00h
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
OFC23 OFC22 OFC21 OFC20 OFC19 OFC18 OFC17 OFC16
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ADS1246 DETAILED REGISTER DEFINITIONS (continued)
FSC23:0
These bits make up the full-scale calibration coefficient register.
FSC0Full-Scale Calibration Coefficient Register 0
FSC0 - ADDRESS 07h RESET VALUE IS PGA DEPENDENT(1)
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
FSC7 FSC6 FSC5 FSC4 FSC3 FSC2 FSC1 FSC0
(1) The reset value for FSC is factory-trimmed for each PGA setting. Note: the factory-trimmed FSC reset value is automatically loaded
whenever the PGA setting is changed.
FSC1Full-Scale Calibration Coefficient Register 1
FSC1 - ADDRESS 08h RESET VALUE IS PGA DEPENDENT(1)
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
FSC15 FSC14 FSC13 FSC12 FSC11 FSC10 FSC9 FSC8
(1) The reset value for FSC is factory-trimmed for each PGA setting. Note: the factory-trimmed FSC reset value is automatically loaded
whenever the PGA setting is changed.
FSC2Full-Scale Calibration Coefficient Register 2
FSC2 - ADDRESS 09h RESET VALUE IS PGA DEPENDENT(1)
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
FSC23 FSC22 FSC21 FSC20 FSC19 FSC18 FSC17 FSC16
(1) The reset value for FSC is factory-trimmed for each PGA setting. Note: the factory-trimmed FSC reset value is automatically loaded
whenever the PGA setting is changed.
IDID Register
IDAC0 - ADDRESS 0Ah RESET VALUE = x0h
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
ID3 ID2 ID1 ID0 DRDY MODE 0 0 0
Bits 7:4 ID3:0
Read-only, factory-programmed bits; used for revision identification.
Bit 3 DRDY MODE
This bit sets the DOUT/DRDY pin functionality. In either setting of the DRDY MODE bit, the DRDY
pin continues to indicate data ready, active low.
0 = DOUT/DRDY pin functions only as Data Out (default)
1 = DOUT/DRDY pin functions both as Data Out and Data Ready, active low
Bits 2:0 These bits must always be set to '000'.
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ADS1247 AND ADS1248 REGISTER MAP
Table 20. ADS1247 and ADS1248 Register Map
ADDRESS REGISTER BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
00h MUX0 BCS1 BCS0 MUX_SP2 MUX_SP1 MUX_SP0 MUX_SN2 MUX_SN1 MUX_SN0
01h VBIAS VBIAS7 VBIAS6 VBIAS5 VBIAS4 VBIAS3 VBIAS2 VBIAS1 VBIAS0
02h MUX1 CLKSTAT VREFCON1 VREFCON0 REFSELT1 REFSELT0 MUXCAL2 MUXCAL1 MUXCAL0
03h SYS0 0 PGA2 PGA1 PGA0 DR3 DR2 DR1 DR0
04h OFC0 OFC7 OFC6 OFC5 OFC4 OFC3 OFC2 OFC1 OFC0
05h OFC1 OFC15 OFC14 OFC13 OFC12 OFC11 OFC10 OFC9 OFC8
06h OFC2 OFC23 OFC22 OFC21 OFC20 OFC19 OFC18 OFC17 OFC16
07h FSC0 FSC7 FSC6 FSC5 FSC4 FSC3 FSC2 FSC1 FSC0
08h FSC1 FSC15 FSC14 FSC13 FSC12 FSC11 FSC10 FSC9 FSC8
09h FSC2 FSC23 FSC22 FSC21 FSC20 FSC19 FSC18 FSC17 FSC16
DRDY
0Ah IDAC0 ID3 ID2 ID1 ID0 IMAG2 IMAG1 IMAG0
MODE
0Bh IDAC1 I1DIR3 I1DIR2 I1DIR1 I1DIR0 I2DIR3 I2DIR2 I2DIR1 I2DIR0
0Ch GPIOCFG IOCFG7 IOCFG6 IOCFG5 IOCFG4 IOCFG3 IOCFG2 IOCFG1 IOCFG0
0Dh GPIODIR IODIR7 IODIR6 IODIR5 IODIR4 IODIR3 IODIR2 IODIR1 IODIR0
0Eh GPIODAT IODAT7 IODAT6 IODAT5 IODAT4 IODAT3 IODAT2 IODAT1 IODAT0
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ADS1247 and ADS1248 DETAILED REGISTER DEFINITIONS
MUX0Multiplexer Control Register 0. This register allows any combination of differential inputs to be selected
on any of the input channels. Note that this setting can be superceded by the MUXCAL and VBIAS bits.
MUX0 - ADDRESS 00h RESET VALUE = 01h
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
BCS1 BCS0 MUX_SP2 MUX_SP1 MUX_SP0 MUX_SN2 MUX_SN1 MUX_SN0
Bits 7:6 BCS1:0
These bits select the magnitude of the sensor detect current source.
00 = Burnout current source off (default)
01 = Burnout current source on, 0.5μA
10 = Burnout current source on, 2μA
11 = Burnout current source on, 10μA
Bits 5:3 MUX_SP2:0
Positive input channel selection bits.
000 = AIN0 (default)
001 = AIN1
010 = AIN2
011 = AIN3
100 = AIN4 (ADS1248 only)
101 = AIN5 (ADS1248 only)
110 = AIN6 (ADS1248 only)
111 = AIN7 (ADS1248 only)
Bits 2:0 MUX_SN2:0
Negative input channel selection bits.
000 = AIN0
001 = AIN1 (default)
010 = AIN2
011 = AIN3
100 = AIN4 (ADS1248 only)
101 = AIN5 (ADS1248 only)
110 = AIN6 (ADS1248 only)
111 = AIN7 (ADS1248 only)
VBIASBias Voltage Register
VBIAS - ADDRESS 01h RESET VALUE = 00h
DEVICE BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
ADS1248 VBIAS7 VBIAS6 VBIAS5 VBIAS4 VBIAS3 VBIAS2 VBIAS1 VBIAS0
ADS1247 0 0 0 0 VBIAS3 VBIAS2 VBIAS1 VBIAS0
Bits 7:0 VBIAS7:0
These bits apply a bias voltage of midsupply (AVDD + AVSS)/2 to the selected analog input.
0 = Bias voltage not enabled (default)
1 = Bias voltage is applied on the corresponding analog input (bit 0 corresponds to AIN0, etc.).
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ADS1247 and ADS1248 DETAILED REGISTER DEFINITIONS (continued)
MUX1Multiplexer Control Register 1
MUX1 - ADDRESS 02h RESET VALUE = 00h
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
CLKSTAT VREFCON1 VREFCON0 REFSELT1 REFSELT0 MUXCAL2 MUXCAL1 MUXCAL0
Bit 7 CLKSTAT
This bit is read-only and indicates whether the internal or external oscillator is being used.
0 = Internal oscillator in use
1 = External oscillator in use
Bits 6:5 VREFCON1:0
These bits control the internal voltage reference. These bits allow the reference to be turned on or
off completely, or allow the reference state to follow the state of the device. Note that the internal
reference is required for operation of the IDAC functions.
00 = Internal reference is always off (default)
01 = Internal reference is always on
10 or 11 = Internal reference is on when a conversion is in progress and shuts down when the
device receives a shutdown opcode or the START pin is taken low
Bits 4:3 REFSELT1:0
These bits select the reference input for the ADC.
00 = REF0 input pair selected (default)
01 = REF1 input pair selected (ADS1248 only)
10 = Onboard reference selected
11 = Onboard reference selected and internally connected to REF0 input pair
Bits 2:0 MUXCAL2:0
These bits are used to select a system monitor. The MUXCAL selection supercedes selections
from registers MUX0 and MUX1 (MUX_SP, MUX_SN, and VBIAS).
000 = Normal operation (default)
001 = Offset measurement
010 = Gain measurement
011 = Temperature diode
100 = External REF1 measurement (ADS1248 only)
101 = External REF0 measurement
110 = AVDD measurement
111 = DVDD measurement
Table 21 provides the ADC input connection and PGA settings for each MUXCAL setting. The PGA setting
reverts to the original SYS0 register setting when MUXCAL is taken back to normal operation or offset
measurement.
Table 21. MUXCAL Settings
MUXCAL[2:0] PGA GAIN SETTING ADC INPUT
000 Set by SYS0 register Normal operation
001 Set by SYS0 register Inputs shorted to midsupply (AVDD + AVSS)/2
010 Forced to 1 VREFP VREFN (full-scale)
011 Forced to 1 Temperature measurement diode
100 Forced to 1 (VREFP1 VREFN1)/4
101 Forced to 1 (VREFP0 VREFN0)/4
110 Forced to 1 (AVDD AVSS)/4
111 Forced to 1 (DVDD DVSS)/4
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ADS1247 and ADS1248 DETAILED REGISTER DEFINITIONS (continued)
SYS0System Control Register 0
SYS0 - ADDRESS 03h RESET VALUE = 00h
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
0 PGA2 PGA1 PGA0 DOR3 DOR2 DOR1 DOR0
Bit 7 This bit must always be set to '0'
Bits 6:4 PGA2:0
These bits determine the gain of the PGA.
000 = 1 (default)
001 = 2
010 = 4
011 = 8
100 = 16
101 = 32
110 = 64
111 = 128
Bits 3:0 DOR3:0
These bits select the output data rate of the ADC. Bits with a value higher than 1001 select the
highest data rate of 2000SPS.
0000 = 5SPS (default)
0001 = 10SPS
0010 = 20SPS
0011 = 40SPS
0100 = 80SPS
0101 = 160SPS
0110 = 320SPS
0111 = 640SPS
1000 = 1000SPS
1001 to 1111 = 2000SPS
OFC23:0
These bits make up the offset calibration coefficient register of the ADS1248.
OFC0Offset Calibration Coefficient Register 0
OFC0 - ADDRESS 04h RESET VALUE = 000000h
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
OFC7 OFC6 OFC5 OFC4 OFC3 OFC2 OFC1 OFC0
OFC1Offset Calibration Coefficient Register 1
OFC1 - ADDRESS 05h RESET VALUE = 000000h
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
OFC15 OFC14 OFC13 OFC12 OFC11 OFC10 OFC9 OFC8
OFC2Offset Calibration Coefficient Register 2
OFC2 - ADDRESS 06h RESET VALUE = 000000h
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
OFC23 OFC22 OFC21 OFC20 OFC19 OFC18 OFC17 OFC16
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ADS1247 and ADS1248 DETAILED REGISTER DEFINITIONS (continued)
FSC23:0
These bits make up the full-scale calibration coefficient register.
FSC0Full-Scale Calibration Coefficient Register 0
FSC0 - ADDRESS 07h RESET VALUE IS PGA DEPENDENT(1)
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
FSC7 FSC6 FSC5 FSC4 FSC3 FSC2 FSC1 FSC0
(1) The reset value for FSC is factory-trimmed for each PGA setting. Note: the factory-trimmed FSC reset value is automatically loaded
whenever the PGA setting is changed.
FSC1Full-Scale Calibration Coefficient Register 1
FSC1 - ADDRESS 08h RESET VALUE IS PGA DEPENDENT(1)
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
FSC15 FSC14 FSC13 FSC12 FSC11 FSC10 FSC9 FSC8
(1) The reset value for FSC is factory-trimmed for each PGA setting. Note: the factory-trimmed FSC reset value is automatically loaded
whenever the PGA setting is changed.
FSC2Full-Scale Calibration Coefficient Register 2
FSC2 - ADDRESS 09h RESET VALUE IS PGA DEPENDENT(1)
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
FSC23 FSC22 FSC21 FSC20 FSC19 FSC18 FSC17 FSC16
(1) The reset value for FSC is factory-trimmed for each PGA setting. Note: the factory-trimmed FSC reset value is automatically loaded
whenever the PGA setting is changed.
IDAC0IDAC Control Register 0
IDAC0 - ADDRESS 0Ah RESET VALUE = x0h
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
ID3 ID2 ID1 ID0 DRDY MODE IMAG2 IMAG1 IMAG0
Bits 7:4 ID3:0
Read-only, factory-programmed bits; used for revision identification.
Bit 3 DRDY MODE
This bit sets the DOUT/DRDY pin functionality. In either setting of the DRDY MODE bit, the DRDY
pin continues to indicate data ready, active low.
0 = DOUT/DRDY pin functions only as Data Out (default)
1 = DOUT/DRDY pin functions both as Data Out and Data Ready, active low
Bits 2:0 IMAG2:0
The ADS1247/8 have two programmable current source DACs that can be used for sensor
excitation. The IMAG bits control the magnitude of the excitation current. The IDACs require the
internal reference to be on.
000 = off (default)
001 = 50μA
010 = 100μA
011 = 250μA
100 = 500μA
101 = 750μA
110 = 1000μA
111 = 1500μA
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ADS1247 and ADS1248 DETAILED REGISTER DEFINITIONS (continued)
IDAC1IDAC Control Register 1
IDAC1 - ADDRESS 0Bh RESET VALUE = FFh
DEVICE BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
ADS1248 I1DIR3 I1DIR2 I1DIR1 I1DIR0 I2DIR3 I2DIR2 I2DIR1 I2DIR0
ADS1247 0 0 I1DIR1 I1DIR0 0 0 I2DIR1 I2DIR0
The two IDACs on the ADS1247/8 can be routed to either the IEXC1 and IEXC2 output pins or directly to the
analog inputs.
Bits 7:4 I1DIR3:0
These bits select the output pin for the first current source DAC.
0000 = AIN0
0001 = AIN1
0010 = AIN2
0011 = AIN3
0100 = AIN4 (ADS1248 only)
0101 = AIN5 (ADS1248 only)
0110 = AIN6 (ADS1248 only)
0111 = AIN7 (ADS1248 only)
10x0 = IEXT1 (ADS1248 only)
10x1 = IEXT2 (ADS1248 only)
11xx = Disconnected (default)
Bits 3:0 I2DIR3:0
These bits select the output pin for the second current source DAC.
0000 = AIN0
0001 = AIN1
0010 = AIN2
0011 = AIN3
0100 = AIN4 (ADS1248 only)
0101 = AIN5 (ADS1248 only)
0110 = AIN6 (ADS1248 only)
0111 = AIN7 (ADS1248 only)
10x0 = IEXT1 (ADS1248 only)
10x1 = IEXT2 (ADS1248 only)
11xx = Disconnected (default)
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ADS1247 and ADS1248 DETAILED REGISTER DEFINITIONS (continued)
GPIOCFGGPIO Configuration Register. The GPIO and analog pins are shared as follows:
GPIO0 shared with REFP0
GPIO1 shared with REFN0
GPIO2 shared with AIN2
GPIO3 shared with AIN3
GPIO4 shared with AIN4 (ADS1248)
GPIO5 shared with AIN5 (ADS1248)
GPIO6 shared with AIN6 (ADS1248)
GPIO7 shared with AIN7 (ADS1248)
GPIOCFG - ADDRESS 0Ch RESET VALUE = 00h
DEVICE BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
ADS1248 IOCFG7 IOCFG6 IOCFG5 IOCFG4 IOCFG3 IOCFG2 IOCFG1 IOCFG0
ADS1247 0 0 0 0 IOCFG3 IOCFG2 IOCFG1 IOCFG0
Bits 7:0 IOCFG7:0
These bits enable the GPIO because the GPIO pins are shared with the analog pins. Note that the
ADS1248 uses all the IOCFG bits, whereas the ADS1247 uses only bits 3:0.
0 = The pin is used as an analog input (default)
1 = The pin is used as a GPIO pin
GPIODIRGPIO Direction Register
GPIODIR - ADDRESS 0Dh RESET VALUE = 00h
DEVICE BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
ADS1248 IODIR7 IODIR6 IODIR5 IODIR4 IODIR3 IODIR2 IODIR1 IODIR0
ADS1247 0 0 0 0 IODIR3 IODIR2 IODIR1 IODIR0
Bits 7:0 IODIR7:0
These bits control the direction of the GPIO when enabled by the IOCFG bits. Note that the
ADS1248 uses all the IODIR bits, whereas the ADS1247 uses only bits 3:0.
0 = The GPIO is an output (default)
1 = The GPIO is an input
GPIODATGPIO Data Register
GPIODAT - ADDRESS 0Eh RESET VALUE = 00h
DEVICE BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
ADS1248 IODAT7 IODAT6 IODAT5 IODAT4 IODAT3 IODAT2 IODAT1 IODAT0
ADS1247 0 0 0 0 IODAT3 IODAT2 IODAT1 IODAT0
Bits 7:0 IODAT7:0
If a GPIO pin is enabled in the GPIOCFG register and configured as an output in the GPIO
Direction register (GPIODIR), the value written to this register appears on the appropriate GPIO
pin. If a GPIO pin is configured as an input in GPIODIR, reading this register returns the value of
the digital I/O pins. Note that the ADS1248 uses all eight IODAT bits, while the ADS1247 uses only
bits 3:0.
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SPI COMMANDS
SPI COMMAND DEFINITIONS
The commands shown in Table 22 control the operation of the ADS1246/7/8. Some of the commands are
stand-alone commands (for example, RESET), whereas others require additional bytes (for example, WREG
requires command, count, and the data bytes).
Operands:
n = number of registers to be read or written (number of bytes 1)
r = register (0 to 15)
x = don't care
Table 22. SPI Commands
COMMAND TYPE COMMAND DESCRIPTION 1st COMMAND BYTE 2nd COMMAND BYTE
WAKEUP Exit sleep mode 0000 000x (00h, 01h)
SLEEP Enter sleep mode 0000 001x (02h, 03h)
System Control SYNC Synchronize the A/D conversion 0000 010x (04h, 05h) 0000-010x (04,05h)
RESET Reset to power-up values 0000 011x (06h, 07h)
NOP No operation 1111 1111 (FFh)
RDATA Read data once 0001 001x (12h, 13h)
Data Read RDATAC Read data continuously 0001 010x (14h, 15h)
SDATAC Stop reading data continuously 0001 011x (16h, 17h)
Read Register RREG Read from register rrrr 0010 rrrr (2xh) 0000_nnnn
Write Register WREG Write to register rrrr 0100 rrrr (4xh) 0000_nnnn
SYSOCAL System offset calibration 0110 0000 (60h)
Calibration SYSGCAL System gain calibration 0110 0001 (61h)
SELFOCAL Self offset calibration 0110 0010 (62h)
Restricted command.
Restricted 1111 0001 (F1h)
Should never be sent to device.
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DIN
SCLK
DRDY
Status
SLEEP
NormalMode SleepMode
FinishCurrentConversion
NormalMode
StartNewConversion
EighthSCLK
WAKEUP
0000001X 0000000X
Synchronization
OccursHere
2tOSC
SYNC
DIN
SCLK
0000010X 0000010X
SCLK
RESET
1 8
AnySPI
Command
DIN
0.6ms
ADS1246
ADS1247
ADS1248
SBAS426G AUGUST 2008REVISED OCTOBER 2011
www.ti.com
SYSTEM CONTROL COMMANDS
WAKEUPWake up from sleep mode that is set by the SLEEP command.
Use this command to awaken the device from sleep mode. After execution of the WAKEUP command, the
device wakes up on the rising edge of the eighth SCLK.
SLEEPSet the device to sleep mode; can only be awakened by the WAKEUP command.
This command places the part into a sleep (power-saving) mode. When the SLEEP command is issued, the
device completes the current conversion and then goes into sleep mode. Note that this command does not
automatically power-down the internal voltage reference; see the VREFCON bits in the MUX1 register for
each device for further details.
To exit sleep mode, issue the WAKEUP command. Single conversions can be performed by issuing a
WAKEUP command followed by a SLEEP command.
Both WAKEUP and SLEEP are the software command equivalents of using the START pin to control the device.
Figure 73. SLEEP and WAKEUP Commands Operation
SYNCSynchronize DRDY.
This command resets the ADC digital filter and starts a new conversion. The DRDY pin from multiple devices
connected to the same SPI bus can be synchronized by issuing a SYNC command to all of devices
simultaneously.
Figure 74. SYNC Command Operation
RESETReset the device to power-up state.
This command restores the registers to the respective power-up values. This command also resets the digital
filter. RESET is the command equivalent of using the RESET pin to reset the device. However, the RESET
command does not reset the SPI interface. If the RESET command is issued when the SPI interface is in the
wrong state, the device does not reset. The CS pin can be used to reset SPI interface first, and then a
RESET command can be issued to reset the device. The RESET command holds the registers and the
decimation filter in a reset state for 0.6ms when the system clock frequency is 4.096MHz, similar to the
hardware reset. Therefore, SPI communication can be only be started 0.6ms after the RESET command is
issued, as shown in Figure 75.
Figure 75. SPI Communication After an SPI Reset
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DIN
DOUT
DRDY
RDATAC
SCLK
24Bits
18124
NOP
0001010X
DIN
DRDY
0001011X
SDATAC
ADS1246
ADS1247
ADS1248
www.ti.com
SBAS426G AUGUST 2008REVISED OCTOBER 2011
DATA RETRIEVAL COMMANDS
RDATACRead data continuously.
The RDATAC command enables the automatic loading of a new conversion result into the output data
register. In this mode, the conversion result can be received once from the device after the DRDY signal
goes low by sending 24 SCLKs. It is not necessary to read back all the bits, as long as the number of bits
read out is a multiple of eight. The RDATAC command must be issued after DRDY goes low, and the
command takes effect on the next DRDY.
Be sure to complete data retrieval (conversion result or register read-back) before DRDY goes low, or the
resulting data will be corrupt. Successful register read operations in RDATAC mode require the knowledge of
when the next DRDY falling edge occurs.
Figure 76. Read Data Continuously
SDATACStop reading data continuously.
The SDATAC command terminates the RDATAC mode. Afterwards, the conversion result is not
automatically loaded into the output shift register when DRDY goes low, and register read operations can be
performed without interruption from new conversion results being loaded into the output shift register. Use
the RDATA command to retrieve conversion data. The SDATAC command takes effect after the next DRDY.
Figure 77. Stop Reading Data Continuously
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SCLK
DIN
DOUT
DRDY
MSB
0001001X
Mid-Byte LSB
1 8 1 24
NOP NOP NOP
RDATA
SCLK
DOUT
DIN
DRDY
NOPNOP NOP RDATA NOP NOP
1
D[23] D[14] D[1] D[1] D[0]D[17] D[16] D[15]D[22] D[23] D[22]
2 1 29 107 8 23 24 23 24
D[0]
ADS1246
ADS1247
ADS1248
SBAS426G AUGUST 2008REVISED OCTOBER 2011
www.ti.com
RDATARead data once.
The RDATA command loads the most recent conversion result into the output register. After issuing this
command, the conversion result can be read out by sending 24 SCLKs, as shown in Figure 78. This
command also works in RDATAC mode.
When performing multiple reads of the conversion result, the RDATA command can be sent when the last
eight bits of the conversion result are being shifted out during the course of the first read operation by taking
advantage of the duplex communication nature of the SPI interface, as shown in Figure 79.
Figure 78. Read Data Once
Figure 79. Using RDATA in Full-Duplex Mode
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DIN
DOUT VBIAS
00100001 00000001
1st
Command
Byte
2nd
Command
Byte
MUX1
DataByte DataByte
DIN 01000010 00000001 MUX2 SYS0
1st
Command
2nd
Command
Data
Byte
Data
Byte
ADS1246
ADS1247
ADS1248
www.ti.com
SBAS426G AUGUST 2008REVISED OCTOBER 2011
USER REGISTER READ AND WRITE COMMANDS
RREGRead from registers.
This command outputs the data from up to 16 registers, starting with the register address specified as part of
the instruction. The number of registers read is one plus the second byte. If the count exceeds the remaining
registers, the addresses wrap back to the beginning.
First Command Byte: 0010 rrrr, where rrrr is the address of the first register to read.
Second Command Byte: 0000 nnnn, where nnnn is the number of bytes to read 1.
It is not possible to use the full-duplex nature of the SPI interface when reading out the register data. For
example, a SYNC command cannot be issued when reading out the VBIAS and MUX1 data, as shown in
Figure 80. Any command sent during the readout of the register data is ignored. Thus, it is advisable to send
NOP through the DIN when reading out the register data.
Figure 80. Read from Register
WREGWrite to registers.
This command writes to the registers, starting with the register specified as part of the instruction. The
number of registers that are written is one plus the value of the second byte.
First Command Byte: 0100 rrrr, where rrrr is the address of the first register to be written.
Second Command Byte: 0000 nnnn, where nnnn is the number of bytes to be written 1.
Data Byte(s): data to be written to the registers.
Figure 81. Write to Register
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SCLK
DIN
DRDY
1 8
tCAL
Calibration
Command
Calibration
Starts
Calibration
Complete
ADS1246
ADS1247
ADS1248
SBAS426G AUGUST 2008REVISED OCTOBER 2011
www.ti.com
CALIBRATION COMMANDS
The ADS1246/7/8 provide system and offset calibration commands and a system gain calibration command.
SYSOCALOffset system calibration.
This command initiates a system offset calibration. For a system offset calibration, the input should be
externally set to zero. The OFC register is updated when this operation completes.
SYSGCALSystem gain calibration.
This command initiates the system gain calibration. For a system gain calibration, the input should be set to
full-scale. The FSC register is updated after this operation.
SELFOCALSelf offset calibration.
This command initiates a self-calibration for offset. The device internally shorts the inputs and performs the
calibration. The OFC register is updated after this operation.
Figure 82. Calibration Command
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DVDD
START
RESET
CS
DRDY
SCLK
3 00 00 00
Conversionresult
forchannel1
Power-upsequence ADCinitialsetup Multiplexerchangeischannel2 DataRetrievalfor
Channel2Conversion
Initialsetting:
AIN0isthepositivechannel,
AIN1isthenegativechannel,
internalreferenceselected,
PGAgain=32,
datarate=2kSPS,
VBIASisconnectedtothe
negativepinsAIN1andAIN3.
AIN2isthepositivechannel,
AIN3isthenegativechannel.
Conversionresult
forchannel2
01 02 03
WREG WREG
DIN
DOUT
tDRDY
0.513ms
for
MUX0
Write
NOP
16ms(1)
ADS1246
ADS1247
ADS1248
www.ti.com
SBAS426G AUGUST 2008REVISED OCTOBER 2011
APPLICATION INFORMATION
SPI COMMUNICATION EXAMPLES negative terminal of both sensors (that is, channels
AIN1 and AIN3). All these settings can be changed
This section contains several examples of SPI by performing a block write operation on the first four
communication with the ADS1246/7/8, including the registers of the device. After the DRDY pin goes low,
power-up sequence. the conversion result can be immediately retrieved by
sending in 16 SPI clock pulses because the device
Channel Multiplexing Example defaults to RDATAC mode. As the conversion result
is being retrieved, the active input channels can be
This first example applies only to the ADS1247 and switched to AIN2 and AIN3 by writing into the MUX0
ADS1248. It explains a method to use the device with register in a full-duplex manner, as shown in
two sensors connected to two different analog Figure 83. The write operation is completed with an
channels. Figure 83 shows the sequence of SPI additional eight SPI clock pulses. The time from the
operations performed on the device. After power-up, write operation into the MUX0 register to the next
216 system clocks are required before communication DRDY low transition is shown in Figure 83 and is
may be started. During the first 216 system clock 0.513ms in this case. After DRDY goes low, the
cycles, the devices are internally held in a reset state. conversion result can be retrieved and the active
In this example, one of the sensors is connected to channel can be switched as before.
channels AIN0 and AIN1 and the other sensor is
connected to channels AIN2 and AIN3. The ADC is
operated at a data rate of 2kSPS. The PGA gain is
set to 32 for both sensors. VBIAS is connected to the
(1) For fOSC = 4.096MHz.
Figure 83. SPI Communication Sequence for Channel Multiplexing
Copyright ©20082011, Texas Instruments Incorporated Submit Documentation Feedback 55
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DVDD
START
RESET
CS
DRDY
SCLK
00
Conversionresult
forchannel1
Power-upsequence ADCinitialsetup
ADCisputtosleep
afterasingleconversion.
Dataareretrievedwhen
ADCissleeping.
Initialsetting:
AIN0isthepositivechannel,
AIN1isthenegativechannel,
internalreferenceselected,
PGAgain=32,
datarate=2kSPS,
VBIASisconnectedtothe
negativepins,AIN1andAIN3.
ADCenters
power-saving
sleepmode
01 02 03
WREG
DIN
DOUT
tDRDY
(0.575ms)
NOP
16ms(1)
ADS1246
ADS1247
ADS1248
SBAS426G AUGUST 2008REVISED OCTOBER 2011
www.ti.com
Sleep Mode Example be changed by performing a block write operation on
the first four registers of the device. After performing
This second example deals with performing one the block write operation, the START pin can be
conversion after power-up and then entering into the taken low. The device enters the power-saving sleep
power-saving sleep mode. In this example, a sensor mode as soon as DRDY goes low 0.575ms after
is connected to input channels AIN0 and AIN1. writing into the SYS0 register. The conversion result
Commands to set up the devices must occur at least can be retrieved even after the device enters sleep
216 system clock cycles after powering up the mode by sending 16 SPI clock pulses.
devices. The ADC operates at a data rate of 2kSPS.
The PGA gain is set to 32 for both sensors. VBIAS is
connected to the negative terminal of both the
sensors (that is, channel AIN1). All these settings can
(1) For fOSC = 4.096MHz.
Figure 84. SPI Communication Sequence for Entering Sleep Mode After a Conversion
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RL
(1)
15W
RL
(1)
15W
RL
(1)
15W
RBIAS
(2)
833W
RCOMP
(2)
110W
IDAC1
1.5mA
REFP0
REFN0
IDAC2
1.5mA
Modulator MSP430
or
other
Microprocessor
ADS1247/48
PGA
Gain=128
VDD
+3.3V
+5V
RESET
AVDD
RTD
AVSS DGND GND
SCLK
AIN0
AIN1
DIN
DOUT/DRDY
CS
START
CLK
DVDD
IN
EN
V
NR
OUT
GND
TPS79333
0.1 Fm2.2 Fm
ADS1246
ADS1247
ADS1248
www.ti.com
SBAS426G AUGUST 2008REVISED OCTOBER 2011
Hardware-Compensated, Three-Wire RTD be equal to the resistance of the PT-100 sensor at
Measurement Example +25°C (approximately 110). The IDAC current is set
to 1.5mA. This setting results in a differential input
Figure 85 is an application circuit to measure swing of ±14.7mV at the inputs of the ADC. The PGA
temperatures in the range of 0°C to +50°C using a gain is set to 128. The full-scale input for the ADC is
PT-100 RTD and the ADS1247 or ADS1248 in a ±19.53mV. Fixing RBIAS at 833fixes the reference at
three-wire, hardware-compensated topology. The two 2.5V and the input common-mode at approximately
onboard matched current DACs of the ADS1247/8 2.7V, ensuring that the voltage at AIN0 is far away
are ideally suited for implementing the three-wire from the IDAC compliance voltage.
RTD topology. This circuit uses a ratiometric
approach, where the reference is derived from the The maximum number of noise-free output codes for
IDAC currents in order to achieve excellent noise this circuit in the 0°C to +50°C temperature range is
performance. The resistance of the PT-100 changes (2ENOB)(14.7mV)/19.53mV.
from 100at 0°C to 119.6at +50°C. The
compensating resistor (RCOMP) has been chosen to
(1) RTD line resistances.
(2) RBIAS and RCOMP should be as close to the ADC as possible.
Figure 85. Three-Wire RTD Application with Hardware Compensation
Copyright ©20082011, Texas Instruments Incorporated Submit Documentation Feedback 57
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ADS1246
ADS1247
ADS1248
SBAS426G AUGUST 2008REVISED OCTOBER 2011
www.ti.com
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision F (June 2011) to Revision G Page
Added Figure 46 ................................................................................................................................................................. 21
Added Figure 47 and Figure 48 .......................................................................................................................................... 22
Changes from Revision E (December, 2010) to Revision F Page
Added footnote to Full-scale input voltage specification in Electrical Characteristics table ................................................. 3
Added test condition for INL parameter of Electrical Characteristics ................................................................................... 3
Updated Figure 1 to show tCSPW timing ............................................................................................................................... 10
Added tCSPW to minimum specification in Timing Characteristics for Figure 1 .................................................................... 10
Corrected grid and axis values for Figure 9 ........................................................................................................................ 15
Corrected grid and axis values for Figure 10 ...................................................................................................................... 15
Updated Figure 51 .............................................................................................................................................................. 24
Added details to Bias Voltage Generation section ............................................................................................................. 29
Added details to Calibration section ................................................................................................................................... 31
Added Equation 8 to Calibration section ............................................................................................................................ 31
Added section to Calibration Commands ........................................................................................................................... 32
Corrected Table 16 ............................................................................................................................................................. 35
Added details to Digital Interface section ........................................................................................................................... 35
Added Restricted command space to Table 22 .................................................................................................................. 49
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PACKAGE OPTION ADDENDUM
www.ti.com 26-Oct-2011
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
ADS1246IPW ACTIVE TSSOP PW 16 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
ADS1246IPWR ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
ADS1247IPW ACTIVE TSSOP PW 20 70 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS1247IPWR ACTIVE TSSOP PW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS1248IPW ACTIVE TSSOP PW 28 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS1248IPWR ACTIVE TSSOP PW 28 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
PACKAGE OPTION ADDENDUM
www.ti.com 26-Oct-2011
Addendum-Page 2
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
ADS1246IPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
ADS1247IPWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
ADS1248IPWR TSSOP PW 28 2000 330.0 16.4 7.1 10.4 1.6 12.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
ADS1246IPWR TSSOP PW 16 2000 367.0 367.0 35.0
ADS1247IPWR TSSOP PW 20 2000 367.0 367.0 38.0
ADS1248IPWR TSSOP PW 28 2000 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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