¡ Semiconductor ML9261/62
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¡ Semiconductor
ML9261/62
60-Bit Vacuum Fluorescent Display Tube Grid/Anode Driver
GENERAL DESCRIPTION
The ML9261/62 is a monolithic IC designed for directly driving the grid and anode of the vacuum
fluorescent display (VFD) tube. The device contains a 60-bit shift register, a 60-bit register circuit,
and 60 VFD tube driving circuits on a single chip.
Display data is serially stored in the shift register at the rising edge of a clock pulse.
Setting the CL pin low allows all the VFD tube driving circuits to be driven low, which makes it
possible to set the display blanking.
Also, setting both of the CL and CHG pins high allows all the VFD tube driving circuits to be
driven high, which provides the easy testing of all lights after final assembly of a VFD tube panel.
FEATURES
• Logic Supply Voltage (VCC) : +3.3V±10% or +5.0V±10%
• Driver Supply Voltage (VHV): +60V
• Driver Output Current
IOHVH1 (Only one driver output : "H") : –40mA (VDISP=40V)
IOHVH2 (All the driver outputs : "H") : –120mA (VDISP=40V)
IOHVL:1mA
• Directly connected to VFD tube by using push-pull output (Pull-down resistors are not
needed)
• Data Transfer Speed: 4MHz
• Package :
70-pin plastic SSOP (SSOP70-P-500-0.80-K) (Product names : ML9261MB and ML9262MB)
E2C0043-19-74
This version: Jul. 1999
Preliminary
¡ Semiconductor ML9261/62
2/16
BLOCK DIAGRAM
VDISP
VDD
CL
CHG
LS
DIN
CLK
HVO 1
HVO 2HVO
HVO60
DOUT
L-GND
D-GND
CSI
PO-1
PO-2
60-Bit
Shift
Register
60-Bit
Register
P0-60
SO
D-60 O-60
D-2
D-1
O-2
O-1
RESET
RRC
¡ Semiconductor ML9261/62
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INPUT AND OUTPUT CONFIGURATION
¡ Semiconductor ML9261/62
4/16
PIN CONFIGURATION (TOP VIEW)
ML9261
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
HVO 25
HVO 24
HVO 23
HVO 22
HVO 21
HVO 20
HVO 19
HVO 18
HVO 17
HVO 16
HVO 15
HVO 14
HVO 13
HVO 12
HVO 11
HVO 10
HVO 26
HVO 27
HVO 28
HVO 29
HVO 30
HVO 31
HVO 32
HVO 33
HVO 34
HVO 35
HVO 36
HVO 37
HVO 38
HVO 39
HVO 40
HVO 41
17
18
19
20
54
53
52
51
HVO 9
HVO 8
HVO 7
HVO 6
HVO 42
HVO 43
HVO 44
HVO 45
21
22
23
24
25
26
50
49
48
47
46
45
HVO 5
HVO 4
HVO 3
HVO 2
HVO 1
VDISP
HVO 46
HVO 47
HVO 48
HVO 49
HVO 50
HVO 51
27
28
29
30
44
43
42
41
VDD
DIN
DOUT
CLK
HVO 52
HVO 53
HVO 54
HVO 55
31 40
LS HVO 56
32
33
34
35
39
38
37
36
CL
CHG
L-GND
D-GND
HVO 57
HVO 58
HVO 59
HVO 60
70-Pin Plastic SSOP
(SSOP70-P-500-0.80-K)
¡ Semiconductor ML9261/62
5/16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
D-GND
L-GND
CHG
CL
LS
CLK
DOUT
DIN
VDD
VDISP
HVO 1
HVO 2
HVO 3
HVO 4
HVO 5
HVO 6
HVO 60
HVO 59
HVO 58
HVO 57
HVO 56
HVO 55
HVO 54
HVO 53
HVO 52
HVO 51
HVO 50
HVO 49
HVO 48
HVO 47
HVO 46
HVO 45
17
18
19
20
54
53
52
51
HVO 7
HVO 8
HVO 9
HVO 10
HVO 44
HVO 43
HVO 42
HVO 41
21
22
23
24
25
26
50
49
48
47
46
45
HVO 11
HVO 12
HVO 13
HVO 14
HVO 15
HVO 16
HVO 40
HVO 39
HVO 38
HVO 37
HVO 36
HVO 35
27
28
29
30
44
43
42
41
HVO 17
HVO 18
HVO 19
HVO 20
HVO 34
HVO 33
HVO 32
HVO 31
31 40
HVO 21 HVO 30
32
33
34
35
39
38
37
36
HVO 22
HVO 23
HVO 24
HVO 25
HVO 29
HVO 28
HVO 27
HVO 26
70-Pin Plastic SSOP
(SSOP70-P-500-0.80-K)
PIN CONFIGURATION (TOP VIEW)
ML9262
¡ Semiconductor ML9261/62
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PIN DESCRIPTION
Symbol Description
CLK
Shift register clock input pin.
Shift register reads data from DIN while the CLK pin is low and the data in the shift register
is shifted from one stage to the next stage at the rising edge of the clock.
Type
I
Serial data input pin of the shift register.
Display data (positive logic) is input in the DIN pin in synchronization with clock.
DIN I
Serial data output pin of the shift register.
Data is output from the DOUT pin in synchronization with the CLK signal.
DOUT O
Latch strobe input pin.
The contents of the parallel outputs (PO1 to PO60) of the shift register are read at the rising
edge of LS (edge-triggered). When the CLK rises while LS is high, the parallel outputs
(PO1 to PO60) and latch outputs (O1 to O60) go low.
LS I
Clear input pin with a built-in pull-down resistor.
The CL pin is normally set high.
If the CL pin is high and the CHG pin is low, the driver outputs (HV01 to HV60) are in phase
with the corresponding register outputs (O1 to O60).
If the CL pin is high and the CHG pin is high, the driver outputs (HV01 to HV60) are high
irrespective of the states of the register outputs.
If the CL pin is set low, the driver outputs are driven low irrespective of the states of the
CHG pin and register outputs.
This allows display blanking to be set.
CL I
Input for testing (with a pull-down resistor).
The CL pin is normally set low.
If the CHG pin is low and the CL pin is high, the driver outputs (HV01 to HV60) are in phase
with the corresponding register outputs (O1 to O60).
If the CHG pin is low and the CL pin is low, the driver outputs (HV01 to HV60) are low
irrespective of the states of the register outputs.
If the CHG pin is set high, the driver outputs are driven high irrespective of the states of the
register outputs.
This provides the easy testing of all lights after final assembly.
CHG I
High voltage driver outputs for driving VFD tube.
If the CL pin is high and the CHG pin is low, the driver outputs are in phase with the
corresponding register outputs (O1 to O60).
The direct connection to the grid or anode of a VFD tube eliminates pull-down resistors.
VHO1-60 O
Power supply pin for driver circuits of VFD tube
V
DISP
Power supply pin for logic
V
DD
GND pin for driver circuits of a VFD tube.
Since the D-GND is not be connected to L-GND, connect this pin to the external L-GND.
D-GND
GND pin for the logic circuits.
Since the L-GND pin is not be connected to D-GND, connect this pin to the external D-GND.
L-GND
¡ Semiconductor ML9261/62
7/16
ABSOLUTE MAXIMUM RATINGS
Parameter Symbol Condition Rating Unit
Applicable to logic supply pin
Supply Voltage (1) V
DD
–0.3 to +6.5 V
Applicable to driver supply pin
Supply Voltage (2) V
DISP
–0.3 to +65 V
Applicable to all input pins
Input Voltage V
IN
–0.3 to V
DD
+0.3 V
Applicable to DOUT
Output Voltage V
O
–0.3 to V
DD
+0.3 V
Output Current I
O
–50 to 0.0 mAApplicable to HVO1 to 60
860
Power Dissipation P
D
mWTa £ 25°C
Package Thermal Resistance
R
j-a
145 °C/WTa > 25°C
Storage Temperature T
STG
–55 to +150 °C—
*1
*1, *2
*1
*1
Withstand Output Voltage
*1, *2 V
HVO
–0.3 to V
DISP
+0.3 VApplicable to HVO1 to 60
*3
Notes: *1 Supply Voltage with respect to L-GND and D-GND
*2 Permanent damage may be caused if the voltage is supplied over the rating value.
*3 Package Thermal Resistance (between junction and ambient)
The junction temperature (Tj) expressed by the equation indicated below should not
exceed 150°C.
Tj=P ¥ Rj–a+Ta (P: Maximum power consumption)
¡ Semiconductor ML9261/62
8/16
RECOMMENDED OPERATING CONDITIONS-1
Unit Power Supply: 5.0V (Typ.)
Parameter Max
Power Supply (1) V
Power Supply (2)
"H" Input Voltage
"L" Input Voltage
Symbol Condition
—
—
Applicable to all inputs
Applicable to all inputs
Typ. Unit
V
V
V
V
DD
V
DISP
V
IH
V
IL
5.0
—
—
—
5.5
60
—
0.3V
DD
Driver Output Current
CLK Frequency
Operating Temperature °C
MHz
mA
mA
+85
4.0
–40
–120
—
—
—
—
T
OP
f
CLK
I
OHVH1
I
OHVH2
All outputs are ON.
Only 1 output is ON.
—
—
Min
4.5
20
0.7V
DD
—
–40
—
—
—
RECOMMENDED OPERATING CONDITIONS-2
Unit Power Supply: 3.3V (Typ.)
Parameter Max
Power Supply (1) V
Power Supply (2)
"H" Input Voltage
"L" Input Voltage
Symbol Condition
—
—
Applicable to all inputs
Applicable to all inputs
Typ. Unit
V
V
V
V
DD
V
DISP
V
IH
V
IL
3.3
—
—
—
3.6
60
—
0.2V
DD
Driver Output Current
CLK Frequency
Operating Temperature °C
MHz
mA
mA
+85
4.0
–40
–120
—
—
—
—
T
OP
f
CLK
I
OHVH1
I
OHVH2
All outputs are ON.
Only 1 output is ON.
—
—
Min
3.0
20
0.8V
DD
—
–40
—
—
—
¡ Semiconductor ML9261/62
9/16
ELECTRICAL CHARACTERISTICS
DC Characteristics-1
Parameter Max
"H" Input Voltege V
"L" Input Voltage
"H" Input Current
"L" Input Current
Applicable pin Condition
—
—
V
DD
=V
IN
=5.5V
V
DD
=5.5V,V
IN
=0V
Typ. Unit
V
mA
mA
All inputs
All inputs
DIN, CLK, LS
All inputs
—
—
—
—
—
0.3V
DD
+1.0
+1.0
Input Capacitance
Supply Current
(Design Goal) mA
mA
pF
10.0
10.0
—
—
—
15
V
DD
V
DD
All inputs Ta=25°C
All inputs: "H"
All inputs: "L"
Min
0.7V
DD
—
–1.0
–1.0
—
—
—
Symbol
V
IH
V
IL
I
IH1
I
IL
I
DD2
I
DD1
C
IN
V
DD
=V
IN
=5.5V mA
CL, CHG —805.0
I
IH2
"H" Output Voltage I
OH
=–0.1mA V
DOUT ——V
DD
–1
V
OH1
I
OH
=–40mA V
HVO1 to 60 ——V
DISP
–4
V
OH2
"L" Output Voltage I
OL
=0.1mA V
DOUT — 1.1—
V
OL1
I
OL
=1mA V
HVO1 to 60 — 3.0—
V
OL2
mA
mA
10.0
10.0
—
—
V
DISP
V
DISP
All inputs: "H"
All inputs: "L"
—
—
I
DISP2
I
DISP1
No load
(V
DD
=4.5 to 5.5V, V
DISP
=40V, Ta=–40 to +85°C)
DC Characteristics-2
Parameter Max
"H" Input Voltege V
"L" Input Voltage
"H" Input Current
"L" Input Current
Applicable pin Condition
—
—
V
DD
=V
IN
=3.3V
V
DD
=3.3V,V
IN
=0V
Typ. Unit
V
mA
mA
All inputs
All inputs
DIN, CLK, LS
All inputs
—
—
—
—
—
0.2V
DD
+1.0
+1.0
Input Capacitance
Supply Current
(Design Goal) mA
mA
pF
10.0
10.0
—
—
—
15
V
DD
V
DD
All inputs Ta=25°C
All inputs: "H"
All inputs: "L"
Min
0.8V
DD
—
–1.0
–1.0
—
—
—
Symbol
V
IH
V
IL
I
IH1
I
IL
I
DD2
I
DD1
C
IN
V
DD
=V
IN
=3.3V mA
CL, CHG —502.0
I
IH2
"H" Output Voltage I
OH
=–0.1mA V
DOUT ——V
DD
–1
V
OH1
I
OH
=–40mA V
HVO1 to 60 ——V
DISP
–4
V
OH2
"L" Output Voltage I
OL
=0.1mA V
DOUT — 1.1—
V
OL1
I
OL
=1mA V
HVO1 to 60 — 3.0—
V
OL2
mA
mA
10.0
10.0
—
—
V
DISP
V
DISP
All inputs: "H"
All inputs: "L"
—
—
I
DISP2
I
DISP1
No load
(V
DD
=3.0 to 3.6V, V
DISP
=40V, Ta=–40 to +85°C)
¡ Semiconductor ML9261/62
10/16
—
CLK-LS Setup Time ns
LS-CLK Setup Time
LS-CHG Setup Time
LS Pulse Width
50 ns
ns
ns
ns
50
50
50
80
—
—
—
—
CHG Pulse Width
Driver Output Slew Rate
ms
ms
ms
5.0
5.0
—
—
—
10
t
H
(CLK-D)
t
SU
(CLK-LS)
t
SU
(LS-CLK)
t
SU
(LS-CHG)
t
W
(LS)
t
THL
t
TLH
t
W
(CHG)
ns50 —
t
SU
(LS-CL)
CL Pulse Width ms10 —
t
W
(CL)
ns—50
t
PD
, t
PRD
Driver Output Delay Time ms— 1.0
t
DLH
ms— 1.0
t
DHL
(V
DD
=4.5 to 5.5V, V
DISP
=40V, Ta=–40 to +85°C)
DIN Hold Time
LS-CL Setup Time
DOUT Delay time
Max.Min. UnitSymbol
Parameter Condition
150
DIN Setup Time ns
80 ns
50 —
t
W
(CLK)
t
SU
(D-CLK)
CLK Pulse Width
ns50 —t
SU
(L-CLK)
During normal operation
At display data reset
CLK-LS Hold Time ns50 —
t
H
(CLK-L) At display data reset
Load: 30pF
ms— 1.0
t
DRHL
Load: 2.0kW resistance in
parallel with 20pF capacitance
Load: 2.0kW resistance in
parallel with 20pF capacitance
AC Characteristics-1
AC Characteristics-2
—
CLK-LS Setup Time ns
LS-CLK Setup Time
LS-CHG Setup Time
LS Pulse Width
50 ns
ns
ns
ns
50
50
50
80
—
—
—
—
CHG Pulse Width
Driver Output Slew Rate
ms
ms
ms
5.0
5.0
—
—
—
10
t
H
(CLK-D)
t
SU
(CLK-LS)
t
SU
(LS-CLK)
t
SU
(LS-CHG)
t
W
(LS)
t
THL
t
TLH
t
W
(CHG)
ns50 —
t
SU
(LS-CL)
CL Pulse Width ms10 —
t
W
(CL)
ns—50
t
PD
, t
PRD
Driver Output Delay Time ms— 3.0
t
DLH
ms— 3.0
t
DHL
(V
DD
=3.0 to 3.6V, V
DISP
=40V, Ta=–40 to +85°C)
DIN Hold Time
LS-CL Setup Time
DOUT Delay time
Max.Min. UnitSymbol
Parameter Condition
—50 nst
SU
(D-CLK)
DIN Setup Time
15080 nst
W
(CLK)
CLK Pulse Width
During normal operation
ns50 —t
SU
(L-CLK) At display data reset
CLK-LS ns50 —
t
H
(CLK-L) At display data reset
Load: 30pF
ms— 3.0
t
DRHL
Load: 2.0kW resistance in
parallel with 20pF capacitance
Load: 2.0kW resistance in
parallel with 20pF capacitance
¡ Semiconductor ML9261/62
11/16
TIMING DIAGRAM
Normal Display Operation
CLK
DIN
LS
HVO (OTHERS)
CL
HVO (1, 2, 59, 60)
CHG
DOUT
T1/2 T3/4 T59/60 T1/2 T3/4
t
SU(D-CLK)
t
PD
t
SU(CLK-LS)
t
SU(LS-CLK)
t
SU(LS-CHG)
t
W(CHG)
t
SU(LS-CL)
t
W(CL)
t
W(CL)
t
DLH
t
DLH
t
DHL
t
DHL
t
TLH
t
TLH
t
THL
t
THL
t
H(CLK-D)
t
W(CHG)
1/f
CLK
t
W(CLK)
t
PD
t
W(LS)
¡ Semiconductor ML9261/62
12/16
Display Data Reset Operation
CLK
DIN
LS
HVO (OTHERS)
CL
HVO (1, 2, 59, 60)
CHG
DOUT
T1/2 T3/4 T59/60 T1/2
t
PRD
t
DRHL
t
SU(L-CLK)
t
H(CLK-L)
¡ Semiconductor ML9261/62
13/16
FUNCTIONAL DESCRIPTION
Display Data Reset
When the power is turned on, the shift register outputs (PO1 to PO60) and register outputs (O1
to O60) are indeterminate. Consequently the display of a VFD tube may flickers because
unnecessary driver outputs go high. To prevent such flicker, it is required to perform the
following operations.
1. Turn on the logic power supply while the CL input is kept low.
2. Set the LS input high.
3. Switch the CLK input from a low level to a high level at least once.
By performing the above operations, the shift register outputs (PO1 to PO60) and register outputs
(O1 to O60) all are set low.
4. Enter display data.
5. Set the CL input high.
Data Transfer
Write display data by using a serial transfer.
Serial data is input in the shift register at the rising edge of a CLK input pulse.
When the LS input rises, display data is written in the latch.
Driver Output Control
1. To turn on or off driver outputs by using display data transfered into the shift register, set the
CL input high and set the CHG input low.
2. To set all the driver outputs low, set the CL input low.
3. To set all the driver outputs high, set the CL input and CHG input high at a time.
¡ Semiconductor ML9261/62
14/16
Function Table
Shift register
Register
CLK
X
X
X
Shift Register Parallel Out Latch Output
POm Om
HH
LL
X No Change
LL
Input
LS
H
X: Don't Care
,
m: 1 to 60
Driver output
Latch Output Output
Om HVOm
HH
LL
XH
XL
Input
CL
H
H
H
L
CHG
L
L
H
X
CLK
X
X
X
X
LS
X
X
X
X
LL
XX H
X: Don't Care, m: 1 to 60
CLK PO1DIN
H H PO1n
PO2
L
X
L
PO1n
PO2n
PO2n
LS
L
L
L
XLLH
Input
PO59
PO58n
PO58n
PO59n
L
PO60
PO59n
PO59n
PO60n
L
DOUT
PO59n
PO59n
PO60n
L
OutputShift Register Parallel Out
X: Don't Care
PO1n to PO59n: PO1 to PO59 data
j
ust before CLOCK rises.
¡ Semiconductor ML9261/62
15/16
Test circuit
DOUT
HVO1
HVO1
HVO1
20pF
1.0kW
V
DISP
DIN CLK LS CL CHG
V
DD
D-GNDL-GND
20pF
20pF
1.0kW
1.0kW
30pF
¡ Semiconductor ML9261/62
16/16
(Unit : mm)
PACKAGE DIMENSIONS
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
SSOP70-P-500-0.80-K
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
2.15 TYP.
Mirror finish
NOTICE
1. The information contained herein can change without notice owing to product and/or
technical improvements. Before using the product, please make sure that the information
being referred to is up-to-date.
2. The outline of action and examples for application circuits described herein have been
chosen as an explanation for the standard action and performance of the product. When
planning to use the product, please ensure that the external conditions are reflected in the
actual circuit, assembly, and program designs.
3. When designing your product, please use our product below the specified maximum
ratings and within the specified operating ranges including, but not limited to, operating
voltage, power dissipation, and operating temperature.
4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or
unexpected operation resulting from misuse, neglect, improper installation, repair, alteration
or accident, improper handling, or unusual physical or electrical stress including, but not
limited to, exposure to parameters beyond the specified maximum ratings or operation
outside the specified operating range.
5. Neither indemnity against nor license of a third party’s industrial and intellectual property
right, etc. is granted by us in connection with the use of the product and/or the information
and drawings contained herein. No responsibility is assumed by us for any infringement
of a third party’s right which may result from the use thereof.
6. The products listed in this document are intended for use in general electronics equipment
for commercial applications (e.g., office automation, communication equipment,
measurement equipment, consumer electronics, etc.). These products are not authorized
for use in any system or application that requires special or enhanced quality and reliability
characteristics nor in any system or application where the failure of such system or
application may result in the loss or damage of property, or death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety
devices, aerospace equipment, nuclear power control, medical equipment, and life-support
systems.
7. Certain products in this document may need government approval before they can be
exported to particular countries. The purchaser assumes the responsibility of determining
the legality of export of these products and will take appropriate and necessary steps at their
own expense for these.
8. No part of the contents contained herein may be reprinted or reproduced without our prior
permission.
9. MS-DOS is a registered trademark of Microsoft Corporation.
Copyright 1999 Oki Electric Industry Co., Ltd.
Printed in Japan
E2Y0002-29-62
