MAX19792
500MHz to 4000MHz Dual Analog Voltage Variable
Attenuator with On-Chip 10-Bit SPI-Controlled DAC
19-6382; Rev 2; 5/15
Ordering Information appears at end of data sheet.
For related parts and recommended products to use with this part,
refer to www.maximintegrated.com/MAX19792.related.
EVALUATION KIT AVAILABLE
General Description
The MAX19792 dual general-purpose analog voltage
variable attenuator (VVA) is designed to interface with
50I systems operating in the 500MHz to 4000MHz
frequency range. The device includes a patented control
circuit that provides 23.2dB of attenuation range (per
attenuator) with a typical linear control slope of 8.5dB/V.
Both attenuators share a common analog control and
can be cascaded together to yield 46.4dB of total attenu-
ation range with a typical combined linear control slope
of 17dB/V (5V operation).
Alternatively, the on-chip 4-wire SPI-controlled 10-bit
DAC can be used to control both attenuators. In addi-
tion, a step-up/down feature allows user-programmable
attenuator stepping through command pulses without
reprogramming the SPI interface.
The MAX19792 is a monolithic device designed using
one of Maxim’s proprietary SiGe BiCMOS processes. The
part operates from a single +5V supply or alternatively
from a single +3.3V supply. It is available in a compact
36-pin TQFN package (6mm x 6mm x 0.8mm) with an
exposed pad. Electrical performance is guaranteed over
the -40NC to +100NC extended temperature range.
Applications
Broadband System Applications, Including
Wireless Infrastructure Digital and
Spread-Spectrum Communication Systems
WCDMA/LTE, TD-SCDMA/TD-LTE, WiMAX®,
cdma2000M, GSM/EDGE, and
MMDS Base Stations
VSAT/Satellite Modems
Microwave Point-to-Point Systems
Lineup Gain Trim
Temperature-Compensation Circuits
Automatic Level Control (ALC)
Transmitter Gain Control
Receiver Gain Control
General Test Equipment
Features
S Wideband Coverage
500MHz to 4000MHz RF Frequency Range
S High Linearity
Greater Than +37.9dBm IIP3 Over the Full
Attenuation Range
+22.7dBm Input P1dB
S Integrates Two Analog Attenuators in One
Monolithic Device
S Two Convenient Control Options
Single Analog Voltage
On-Chip SPI-Controlled 10-Bit DAC
S Step-Up /Down Pulse Command Inputs
S Flexible Attenuation Control Ranges
23.2dB (Per Attenuator)
46.4dB (Both Attenuators Cascaded)
S Linear dB/V Analog Control Response Curve
Simplifies Automatic Leveling Control and
Gain-Trim Algorithms
S Excellent Attenuation Flatness Over Wide
Frequency Ranges and Attenuation Settings
S On-Chip Comparator (for Successive
Approximation Measurement of Attenuator
Control Voltage)
S Low 13mA Supply Current
S Single 5V or 3.3V Supply Voltage
S Pin-Compatible with the MAX19791 and MAX19793
S Pin-Compatible with the MAX19794 with Addition
of Two Shunt Capacitors
S PCB-Compatible with the MAX19790
S Lead(Pb)-Free Package
WiMAX® is a registered certification mark and registered service mark of WiMAX Forum.
cdma2000 is a registered trademark of Telecommunications Industry Association.
For pricing, delivery, and ordering information, please contact Maxim Direct
at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com.
2Maxim Integrated
MAX19792
500MHz to 4000MHz Dual Analog Voltage Variable
Attenuator with On-Chip 10-Bit SPI-Controlled DAC
VCC ....................................................................... -0.3V to +5.5V
REF_IN ..............................-0.3V to Minimum (VCC + 0.3V, 3.6V)
REF_SEL, DAC_LOGIC, MODE, DWN, UP,
DIN, CLK, CS ............... -0.3V to Minimum (VCC + 0.3V, 3.6V)
COMP_OUT, DOUT ..............................................-0.3V to +3.6V
IN_A, OUT_A, IN_B, OUT_B .......................-0.3V to VCC + 0.3V
CTRL (except for test mode) .......................-0.3V to VCC + 0.3V
Maximum CTRL Pin Load Current
(CTRL configured as an output) ....................................0.3mA
RF Input Power at IN_A, IN_B, OUT_A, OUT_B ........... +20dBm
Continuous Power Dissipation (Note 1) ..............................2.8W
Operating Case Temperature Range (Note 2)…-40NC to +100NC
Maximum Junction Temperature .....................................+150NC
Storage Temperature Range ............................ -65NC to +150NC
Lead Temperature (soldering, 10s) ................................+300NC
Soldering Temperature (reflow) ......................................+260NC
ABSOLUTE MAXIMUM RATINGS
Note 3: Junction temperature TJ = TA + (BJA x VCC x ICC). This formula can be used when the ambient temperature of the PCB is
known. The junction temperature must not exceed +150NC.
Note 4: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
Note 1: Based on junction temperature TJ = TC + (BJC x VCC x ICC). This formula can be used when the temperature of the
exposed pad is known while the device is soldered down to a PCB. See the Applications Information section for details.
The junction temperature must not exceed +150NC.
Note 2: TC is the temperature on the exposed pad of the package. TA is the ambient temperature of the device and PCB.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional opera-
tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
TQFN
Junction-to-Ambient Thermal Resistance (qJA)
(Notes 3, 4) ............................................................... +36NC/W
Junction-to-Case Thermal Resistance (qJC)
(Notes 1, 4) ............................................................... +10NC/W
PACKAGE THERMAL CHARACTERISTICS
3.3V DC ELECTRICAL CHARACTERISTICS
(VCC = 3.15V to 3.45V, VCTRL = 1V, VDAC_LOGIC = 0V, RDBK_EN(D9, REG3) = logic 0, no RF signals applied, all input and output
ports terminated with 50I through DC blocks, TC = -40NC to +100NC, unless otherwise noted. Typical values are at VCC = 3.3V,
VCTRL = 1V, VDAC_LOGIC = 0V, RDBK_EN(D9, REG3) = logic 0, TC = +25NC, unless otherwise noted.) (Note 5)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Supply Voltage VCC 3.15 3.3 3.45 V
Supply Current ICC 9.5 14 mA
Control Voltage Range VCTRL 1 2.5 V
CTRL Input Resistance RCTRL 1.0 MI
Input Current Logic-High IIH -1 +1 µA
Input Current Logic-Low IIL -1 +1 µA
REF_IN Voltage 1.4 V
REF_IN Input Resistance 1.0 MI
DAC Number of Bits Monotonic 10 Bits
Input Voltage Logic-High VIH 2 V
Input Voltage Logic-Low VIL 0.8 V
COMP_OUT Logic-High RDBK_EN(D9, REG3) = logic 1,
RLOAD = 47kI3.3 V
COMP_OUT Logic-Low RDBK_EN(D9, REG3) = logic 1,
RLOAD = 47kI0 V
3Maxim Integrated
MAX19792
500MHz to 4000MHz Dual Analog Voltage Variable
Attenuator with On-Chip 10-Bit SPI-Controlled DAC
RECOMMENDED AC OPERATING CONDITIONS
5V DC ELECTRICAL CHARACTERISTICS
(VCC = 4.75V to 5.25V, VCTRL = 1V, VDAC_LOGIC = 0V, RDBK_EN(D9, REG3) = logic 0, no RF signals applied, all input and output
ports terminated with 50I through DC blocks, TC = -40NC to +100NC, unless otherwise noted. Typical values are at VCC = 5V, VCTRL
= 1V, V
DAC_LOGIC
= 0V, RDBK_EN(D9, REG3) = logic 0, TC = +25NC, unless otherwise noted.) (Note 5)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Supply Voltage VCC 4.75 5.0 5.25 V
Supply Current ICC 13 20 mA
CTRL Voltage Range VCTRL 1 4 V
CTRL Input Resistance RCTRL 124 kI
Input Current Logic-High IIH -1 +1 µA
Input Current Logic-Low IIL -1 +1 µA
REF_IN Voltage Range 1.4 V
REF_IN Input Resistance 1.0 MI
DAC Number of Bits Monotonic 10 Bits
Input Voltage Logic-High VIH 2 V
Input Voltage Logic-Low VIL 0.8 V
COMP_OUT Logic-High RDBK_EN(D9, REG3) = logic 1,
RLOAD = 47kI3.3 V
COMP_OUT Logic-Low RDBK_EN(D9, REG3) = logic 1,
RLOAD = 47kI0 V
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
RF Frequency Range fRF (Note 6) 500 4000 MHz
RF Port Input Power PRF Continuous operation 15 dBm
4Maxim Integrated
MAX19792
500MHz to 4000MHz Dual Analog Voltage Variable
Attenuator with On-Chip 10-Bit SPI-Controlled DAC
3.3V AC ELECTRICAL CHARACTERISTICS
(Typical Application Circuit, one attenuator, VCC = 3.15V to 3.45V, RF ports are driven from 50I sources and loaded into 50I, input
PRF = 0dBm, fRF = 950MHz to 2150MHz, VCTRL = 1V to 2.5V, VDAC_LOGIC = 0V,
RDBK_EN(D9, REG3) = logic 0,
TC = -40NC to
+100NC. Typical values are for TC = +25NC, VCC = 3.3V, input PRF = 0dBm, fRF = 1500MHz, VCTRL = 1V,
V
DAC_LOGIC
= 0V, RDBK_EN
(D9, REG3) = logic 0,
unless otherwise noted.) (Notes 5, 7)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Insertion Loss IL One attenuator 2.8 dB
Two attenuators 5.3
Loss Variation Over
Temperature TC = -40NC to +100NC0.21 dB
Input P1dB IP1dB 17.3 dBm
Minimum Input Second-Order
Intercept Point Over Full
Attenuation Range (Note 8)
IIP2
One attenuator, fRF1 +fRF2 term,
fRF1 -fRF2 = 1MHz, VCTRL = 1V to 2.5V,
PRF = 0dBm/tone applied to attenuator
input
55
dBm
Two attenuators, fRF1 + fRF2 term,
fRF1 - fRF2 = 1MHz, VCTRL = 1V to 2.5V,
PRF = 0dBm/tone applied to attenuator
input
52
Minimum Input Third-Order
Intercept Point Over Full
Attenuation Range (Note 8)
IIP3
One attenuator, VCTRL = 1V to 2.5V,
fRF1 - fRF2 = 1MHz, PRF = 0dBm/tone
applied to attenuator input
34.8
dBm
Two attenuators, VCTRL = 1V to 2.0V,
fRF1 - fRF2 = 1MHz, PRF = 0dBm/tone
applied to attenuator input
34.1
Second Harmonic 62.7 dBc
Third Harmonic 90.6 dBc
Attenuation Control Range One attenuator, VCTRL = 1V to 2.5V 23.4 dB
Two attenuators, VCTRL = 1V to 2.5V 46.8
Average Attenuation-Control
Slope VCTRL = 1.4V to 2.3V 22 dB/V
Maximum Attenuation-Control
Slope VCTRL = 1V to 2.5V 40 dB/V
S21 Attenuation Deviation from
a Straight Line VCTRL = 1.4V to 2.1V ±0.4 dB
5Maxim Integrated
MAX19792
500MHz to 4000MHz Dual Analog Voltage Variable
Attenuator with On-Chip 10-Bit SPI-Controlled DAC
5V AC ELECTRICAL CHARACTERISTICS
(Typical Application Circuit, one attenuator, VCC = 4.75V to 5.25V, RF ports are driven from 50I sources and loaded into 50I,
input PRF = 0dBm, fRF = 950MHz to 2150MHz, VCTRL = 1V to 4V, VDAC_LOGIC = 0V,
RDBK_EN(D9, REG3) = logic 0,
TC = -40NC to
+100NC. Typical values are for TC = +25NC, VCC = 5V, input PRF = 0dBm, fRF = 1500MHz, VCTRL = 1V,
V
DAC_LOGIC
= 0V, RDBK_EN
(D9, REG3) = logic 0,
unless otherwise noted.) (Notes 5, 7)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT
Insertion Loss IL One attenuator 2.64 dB
Two attenuators 5.2
Loss Variation Over
Temperature TC = -40NC to +100NC0.22 dB
Input P1dB IP1dB 22.7 dBm
Minimum Input Second-Order
Intercept Point Over Full
Attenuation Range (Note 8)
IIP2
One attenuator, fRF1 + fRF2 term,
fRF1 - fRF2 = 1MHz, VCTRL = 1V to 4V,
PRF = 0dBm/tone applied to attenuator
input
63.4
dBm
Two attenuators, fRF1 + fRF2 term,
fRF1 - fRF2 = 1MHz, VCTRL = 1V to 4V,
PRF = 0dBm/tone applied to attenuator
input
59.4
Minimum Input Third-Order
Intercept Point Over Full
Attenuation Range (Note 8)
IIP3
One attenuator, VCTRL from 1V to 4V,
fRF1 - fRF2 = 1MHz, PRF = 0dBm/tone
applied to attenuator input
37.9
dBm
Two attenuators, VCTRL from 1V to 3.5V,
fRF1 - fRF2 = 1MHz, PRF = 0dBm/tone
applied to attenuator input
34.6
Second Harmonic 73.4 dBc
Third Harmonic 101.7 dBc
Attenuation Control Range One attenuator, VCTRL = 1V to 4V 23.2 dB
Two attenuators, VCTRL = 1V to 4V 46.4 dB
Average Attenuation-Control
Slope VCTRL = 1.4V to 3.1V 8.5 dB/V
Maximum Attenuation-Control
Slope VCTRL = 1V to 3.5V 35 dB/V
Attenuation Flatness Over any
125MHz Band VCTRL = 1V to 3.1V 0.2 dB
6Maxim Integrated
MAX19792
500MHz to 4000MHz Dual Analog Voltage Variable
Attenuator with On-Chip 10-Bit SPI-Controlled DAC
5V AC ELECTRICAL CHARACTERISTICS (continued)
(Typical Application Circuit, one attenuator, VCC = 4.75V to 5.25V, RF ports are driven from 50I sources and loaded into 50I,
input PRF = 0dBm, fRF = 950MHz to 2150MHz, VCTRL = 1V to 4V, VDAC_LOGIC = 0V,
RDBK_EN(D9, REG3) = logic 0,
TC = -40NC to
+100NC. Typical values are for TC = +25NC, VCC = 5V, input PRF = 0dBm, fRF = 1500MHz, VCTRL = 1V,
V
DAC_LOGIC
= 0V, RDBK_EN
(D9, REG3) = logic 0,
unless otherwise noted.) (Notes 5, 7)
Note 5: Production tested at TC = +100NC. All other temperatures are guaranteed by design and characterization.
Note 6: Recommended functional range. Not production tested. Operation outside this range is possible, but with degraded
performance of some parameters.
Note 7: All limits include external component losses, connectors and PCB traces. Output measurements taken at the RF port of
the Typical Application Circuit.
Note 8: fRF1 = 1501MHz, fRF2 = 1500MHz, PRF = 0dBm/tone applied to attenuator input.
Note 9: Switching time measured from 50% of the CTRL signal to when the RF output settles to Q1dB (R3 = 0I).
Note 10: Switching time measured from when CS is asserted to when the RF output settles to Q1dB.
Note 11: Switching time measured from when MODE is asserted to when the RF output settles to Q1dB.
Note 12: Typical minimum time for proper SPI operation.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT
CTRL Switching Time (Note 9) 15dB to 0dB range 360 ns
0dB to 15dB range 780
CS Switching Time (Note 10) 15dB to 0dB range 700 ns
0dB to 15dB range 2200
MODE Switching Time (Note
11)
15dB to 0dB range (MODE 1 to 0) 700 ns
0dB to 15dB range (MODE 0 to 1) 2200
Input Return Loss 21 dB
Output Return Loss 31 dB
Group Delay Input/output 50I lines deembedded 190 ps
Group Delay Flatness Over Any
125MHz Band Peak to peak 25 ps
Group Delay Change VCTRL = 1V to 4V -85 ps
Insertion Phase Change vs.
Attenuation Control VCTRL = 1V to 4V 17.8 Degrees
S21 Attenuation Deviation from
a Straight Line VCTRL = 1.4V to 3.1V ±0.4 dB
SERIAL PERIPHERAL INTERFACE (SPI)
Maximum Clock Speed 20 MHz
Data-to-Clock Setup Time tCS (Note 12) 2 ns
Data-to-Clock Hold Time tCH (Note 12) 2.5 ns
CS-to-CLK Setup Time tEWS (Note 12) 3 ns
CS Positive Pulse Width tEW (Note 12) 7 ns
Clock Pulse Width tCW (Note 12) 5 ns
7Maxim Integrated
MAX19792
500MHz to 4000MHz Dual Analog Voltage Variable
Attenuator with On-Chip 10-Bit SPI-Controlled DAC
Typical Operating Characteristics
(Typical Application Circuit, VCC = 5V, configured for single attenuator, RF ports are driven from 50I sources and loaded into 50I,
VDAC_LOGIC = 0V, RDBK_EN = Logic 0, VCTRL = 1V, PIN = 0dBm, fRF = 1500MHz, TC = 25°C, unless otherwise noted.).
S21 vs. RF FREQUENCY
OVER CODE SETTINGS
MAX19792 toc04
RF FREQUENCY (MHz)
S21 (dB)
3300260019001200
-20
-10
0
-30
500 4000
S21 vs. DAC CODE
MAX19792 toc07
DAC CODE
S21(dB)
768512256
-25
-20
-15
-10
-5
0
-30
0 1024
2250MHz
950MHz
1500MHz
3500MHz
S21 vs. DAC CODE
MAX19792 toc08
DAC CODE
S21(dB)
768512256
-25
-20
-15
-10
-5
0
-30
0 1024
TC = -40°C, +25°C, +85°C
fRF = 950MHz
INPUT MATCH vs. RF FREQUENCY
OVER CODE SETTINGS
MAX19792 toc02
RF FREQUENCY (MHz)
S11 (dB)
3300260019001200
-20
-10
0
-30
500 4000
SUPPLY CURRENT vs. VCC
MAX19792 toc01
VCC (V)
SUPPLY CURRENT (mA)
5.1255.0004.875
TC = +25°C
TC = +85°C
11
12
13
14
15
10
4.750 5.250
TC = -40°C
INPUT MATCH vs. DAC CODE
MAX19792 toc05
DAC CODE
S11(dB)
768512256
-25
-20
-15
-10
-5
0
-30
0 1024
3500MHz
2250MHz
950MHz
1500MHz
OUTPUT MATCH vs. RF FREQUENCY
OVER CODE SETTINGS
MAX19792 toc03
RF FREQUENCY (MHz)
S22 (dB)
3300260019001200
-40
-30
-20
-10
0
-50
500 4000
OUTPUT MATCH vs. DAC CODE
MAX19792 toc06
DAC CODE
S22(dB)
768512256
3500MHz
-40
-30
-20
-10
0
-50
0 1024
1500MHz
950MHz
2250MHz
8Maxim Integrated
MAX19792
500MHz to 4000MHz Dual Analog Voltage Variable
Attenuator with On-Chip 10-Bit SPI-Controlled DAC
Typical Operating Characteristics (continued)
(Typical Application Circuit, VCC = 5V, configured for single attenuator, RF ports are driven from 50I sources and loaded into 50I,
VDAC_LOGIC = 0V, RDBK_EN = Logic 0, VCTRL = 1V, PIN = 0dBm, fRF = 1500MHz, TC = 25°C, unless otherwise noted.).
S21 PHASE CHANGE vs. DAC CODE
MAX19792 toc09
DAC CODE
S21 PHASE CHANGE (DEG)
768512256
-25
0
25
50
75
100
-50
0 1024
REFERENCED TO INSERTION LOSS STATE
POSITIVE PHASE = ELECTRICALLY SHORTER
2250MHz
950MHz
1500MHz
3500MHz
INPUT IP3 vs. VCTRL
MAX19792 toc12
VCTRL (V)
INPUT IP3 (dBm)
LSB, USB
32
35
40
45
50
30
14
fRF = 1700MHz
PIN = 0dBm/TONE
INPUT IP3 vs. VCTRL
MAX19792 toc15
VCTRL (V)
INPUT IP3 (dBm)
32
35
40
45
50
30
14
LSB, USB
fRF = 3500MHz
PIN = 0dBm/TONE
INPUT IP3 vs. VCTRL
MAX19792 toc16
VCTRL (V)
INPUT IP3 (dBm)
32
35
40
45
50
30
14
TC = -40°C, +25°C, +85°C,
LSB, USB
fRF = 1500MHz
PIN = 0dBm/TONE
INPUT IP3 vs. VCTRL
MAX19792 toc10
VCTRL (V)
LSB
INPUT IP3 (dBm)
USB
32
35
40
45
50
30
14
fRF = 500MHz
PIN = 0dBm/TONE
INPUT IP3 vs. VCTRL
MAX19792 toc13
VCTRL (V)
INPUT IP3 (dBm)
32
35
40
45
50
30
14
fRF = 2200MHz
PIN = 0dBm/TONE
LSB, USB
INPUT IP3 vs. VCTRL
MAX19792 toc11
VCTRL (V)
INPUT IP3 (dBm)
LSB, USB
32
35
40
45
50
30
14
fRF = 900MHz
PIN = 0dBm/TONE
INPUT IP3 vs. VCTRL
MAX19792 toc14
VCTRL (V)
INPUT IP3 (dBm)
32
35
40
45
50
30
14
fRF = 2700MHz
PIN = 0dBm/TONE
LSB, USB
9Maxim Integrated
MAX19792
500MHz to 4000MHz Dual Analog Voltage Variable
Attenuator with On-Chip 10-Bit SPI-Controlled DAC
Typical Operating Characteristics (continued)
(Typical Application Circuit, VCC = 5V, configured for single attenuator, RF ports are driven from 50I sources and loaded into 50I,
VDAC_LOGIC = 0V, RDBK_EN = Logic 0, VCTRL = 1V, PIN = 0dBm, fRF = 1500MHz, TC = 25°C, unless otherwise noted.).
INPUT IP2 vs. VCTRL
MAX19792 toc17
VCTRL (V)
INPUT IP2 (dBm)
2 3
60
80
100
40
14
fRF = 500MHz
PIN = 0dBm/TONE
INPUT IP2 vs. VCTRL
MAX19792 toc22
VCTRL (V)
INPUT IP2 (dBm)
32
70
80
90
100
60
14
fRF = 3500MHz
PIN = 0dBm/TONE
INPUT IP2 vs. VCTRL
MAX19792 toc20
VCTRL (V)
INPUT IP2 (dBm)
32
70
80
90
100
60
14
fRF = 2200MHz
PIN = 0dBm/TONE
INPUT IP2 vs. VCTRL
MAX19792 toc23
VCTRL (V)
INPUT IP2 (dBm)
32
70
80
90
100
60
14
fRF = 1500MHz
PIN = 0dBm/TONE
TC = -40°C, +25°C, +85°C
INPUT IP2 vs. VCTRL
MAX19792 toc21
VCTRL (V)
INPUT IP2 (dBm)
32
70
80
90
100
60
14
fRF = 2700MHz
PIN = 0dBm/TONE
INPUT IP2 vs. VCTRL
MAX19792 toc18
VCTRL (V)
INPUT IP2 (dBm)
2 3
50
60
70
40
14
fRF = 900MHz
PIN = 0dBm/TONE
INPUT IP2 vs. VCTRL
MAX19792 toc19
VCTRL (V)
INPUT IP2 (dBm)
32
70
80
90
100
60
14
fRF = 1700MHz
PIN = 0dBm/TONE
10Maxim Integrated
MAX19792
500MHz to 4000MHz Dual Analog Voltage Variable
Attenuator with On-Chip 10-Bit SPI-Controlled DAC
Typical Operating Characteristics (continued)
(Typical Application Circuit, VCC = 5V, configured for single attenuator, RF ports are driven from 50I sources and loaded into 50I,
VDAC_LOGIC = 0V, RDBK_EN = Logic 0, VCTRL = 1V, PIN = 0dBm, fRF = 1500MHz, TC = 25°C, unless otherwise noted.).
INPUT P1dB vs. RF FREQUENCY
MAX19792 toc24
RF FREQUENCY(MHz)
INPUT P1dB (dBm)
240018001200
21
22
23
24
25
26
20
600 3000
TC = -40°C, +25°C, +85°C
RESPONSE TIME WITH CS STEP
MAX19792 toc29
TIME (ns)
S21 (dB)
15001000500
-25
-20
-15
-10
-5
0
-30
0 2000
CS STEP OCCURS AT t = t0
CODE 250 TO 0
CODE 500 TO 0
CODE 640 TO 0
CODE 950 TO 0
CODE 1023 TO 0
RESPONSE TIME VCTRL STEP
MAX19792 toc27
TIME (ns)
S21 (dB)
750500250
-25
-20
-15
-10
-5
0
-30
0 1000
VCTRL STEP OCCURS AT t = t0
VCTRL STEP FROM 4V TO 1V
VCTRL STEP FROM 3V TO 1V
RESPONSE TIME WITH MODE STEP
MAX19792 toc30
TIME (ns)
S21 (dB)
300020001000
-25
-20
-15
-10
-5
0
-30
0 4000
MODE STEP OCCURS AT t = t0
MODE 0 TO 1 (CODE 0 TO 1023)
MODE 0 TO 1 (CODE 0 TO 500)
MODE 1 TO 0 (CODE 500 TO 0)
MODE 1 TO 0 (CODE 1023 TO 0)
RESPONSE TIME WITH CS STEP
MAX19792 toc28
TIME (ns)
S21 (dB)
300020001000
-25
-20
-15
-10
-5
0
-30
0 4000
CS STEP OCCURS AT t = t0
CODE 0 TO 250
CODE 0 TO 500
CODE 0 TO 950
CODE 0 TO 640
CODE 0 TO 1023
INPUT P1dB vs. RF FREQUENCY
MAX19792 toc25
RF FREQUENCY(MHz)
INPUT P1dB (dBm)
240018001200
21
22
23
24
25
26
20
600 3000
VCC = 4.75V
VCC = 5.25V VCC = 5.00V
RESPONSE TIME VCTRL STEP
MAX19792 toc26
TIME (ns)
S21 (dB)
15001000500
-25
-20
-15
-10
-5
0
-30
0 2000
VCTRL STEP OCCURS AT t = t0
VCTRL STEP FROM 1V TO 3V
VCTRL STEP FROM 1V TO 4V
11Maxim Integrated
MAX19792
500MHz to 4000MHz Dual Analog Voltage Variable
Attenuator with On-Chip 10-Bit SPI-Controlled DAC
Typical Operating Characteristics (continued)
(Typical Application Circuit, VCC = 3.3V, configured for single attenuator, RF ports are driven from 50I sources and loaded into 50I,
VDAC_LOGIC = 0V, RDBK_EN = logic 0, VCTRL = 1V, PIN = 0dBm, fRF = 1500MHz, TC = 25°C, unless otherwise noted.).
SUPPLY CURRENT vs. VCC
MAX19792 toc31
VCC (V)
SUPPLY CURRENT (mA)
3.403.353.303.253.20
9
10
11
8
3.15 3.45
TC = -40°C
TC = +85°C
TC = +25°C
RF FREQUENCY (MHz)
S21 (dB)
3300260019001200
-25
-20
-15
-10
-5
0
-30
500 4000
S21 vs. RF FREQUENCY
OVER CODE SETTINGS
MAX19792 toc34
S21 vs. DAC CODE
MAX19792 toc37
DAC CODE
S21(dB)
768512256
-25
-20
-15
-10
-5
0
-30
0 1024
3500MHz
950MHz, 1500MHz, 2250MHz
INPUT MATCH vs. RF FREQUENCY
OVER CODE SETTINGS
MAX19792 toc32
RF FREQUENCY (MHz)
S11 (dB)
2600 330019001200
-20
-10
0
-30
500 4000
INPUT MATCH vs. DAC CODE
MAX19792 toc35
DAC CODE
S11(dB)
768512256
-25
-20
-15
-10
-5
0
-30
0 1024
3500MHz
1500MHz
2250MHz
950MHz
S21 vs. DAC CODE
MAX19792 toc38
DAC CODE
S21(dB)
768512256
-25
-20
-15
-10
-5
0
-30
0 1024
fRF = 950MHz
TC = -40°C, +25°C, +85°C
OUTPUT MATCH vs. RF FREQUENCY
OVER CODE SETTINGS
MAX19792 toc33
RF FREQUENCY (MHz)
S22 (dB)
3300260019001200
-40
-30
-20
-10
0
-50
500 4000
OUTPUT MATCH vs. DAC CODE
MAX19792 toc36
DAC CODE
S22(dB)
768512256
-40
-30
-20
-10
0
-50
0 1024
3500MHz
1500MHz
950MHz
2250MHz
S21 PHASE CHANGE vs. DAC CODE
MAX19792 toc39
DAC CODE
S21 PHASE CHANGE (DEG)
768512256
-25
0
25
50
75
100
-50
0 1024
3500MHz
950MHz 1500MHz
2250MHz
REFERENCED TO INSERTION LOSS STATE
POSITIVE PHASE = ELECTRICALLY SHORTER
12Maxim Integrated
MAX19792
500MHz to 4000MHz Dual Analog Voltage Variable
Attenuator with On-Chip 10-Bit SPI-Controlled DAC
Typical Operating Characteristics (continued)
(Typical Application Circuit, VCC = 3.3V, configured for single attenuator, RF ports are driven from 50I sources and loaded into 50I,
VDAC_LOGIC = 0V, RDBK_EN = logic 0, VCTRL = 1V, PIN = 0dBm, fRF = 1500MHz, TC = 25°C, unless otherwise noted.).
INPUT IP3 vs. VCTRL
MAX19792 toc40
VCTRL (V)
INPUT IP3 (dBm)
2.01.5
30
35
40
45
50
25
1.0 2.5
fRF = 900MHz
PIN = 0dBm/TONE
LSB, USB
INPUT IP3 vs. VCTRL
MAX19792 toc43
VCTRL (V)
INPUT IP3 (dBm)
2.01.5
35
40
45
50
30
1.0 2.5
LSB, USB
fRF = 2700MHz
PIN = 0dBm/TONE
INPUT IP2 vs. VCTRL
MAX19792 toc46
VCTRL (V)
INPUT IP2 (dBm)
2.01.5
60
70
80
90
50
1.0 2.5
fRF = 1700MHz
PIN = 0dBm/TONE
INPUT IP3 vs. VCTRL
MAX19792 toc41
VCTRL (V)
INPUT IP3 (dBm)
2.01.5
35
40
45
50
30
1.0 2.5
LSB, USB
fRF = 1700MHz
PIN = 0dBm/TONE
INPUT IP3 vs. VCTRL
MAX19792 toc44
VCTRL (V)
INPUT IP3 (dBm)
2.01.5
35
40
45
50
30
1.0 2.5
TC = -40°C, +25°C, +85°C,
LSB, USB
fRF = 1500MHz
PIN = 0dBm/TONE
INPUT IP2 vs. VCTRL
MAX19792 toc47
VCTRL (V)
INPUT IP2 (dBm)
2.01.5
60
70
80
90
50
1.0 2.5
fRF = 2200MHz
PIN = 0dBm/TONE
INPUT IP3 vs. VCTRL
MAX19792 toc42
VCTRL (V)
INPUT IP3 (dBm)
2.01.5
35
40
45
50
30
1.0 2.5
LSB, USB
fRF = 2200MHz
PIN = 0dBm/TONE
INPUT IP2 vs. VCTRL
MAX19792 toc45
VCTRL (V)
INPUT IP2 (dBm)
1.5 2.0
50
60
70
40
1.0 2.5
fRF = 900MHz
PIN = 0dBm/TONE
INPUT IP2 vs. VCTRL
MAX19792 toc48
VCTRL (V)
INPUT IP2 (dBm)
2.01.5
60
70
80
90
50
1.0 2.5
fRF = 2700MHz
PIN = 0dBm/TONE
13Maxim Integrated
MAX19792
500MHz to 4000MHz Dual Analog Voltage Variable
Attenuator with On-Chip 10-Bit SPI-Controlled DAC
Typical Operating Characteristics (continued)
(Typical Application Circuit, VCC = 3.3V, configured for single attenuator, RF ports are driven from 50I sources and loaded into 50I,
VDAC_LOGIC = 0V, RDBK_EN = logic 0, VCTRL = 1V, PIN = 0dBm, fRF = 1500MHz, TC = 25°C, unless otherwise noted.).
INPUT IP2 vs. VCTRL
MAX19792 toc49
VCTRL (V)
INPUT IP2 (dBm)
2.01.5
60
70
80
90
50
1.0 2.5
fRF = 1500MHz
PIN = 0dBm/TONE
TC = -40°C, +25°C, +85°C
RESPONSE TIME VCTRL STEP
MAX19792 toc52
TIME (ns)
S21 (dB)
15001000500
-25
-20
-15
-10
-5
0
-30
0 2000
VCTRL STEP OCCURS AT t = t0
VCTRL STEP FROM 1V TO 1.5V
VCTRL STEP FROM 1V TO 2.5V
RESPONSE TIME WITH CS STEP
MAX19792 toc55
TIME (ns)
S21 (dB)
15001000500
-25
-20
-15
-10
-5
0
-30
0 2000
CODE 500 TO 0
CODE 640 TO 0
CODE 950 TO 0
CODE 1023 TO 0
CS STEP OCCURS AT t = t0
RESPONSE TIME WITH MODE STEP
MAX19792 toc56
TIME (ns)
S21 (dB)
300020001000
-25
-20
-15
-10
-5
0
-30
0 4000
MODE 1 TO 0 (CODE 500 to 0)
MODE 1 TO 0 (CODE 1023 TO 0)
MODE 0 TO 1 (CODE 0 TO 500)
MODE 0 TO 1 (CODE 0 TO 1023)
MODE STEP OCCURS AT t = t0
INPUT P1dB vs. RF FREQUENCY
MAX19792 toc50
RF FREQUENCY(MHz)
INPUT P1dB (dBm)
240018001200
16
17
18
19
20
15
600 3000
TC = +85°C
TC = -40°C
TC = +25°C
RESPONSE TIME VCTRL STEP
MAX19792 toc53
TIME (ns)
S21 (dB)
750500250
-25
-20
-15
-10
-5
0
-30
0 1000
VCTRL STEP FROM 1.5V TO 1V
VCTRL STEP FROM 2.5V TO 1V
VCTRL STEP OCCURS AT t = t0
INPUT P1dB vs. RF FREQUENCY
MAX19792 toc51
RF FREQUENCY (MHz)
INPUT P1dB (dBm)
240018001200
16
17
18
19
20
15
600 3000
VCC = 3.30V
VCC = 3.45V
VCC = 3.15V
RESPONSE TIME WITH CS STEP
MAX19792 toc54
TIME (ns)
S21 (dB)
300020001000
-25
-20
-15
-10
-5
0
-30
0 4000
CS STEP OCCURS AT t = t0
CODE 0 TO 500
CODE 0 TO 640
CODE 0 TO 950
CODE 0 TO 1023
14Maxim Integrated
MAX19792
500MHz to 4000MHz Dual Analog Voltage Variable
Attenuator with On-Chip 10-Bit SPI-Controlled DAC
Pin Description
Pin Configuration
PIN NAME DESCRIPTION
1, 3, 6, 7, 9, 10,
12, 26, 27, 28,
30, 33, 34, 36
GND Ground. Connect to the board’s ground plane using low-inductance layout techniques.
2 OUT_A Attenuator A RF Output. Internally matched to 50I over the operating frequency band. This pin,
if used, requires a DC block. If this attenuator is not used, the pin can be left unconnected.
4, 31 N.C.
No Internal Connection. This pin can be left open or ground.
Note: If a common layout is desired to support the MAX19794, connect a 0402 capacitor to
ground on each of these pins.
5 VCC Attenuator A Power Supply. Bypass to GND with a capacitor and resistor, as shown in the
Typical Application Circuit.
8 IN_A Attenuator A RF Input. Internally matched to 50I over the operating frequency band. This pin, if
used, requires a DC block. If this attenuator is not used, the pin can be left unconnected.
11 CTRL
Attenuator Control Voltage Input. Except in test mode, where no voltage can be applied
to this pin. VCC must be present unless using a current-limiting resistor as noted in the
Applications Information section.
TQFN
(6mm x 6mm)
*INTERNALLY CONNECTED TO GND.
MODE
COMP_OUT
REF_SEL
REF_IN
CTRL
GND
VCC
GND
DAC_LOGIC
GND
N.C.
VCC
GND
IN_B
GND
GND
VCC
GND
GND
GND
N.C.
GND
OUT_A
GND
GND
VCC
CS
DOUT
DIN
CLK
UP
DWN
GND
TOP VIEW
GND
IN_A
OUT_B
MAX19792
35
36
34
33
12
11
10
13
14
12
EP*
4567
27 26 24 23 22
3
25
+
32
15
31
28
29
30 16
17
18
89
21 20 19
15Maxim Integrated
MAX19792
500MHz to 4000MHz Dual Analog Voltage Variable
Attenuator with On-Chip 10-Bit SPI-Controlled DAC
Pin Description (continued)
PIN NAME DESCRIPTION
13 VCC Analog Supply Voltage. Bypass to GND with a capacitor as close as possible to the device. See
the Typical Application Circuit.
14 REF_IN DAC Reference Voltage Input (Optional)
15 REF_SEL
DAC Reference Voltage Selection Logic Input
Logic = 0 to enable on-chip DAC reference.
Logic = 1 to use off-chip DAC reference (pin 14).
16 DAC_LOGIC DAC Logic Control Input (Table 1)
17 COMP_OUT Comparator Logic Output. Use a 4.7pF capacitor to reduce any potential rise-time glitching
when the comparator changes state.
18 MODE
Attenuator Control Mode Logic Input
Logic = 1 to enable attenuator step control.
Logic = 0 to enable attenuator SPI control.
19 DWN Down Pulse Input
Logic pulse = 0 for each step-down.
20 UP Up Pulse Input
Logic pulse = 0 for each step-up.
19/20 DWN/UP Logic = 0 to both pins to reset the attenuator to a minimum attenuation state
21 CLK SPI Clock Input
22 DIN SPI Data Input
23 DOUT SPI Data Output
24 CS SPI Chip-Select Input
25 VCC Digital Supply Voltage. Bypass to GND with a capacitor as close as possible to the device.
See the Typical Application Circuit.
29 OUT_B Attenuator B RF Output. Internally matched to 50I over the operating frequency band. This pin,
if used, requires a DC block. If this attenuator is not used, the pin can be left unconnected.
32 VCC Attenuator B Power Supply. Bypass to GND with a capacitor and resistor, as shown in the
Typical Application Circuit.
35 IN_B Attenuator B RF Input. Internally matched to 50I over the operating frequency band. This pin,
if used, requires a DC block. If this attenuator is not used, the pin can be left unconnected.
— EP
Exposed Pad. Internally connected to GND. Solder this exposed pad to a PCB pad that uses
multiple ground vias to provide heat transfer out of the device into the PCB ground planes.
These multiple via grounds are also required to achieve the noted RF performance. See the
Layout Considerations section.
16Maxim Integrated
MAX19792
500MHz to 4000MHz Dual Analog Voltage Variable
Attenuator with On-Chip 10-Bit SPI-Controlled DAC
Detailed Description
The MAX19792 is a dual general-purpose analog VVA
designed to interface with 50I systems operating in the
500MHz to 4000MHz frequency range. Each attenuator
provides 23.2dB of attenuation range with a linear con-
trol slope of 8.5dB/V. Both attenuators share a common
analog control and can be cascaded together to yield
46.4dB of total dynamic range with a combined linear
control slope of 17dB/V. Alternatively, the on-chip 4-wire
SPI-controlled 10-bit DAC can be used to control both
attenuators. In addition, a step-up/down feature allows
user-programmable attenuator stepping through com-
mand pulses without reprogramming the SPI interface.
Applications Information
Attenuation Control and Features
The device has various states used to control the analog
attenuator along with some monitoring conditions. The
device can be controlled by an external control voltage,
an internal SPI bus, or a combination of the two. The
various states are described in Table 1. The SPI bus has
multiple registers used to control the device when not
configured for the analog-only mode. For cases where
CTRL is used, the control range is 1V to 4V for VCC = 5V,
and is 1V to 2.5V for VCC = 3.3V.
Up to 23.2dB of attenuation control range is provided per
attenuator. At the insertion-loss setting, the single attenu-
ator’s loss is approximately 2.7dB. If a larger attenuation-
control range is desired, the second on-chip attenuator
can be connected in series to provide an additional
23.2dB of gain-control range.
Note that the on-chip control driver simultaneously
adjusts both on-chip attenuators. It is suggested that a
current-limiting resistor be included in series with CTRL
to limit the input current to less than 40mA, should the
control voltage be applied when VCC is not present. A
series resistor of greater than 200I provides complete
protection for 5V control voltage ranges.
Analog-Only Mode Control
In the Table 1 state (0, 0), the attenuators are controlled
using a voltage applied to the CTRL pin of the device and
the on-chip DAC is disabled. In cases where features of
the SPI bus are not needed, the part can be operated in
a pure analog control mode by grounding pins 14–25.
This method allows the MAX19792 to be pin compatible
with the MAX19790.
DAC Mode Control
In the Table 1 state (1, 0), the attenuators are controlled
by the on-chip 10-bit DAC register. See the Register
Mode Up/Down Operation section. In this condition, no
signal is applied to the CTRL pin and the load on the
CTRL pin should be > 100kI. The DAC is set using the
SPI-loaded code in the registers, along with the setting
of the MODE pin.
Analog Mode Control
with Alarm Monitoring
In the Table 1 state (0, 1), the attenuators are controlled
using a voltage applied to the CTRL pin of the device.
See the Register Mode Up/Down Operation section.
In this condition, the DAC is enabled and a voltage is
also applied to the CTRL pin. The on-chip switches are
set to compare the DAC voltage to the CTRL voltage
at the comparator input; the output of the comparator
(COMP_OUT) trips from high to low when VCTRL exceeds
the on-chip DAC voltage.
DAC Test Mode
In the Table 1 state (1, 1), the attenuators are controlled
by the on-chip 10-bit DAC register. See the Register
Mode Up/Down Operation section. In this condition, the
DAC is enabled and the DAC voltage appears at the
CTRL pin. In this condition, no signal can be applied to
the CTRL pin and the load on the CTRL pin should be >
100kI. This mode is only used in production testing of the
DAC voltage and is not recommended for customer use.
Register Mode Up/Down Operation
The device has four 13-bit registers that are used for the
operation of the device. The first bit is the read/write bit,
the following two are address bits, and the remaining 10
are the desired data bits. The read/write bit determines
whether the register is being written to or read from. The
next two address bits select the desired register to write
or read from. These address bits can be seen in Table 2.
Table 3 describes the contents of the four registers.
Figure 1 shows the configuration of the internal regis-
ters of the device and Figure 2 shows the timing of the
SPI bus. Register 0 sets the DAC code to the desired
value, register 1 selects the step-up code, and register 2
selects the step-down code.
The device also contains a mode control pin (Table 4),
along with UP and DWN controls (Table 5). When MODE
is 0, the contents of register 0 get loaded into the 10-bit
DAC register and set the value of the on-chip DAC. In this
condition, the UP and DWN control pins have no effect on
17Maxim Integrated
MAX19792
500MHz to 4000MHz Dual Analog Voltage Variable
Attenuator with On-Chip 10-Bit SPI-Controlled DAC
the part. In MODE 1, the effective DAC code fed to the
10-bit DAC register is equal to:
m x Register 1 - n x Register 2
where m and n are the number of UP and DWN control
steps accumulated, respectively.
After powering up the device, UP and DWN should both
be set to 0 to reset the m and n counters to 0. This results
in a 10-bit all 0 code out of the mathematical block in
Figure 1, and applied to the 10-bit DAC register that
drives the DAC. To increase (decrease) the code using
the UP (DWN) pin, the DWN (UP) pin must be high and
the UP (DWN) pin should be pulsed low to high. The
device is designed to produce no wraparounds when
using UP and DWN stepping so that the DAC code
maxes out at 1023 or goes no lower than 0. See Figure 3
for the UP and DWN control operation.
Switching back to MODE = 0 produces the same 10-bit
DAC code as was previously loaded into register 0.
Switching back to MODE = 1 results in the previous
10-bit DAC code from the register 1 and 2 combiner/
multiplier block.
Register 3 is used to set the RDBK_EN register in the
write mode and is used to read back the RDBK_EN reg-
ister and COMP_OUT in the read mode.
SPI Interface
The device can be controlled with a 4-wire, SPI-compatible
serial interface. Figure 2 shows a timing diagram for the
interface. In the write mode, a 13-bit word is loaded into
the device through the DIN pin, with CS set low. The first
bit of the word in the write mode is 0, and the next two
bits select the register to be written to (Table 2). The
next 10 bits contain the data to be written to the selected
register. After the 13 bits are shifted in, a low-to-high CS
command is applied and this latches the 10 bits into the
selected register. The entire write command is ignored if
CS is pulsed low to high before the last data bit is suc-
cessfully captured.
For the read cycle, the first bit clocked in is a 1 and this
establishes that a register is to be read. The next two
clocked bits form the address of the register to be read
(Table 2). In this read mode, data starts to get clocked
out of the DOUT pin after A0 is captured. The DOUT
pin goes to a high-impedance state after the 10 bits are
transmitted or if CS goes high at any point during the
transmission.
Voltage Reference
The device has an on-chip voltage reference for the DAC
and a provision to operate with an off-chip reference.
Table 6 provides details in selecting the desired reference.
Table 1. Attenuator Control Logic States
DAC_LOGIC RDBK_EN
(D9, REG 3)
INTERNAL SWITCH
STATES ATTENUATOR 10-BIT DAC
0 0 S1 = closed
S2, S3, S4 = open
Controlled by an external analog voltage on the
CTRL pin. Disabled
1 0 S1, S3, S4 = open
S2 = closed
Controlled by an on-chip DAC; no voltage is
applied to the CTRL pin. Enabled
0 1 S1, S3, S4 = closed
S2 = open
Controlled by an external analog voltage on the
CTRL pin. CTRL is compared with the
DAC output. The comparator drives the
COMP_OUT pin.
Enabled
(update DAC code
to estimate voltage
on the CTRL pin)
1 1 S1, S2 = closed
S3, S4 = open
Controlled by an on-chip DAC. The DAC output
is connected to the CTRL pin. This state can be
used to test the DAC output. In this condition,
no voltage can be applied to the CTRL pin and
the load on this pin must be > 100kΩ.
Enabled
18Maxim Integrated
MAX19792
500MHz to 4000MHz Dual Analog Voltage Variable
Attenuator with On-Chip 10-Bit SPI-Controlled DAC
Figure 1. Register Configuration Diagram
Table 2. Address Data Bits
Table 3. Register Definitions
*RDBK_EN = Enable bit for the voltage comparator that drives the COMP_OUT pin.
**RDBK_EN = Enable bit for the voltage comparator that drives the COMP_OUT pin.
COMP_OUT = Read logic level of COMP_OUT pin.
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
REGISTER 0 (Read/Write Bits, 10-Bit DAC Code)
DAC MSB — — — — — — — — DAC LSB
REGISTER 1 (Read/Write Bits, 10-Bit Step-Up Code)
Step-up MSB — — — — — — — — Step-up LSB
REGISTER 2 (Read/Write Bits, 10-Bit Step-Down Code)
Step-down MSB — — — — — — — — Step-down LSB
REGISTER 3 (Write Bits)*
RDBK_EN Not used (set to 0)
REGISTER 3 (Read Bits)**
RDBK_EN COMP_
OUT Not used (set to 0)
R/W A1 A0 DESCRIPTION
000Write to register 0 using DIN
001Write to register 1 using DIN
010Write to register 2 using DIN
011Write to register 3 using DIN
100Read from register 0 using DOUT
101Read from register 1 using DOUT
110Read from register 2 using DOUT
111Read from register 3 using DOUT
m x REGISTER 1 - n x REGISTER 2
m = NUMBER OF UP PULSES
n = NUMBER OF DOWN PULSES
RESET TO ALL ZEROS WHEN UP/DOWN
PULSED TOGETHER
OR
10-BIT DAC REGISTER
REGISTER 3
REGISTER 2
REGISTER 1
REGISTER 0
m
n
DOWN
UP
MODE
DIN DOUT
19Maxim Integrated
MAX19792
500MHz to 4000MHz Dual Analog Voltage Variable
Attenuator with On-Chip 10-Bit SPI-Controlled DAC
Table 4. Attenuator-Mode Control Logic State
Table 5. Step-Mode Logic State (MODE = 1)
*Continued UP or DWN stepping results in saturation (no code wrapping).
Table 6. REF_SEL Logic State
SPI Interface Programming
Figure 2. SPI Timing Diagram Figure 3. UP/DWN Control Diagram (MODE = 1)
MODE PIN ATTENUATOR
0SPI-mode control (the DAC code is located in register 0).
1Step-mode control using the UP and DWN pins (the step-up code is located in register 1 and the step-down
code is located in register 2).
UP DWN ATTENUATOR
Logic 0 Logic 0 Reset the DAC for the minimum attenuation state (DAC code = 0000000000).
Logic 0 pulse Logic 1 Increase the DAC code* by the amount located in register 1.
UP is pulsed from high to low to high (see Figure 3).
Logic 1 Logic 0 pulse Decrease the DAC code* by amount located in register 2.
DWN is pulsed from high to low to high (see Figure 3).
REF_SEL DAC REFERENCE
0Uses an on-chip DAC reference.
1User provides off-chip DAC reference voltage on REF_IN pin.
R/W A1 A0 D[9:0] TO REGISTER 0, 1, 2, 3
CS
CLK
DIN
D[9:0] FROM REGISTER 0, 1, 2, 3
DOUT
tCS
HIGH-
IMPEDANCE
HIGH-
IMPEDANCE
tCW tES
tEW
tCH
tEWS
UP
1
1
0
0
DWN
NO DAC
CODE CHANGE
DAC CODE
INCREASED
BY UP STEP
DAC CODE
DECREASED
BY DWN STEP
DAC CODE
RESET TO
ALL 0's
20Maxim Integrated
MAX19792
500MHz to 4000MHz Dual Analog Voltage Variable
Attenuator with On-Chip 10-Bit SPI-Controlled DAC
Table 7. Typical Application Circuit
Component Values
Layout Considerations
A properly designed PCB is an essential part of any RF/
microwave circuit. Keep RF signal lines as short as pos-
sible to reduce losses, radiation, and inductance. For best
performance, route the ground-pin traces directly to the
exposed pad underneath the package. This pad MUST
be connected to the ground plane of the board by using
multiple vias under the device to provide the best RF and
thermal conduction path. Solder the exposed pad on the
bottom of the device package to a PCB. Pins 4 and 31
for the MAX19792 have no internal connection. These two
pins are in place to support the MAX19794 part in the fam-
ily. The MAX19794 requires an additional bypass capaci-
tor on each of these pins for proper operation. If desired
to have a common layout to support the MAX19794, then
include these capacitors in the common layout. Refer to
the MAX19794 data sheet for details.
Power-Supply Bypassing
Proper voltage-supply bypassing is essential for high-
frequency circuit stability. Bypass each VCC pin with
capacitors placed as close as possible to the device.
Place the smallest capacitor closest to the device. See
the Typical Application Circuit and Table 7 for details.
Exposed Pad RF and
Thermal Considerations
The exposed pad (EP) of the device’s 36-pin TQFN pack-
age provides a low thermal-resistance path to the die. It
is important that the PCB on which the IC is mounted be
designed to conduct heat from this contact.
In addition, provide the EP with a low-inductance RF
ground path for the device. The EP must be soldered to
a ground plane on the PCB, either directly or through an
array of plated via holes. Soldering the pad to ground is
also critical for efficient heat transfer. Use a solid ground
plane wherever possible.
*Add two additional 10I series resistors between VCC’s lead-
ing to C5 and C6, unless a VCC power plane is used.
DESIGNATION QTY DESCRIPTION
C1, C2, C4 322pF Q5%, 50V C0G ceramic
capacitors (0402)
C3 1
22pF Q5%, 50V C0G ceramic
capacitors (0402)
Not installed for two attenuators
in cascade.
C5–C9 5 1000pF Q5%, 50V C0G ceramic
capacitors (0402)
C12 1
120pF Q5%, 50V C0G ceramic
capacitor (0402)
Provides some external noise
filtering along with R3.
C13 0
Not installed, 4.7pF capacitor
could be used to reduce any
potential rise time glitching when
the comparator changes state.
R1, R2 210I Q5% resistors* (0402)
R3 1
200I Q5% resistor (0402)
Use this resistor to provide some
lowpass noise filtering when used
with C12. The value of R3 slows
down the response time. R3 also
provides protection for the device
in case VCTRL is applied without
VCC present.
U1 1 Maxim MAX19792
21Maxim Integrated
MAX19792
500MHz to 4000MHz Dual Analog Voltage Variable
Attenuator with On-Chip 10-Bit SPI-Controlled DAC
Typical Application Circuit
MAX19792
EP
C1
RFIN_A
VCC
IN_B
GND
NOTE:
FOR ATTENUATOR A ONLY CONFIGURATION, REMOVE C3 AND MOVE C2 DIAGONALLY TO CONNECT
PIN 2 TO THE OUTPUT CONNECTION RF_AB.
FOR ATTENUATOR B ONLY CONFIGURATION, REMOVE C2.
FOR CASCADED CONFIGURATION, REMOVE C3 AND USE C2 TO CONNECT OUT_A TO IN_B.
234567
S1
S2
S3 S4
89
10
11
12
13
14
DAC
15
16
17
18
192021222324252627
28
29
ATTEN_B
ATTEN_A
30
31
32
33
34
35
36
OUT_A
GND
IN_A
OUT_B
1
ATTENUATION-
CONTROL
CIRCUITRY
GND
N.C.
GND
GND
GND
R1
C5
VCC
CTRL
GND C12
C7
C13
C8
VCTRL
REF_IN
R3
GND
GND
GND
GND
GND
N.C.
REF_IN
REF_SEL REF_SEL
DAC_LOGIC DAC_LOGIC
MODE MODE
COMP_OUT COMP_OUT
VCC R2
C4
C3
C6
C9
C2
RFOUT_B
RF_AB
VCC
GND
GND
VCC
VCC
CS
CS
VCC
VCC
DOUT
DOUT
DIN
DIN
CLK
CLK
UP
UP
DWN
DWN
22Maxim Integrated
MAX19792
500MHz to 4000MHz Dual Analog Voltage Variable
Attenuator with On-Chip 10-Bit SPI-Controlled DAC
Chip Information
PROCESS: SiGe BiCMOS
Package Information
For the latest package outline information and land patterns (foot-
prints), go to www.maximintegrated.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but the
drawing pertains to the package regardless of RoHS status.
Ordering Information
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
T = Tape and reel. PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
36 TQFN-EP T3666+2 21-0141 90-0049
PART TEMP RANGE PIN-PACKAGE
MAX19792ETX+ -40NC to +100NC36 TQFN-EP*
MAX19792ETX+T -40NC to +100NC36 TQFN-EP*
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent
licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and
max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000 23
© 2015 Maxim Integrated Products, Inc. Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
MAX19792
500MHz to 4000MHz Dual Analog Voltage Variable
Attenuator with On-Chip 10-Bit SPI-Controlled DAC
Revision History
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
0 6/12 Initial release —
1 9/12 Updated Electrical Characteristics table, corrected TOC titles 3, 4, 6, 7, 8, 9,
10, 11, 12, 13,
2 5/15 Removed military reference from data sheet 1
