16Maxim Integrated
MAX19792
500MHz to 4000MHz Dual Analog Voltage Variable
Attenuator with On-Chip 10-Bit SPI-Controlled DAC
Detailed Description
The MAX19792 is a dual general-purpose analog VVA
designed to interface with 50I systems operating in the
500MHz to 4000MHz frequency range. Each attenuator
provides 23.2dB of attenuation range with a linear con-
trol slope of 8.5dB/V. Both attenuators share a common
analog control and can be cascaded together to yield
46.4dB of total dynamic range with a combined linear
control slope of 17dB/V. Alternatively, the on-chip 4-wire
SPI-controlled 10-bit DAC can be used to control both
attenuators. In addition, a step-up/down feature allows
user-programmable attenuator stepping through com-
mand pulses without reprogramming the SPI interface.
Applications Information
Attenuation Control and Features
The device has various states used to control the analog
attenuator along with some monitoring conditions. The
device can be controlled by an external control voltage,
an internal SPI bus, or a combination of the two. The
various states are described in Table 1. The SPI bus has
multiple registers used to control the device when not
configured for the analog-only mode. For cases where
CTRL is used, the control range is 1V to 4V for VCC = 5V,
and is 1V to 2.5V for VCC = 3.3V.
Up to 23.2dB of attenuation control range is provided per
attenuator. At the insertion-loss setting, the single attenu-
ator’s loss is approximately 2.7dB. If a larger attenuation-
control range is desired, the second on-chip attenuator
can be connected in series to provide an additional
23.2dB of gain-control range.
Note that the on-chip control driver simultaneously
adjusts both on-chip attenuators. It is suggested that a
current-limiting resistor be included in series with CTRL
to limit the input current to less than 40mA, should the
control voltage be applied when VCC is not present. A
series resistor of greater than 200I provides complete
protection for 5V control voltage ranges.
Analog-Only Mode Control
In the Table 1 state (0, 0), the attenuators are controlled
using a voltage applied to the CTRL pin of the device and
the on-chip DAC is disabled. In cases where features of
the SPI bus are not needed, the part can be operated in
a pure analog control mode by grounding pins 14–25.
This method allows the MAX19792 to be pin compatible
with the MAX19790.
DAC Mode Control
In the Table 1 state (1, 0), the attenuators are controlled
by the on-chip 10-bit DAC register. See the Register
Mode Up/Down Operation section. In this condition, no
signal is applied to the CTRL pin and the load on the
CTRL pin should be > 100kI. The DAC is set using the
SPI-loaded code in the registers, along with the setting
of the MODE pin.
Analog Mode Control
with Alarm Monitoring
In the Table 1 state (0, 1), the attenuators are controlled
using a voltage applied to the CTRL pin of the device.
See the Register Mode Up/Down Operation section.
In this condition, the DAC is enabled and a voltage is
also applied to the CTRL pin. The on-chip switches are
set to compare the DAC voltage to the CTRL voltage
at the comparator input; the output of the comparator
(COMP_OUT) trips from high to low when VCTRL exceeds
the on-chip DAC voltage.
DAC Test Mode
In the Table 1 state (1, 1), the attenuators are controlled
by the on-chip 10-bit DAC register. See the Register
Mode Up/Down Operation section. In this condition, the
DAC is enabled and the DAC voltage appears at the
CTRL pin. In this condition, no signal can be applied to
the CTRL pin and the load on the CTRL pin should be >
100kI. This mode is only used in production testing of the
DAC voltage and is not recommended for customer use.
Register Mode Up/Down Operation
The device has four 13-bit registers that are used for the
operation of the device. The first bit is the read/write bit,
the following two are address bits, and the remaining 10
are the desired data bits. The read/write bit determines
whether the register is being written to or read from. The
next two address bits select the desired register to write
or read from. These address bits can be seen in Table 2.
Table 3 describes the contents of the four registers.
Figure 1 shows the configuration of the internal regis-
ters of the device and Figure 2 shows the timing of the
SPI bus. Register 0 sets the DAC code to the desired
value, register 1 selects the step-up code, and register 2
selects the step-down code.
The device also contains a mode control pin (Table 4),
along with UP and DWN controls (Table 5). When MODE
is 0, the contents of register 0 get loaded into the 10-bit
DAC register and set the value of the on-chip DAC. In this
condition, the UP and DWN control pins have no effect on