YLCDRZA1H HIGH RESOLUTION EMBEDDED GUI SOLUTIONS KIT TECHNICAL REFERENCE MANUAL Renesas Electronics America Rev 2.20 Revision Date: Jul 21, 2015 www.renesas.com YLCDRZA1H Technical Reference Manual Disclaimer By using this Renesas YLCDRZA1H, the user accepts the following terms. The YLCDRZA1H is not guaranteed to be error free, and the entire risk as to the results and performance of the YLCDRZA1H is assumed by the User. The YLCDRZA1H is provided by Renesas on an "as is" basis without warranty of any kind whether express or implied, including but not limited to the implied warranties of satisfactory quality, fitness for a particular purpose, title and non- infringement of intellectual property rights with regard to the YLCDRZA1H. Renesas expressly disclaims all such warranties. Renesas or its affiliates shall in no event be liable for any loss of profit, loss of data, loss of contract, loss of business, damage to reputation or goodwill, any economic loss, any reprogramming or recall costs (whether the foregoing losses are direct or indirect) nor shall Renesas or its affiliates be liable for any other direct or indirect special, incidental or consequential damages arising out of or in relation to the use of this YLCDRZA1H, even if Renesas or its affiliates have been advised of the possibility of such damages. Precautions This Renesas YLCDRZA1H is only intended for use in a laboratory environment under ambient temperature and humidity conditions. A safe separation distance should be used between this and sensitive equipment. Its use outside the laboratory, classroom, study area or similar such area invalidates conformity with the protection requirements of the Electromagnetic Compatibility Directive and could lead to prosecution. The product generates, uses, and can radiate radio frequency energy and may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment causes harmful interference to radio or television reception, which can be determined by turning the equipment off or on, you are encouraged to try to correct the interference by one or more of the following measures; * * * * * * Ensure attached cables do not lie across the equipment Reorient the receiving antenna Increase the distance between the equipment and the receiver Connect the equipment into an outlet on a circuit different from that which the receiver is connected Power down the equipment when not in use Consult the dealer or an experienced radio/TV technician for help NOTE: It is recommended that wherever possible shielded interface cables are used. The product is potentially susceptible to certain EMC phenomena. To mitigate against them it is recommended that the following measures be undertaken; * * The user is advised that mobile phones should not be used within 10m of the product when in use. The user is advised to take ESD precautions when handling the equipment. The Renesas YLCDRZA1H does not represent and ideal reference design for an end product and does not fulfill the regulatory standards for an end product. Rev 2.20 Jul 21, 2015 Page 2 of 68 YLCDRZA1H Technical Reference Manual Table of Contents Chapter 1 - Preface ......................................................................................................................................................1 Chapter 2 - Introduction and Purpose .........................................................................................................................2 2.1 - Hardware.........................................................................................................................................................2 2.2 - Hardware Block Diagrams ...............................................................................................................................3 2.3 - Box Contents ...................................................................................................................................................4 2.4 - Software & Software Development Tools .......................................................................................................4 2.5 - Usage Models ..................................................................................................................................................4 2.6 - Versions...........................................................................................................................................................5 Chapter 3 - Getting Started .........................................................................................................................................6 3.1 - Powering the YLCDRZA1H ...............................................................................................................................6 3.2 - See the Demo ..................................................................................................................................................6 3.3 - Connecting to the Segger J-Link On-Board Debugger ......................................................................................6 Chapter 4 - Specifications ...........................................................................................................................................7 4.1 - DC Characteristics ...........................................................................................................................................7 4.2 - AC Characteristics............................................................................................................................................7 4.3 - Environmental Characteristics.........................................................................................................................7 4.4 - Physical Characteristics ...................................................................................................................................7 Chapter 5 - Power .......................................................................................................................................................8 5.1 - Main Power Subsystem ...................................................................................................................................8 5.2 - 3.3V/1.8V Main Baseboard Power Subsystem ................................................................................................8 5.3 - LCD Backlight Power Subsystem......................................................................................................................8 5.4 - LCD Logic and Bias Subsystem .........................................................................................................................8 5.5 - USB Host Power Subsystem ............................................................................................................................9 5.6 - 3.3V/1.18V Module Power Subsystem ............................................................................................................ 9 Chapter 6 - Graphics Capacitive Touch LCD .............................................................................................................10 6.1 - LCD Interface .................................................................................................................................................10 6.2 - Capacitive Touch Controller ..........................................................................................................................11 Chapter 7 - The MCU/Memory Module ...................................................................................................................13 7.1 - Renesas RZ/A1 MCU ......................................................................................................................................13 7.2 - System Reset .................................................................................................................................................13 7.3 - MCU Boot Mode Selection ............................................................................................................................14 7.4 - 64Mbytes SDRAM .........................................................................................................................................14 7.5 - 64Mbytes Dual QSPI Serial NOR FLASH .........................................................................................................14 7.6 - On-Module Clocking ......................................................................................................................................14 7.7 - Spread Spectrum Clock Generator (SSCG) .....................................................................................................15 7.8 - EEPROM ........................................................................................................................................................15 Rev 2.20 Jul 21, 2015 Page 3 of 68 YLCDRZA1H Technical Reference Manual 7.9 - Switches and LEDs .........................................................................................................................................15 Chapter 8 - Baseboard..............................................................................................................................................16 8.1 - Power ............................................................................................................................................................16 8.2 - Clocking .........................................................................................................................................................16 8.3 - LCD Connection and RGB888 to LVDS Translation ........................................................................................16 8.4 - e-MMC Memory ............................................................................................................................................16 8.5 - 10/100 Ethernet Port ....................................................................................................................................17 8.6 - Audio Subsystem ...........................................................................................................................................18 8.7 - Industrial Networking: CAN, RS232, RS485 ...................................................................................................18 8.7.1 - RS232, RS433, and RS485 .......................................................................................................................19 8.7.2 - CAN ........................................................................................................................................................21 8.8 - SD Card Socket ..............................................................................................................................................21 8.9 - USB Host and Device .....................................................................................................................................21 8.10 - Battery Backed Real Time Clock Calendar (RTCC) ........................................................................................22 8.11 - PMOD Port ..................................................................................................................................................22 8.12 - Segger J-Link On-Board Debugger/Programmer .........................................................................................24 8.13 - Ambient Light Sensor ..................................................................................................................................24 8.14 - Digital Video Camera ...................................................................................................................................25 8.15 - Switches ......................................................................................................................................................25 8.16 - LEDs .............................................................................................................................................................26 8.17 - CryptoAuthentication ..................................................................................................................................26 Chapter 9 - External Interrupt Summary ..................................................................................................................27 Chapter 10 - I2C Device Summary ............................................................................................................................28 Chapter 11 - SPI Device Summary ............................................................................................................................29 Chapter 12 - Schematics & Bills of Materials .............................................................................................................31 12.1 - SO-DIMM Detail ..........................................................................................................................................31 12.2 - RZ Module Schematics ................................................................................................................................35 12.3 - RZ Module BOM ..........................................................................................................................................44 12.4 - Baseboard Schematics.................................................................................................................................45 12.5 - Baseboard BOM ..........................................................................................................................................59 Chapter 13 - Post Production Modifications ...............................................................................................................62 13.1 - I/O Baseboard v2.0 .....................................................................................................................................62 Chapter 14 - Additional Information ..........................................................................................................................63 Rev 2.20 Jul 21, 2015 Page 4 of 68 YLCDRZA1H Technical Reference Manual Chapter 1 - Preface Cautions This document may be, wholly or partially, subject to change without notice. All rights reserved. Duplication of this document, either in whole or part is prohibited without the written permission of Renesas Solutions Corporation. Trademarks *All brand or product names used in this manual are trademarks or registered trademarks of their respective companies or organizations. Copyright (c) 2014 Renesas Electronics America, Inc. All rights reserved. (c) 2014 Renesas Electronics Europe Ltd. All rights reserved. (c) 2014 Renesas Electronics Corporation. All rights reserved. (c) 2014 Renesas Solutions Corporation. All rights reserved. Website: http://www.renesas.com/ Glossary CPU Central Processing Unit GUI Graphical User Interface Rev 2.20 Jul 21, 2015 USB Universal Serial Bus Page 1 of 68 YLCDRZA1H Technical Reference Manual Chapter 2 - Introduction and Purpose The Renesas YLCDRZA1H High Resolution Embedded GUI Solution Kit is a flexible and full-featured Human Machine Interface plus communications platform based on the Renesas RZ/A1H Microcontroller. While production worthy, the YLCDRZA1H is primarily intended for software and hardware developers to experiment and evaluate the extensive I/O features of the RZA1H on the YLCDRZA1H prior to development of their own customized and focused hardware daughter-cards and/or add-on hardware adjacent to the host module. The YLCDRZA1H contains several communications ports, including 10/100 Ethernet, CAN, RS232, and RS485, as well as the popular PMODTM connectors for external prototyping modules from Digilent and other vendors. Distributor inventory of Renesas products can be found here. For more information on the Renesas YLCDRX63N Embedded GUI Solution Kit, visit the Renesas website. 2.1 - Hardware The YLCDRZA1H has three main elements: * a re-usable SO-DIMM style module (the "RZ Module") with MCU, DRAM, FLASH, local power and clocks, * a full featured I/O baseboard, and, * a high resolution 1280x800 IPS LCD with LVDS 24-bit color interface and capacitive touch sensing. These elements come pre-assembled in the YLCDRZA1H kit in an acrylic enclosure along with various cables, power supplies, and accessories. The MCU/memory module (the "RZ Module") in the kit includes: * Renesas RZ/A1H MCU with o 10Mbytes on-chip RAM, 400MHz ARM CortexTM-A9 processor o 32-Kbyte L1 instruction cache, a 32-Kbyte L1 data cache, and a 128-Kbyte L2 cache o 10-Mbyte large-capacity on-chip high-speed RAM with parallel data/address paths o OpenVG*-compliant Renesas graphics accelerator with JPEG encoder/decoder, capture engine unit, and pixel format converter Rev 2.20 Jul 21, 2015 Page 2 of 68 YLCDRZA1H * * * * Technical Reference Manual 64Mbytes DRAM 64Mbytes Serial boot/XIP NOR FLASH in a dual-QSPI (x8) configuration On-DIMM power supplies for all on-module circuits 32.768kHz RTCC crystal and MCU clocks The I/O Baseboard includes: * 4GBytes e-MMC intelligent NAND flash "drive on chip" * 9-25VDC barrel jack power input; standard 12V 10W EU/US wall adapter included in the kit * CAN plus RS232/RS485 port on a 3.5mm screw terminal plug connector * Digilent PMOD port with Type 2A (expanded SPI) and Type 4A (expanded UART) support * 10/100 Ethernet Port on standard RJ45 CAT5/6 jack with dual indicator LEDs * Stereo Audio with Dual 1W speakers, line in, line out, headset-style headphone out/microphone in * Color VGA forward facing digital video camera * SD Card socket (SDIO) * High Speed USB 2.0 Host and Device ports * Coin-cell battery-backed real time clock * 0 to 50C operating temperature range * Segger J-Link On Board programmer/debugger * Ambient light sensor, reset button, power indicator LED 2.2 - Hardware Block Diagrams The RZ Module conceptually is structured as follows: Rev 2.20 Jul 21, 2015 Page 3 of 68 YLCDRZA1H Technical Reference Manual The baseboard incorporates the module as follows: 2.3 - Box Contents The following items are included in the YLCDRZA1H package: * YLCDRZA1H assembly, including I/O baseboard, LCD display, and RZ module, camera in an acrylic demo enclosure with adhesive silicone feet * 9-25VDC US/EU Wall Power Supply * 8 pin screw terminal plug for CAN/RS232/RS485 port * Ethernet cable (1) and USB Micro B cables (2) 2.4 - Software & Software Development Tools Renesas and their Platinum Partners, including Serious Integrated and Express Logic have developed numerous example projects demonstrating the various features of the YLCDRZA1H. Visit the Renesas website for more information. Development for the YLCDRZA1H is supported under the Renesas e2Studio Eclipse-based framework, ARM(R) DS-5 Development Studio, as well as the IAR Embedded Workbench. No-cost fully-unlocked GNU C development tools from Renesas are available, as well as professional and fully-supported tools from IAR. 2.5 - Usage Models The YLCDRZA1H is designed as an initial hardware reference platform as well as software development platform for OEM applications not only requiring sophisticated LCD-based GUI Human Machine Interface (HMI) capabilities but also extensive communications. The platform has little to no GPIO control on-board, and generally will be used in conjunction with an OEM's I/O subsystem, possibly communicating with the YLCDRZA1H over RS232, RS485, or UART/SPI using the PMOD connectivity. For more extensive GPIO connectivity, more flexible port assignments and experimentation with MCU features, the complete Renesas RZ/A1H Development Kit YR0K77210S003BE is recommended. Rev 2.20 Jul 21, 2015 Page 4 of 68 YLCDRZA1H Technical Reference Manual 2.6 - Versions The production version of the MCU/Memory module is v2.0 as marked on the module silk screen. All units in circulation should have this version. Two versions of the Baseboard have been distributed, marked v2.0 and v2.1 on the silk screen respectively. The v2.1 Baseboard has two notable changes from v2.0: 1) The USBH Power Enable, hardwired to "always on" in v2.0, is now connected through an inverter to P1.6. On power up, the USBH power delivery is disabled. When the port pin is asserted low, the inverted (active high) signal enables the USBH Power subsystem. 2) Improved USB signal routing/integrity for more reliable High Speed operation Rev 2.20 Jul 21, 2015 Page 5 of 68 YLCDRZA1H Technical Reference Manual Chapter 3 - Getting Started The YLCDRZA1H assembly comes pre-assembled, and requires no initial assembly to operate out of the box. Some elements, such as the LCD to the top acrylic ring, are bonded with high performance adhesive: do not attempt to detach the LCD from the acrylic or disassemble any element not fastened by simple nylon screws. The RZ Module comes pre-inserted into the SO-DIMM socket and fastened to the Baseboard via two screws. Only remove/install this module with the power completely removed. 3.1 - Powering the YLCDRZA1H The YLCDRZA1H can only be powered via the barrel jack, and can accept any input voltage from 9 to 25VDC (center positive) power supply with 10W or more capability; the kit comes with a standard UL/CSA/CE 12V 10W adapter with both an EU and US capability more than sufficient to power the unit. Plugging in the 12V adapter will light up the green LED near the barrel jack, confirming the board is powered. The RZ Module also has a local green power LED showing that it, too, is powered. The Baseboard LED near the barrel jack may flash orange - this is the Segger J-Link debugger activity notification. 3.2 - See the Demo A demo, pre-installed in the RZ Module's serial FLASH, will start up when the module is first powered. If during the course of software development this demo is erased from the serial FLASH you can download this demo from the Renesas website and re-install it using your software development tools and the on-board Segger J-Link On-Board debugger. 3.3 - Connecting to the Segger J-Link On-Board Debugger The kit comes with two (2) USB Micro B cables suitable for connecting a PC to the YLCDRZA1H. Use one of these to connect to the USB Micro connector J9 near the power jack. This is your debugger connection, and is only required when doing software development with the YLCDRZA1H. Rev 2.20 Jul 21, 2015 Page 6 of 68 YLCDRZA1H Technical Reference Manual Chapter 4 - Specifications 4.1 - DC Characteristics The DC characteristics of the I/O elements of the platform are governed by the underlying AC timing characteristics of the individual components. Consult the bill of materials and component data sheets for more information. Specification Input Voltage to Barrel Jack Input Power to Barrel Jack Minimum 9 Permissible Typical Maximum 12 25 10 Unit VDC W 4.2 - AC Characteristics The AC timing characteristics at the module level are governed by the underlying AC timing characteristics of the individual components. Consult the bill of materials and component data sheets for more information. 4.3 - Environmental Characteristics The YLCDRZA1H, while designed with production-worthy methods and components, is not designed as a production unit to be used direction in OEM equipment. Contact Renesas for a list of hardware design partners who can develop and deliver production-ready platforms based on the ingredients used in the YLCDRZA1H kit. Specification Operating Temperature Storage Temperature Humidity (Non-condensing) Minimum 0 -20 Permissible Typical Maximum 50 60 90%@50C Unit C C RH 4.4 - Physical Characteristics The outer dimensions of the YLCDRZA1H, with acrylic enclosure, are approximately 207mm x 53mm x 33mm. Rev 2.20 Jul 21, 2015 Page 7 of 68 YLCDRZA1H Technical Reference Manual Chapter 5 - Power The YLCDRZA1H has 6 different power subsystems on board: * * Baseboard Power: o Main power input 9-25VDC in, 5VDC out 2A buck switcher o 3.3V/1.8V buck switcher for Baseboard logic and I/O o LCD Backlight boost constant-current supply o LCD bias and drive voltage boost supplies o USB Host 150mA current-limited supply RZ Module Power o 3.3V/1.18V buck switcher for local RZ Module clocks, memory, and the MCU Many of these may not be needed in your own derivative designs, but are included in the design so you can pick and choose depending on your specific requirements. A detailed discussion of each subsystem follows. 5.1 - Main Power Subsystem The YLCDRZA1H can accept 9-25VDC from the Switchcraft RASM712PX barrel jack. The jack is designed to accept an industry-standard 5.5mm OD/2.5mm ID barrel plug with positive center. The two power signals +VIN and GND are connected downstream directly to the main buck converter which delivers 5VDC at up to 2A (via signal +5V) to the whole assembly for use by various subsystems and further regulation. No other circuits on the YLCDRZA1H use the 9-25VDC +VIN power signal. The +5V power signal directly powers the green portion of the Baseboard tri-color LED. The red portion of that LED is driven by the Segger J-Link On Board activity indicator. The +5V power signal is the only power delivered for use by the RZ Module, which has its own subsequent regulation on-module. 5.2 - 3.3V/1.8V Main Baseboard Power Subsystem Almost all the circuits on the Baseboard require 3.3 volts. The camera module and audio subsystem, in addition, both requires 1.8V. A dual buck switcher takes the +5V power signal and delivers 3.3V at up to 2A (+3V3) for most circuits on the board as well as 1.8V (+1V8) required by the audio subsystems. 5.3 - LCD Backlight Power Subsystem The LCD on the YLCDRZA1H is backlit by an array of LEDs. This array requires a constant current supply of 100 mA at approximately 12.8VDC. The ability to pulse width modulate (PWM) this supply is important to enable wellcontrolled backlight dimming, and the ability to turn off the backlight is important for power management - 100mA at 12.8V is approximately 1.3W of power, and factoring in the boost conversion efficiency approximately 1.6W of power from the input supply. Unlike other power systems where typical is normally much less than maximum, this is a typical number as the LEDs are actually run at this power. The +5V main power signal feeds a constant current boost controller delivering this 100mA to the LCD backlight. A PWM-capable MCU port bit is connected to this controller's ENABLE# pin: MCU Schematic Operation Port Function Module # Baseboard P8.12 PWM1E P8_12/PWM1EBLEN 18 RZM-BLEN LCD Backlight Enable (active high) 5.4 - LCD Logic and Bias Subsystem As is common with most LCDs, the LCD panel in the kit requires a 3.3V supply. In this case, the 3.3V supply must be up to 300mA and is provided by the 5.2 - 3.3V/1.8V Main Baseboard Power Subsystem signal +3V3. This power supply is always on when the system is powered. Rev 2.20 Jul 21, 2015 Page 8 of 68 YLCDRZA1H Technical Reference Manual LCD panels also need a variety of other voltages to drive the LCD active elements, and most small LCD panels have all the voltage converters internally in the panel to make the system designer's life easy. As the panels increase in size, these voltages are often expected from the system rather than generated in the panel, especially for thin panels with minimal internal space. In addition to 3.3V, the panel on the YLCDRZA1H requires all these voltages to be supplied: The Baseboard has a complete power generation subsystem for these other voltages. This subsystem is also always enabled when the system is powered. 5.5 - USB Host Power Subsystem While the USB host A connector could have been driven directly from +5V (or at least via a high-side FET power switch for enable control), the design incorporates a 150mA current limited design to ensure that an inappropriate high-load device does not crash the board or overstress the main power system. At currents above 150mA, the voltage on the output to the connector drops precipitously to limit the current. MCU Schematic Operation Port Mode Module # Baseboard P1.6 VBUSIN1 VBUSIN1 41 RZM-USBF_VBUS USB Device ("Function") VBUS Detect see below 1P1_6-USBH_5V_EN# 13 RZM-USBH_5V_EN# 2 USB Host VBUS Power Out Enable (active low) VBUSIN0 VBUSIN0 43 RZM-USBH_VBUS USB Host VBUS Detect USB Host VBUS Overcurrent Detect (active low) On v2.0 units, P1.6 was incorrectly used to drive the USB Host Power Enable (RZM-USBH_5V_EN on the RZ Module; DIMM pin 132). This port is open drain only on the MCU, and is incapable of driving high and enabling the power supply. All v2.0 units should include a post-production modification connecting U21 pin 7 (ENUSB) to U21 pin 8 (FAULT#) to enable the USB supply during all non-overcurrent situations. Version 2.1 units have an inverter with input pull-up added to this path. In this configuration, the RESET# condition disables the USB Host Power Enable, and asserting P1_6 low enables the USB Host Power. P1.12 TINT20/GPI P1_12/TINT20-USBH_OC 56 RZM_USBH_OC# Software intending on using the USB Host Power Subsystem needs to accommodate both the v2.0 with post-production modification as well as the v2.1 units, since in the former case the USBH_5V_EN# pin should not be driven low and in the latter, driving it low is required to enable USB Host power. During driver initialization, perform the following sequence to determine a v2.0 vs. v2.1 baseboard: Set USBH_5V_EN# to low USBH_EnableValue = inverse of read value of USBH_OC# On v2.1, setting USBH_5V_EN# low will drive the enable high (via the inverter); assuming a non-overcurrent situation immediately after the enable the read value of OC# will be high, indicating a 2.1 board. On v2.0, setting USBH_5V_EN# low drive the enable low (no inverter), which since pin 7 & 8 are tied together, we'll see an overcurrent active (low) as well, indicating a 2.0 board. Use the inverted value of the OC# test read from now on in the driver to enable or disable the USB Host Power subsystem. 5.6 - 3.3V/1.18V Module Power Subsystem The RZ Module is powered by the +5V power signal from the Baseboard. The MCU, memory, and clocks on the module require 3.3V and the MCU requires 1.18V for its core voltage. The RZ Module contains a dual 5V in dual output 3.3/1.18V buck switcher that delivers the voltages exclusively for the module's usage as module schematic signals +3V3 and +1V18 respectively. These are not joined with any power signals on the Baseboard except by sharing a common system ground. Rev 2.20 Jul 21, 2015 Page 9 of 68 YLCDRZA1H Technical Reference Manual Chapter 6 - Graphics Capacitive Touch LCD One of the most important features of the YLCDRZA1H is the high resolution LCD graphic color display with the following characteristics: * 1280x800 pixel resolution * In Plane Switching (IPS) technology for excellent visibility at nearly any viewing angle * Integrated capacitive touch controller * 24-bit color Low Voltage Differential Signaling (LVDS) interface 6.1 - LCD Interface Lower resolution displays, typically at and below 800x480 (WVGA), use parallel RGB (red green blue) interfaces, for example 8 bits for red, 8 for blue, and 8 for green over a 24-bit wide cable to the LCD along with other control signals such as clock, data enable, vertical, and horizontal sync. The RZ/A1H has a built-in RGB LCD interface capable of driving such displays at 16, 18, or 24 bits wide for RGB565 (65,536 color), RGB666 (262,144 color), or RGB888 (16M color) support respectively. As pixel resolutions increase, the electrical noise generated and routing challenges due to wide high speed parallel buses over the 3-10" cable to the LCD become problematic and a few Low Voltage Differential Signal (LVDS) channels are used where each color (red, green, blue) along with and the control signals are encoded and serialized, often resulting in an 8 signal cable (4 differential pairs). The Renesas RZ/A1H MCU, in addition to its 24-bit RGB interface, also has an 18-bit color LVDS interface. The MCU's LVDS interface is very well suited to many high-resolution OEM applications. It is very cost effective, requiring smaller cables and connectors than parallel RGB and is natively supported by the MCU with minimal external components beyond a few impedance matching resistors. For lower resolution applications, typically 800x480 and below, the RGB interface is an excellent solution. In order to fully highlight the capabilities of the MCU's graphics controller, the YLCDRZAH1 uses the full 24-bit color RGB888 interface. However the LCD panel is an LVDS panel. The YLCDRZA1H Baseboard includes a low cost RGB888 to LVDS serializer to convert the signal format from the MCU to the LCD's required timing/orientation: Rev 2.20 Jul 21, 2015 Page 10 of 68 YLCDRZA1H Technical Reference Manual Both the MCU's RGB and LVDS interfaces are fully exposed to the RZ Module's edge fingers, however the LVDS signals are not connected or used on the YLCDRZA1H Baseboard. The RZ Module chapter describes the edge finger assignment. A baseboard could be designed that uses the RZ Module and employs the LVDS rather than RGB interface. The LCD RGB data, control and power signals are wired on the YLCDRZA1H assembly as follows: Port MCU Function Module Schematic # Baseboard Operation P8.12 PWM1E P8_12/PWM1E-BLEN 18 RZM-BLEN LCD Backlight Enable (active high) P3.0 LCD0_CLK P3_0/LCD_CLK 23 RZM-LCD_CLK Dot Clock P11.8 LCD0_TCON6 P11_8/LCD_DEN 3 RZM-LCD_DEN Data Enable P11.9 LCD0_TCON5 P11_9/LCD_VSYNC 5 RZM-LCD_VSYNC Vertical Sync P11.10 LCD0_TCON4 P11_10/LCD_HSYNC 8 RZM-LCD_HSYNC Horizontal Sync P11.7 LCD_DATA0 P11_7/LCD_DATA0 4 RZM-LCD_DATA0 Blue 0 (LSB) P11.6 LCD_DATA1 P11_6/LCD_DATA1 6 RZM-LCD_DATA1 Blue 1 P11.5 LCD_DATA2 P11_5/LCD_DATA2 199 RZM-LCD_DATA2 Blue 2 P11.4 LCD_DATA3 P11_4/LCD_DATA3 197 RZM-LCD_DATA3 Blue 3 P11.3 LCD_DATA4 P11_3/LCD_DATA4 177 RZM-LCD_DATA4 Blue 4 P11.2 LCD_DATA5 P11_2/LCD_DATA5 183 RZM-LCD_DATA5 Blue 5 P11.1 LCD_DATA6 P11_1/LCD_DATA6 175 RZM-LCD_DATA6 Blue 6 P11.7 LCD_DATA0 P11_7/LCD_DATA0 181 RZM-LCD_DATA7 Blue 7 (MSB) P4.0 LCD_DATA8 P4_0/LCD_DATA8 103 RZM-LCD_DATA8 Green 0 (LSB) P4.1 LCD_DATA9 P4_1/LCD_DATA9 66 RZM-LCD_DATA9 Green 1 P4.2 LCD_DATA10 P4_2/LCD_DATA10 68 RZM-LCD_DATA10 Green 2 P4.3 LCD_DATA11 P4_3/LCD_DATA11 70 RZM-LCD_DATA11 Green 3 P4.4 LCD_DATA12 P4_4/LCD_DATA12 105 RZM-LCD_DATA12 Green 4 P4.5 LCD_DATA13 P4_5/LCD_DATA13 78 RZM-LCD_DATA13 Green 5 P4.6 LCD_DATA14 P4_6/LCD_DATA14 82 RZM-LCD_DATA14 Green 6 P4.7 LCD_DATA15 P4_7/LCD_DATA15 111 RZM-LCD_DATA15 Green 7 (MSB) P5.0 LCD_DATA16 P5_0/LCD_DATA16 142 RZM-LCD_DATA16 Red 0 (LSB) P5.1 LCD_DATA17 P5_1/LCD_DATA17 144 RZM-LCD_DATA17 Red 1 P5.2 LCD_DATA18 P5_2/LCD_DATA18 154 RZM-LCD_DATA18 Red 2 P5.3 LCD_DATA19 P5_3/LCD_DATA19 156 RZM-LCD_DATA19 Red 3 P5.4 LCD_DATA20 P5_4/LCD_DATA20 148 RZM-LCD_DATA20 Red 4 P5.5 LCD_DATA21 P5_5/LCD_DATA21 150 RZM-LCD_DATA21 Red 5 P5.6 LCD_DATA22 P5_6/LCD_DATA22 160 RZM-LCD_DATA22 Red 6 P5.7 LCD_DATA23 P5_7/LCD_DATA23 162 RZM-LCD_DATA23 Red 7 (MSB) 6.2 - Capacitive Touch Controller The LCD on the YLCDRZA1H includes a capacitive touch sensor system and built-in Pixcir Tango C48 controller. The C48 has the following features: * 400kHz I2C interface with activity interrupt out * 5 finger simultaneous multi-touch detection * Palm detection for lock function, and * <100 idle-to-active touch response time. Rev 2.20 Jul 21, 2015 Page 11 of 68 YLCDRZA1H Technical Reference Manual The 7-bit I2C address of the C48 controller is 0x5C: Address I2C Max Location 7-bit Read Write Bus kHz 0x5C 0xB9 0xB8 1 Baseboard 400 Device Pixcir C48 Capacitive Touch Controller Chapter 10 - I2C Device Summary lists all the I2C devices on the YLCRZA1H. On system boot the controller is held in reset with a weak pull-up on the P8_13-TOUCH_RST signal and the driver should drive this signal low to enable the C48 to accept commands. The controller is connected as follows: MCU Schematic Operation Port Function Module # Baseboard P8.13 GPIO P8_13-TOUCH_RST 7 RZM-TOUCH_RST LCD Touch controller reset (active high) P1.10 IRQ4 P1_10/IRQ4-TOUCH_IRQ 52 RZM-TOUCH_IRQ LCD Touch controller interrupt P1.2 SCL1 P1_2/SCL1 165 RZM-SCL1 Touch dedicated I2C1 Clock P1.3 SDA1 P1_3/SDA1 169 RZM-SDA1 Touch dedicated I2C1 Data The Pixcir Tango C48 instruction set and data sheet are available only under non-disclosure agreement from Pixcir. Rev 2.20 Jul 21, 2015 Page 12 of 68 YLCDRZA1H Technical Reference Manual Chapter 7 - The MCU/Memory Module As discussed, the YLCDRZA1H is comprised of two circuit boards, the Baseboard and the MCU/Memory module, or "RZ Module" that plugs into the Baseboard via a commodity 200 pin SO-DIMM socket. For a complete pin-out of the SO-DIMM socket, see Chapter 12.1 - SO-DIMM Detail. The MCU/memory module (the "RZ Module") in the kit includes: * Renesas RZ/A1H MCU * 64Mbytes DRAM * 64Mbytes Serial boot/XIP NOR FLASH in a dualQSPI (x8) configuration * On-DIMM power supplies for all on-module circuits * 32.768kHz RTCC crystal and 12MHz MCU clock * 2kbit configuration/user EEPROM * On-module system reset The local power supplies are fully described in Section 5.6 - 3.3V/1.18V Module Power Subsystem. 7.1 - Renesas RZ/A1 MCU The Renesas RZ/A1 MCU family has several members; the YLCDRZA1H uses the R7S721001VCBG with the following key features: * 10Mbytes on-chip RAM, 400MHz ARM CortexTM-A9 processor * 32-Kbyte L1 instruction cache, a 32-Kbyte L1 data cache, and a 128-Kbyte L2 cache * 10-Mbyte large-capacity on-chip high-speed RAM with parallel data/address paths * OpenVGTM-compliant Renesas graphics accelerator with JPEG encoder/decoder, capture engine unit, and pixel format converter * SDRAM controller * 324 pin BGA The MCU is fully described in the Renesas RZ/A1H Group User's Manual: Hardware along with other documentation on the Renesas RZ/A1 Family Documentation Website. 7.2 - System Reset The RZ Module includes a small system reset chip, designed to not only reset the MCU but any attached baseboard if desired. On power-up, the system reset is asserted low for approximately 100-250mS and then is released to rise high with a simple pull-up resistor. Pushbutton S3 on the baseboard is connected directly to this reset signal - the reset chip automatically senses the pushbutton and, when pressed (RESET# grounded) debounces the switch and initiates a reset cycle as if power were being applied for the first time. MCU Schematic Operation Port Function Module # Baseboard RES RES Rev 2.20 Jul 21, 2015 RESET# 27 RZM-RESET# System Reset (open drain, active low) Also RESET Pushbutton S3 on Baseboard Page 13 of 68 YLCDRZA1H Technical Reference Manual 7.3 - MCU Boot Mode Selection The RZ/A1H MCU can boot from a variety of memory devices, selectable by the levels present on the MD_BOOT2/1/0 pins on the MCU when RES is de-asserted. The Baseboard includes a 4 element DIP Switch where switch 1 and 2 control MD_BOOT1/2 respectively. Option Boot Mode YLCDRZA1H MD_BOOT2 MD_BOOT1 MD_BOOT0 # Description Support 0 1 0 1 1 1 0 1 0 0 1 1 1 0 1 3 4 5 CS0# RAM/ROM CS1# RAM/ROM Serial FLASH SD Card e-MMC No No Default via Baseboard via Baseboard On the YLDRZA1H, the BOOTMD2/1/0 pins have a default weakly strapped selection to the serial FLASH on the RZ Module (since the module has the serial FLASH populated), but the boot mode can be changed on the Baseboard through DIP switch S1. The boot pins are controlled/connected as follows: MCU Schematic Operation Port Function Module # Baseboard P7.0 MD_BOOT2 P7_0/MD_BOOT2 179 RZM-BOOT2 P0.1 MD_BOOT1 P0_1/MD_BOOT1 61 RZM-BOOT1 P0.0 MD_BOOT0 P0_0/MD_BOOT0 - - Weakly high (47k) on RZ Module S1.2 pulls this low (GND) when ON Weakly low (47k) on RZ Module S1.1 pulls this high (4.7k) when ON Permanently high on RZ Module 7.4 - 64Mbytes SDRAM The Renesas RZ/A1H MCU has a full on-chip 16-bit SDRAM controller. The YLCDRZA1H RZ Module has this SDRAM connection (address, data, control) isolated on the module connected to two (2) Micron 32MByte SDRAM devices for a total of 64MBytes of system DRAM. 7.5 - 64Mbytes Dual QSPI Serial NOR FLASH The Renesas RZ/A1H MCU supports two (2) parallel Quad SPI (QSPI) interfaces designed for direct-attach to Serial NOR FLASH devices. In this configuration, the MCU can boot from the primary device in single-SPI traditional 4-wire (MISO, MOSI, SCLK, SSL#) mode and software can switch access modes such that both devices are accessed simultaneously in QSPI mode for an equivalent 8-bit wide interface at very high speed. Not only can the MCU access these devices as data storage areas, but it can also execute in place (XIP) from the devices at surprisingly high speeds - the MCU's SPI Multi I/O Bus Controller handles all the SPI traffic and FLASH commands to make the devices completely memory mapped and accessible as if it were on a traditional address/data bus. The YLCDRZA1H features two Micron N25Q256A13EF840E NOR Serial FLASH devices with 32Mbytes each, totaling 64Mbytes connected in the Dual QSPI configuration. 7.6 - On-Module Clocking On the RZ Module there are two local clocks for use by the MCU. A simple 32.768 kHz tuning fork crystal is attached to the MCU to drive the on-chip Real Time Clock Calendar (RTCC). There is no VBAT battery backup capability on the chip, so this oscillator must be re-enabled at each MCU reset. The YLCDRZA1H has an I2C Battery Backed RTCC chip with coin cell for this purpose, and on system reset software can retrieve the battery-backed date/time from the external RTCC and load the internal RTCC for quick software access at runtime. While the MCU can operate with as little as a single 12MHz oscillator for the core, USB, and peripherals, to fully exploit the capabilities of the MCU a variety of input clocks are desirable: * 13.3333MHz to enable the core at 400MHz * 27.0MHz for video Rev 2.20 Jul 21, 2015 Page 14 of 68 YLCDRZA1H * * Technical Reference Manual 24.576MHz to deliver industry standard audio frequencies 48.000MHz for USB The RZ Module includes a complete clock oscillator/synthesizer subsystem generating and delivering all four of these frequencies to the MCU. These are not crystals but rather external clock sources to the MCU therefore software should not turn on the crystal oscillator drivers for these clock inputs. The clock synthesizer/generator is a Silicon Labs Si5351C. At power-up, the device is factory programmed for the frequencies listed above, but the Si5351C is an I2C device and the generated frequencies can be modified at runtime if desired. Whether for EMI tuning, power management, or, for example, to change the input frequencies for different audio sampling/generation time bases beyond the capabilities of the MCU's programmable prescaler, this feature can be valuable in many system designs. The Si5351C is available on the I2C bus 0 as device number 0x60: Address I2C Max Location Device 7-bit Read Write Bus kHz 0x60 0xC1 0xC0 0 400 Module Si5351C Clock Synthesizer Chapter 10 - I2C Device Summary lists all the I2C devices on the YLCRZA1H. The interrupt output (INTR) of the Si5351C is not connected to the MCU. 7.7 - Spread Spectrum Clock Generator (SSCG) The Renesas RZ/A1H MCU has the ability to slightly and randomly modulate the internal PLLs to dampen potential and undesirable RF emissions. This feature is controlled by the MCU's MD_CLKS pin, which is weakly (47k) pulled low (disabled) on the RZ Module. The Baseboard DIP Switch S1 position 3 (when ON) strongly (4.7k) pulls this high and enables this feature on the MCU. MCU Schematic Operation Port Function Module # Baseboard P0.3 MD_CLKS/G PIO P0_3/MD_CLKS 176 RZM-SSCG Enables Spread Spectrum Clocking in MCU by Baseboard S1.2 (ON/active GND,OFF pulled high (4.7k) on RZ Baseboard) Note this pin is sampled on the release of system reset, after which a different Baseboard design could optionally use this signal for a GPIO or other function at runtime. 7.8 - EEPROM On the MCU/Memory module is a small I2C EEPROM, an On Semiconductor CAT34C02, located on I2C bus 0 at 7bit address 0x57: Address I2C Max Location Device 7-bit Read Write Bus kHz 0x57 0xAD 0xAC 0 400 Module CAT34C02 EEPROM Chapter 10 - I2C Device Summary lists all the I2C devices on the YLCRZA1H. 7.9 - Switches and LEDs The MCU/Memory module has a single dual-color red and green LED that can be turned on independently and when both are on simultaneously the LED appears orange. The green LED is powered automatically when the local 3.3V power is present. The red LED is controlled by a processor GPIO for software use: Port P11.11 MCU Function GPO Module P11_11-LED1R Schematic # Baseboard Operation Module LED Red (active high) There are no other switches, jumpers or other user I/O on the module. Rev 2.20 Jul 21, 2015 Page 15 of 68 YLCDRZA1H Technical Reference Manual Chapter 8 - Baseboard The I/O Baseboard included with the YLCDRZA1H includes: * * * * * * * * * * * * * * 9-25VDC barrel jack power input with 5V 2A DC-DC converter for Baseboard and RZ Module All local power supplies and clocks RGB888 to LVDS translator and connection to LVDS LCD Connection to the 4GBytes e-MMC intelligent NAND flash "drive on chip" CAN plus RS232/RS485 port on a 3.5mm screw terminal plug connector 10/100 Ethernet Port on standard RJ45 CAT5/6 jack with dual indicator LEDs Stereo Audio with Dual 1W speakers, line in, line out, headset-style headphone out/microphone in Color VGA forward facing digital video camera SD Card socket (SDIO) High Speed USB 2.0 Host and Device ports Coin-cell battery-backed real time clock Digilent PMOD* port with Type 2A (expanded SPI) and Type 4A (expanded UART) support Segger J-Link On Board programmer/debugger User I/O including ambient light sensor, user and reset pushbuttons, user and power LEDs 8.1 - Power The YLCDRZA1H's Baseboard has 5 different power subsystems: * Main power input 9-25VDC in, 5VDC out 2A buck switcher * 3.3V/1.8V buck switcher for Baseboard logic and I/O * LCD Backlight boost constant-current supply * LCD bias and drive voltage boost supplies * USB Host 150mA current-limited supply These are all described in Chapter 5 - Power. 8.2 - Clocking There are several clock sources generated and used on the Baseboard for various peripherals. * 32,768 kHz crystal for the Battery Backed Real Time Clock Calendar (RTCC) * 25.000 MHz oscillator for the 10/100 Ethernet Port * 24.000 MHz oscillator for the Digital Video Camera * Audio clock generated in the RZ MCU on the RZ Module for the Audio Subsystem 8.3 - LCD Connection and RGB888 to LVDS Translation As mentioned above, even though the RZ/A1H has an 18-bit color LVDS port native on the MCU (and brought to the connector for optional use by a baseboard), the YLCDRZA1H elects to feature the full 24-bit color capabilities of the RZ/A1H and use the RGB888 port instead. The LCD display, however, is LVDS. Therefore the baseboard includes a straightforward and inexpensive RBG888 to LVDS translator. This interface, including MCU signals and connector pins, are described in detail in Chapter 6.1 - LCD Interface 8.4 - e-MMC Memory In addition to the memory on the RZ Module, the Baseboard adds a 4 Gigabyte "embedded MultiMedia Card" or eMMC. This is a complete FLASH drive-on-a-chip, with built in wear levelling, bad block management, and more. Software drivers are greatly simplified compared with using NAND FLASH directly. The Micron MTFC4GMDEA-4M Rev 2.20 Jul 21, 2015 Page 16 of 68 YLCDRZA1H Technical Reference Manual is an e-MMC v4.41 compatible device; for more information about the e-MMC specification see the JEDEC MMC Specification. Normally, the e-MMC will be used by a software application to run a file system, such as a FAT file system, storing GUI data and other files, possibly including applications and demos. The RZ/A1H MCU has a built-in MMC controller, and the e-MMC chip is connected as follows: MCU Schematic Operation Port Function Module # Baseboard P0.4 GPO P0_4-MMC_RST# 31 RZM-MMC_RST MMC Reset (active low with pull-up) P3.13 MMC_CMD P3_13/MMC_CMD 97 RZM-MMC_CMD MMC Command/response P3.12 MMC_CLK P3_12/MMC_CLK 91 RZM-MMC_CLK MMC clock P3.11 MMC_D0 P3_11/MMC_D0 93 RZM-MMC_D0 e-MMC Data Bus D0 (LSB) P3.10 MMC_D1 P3_10/MMC_D1 89 RZM-MMC_D1 e-MMC Data Bus D1 P3.15 MMC_D2 P3_15/MMC_D2 99 RZM-MMC_D2 e-MMC Data Bus D2 P3.14 MMC_D3 P3_14/MMC_D3 64 RZM-MMC_D3 e-MMC Data Bus D3 P11.12 MMC_D4 P11_12/MMC_D4 187 RZM-MMC_D4 e-MMC Data Bus D4 P11.13 MMC_D5 P11_13/MMC_D5 191 RZM-MMC_D5 e-MMC Data Bus D5 P11.14 MMC_D6 P11_14/MMC_D6 185 RZM-MMC_D6 e-MMC Data Bus D6 P11.15 MMC_D7 P11_15/MMC_D7 193 RZM-MMC_D7 e-MMC Data Bus D7 (MSB) With 8.16 - DIP Switch S1 set in the correct position and the e-MMC carefully partitioned and programmed, the YLCDRZA1H is capable of booting directly from this device. 8.5 - 10/100 Ethernet Port The RZ/A1H has a full 10/100 Ethernet MAC with MII interface. The RZ Module brings these signals to the edge connector, and the YLCDRZA1H Baseboard delivers these signals interface through a Micrel KSZ8081MNX MII PHY to a standard RJ45 jack. The MII interface is as follows: MCU Port Function Module Schematic # Baseboard Operation RZM-ET_RESET# Holds PHY in reset (active low) 171 RZM-ET_IRQ PHY Interrupt (active low) P3_3/ET_MDIO 21 RZM-ET_MDIO Management data I/O MDC P5_9/ET_MDC 168 RZM-ET_MDC Management data clock P1.14 COL P1_14/ET_COL 58 RZM-ET_COL Collision detection P2.3 CRS P2_3/ET_CRS 121 RZM-ET_CRS Carrier detection P3.6 RXDV P3_6/ET_RXDV 28 RZM-ET_RXDV Receive data valid P3.5 RXER P3_5/ET_RXER 36 RZM-ET_RXER Receive error P3.4 RXCLK P3_4/ET_RXCLK 40 RZM-ET_RXCLK Receive clock P2.8 RXD[0] P2_8/ET_RXD0 137 RZM-ET_RXD0 Receive data 0 (LSB) P2.9 RXD[1] P2_9/ET_RXD1 118 RZM-ET_RXD1 Receive data 1 P2.10 RXD[2] P2_10/ET_RXD2 122 RZM-ET_RXD2 Receive data 2 P2.11 RXD[3] P2_11/ET_RXD3 131 RZM-ET_RXD3 Receive data 3 (MSB) P2.0 TXCLK P2_0/ET_TXCLK 80 RZM-ET_TXCLK Transmit clock P2.1 P2.1/ET_TXER P2_1/ET_TXER 86 RZM-ET_TXER Transmit Error or GPIO (unused on Baseboard) P2.2 TXEN P2_2/ET_TXEN 104 RZM-ET_TXEN Transmit enable P2.4 TXD[0] P2_4/ET_TXD0 129 RZM-ET_TXD0 Transmit data 0 (LSB) P2.5 TXD[1] P2_5/ET_TXD1 110 RZM-ET_TXD1 Transmit data 1 P0.5 GPO P0_5-ET_RESET# P1.5 IRQ5 P1_5/IRQ5-ET_IRQ P3.3 MDIO P5.9 Rev 2.20 Jul 21, 2015 29 Page 17 of 68 YLCDRZA1H Technical Reference Manual P2.6 TXD[2] P2_6/ET_TXD2 135 RZM-ET_TXD2 Transmit data 2 P2.7 TXD[3] P2_7/ET_TXD3 120 RZM-ET_TXD3 Transmit data 3 (MSB) In order to use the Ethernet interface, a globally unique 48-bit MAC address is required. Most companies purchase batches of thousands of these to assign to their devices. To simplify the demonstration of the YLCDRZA1H, the Baseboard includes a tiny I2C chip, the Microchip 24AA02E48T, which contains a single unique MAC address that software can retrieve and use for the board: Address I2C Max Location Device 7-bit Read Write Bus kHz 0x50 0xA1 0xA0 0 400 Baseboard 24AA02E48T EEPROM/MAC Address 8.6 - Audio Subsystem One of the features of the Renesas RZ/A1 family is extensive support for external audio codecs for audio input/output. The YLCDRZA1H highlights this capability using the Maxim MAX98089ETN+ Audio Codec/Amplifier, exposing: * * * * stereo line in jack (blue) stereo line out jack (green) stereo headphone and microphone mobile phone headset-style jack (black) stereo amplified bass-enhanced "B-Bass" speakers from BeStar The codec is connected to the high performance full-duplex Serial Sound Interface (SSI) on the RZ MCU as follows: MCU Schematic Operation Port Function Module # Baseboard CLKAUDIO_24MHZ 67 RZM-AUDIO_CLK 24MHz Base Codec Clock from RZ Module P1.9 IRQ3 P1_9/IRQ3-AUDIO_IRQ 63 RZM-AUDIO_IRQ Audio Codec Interrupt P10.12 SSICLK1 P10_12/SSISCK 108 RZM_SSISCK Serial Sound Interface Clock P10.13 SSIWS1 P10_13/SSIWS 133 RZM_SSIWS Serial Sound Word Select P10.15 SSITxD1 P10_15/SSITxD 112 RZM_SSITxD Serial Sound Transmit Data (output) P10.14 SSIRxD1 P10_14/SSIRxD 116 RZM_SSIRxD Serial Sound Receive Data (input) The Maxim codec is an I2C controlled device, appearing on I2C Bus 0 at 7-bit I2C address 0x20: Address I2C Max Location Device 7-bit Read Write Bus kHz 0x10 0x21 0x20 0 400 Baseboard MAX98089ETN+ Audio Codec/Amplifier 8.7 - Industrial Networking: CAN, RS232, RS485 The large green 3.5mm connector J13 delivers RS232, RS422, or RS485 as well as high performance CAN to external industrial networks. A screw terminal plug is supplied, enabling easy wiring of termination or daisy chained cabling. The connector's signals are clearly marked on the Baseboard PCB as follows: Rev 2.20 Jul 21, 2015 Page 18 of 68 YLCDRZA1H Technical Reference Manual Pin 1 2 3 4 5 6 7 8 Name GND RS485_A RS485_B RS485_X RS485_Y CANH CANL Description No connection Ground Receive non-inverting input Receive inverting input Transmit non-inverting output Transmit inverting output CAN Transmit/Receive H CAN Transmit/Receive L There is no termination facility on the YLCDRZA1H; if cable termination is required insert a 75 ohm resistor across the appropriate signals at the screw-in connector. Note that two additional UARTs and an additional CAN port are available on the PMOD Port; only one of those UARTs is in a standard Digilent PMOD configuration however it is possible to create custom non-standard PMODs for that port and access these extra serial interfaces. 8.7.1 - RS232, RS433, and RS485 The YLCDRZA1H employs an Intersil ISL41387IRZ-T multi-protocol transceiver has the following key features: * * * * * * * * * Selectable RS232 or RS485/RS422 15kV (HBM) ESD protected Single ended or differential Half or full duplex Large (2.7V) differential VOUT for improved noise immunity in RS485/RS422 networks Full failsafe (open/short) RX in RS485/RS422 mode RS232 transmit rates up to 650kbps, receive rates to 2mbps RS485/RS422 data rates up to 20Mbps RS485/RS422 slew rate limit options for 460kbps and 115kbps It is an excellent choice for many RS485 point-to-point and multi-drop networks and works particularly well in many industrial PLC configurations. The dual mode support enables, via the S4 DIP switch, RS232 instead of RS485 levels. Only one mode (RS232 or RS422/485) can be supported at any given time, and the mode is not software selectable - it is assumed that the installation process and environment determines which transmission standard is being connected. The transceiver is connected to the MCU's UART as follows: MCU Schematic Port Function Module # Baseboard Operation P8.10 GPO P8_10/RS_DEN 11 RZM-RS_DEN Transmit Drive Enable (active high) P8.11 GPO P8_11/RS_ON 9 RZM-RS_ON Transceiver Enable (active high) P3.1 TxD2 P3_1/UART_TX 25 RZM_UART_TX Transmit Data P3.2 RxD2 P3_2/UART_RX 15 RZM-UART_RX Receive Data The DIP Switch S4 enables a variety of features on this port. The legend on the Baseboard PCB can help with these settings. Rev 2.20 Jul 21, 2015 Page 19 of 68 YLCDRZA1H Technical Reference Manual RS232 or RS422/RS485 Mode DIP switch S4.3 controls which standard the transceiver conforms to; setting this switch ON puts the transceiver in RS232 level mode; the switch OFF puts the transceiver in RS422/RS485 mode. Slew Rate and Speed Limiting (RS422/RS485 only) In RS422/485 mode, DIP switch S4.1 and S4.2 control the slew rate and speed limits respectively. Set these switches as slow as possible but adequate for the target network rate according to the table. RSXXX Half/Full Duplex Selection The RSXXX port can operate in full duplex mode where data can be independently and simultaneously flowing in the receive and out the transmit pins. It can also be configured to operate in half duplex mode where input/output data is often carried on the same wire(s) and the directionality takes turns. The main difference between the modes lies in how the transmit and receive enable of the transceiver are configured and used. In full duplex mode, the transceiver receive data is always enabled and being processed by the RZ MCU. In half duplex mode, the receive data is only valid when not transmitting - this avoids receive MCU algorithms from "seeing" the same data that they send if the network shares the same wires for transmit and receive. Full duplex mode always implies separate network wires for transmit and receive. Even then, you may not want to always have your transmitter enabled - there are many custom networks where the "master" in a network owns one network wire (or pair in differential mode) and can broadcast at any time to the "slaves" whereas the slaves must share the return line according to some convention to avoid collisions. Given the many possible combinations on custom networks, there are two key elements that need to be addressed: 1. Is the receiver always on, delivering data to the MCU's UART all the time, or is the network wiring half duplex and the receiver disabled during transmission to avoid "seeing your own packets"? 2. Is the transmitter always on, or must it be only turned on when the UART transmits on the network? Receive Enable: Full and Half Duplex Selection DIP switch S4.4 controls how the RSXXX transceiver's receiver is enabled. When S4.4 is OFF (full duplex mode), a weak pull-up on the RSXXX transceiver's RXEN pin ensures that by default the RSXXX transceiver's receiver is always enabled and delivering data to the MCU. When S4.4 is ON (half duplex mode), the RSXXX transceiver's RXEN pin is connected to GND. In this mode, the RSXXX transceiver's receive enable is controlled by its RXEN# which is connected to the opposite polarity DEN (drive enable) pin. In this configuration, whenever the transmitter is enabled, the receiver is disabled and the receive data "marks idle" with a weak pull-up. Transmit Enable The transceiver's transmit drive enable (DEN) pin (when asserted/high) turns on the output drivers on the transceiver and presents UART transmit data onto the network. To avoid any network glitches on power-up, this is always held low (inactive) until the MCU explicitly asserts this signal active/high. Rev 2.20 Jul 21, 2015 Page 20 of 68 YLCDRZA1H Technical Reference Manual 8.7.2 - CAN The CAN transceiver on the YLCDRZA1H Baseboard is implemented with an Infineon IFX1050GVIO or similar device with the following specifications: CAN data transmission rate up to 1 Mbaud Suitable for 12V and 24V network applications Excellent EMC performance (very high immunity and very low emission) ISO/DIS 11898 compatible The transceiver is connected to the MCU's CAN1 port as follows: MCU Schematic Port Function Module # Baseboard Operation P5.10 CAN1TX P5_10/CAN1TX 170 RZM-CANTX CAN Transmit Data P1.4 CAN1RX P1_4/CAN1RX 134 RZM_CANRX CAN Receive Data 8.8 - SD Card Socket The full sized SD Card socket on the Baseboard is connected directly to the MCU via the Renesas RZ/A1H's built-in SD Card controller, channel 0: Port MCU Function Module Schematic # Baseboard Operation P4.13 SD_CMD_0 P4_13/SD_CMD 98 RZM-SD_CMD SD Command/Response P4.12 SD_CLK_0 P4_12/SD_CLK 96 RZM-SD_CLK SD Clock P4.8 SD_CD_0 P4_8/SD_CD 115 RZM-SD_CD SD Card Detect (active low, pulled high) P4.9 SD_WP_0 P4_9/SD_WP 84 RZM-SD_WP SD Write Protect (active low, pulled high) P4.11 SD_D0_0 P4_11/SD_D0 119 RZM-SD_D0 SD Data Bus D0 (LSB) P4.10 SD_D1_0 P4_10/SD_D1 92 RZM-SD_D1 SD Data Bus D1 P4.15 SD_D2_0 P4_15/SD_D2 106 RZM-SD_D2 SD Data Bus D2 P4.14 SD_D3_0 P4_14/SD_D3 123 RZM-SD_D3 SD Data Bus D3 (MSB) With 8.16 - DIP Switch S1 set in the correct position, and an SD Card correctly formatted inserted in the SD Card socket, the YLCDRZA1H is capable of booting directly from this device. 8.9 - USB Host and Device The Renesas RZ/A1H MCU features independent USB 2.0 host and USB 2.0 device (or "function") ports, both capable of 480mbps data rates. The USB Device port is exposed via a standard USB Micro B connector on the YLCDRZA1H Baseboard and is connected to the MCU as follows: MCU Schematic Operation Port Function Module # Baseboard VBUSIN1 VBUSIN1 41 RZM-USBF_VBUS USB Device ("Function") VBUS Detect DP_0 USBF_P 37 RZM-USBF_P USB Device ("Function") D+ DP_1 USBF_N 35 RZM-USBF_N USB Device ("Function") D- The USB host port is exposed via a standard USB A connector on the YLCDRZA1H Baseboard, and is current limited to 150mA to prevent inappropriately large current devices from affecting the operation of the YLCDRZA1H system. See Chapter 5.5 - USB Host Power Subsystem for more information. The port is connected to the MCU as follows: Rev 2.20 Jul 21, 2015 Page 21 of 68 YLCDRZA1H Port P1.6 Technical Reference Manual MCU Function Schematic # Baseboard Module see note 1P1_6-USBH_5V_EN# 1 132 RZM-USBH_5V_EN# USBH_5V USB Host VBUS Power Out Enable (active low) USB Host VBUS Power Out VBUSIN0 43 RZM-USBH_VBUS USB Host VBUS Detect TINT20/GPI P1_12/TINT20-USBH_OC 56 RZM_USBH_OC# USB Host VBUS Overcurrent Detect (active low) DP_1 USBH_P 47 RZM-USBH_P USB Host D+ VBUSIN0 P1.12 Operation DM_1 USBH_N 49 RZM-USBH_N USB Host Don v2.0 units, P1.6 was incorrectly used to drive the USB Host Power Enable (RZM-USBH_5V_EN on the RZ Module; DIMM pin 132). This port is open drain only on the MCU, and is incapable of driving high and enabling the power supply. All v2.0 units should include a post-production modification connecting U21 pin 7 (ENUSB) to U21 pin 8 (FAULT#) to enable the USB supply during all non-overcurrent situations. Version 2.1 units have an inverter with input pull-up added to this path. In this configuration, the RESET# condition disables the USB Host Power Enable, and asserting P1_6 low enables the USB Host Power. 1 8.10 - Battery Backed Real Time Clock Calendar (RTCC) The Renesas RZ/A1H MCU has a built-in Real Time Clock Calendar (RTCC), and the RZ Module provides a 32.768 kHz dedicated crystal to enable precise timekeeping while power is connected. Often network connected , systems can fetch the current time from the network on boot and program the MCU's RTCC to the correct time, which will be maintained for the duration of the powered session. The Baseboard adds an extra feature: a separate lithium coin-cell backed I2C RTCC subsystem. The NXP PCF8523 RTCC requires less than a few hundred nano Amperes to operate and the small CR1025 3V 30mAH coin cell can keep the RTCC running for several years without replacement. When replacing the battery, ensure correct orientation: the flat side (+) should be up and away from the PCB surface, and the rounded side (-) should be contacting the PCB surface. The NXP RTCC is an I2C controlled device, appearing on I2C Bus 0 at 7-bit I2C address 0x68: Address I2C Max Location Device 7-bit Read Write Bus kHz 0x68 0xD1 0xD0 0 1000 Baseboard PCF8523 Real Time Clock Calendar Chapter 10 - I2C Device Summary lists all the I2C devices on the YLCRZA1H. YLCDRZA1H v2.1 Baseboards have an additional R/C circuit on the main power input as recommended by NXP to improve battery to main power switchover. 8.11 - PMOD Port The YLCDRZA1H has one Digilent PMODTM compatible 2x6 host port. It supports, depending on MCU configuration and software, one of these standard PMOD configurations: * Type 1 - GPIO * Type 2 - SPI * Type 2A - Expanded SPI * Type 4 - UART without CTS/RTS flow control * Type 4A - Expanded UART without CTS/RTS flow control For information on the PMOD convention, see the Digilent website, or read the PMOD standard. Rev 2.20 Jul 21, 2015 Page 22 of 68 YLCDRZA1H Technical Reference Manual The PMOD port on the YLCDRZA1H also has some non-standard and unique features you can exploit with custom cards. Normally with PMOD mode 2/2A/4/4A support, you choose SPI or UART mode. The YLCDRZA1H's PMOD offers the following choices: * SPI (standard pin-out mode 2/2A) * UART (standard pin-out mode 4/4A) * UART + CAN (both non-standard pin-out) * UART + UART (one UART standard pin-out, one non-standard) These ports do not have transceivers, are in addition and separate from the Industrial Networking: CAN, RS232, RS485 ports which have full transceivers on the Baseboard. With custom PMOD-like cards, or a simple wire harness from the YLCDRZA1H's PMOD connector, you can access this additional functionality. Contact Renesas for information about any example cards available. Pay special attention to the pin order of the PMOD connectors: it is not the zigzag numbering convention normally used for headers. Incorrectly wiring to the PMOD connectors may damage your YLCDRZA1H or even other connected equipment. The PMOD signals are 3.3V only. Do not connect 5V or higher signals, for example full-level RS232 signals, to this port directly. If, for example, a full-level RS232 port is desired the Digilent PMOD RS232X plugs into the connector and translates these voltages. The PMOD connector signals are connected throughout the YLCDRZA1H as follows; the PMOD pin numbers are per the PMOD (non-zigzag) specification: MCU Schematic PMOD Operation Port Function Module # Baseboard Pin +3V3 12 +3.3V to PMOD GND 11 System GND 10 NC 9 NC P3_7-PMOD_RST# 30 RZM-PMOD_RST# 8 PMOD Reset Out (active low) P1.11 TINT19/GPIO P1_11/TINT19-PMOD_IRQ 57 RZM-PMOD_IRQ 7 PMOD connector IRQ or GPIO P8.14 GPIO/RXPCK2/TxD4 P8_14/RSPCK2 22 RZM_RSPCK2 4 P9.1 P8.9 GPIO/MISO2/CAN0RX GPIO/RXD3/SPDIF_OUT P9_1/MISO2-P8_9/RXD3 26 RZM_PMOD_RX 3 P9.0 P8.8 GPIO/MOSI2/CAN0TX GPIO/TXD3/SPDIF_IN P9_0/MOSI2-P8_8/TXD3 24 RZM_PMOD_TX 2 P8_15/SSL20 20 RZM_SSL20 1 PMOD SPI Clock or UART Tx PMOD SPI Master In/Slave Out or CAN RX PMOD UART RxD or SPDIF OUT PMOD SPI Master Out/Slave In or CAN Tx PMOD UART TxD or SPDIF IN PMOD SPI Slave Select or UART Rx P3.7 GPIO P8.15 GPIO/SSL20/RxD4 Note how two pairs of MCU pins are joined and overlaid on the PMOD connector. This enables both the standard UART and SPI modes as well as other possibilities, including CAN, SPDIF, and a second UART. Only enable one function per joined signal (e.g. P9.1 & P8.9) on the MCU to be an output to avoid damaging the MCU. Rev 2.20 Jul 21, 2015 Page 23 of 68 YLCDRZA1H Technical Reference Manual This table summarizes the configuration of the MCU pins for the various standard PMOD modes: MCU PMOD Standard PMOD Configuration for Mode 1A 4A 4B 2A Port Pin GPIO UART XUART SPI P3.7 P1.11 P8.14 P9.1 P8.9 P9.0 P8.8 P8.15 8 7 4 3 2 1 GPIO GPIO/TINT19 GPIO GPIO GPIO GPIO GPIO GPIO GPO/RTS# GPO TINT19 GPO/RTS# RxD3 RxD3 TxD3 GPI/CTS# TxD3 GPI/CTS# 2B XSPI RXPCK2 MISO2 GPO TINT19 RXPCK2 MISO2 MOSI2 MOSI2 SSL20/GPO SSL20/GPIO This table summarizes the configuration of the MCU pins for the various non-standard PMOD modes: MCU PMOD Non-Standard PMOD Configuration for Mode CAN CAN UART UART SPDIF Port Pin GPIO UART GPIO UART GPIO P3.7 P1.11 P8.14 P9.1 P8.9 P9.0 P8.8 P8.15 8 7 4 3 2 1 GPIO/TINT47 GPIO/TINT19 TxD4 CAN0RX GPIO/TINT47 GPIO/TINT19 TxD4 CAN0RX GPIO/TINT47 GPIO/TINT19 TxD4 GPIO/TINT132 CAN0TX CAN0TX GPIO/TINT131 RxD4 RxD4 TxD4 UART SPDIF GPIO/TINT47 GPIO/TINT19 TxD4 GPIO/TINT47 GPIO/TINT19 GPIO/TINT47 GPIO/TINT19 TxD4 RxD3 SPDIF_OUT SPDIF_OUT TxD3 TxD4 SPDIF_IN SPDIF_IN TxD4 8.12 - Segger J-Link On-Board Debugger/Programmer The YLCDRZA1H Baseboard includes a Segger J-Link On-Board debugger/programmer to enable easy and effective software development without the need for an external programmer/debugger. The USB Micro connector near the barrel power jack is the PC's connection point for this debugger - see Chapter 3 - Getting Started, Section 3.3 Connecting to the Segger J-Link On-Board Debugger. The debugger is connected directly to the MCU: MCU Schematic Operation Port Function Module # Baseboard JP0_1 TDO TDO 81 RZM-TDO JTAG test data out TCK TCK TCK 85 RZM-TCK JTAG test clock JP0_0 TDI TDI 79 RZM-TDI JTAG test data In TMS TMS TMS 83 RZM-TMS JTAG test mode select TRST TRST TRST# 77 RZM-TRST# RES RES RESET# 27 RZM-RESET# JTAG test reset (active low) System Reset (open drain, active low) Also RESET Pushbutton S3 on Baseboard Details of this circuit are the proprietary and confidential property of SEGGER Microcontroller GmbH & Co. KG, and can only be implemented under license from Segger; contact Segger for details. The Baseboard's LED2 green element is controlled directly by the Segger J-Link On-Board and flashes to indicate activity on the debugger. 8.13 - Ambient Light Sensor In low-light conditions, the LCD can be so bright it can visually "bloom" and difficult to read. As in mobile phones and tablets, the YLCDRZA1H includes a forward-facing through-glass ambient light sensor, enabling software to monitor the ambient light conditions and dynamically adjust the LCD backlight intensity. The Avago APDS-9002-021 Ambient Light Sensor (ALS) is a simple device that outputs a current proportional to the ambient light conditions. Through a resistor, this appears as a voltage between 0 and 3.3V on an Analog to Digital Converter (ADC) input on the MCU. Software can poll this ADC periodically. The ALS is connected as follows: Rev 2.20 Jul 21, 2015 Page 24 of 68 YLCDRZA1H Port P1.8 Technical Reference Manual MCU Function Schematic # Baseboard Module AN0 P1_8/AN0_ALS 53 Operation RZM-AN0_ALS Ambient light sensor analog input 8.14 - Digital Video Camera A forward-facing VGA (640x480) color digital video camera module based on the popular OmniVision OV7670 smart sensor is included in the YLCDRZA1H. The video data is moved over a dedicated high speed parallel video data channel. Operation and features of the camera are controlled over I2C. The camera module is connected as follows: Port MCU Function Schematic DIMM Baseboard Module Operation P10.0 VIO_CLK P10_0/VIO_CLK 32 RZM-VIO_CLK Camera CLK P10.1 VIO_VD P10_1/VIO_VSYNC 19 RZM-VIO_VSYNC Camera Vertical Sync P10.2 VIO_HD P10_2/VIO_HSYNC 17 RZM-VIO_HSYNC Camera Horizontal Sync P10.3 VIO_FLD P10_3/VIO_FLD 38 RZM-VIO_FLD Camera FLD P10.4 VIO_D0 P10_4/VIO_D0 109 RZM-VIO_D0 P10.5 VIO_D1 P10_5/VIO_D1 107 RZM-VIO_D1 Camera D0 (LSB) Camera D1 P10.6 VIO_D2 P10_6/VIO_D2 72 RZM-VIO_D2 Camera D2 P10.7 VIO_D3 P10_7/VIO_D3 76 RZM-VIO_D3 Camera D3 P10.8 VIO_D4 P10_8/VIO_D4 90 RZM-VIO_D4 Camera D4 P10.9 VIO_D5 P10_9/VIO_D5 127 RZM-VIO_D5 Camera D5 P10.10 VIO_D6 P10_10/VIO_D6 94 RZM-VIO_D6 Camera D6 P10.11 VIO_D7 P10_11/VIO_D7 117 RZM-VIO_D7 Camera D7 (MSB) P1.0 P1.0/SCL0 P1_0/SCL0 126 RZM-SCL0 I2C0 Clock P1.0 P1.1/SDA0 P1_1/SDA0 128 RZM-SDA0 I2C0 Data The OV7670 I2C communication protocol is described in detail in the OmniVision Serial Camera Control Bus (SCCB) Functional Specification, and is present on I2C bus 0 at 7-bit address 0x21: Address I2C Max Location Device 7-bit Read Write Bus kHz 0x21 0x43 0x42 0 400 Baseboard OV7670 Camera Module See Chapter 10 - I2C Device Summary for a complete list of I2C Devices on the YLCDRZA1H. 8.15 - Switches The baseboard has two pushbuttons and two 4-position DIP switches for selecting YLCDRZA1H features: Switch Type Purpose S1 4 Switch DIP Slide S2 NOMC SPST Pushbutton User Input S3 NOMC SPST Pushbutton System Reset when pressed S4 4 Switch DIP Slide MCU Boot Mode and Spread Spectrum Clocking RS232/485 Transceiver Options DIP Switch S1 controls the MCU boot modes and spread spectrum clocking. See Chapter 7.3 - MCU Boot Mode Selection and Chapter 7.6 - On-Module Clocking. DIP Switch S4 controls various RS232/485 transceiver capabilities: See Chapter 8.7 - Industrial Networking: CAN, RS232, RS485. Rev 2.20 Jul 21, 2015 Page 25 of 68 YLCDRZA1H Technical Reference Manual S2 is a simple GPIO/Interrupt input into the MCU, and can be used by software for any user-input purpose. S3 is connected to the system RESET# line, debounced and managed on the RZ Module as described in 7.2 - System Reset. They are connected as follows: MCU Schematic Operation Port Function Module # Baseboard P7.8 GPI/IRQ1 P7_8/IRQ1 RES RES RESET# 195 27 Baseboard Pushbutton S2 (active low w/ IRQ) System Reset (open drain, active low) Also RESET Pushbutton S3 on Baseboard RZM-P7_8/IRQ1 RZM-RESET# 8.16 - LEDs The Baseboard has two tri-color LEDs (red, green, orange=red+green): LED Green Red LED1 Software P3.9 (active high) Software P3.8 (active high) LED2 Segger J-Link Activity Baseboard Power Present LED1 is connected as follows: Port MCU Function Module Schematic DIMM Operation Baseboard P3.8 P3.8 P3_8-RZM_LED_RED 71 RZM-LED_RED Baseboard LED1 Red element (active high) P3.9 P3.9 P3_9-RZM_LED_GRN 65 RZM-LED_GRN Baseboard LED1 Green element (active high) 8.17 - CryptoAuthentication The YLCDRZA1H Baseboard includes an Atmel ATSHA204A CryptoAuthentication Chip, which includes 4.5kbit EEPROM and a Random Number Generator (RNG). The encryption key OTP area within the 4.5kbit EEPROM is pre-programmed by Serious Integrated Inc. for support of the Serious Human InterfaceTM Platform (SHIP) and is unavailable for other uses. Modifying or writing to this area will permanently remove your ability to use SHIP on the YLCDRZA1H. The chip appears on I2C bus 0 at 7-bit address 0x64: Address I2C Max Location 7-bit Read Write Bus kHz 0x64 0xC9 0xC8 0 1000 Baseboard Device ATSHA204A Crypto + RNG + EEPROM Consult the Atmel ATSHA204 Data Sheet for programming and hardware information of the ATSHA204 device. Rev 2.20 Jul 21, 2015 Page 26 of 68 YLCDRZA1H Technical Reference Manual Chapter 9 - External Interrupt Summary Port MCU Function Module Schematic # Baseboard Operation IRQ0 P7.8 IRQ1/GPIO P7_8/IRQ1 195 RZM-P7_8/IRQ1 Baseboard Pushbutton S2 (active low w/IRQ) Audio System LCD Touch controller Ethernet PHY (WOL) IRQ2 P1.9 IRQ3 P1_9_IRQ-AUDIO_IRQ 63 RZM-AUDIO_IRQ P1.10 IRQ4 P1_10/IRQ4-TOUCH_IRQ 52 RZM-TOUCH_IRQ P1.5 IRQ5 P1_5/IRQ5-ET_IRQ 171 RZM-ET_IRQ IRQ6 IRQ7 P1.11 TINT19/GPIO P1_11/TINT19-PMOD_IRQ 57 RZM-PMOD_IRQ P1.12 TINT20/GPI P1_12/TINT20-USBH_OC 56 RZM-USBH_OC# Rev 2.20 Jul 21, 2015 PMOD connector IRQ or GPIO USB host overcurrent Page 27 of 68 YLCDRZA1H Technical Reference Manual Chapter 10 - I2C Device Summary The two I2C interfaces on the YLCDRZA1H are as follows: MCU Schematic Port Function Module DIMM Baseboard Operation P1.0 SCL0 P1_0/SCL0 126 RZM-SCL0 I2C0 Clock P1.1 SDA0 P1_1/SDA0 128 RZM-SDA0 I2C0 Data P1.2 P1.2/SCL1 P1_2/SCL1 165 RZM-SCL1 I2C1 Clock (Touch dedicated) P1.3 P1.3/SDA1 P1_3/SDA1 169 RZM-SDA1 I2C1 Data (Touch dedicated) The devices on these channels are as follows: Address I2C Max Location 7-bit Read Write Bus kHz Rev 2.20 Jul 21, 2015 Device 0x10 0x21 0x20 0 400 Baseboard MAX98089ETN+ Audio Codec/Amplifier 0x21 0x43 0x42 0 400 Baseboard OV7670 Camera Module 0x50 0xA1 0xA0 0 400 Baseboard 24AA02E48T EEPROM/MAC Address 0x57 0xAD 0xAC 0 400 Module CAT34C02 EEPROM 0x60 0xC1 0xC0 0 400 Module Si5351C Clock Synthesizer 0x64 0xC9 0xC8 0 1000 Baseboard ATSHA204A Crypto + RNG + EEPROM 0x68 0xD1 0xD0 0 1000 Baseboard PCF8523 Real Time Clock Calendar 0x5C 0xB9 0xB8 1 400 LCD Pixcir C48 Capacitive Touch Controller Page 28 of 68 YLCDRZA1H Technical Reference Manual Chapter 11 - SPI Device Summary The SPI interfaces on the YLCDRZA1H are as follows: MCU Schematic Port Function Module # Baseboard Operation P9.2 SPBCLK0 P9_2/SPBCLK0 166 RZM-SPBCLK0 XIP/Boot Serial FLASH Clock P9.3 SPBSSL0 P9_3/SPBSSL0 174 RZM-SPBSSL0 XIP/Boot Serial FLASH SSL# P9.4 SPBIO00 P9_4/SPBIO00 178 RZM-SPBIO00 XIP Lo/Boot Serial FLASH Data 0/MOSI P9.5 SPBIO10 P9_5/SPBIO10 173 RZM-SPBIO10 XIP Lo/Boot Serial FLASH Data 1/MISO P9.6 SPBIO20 P9_6/SPBIO20 XIP Lo/Boot Serial FLASH Data 2 P9.7 SPBIO30 P9_7/SPBIO30 XIP Lo/Boot Serial FLASH Data 3 P2.12 SPBIO01 P2_12/SPBIO01 178 RZM-SPBIO01 XIP Hi Serial FLASH Data 0 P2.13 SPBIO11 P2_13/SPBIO11 173 RZM-SPBIO11 XIP Hi XIP Serial FLASH Data 1 P2.14 SPBIO21 P2_14/SPBIO21 XIP Hi XIP Serial FLASH Data 2 P2.15 SPBIO31 P2_15/SPBIO31 XIP Hi XIP Serial FLASH Data 3 The devices on these interfaces are: SPI Slave Select Bus P9_3/SPBSSL0 Rev 2.20 Jul 21, 2015 0 Max MHz Location Device Module Both Serial FLASH Devices Page 29 of 68 YLCDRZA1H Rev 2.20 Jul 21, 2015 Technical Reference Manual Page 30 of 68 YLCDRZA1H Technical Reference Manual Chapter 12 - Schematics & Bills of Materials 12.1 - SO-DIMM Detail The SO-DIMM socket on the YLCDRZA1H Baseboard is an inexpensive and readily-available TE 1473005-4 200Pos 0.6mm pitch socket. Designers can make their own baseboards and reuse the RZ Module as a time-to-prototype vehicle. The DIMM socket has the following pin-out: MCU Schematic Operation Port Function Module # Baseboard GND 1 GND +5V 2 +5V P11.8 LCD0_TCON6 P11_8/LCD_DEN 3 RZM-LCD_DEN P11.7 LCD_DATA0 P11_7/LCD_DATA0 4 RZM-LCD_DATA0 P11.9 LCD0_TCON5 P11_9/LCD_VSYNC 5 RZM-LCD_VSYNC P11.6 LCD_DATA1 P11_6/LCD_DATA1 6 RZM-LCD_DATA1 P8.13 P11.1 0 P8.11 GPIO P8_13-TOUCH_RST# 7 RZM-TOUCH_RST# LCD0_TCON4 P11_10/LCD_HSYNC 8 RZM-LCD_HSYNC GPO P8_11/RS_ON 9 RZM-RS_ON CKIO CKIO 10 RZM-CKIO GPO GPIO/TXD3/SP DIF_IN P8_10/RS_DEN P9_0/MOSI2P8_8/TXD3 GND 11 RZM-RS_DEN 12 RZM_PMOD_TX 13 GND +5V 14 +5V P3_2/UART_RX P9_1/MISO2P8_9/RXD3 P10_2/VIO_HSYNC 15 RZM-UART_RX 16 RZM_PMOD_RX P10.2 RxD2 GPIO/RXD3/SP DIF_OUT VIO_HD 17 RZM-VIO_HSYNC P8.12 PWM1E P8_12/PWM1E-BLEN 18 RZM-BLEN P10.1 VIO_VD GPIO/SSL20/R xD4 MDIO GPIO/RXPCK2/ TxD4 LCD0_CLK GPIO/MOSI2/C AN0TX TxD2 GPIO/MISO2/C AN0RX P10_1/VIO_VSYNC 19 RZM-VIO_VSYNC P8_15/SSL20 20 RZM_SSL20 P3_3/ET_MDIO 21 RZM-ET_MDIO P8_14/RSPCK2 22 RZM_RSPCK2 P3_0/LCD_CLK P9_0/MOSI2P8_8/TXD3 P3_1/UART_TX P9_1/MISO2P8_9/RXD3 23 RZM-LCD_CLK 24 RZM_PMOD_TX 25 RZM_UART_TX 26 RZM_PMOD_RX RES RESET# 27 RZM-RESET# P3.6 RXDV P3_6/ET_RXDV 28 RZM-ET_RXDV P0.5 GPO P0_5-ET_RESET# 29 RZM-ET_RESET# P3.7 GPIO P3_7-PMOD_RST# 30 RZM-PMOD_RST# P0.4 GPO P0_4-MMC_RST# 31 RZM-MMC_RST P10.0 VIO_CLK P10_0/VIO_CLK 32 RZM-VIO_CLK GND 33 GND +5V 34 +5V DP_1 USBF_N 35 RZM-USBF_N RXER P3_5/ET_RXER 36 RZM-ET_RXER DP_0 USBF_P 37 RZM-USBF_P VIO_FLD P10_3/VIO_FLD 38 RZM-VIO_FLD GND 39 GND RXCLK P3_4/ET_RXCLK 40 RZM-ET_RXCLK VBUSIN1 VBUSIN1 41 RZM-USBF_VBUS +3V3 42 RZM_3V3 VBUSIN0 43 RZM-USBH_VBUS P8.10 P8.8 P3.2 P8.9 P8.15 P3.3 P8.14 P3.0 P9.0 P3.1 P9.1 P3.5 P10.3 P3.4 VBUSIN0 44 Rev 2.20 Jul 21, 2015 System Ground System +5V Main Supply LCD Data Enable LCD Blue 0 (LSB) LCD Vertical Sync LCD Blue 1 LCD Touch controller reset (active low) LCD Horizontal Sync RSXXX Transceiver Enable (active high) MCU System Clock Out (unused on Baseboard) RSXXX Transmit Drive Enable (active high) PMOD UART TxD or SPDIF IN System Ground System +5V Main Supply RSXXX Receive Data PMOD UART RxD or SPDIF OUT Camera Horizontal Sync LCD Backlight Enable (active high) Camera Vertical Sync PMOD SPI Slave Select or UART Rx MII Management data I/O PMOD SPI Clock or UART Tx Dot Clock PMOD SPI Master Out/Slave In or CAN Tx RSXXX Transmit Data PMOD SPI Master In/Slave Out or CAN RX System Reset (open drain, active low) Also RESET Pushbutton S3 on Baseboard MII Receive data valid MII PHY Reset (active low) PMOD Reset Out (active low) MMC Reset (active low with pull-up) Camera CLK System Ground System +5V Main Supply USB Device ("Function") DMII Receive error USB Device ("Function") D+ Camera FLD System Ground MII Receive Clock USB Device ("Function") VBUS Detect +3.3V Module Supply Out (unconnected on Baseboard) USBH Power Detection (active high) unconnected/reserved Page 31 of 68 YLCDRZA1H Technical Reference Manual MCU Schematic GND 45 Operation GND 46 DP_1 DM_1 USBH_P 47 RZM-USBH_P +5V 48 +5V USBH_N 49 RZM-USBH_N 50 51 GND 52 RZM-TOUCH_IRQ AN0 GND P1_10/IRQ4TOUCH_IRQ P1_8/AN0_ALS 53 RZM-AN0_ALS GPIO P1_15-LCD_ON 54 RZM-P1_15 P1.13 GPIO 55 RZM-P1_13 P1.12 TINT20/GPIO 56 RZM_USBH_OC# P1.11 TINT19/GPIO 57 RZM-PMOD_IRQ P1.14 COL P1_13-USBH_5V_EN P1_12/TINT20USBH_OC P1_11/TINT19PMOD_IRQ P1_14/ET_COL 58 RZM-ET_COL GND 59 GND +5V 60 +5V P0_1/MD_BOOT1 P1_9/IRQ3AUDIO_IRQ 61 RZM-BOOT1 63 RZM-AUDIO_IRQ P1.10 IRQ4 P1.8 P1.15 P0.1 MD_BOOT1 P1.9 IRQ3 62 63 RZM-AUDIO_IRQ MMC_D3 P1_9_IRQAUDIO_IRQ P3_14/MMC_D3 64 RZM-MMC_D3 P3.9 P3.9 P3_9-RZM_LED_GRN 65 RZM-LED_GRN P4.1 LCD_DATA9 P4_1/LCD_DATA9 66 RZM-LCD_DATA9 CLKAUDIO_24MHZ 67 RZM-AUDIO_CLK P4.2 LCD_DATA10 P4_2/LCD_DATA10 68 RZM-LCD_DATA10 P1.9 IRQ3 P3.14 69 P4.3 LCD_DATA11 P4_3/LCD_DATA11 70 RZM-LCD_DATA11 P3.8 P3.8 P3_8-RZM_LED_RED 71 RZM-LED_RED P3.8 P3.8 P3_8-RZM_LED_RED 71 RZM-LED_RED P10.6 VIO_D2 P10_6/VIO_D2 72 RZM-VIO_D2 73 +5V 74 +5V GND 75 GND VIO_D3 P10_7/VIO_D3 76 RZM-VIO_D3 TRST TRST# 77 RZM-TRST# P4.5 LCD_DATA13 P4_5/LCD_DATA13 78 RZM-LCD_DATA13 JP0.0 TDI TDI 79 RZM-TDI P2.0 TXCLK P2_0/ET_TXCLK 80 RZM-ET_TXCLK JP0.1 TDO TDO 81 RZM-TDO P4.6 LCD_DATA14 P4_6/LCD_DATA14 82 RZM-LCD_DATA14 TMS TMS 83 RZM-TMS SD_WP_0 P4_9/SD_WP 84 RZM-SD_WP TCK TCK 85 RZM-TCK P2.1/ET_TXER P2_1/ET_TXER 86 RZM-ET_TXER GND 87 GND +5V 88 +5V P10.7 P4.9 P2.1 P3.10 MMC_D1 P3_10/MMC_D1 89 RZM-MMC_D1 P10.8 VIO_D4 P10_8/VIO_D4 90 RZM-VIO_D4 P3.12 MMC_CLK P3_12/MMC_CLK 91 RZM-MMC_CLK P4.10 SD_D1_0 P4_10/SD_D1 92 RZM-SD_D1 P3.11 P10.1 0 MMC_D0 P3_11/MMC_D0 93 RZM-MMC_D0 VIO_D6 P10_10/VIO_D6 94 RZM-VIO_D6 GND 95 GND P4.12 SD_CLK_0 P4_12/SD_CLK 96 RZM-SD_CLK P3.13 MMC_CMD P3_13/MMC_CMD 97 RZM-MMC_CMD Rev 2.20 Jul 21, 2015 System Ground unconnected/reserved USB Host D+ System +5V Main Supply USB Host Dunconnected/reserved System Ground LCD Touch controller interrupt Ambient light sensor analog input (unused on Baseboard, input only signal) (unused on Baseboard, input only signal) USB Host VBUS Overcurrent Detect (active low) PMOD connector IRQ or GPIO MII Collision detection System Ground System +5V Main Supply MCU Boot Mode Audio Codec Interrupt unconnected/reserved Audio System e-MMC Data Bus D3 Baseboard LED1 Green element (active high) LCD Green 1 24MHz Base Codec Clock from RZ Module LCD Green 2 unconnected/reserved LCD Green 3 Baseboard LED1 Red element (active high) Baseboard LED1 Red element (active high) Camera D2 unconnected/reserved System +5V Main Supply System Ground Camera D3 JTAG test reset (active low) LCD Green 5 JTAG test data In Transmit Clock JTAG test data out LCD Green 6 JTAG test mode select SD Write Protect (active low, pulled high) JTAG test clock MII Transmit Error or GPIO (unused on Baseboard) System Ground System +5V Main Supply e-MMC Data Bus D1 Camera D4 MMC clock SD Data Bus D1 e-MMC Data Bus D0 (LSB) Camera D6 System Ground SD Clock MMC Command/response Page 32 of 68 YLCDRZA1H Technical Reference Manual MCU Schematic Operation P4.13 SD_CMD_0 P4_13/SD_CMD 98 RZM-SD_CMD P3.15 MMC_D2 P3_15/MMC_D2 99 RZM-MMC_D2 +5V 100 +5V GND 101 GND +5V 102 +5V P4.0 LCD_DATA8 P4_0/LCD_DATA8 103 RZM-LCD_DATA8 P2.2 TXEN P2_2/ET_TXEN 104 RZM-ET_TXEN P4.4 LCD_DATA12 P4_4/LCD_DATA12 105 RZM-LCD_DATA12 P4.15 SD_D2_0 P4_15/SD_D2 106 RZM-SD_D2 P10.5 P10.1 2 P10.4 VIO_D1 P10_5/VIO_D1 107 RZM-VIO_D1 SSICLK1 P10_12/SSISCK 108 RZM_SSISCK VIO_D0 P10_4/VIO_D0 109 RZM-VIO_D0 P2.5 TXD[1] P2_5/ET_TXD1 110 RZM-ET_TXD1 P4.7 P10.1 5 LCD_DATA15 P4_7/LCD_DATA15 111 RZM-LCD_DATA15 SSITxD1 P10_15/SSITxD 112 RZM_SSITxD GND 113 GND +5V 114 +5V P4.8 P10.1 4 P10.1 1 P2.9 SD_CD_0 P4_8/SD_CD 115 RZM-SD_CD SSIRxD1 P10_14/SSIRxD 116 RZM_SSIRxD VIO_D7 P10_11/VIO_D7 117 RZM-VIO_D7 RXD[1] P2_9/ET_RXD1 118 RZM-ET_RXD1 P4.11 SD_D0_0 P4_11/SD_D0 119 RZM-SD_D0 P2.7 TXD[3] P2_7/ET_TXD3 120 RZM-ET_TXD3 P2.3 CRS P2_3/ET_CRS 121 RZM-ET_CRS P2.10 RXD[2] P2_10/ET_RXD2 122 RZM-ET_RXD2 P4.14 SD_D3_0 P4_14/SD_D3 123 RZM-SD_D3 124 GND 125 GND P1.0 SCL0 P1_0/SCL0 126 RZM-SCL0 P10.9 VIO_D5 P10_9/VIO_D5 127 RZM-VIO_D5 P1.1 SDA0 P1_1/SDA0 128 RZM-SDA0 P2.4 TXD[0] P2_4/ET_TXD0 129 RZM-ET_TXD0 +5V 130 +5V P2.11 RXD[3] P2_11/ET_RXD3 131 P1.6 P10.1 3 P1.4 P1.6/SCL3 P1_6/SCL3 132 SSIWS1 P10_13/SSIWS 133 RZM-ET_RXD3 RZMUSBH_5V_EN# RZM_SSIWS CAN1RX P1_4/CAN1RX 134 RZM_CANRX P2.6 TXD[2] P2_6/ET_TXD2 135 RZM-ET_TXD2 P1.7 P1.7/SDA3 P1_7/SDA3 136 RZM-P1_7 P2.8 RXD[0] P2_8/ET_RXD0 137 RZM-ET_RXD0 +5V 138 +5V GND 139 GND GND 140 GND GND 141 GND P5_0/LCD_DATA16 142 RZM-LCD_DATA16 GND 143 P5_1/LCD_DATA17 144 RZM-LCD_DATA17 GND 145 GND GND 146 GND GND 147 GND P5_4/LCD_DATA20 148 RZM-LCD_DATA20 GND 149 GND P5_5/LCD_DATA21 150 RZM-LCD_DATA21 GND 151 GND GND 152 GND GND 153 GND P5.0 P5.1 P5.4 P5.5 LCD_DATA16 LCD_DATA17 LCD_DATA20 LCD_DATA21 Rev 2.20 Jul 21, 2015 SD Command/Response e-MMC Data Bus D2 System +5V Main Supply System Ground System +5V Main Supply LCD Green 0 (LSB) MII Transmit Enable LCD Green 4 SD Data Bus D2 Camera D1 Serial Sound Interface Clock Camera D0 (LSB) MII Transmit Data 1 LCD Green 7 (MSB) Serial Sound Transmit Data (output) System Ground System +5V Main Supply SD Card Detect (active low, pulled high) Serial Sound Receive Data (input) Camera D7 (MSB) MII Receive Data 1 SD Data Bus D0 (LSB) MII Transmit Data 3 (MSB) Carrier detection MII Receive Data 2 SD Data Bus D3 (MSB) unconnected/reserved System Ground I2C0 Clock Camera D5 I2C0 Data MII Transmit Data 0 (LSB) System +5V Main Supply MII Receive Data 3 (MSB) See 5.5 - USB Host Power Subsystem Serial Sound Word Select CAN Receive Data MII Transmit Data 2 (unused on Baseboard) MII Receive Data 0 (LSB) System +5V Main Supply System Ground System Ground System Ground LCD Red 0 (LSB) System Ground LCD Red 1 System Ground System Ground System Ground LCD Red 4 System Ground LCD Red 5 System Ground System Ground System Ground Page 33 of 68 YLCDRZA1H Technical Reference Manual MCU P5.2 P5.3 P5.6 P5.7 P9.2 P5.9 LCD_DATA18 LCD_DATA19 LCD_DATA22 LCD_DATA23 SPBCLK0 MDC Schematic Operation P5_2/LCD_DATA18 154 RZM-LCD_DATA18 GND 155 GND P5_3/LCD_DATA19 156 RZM-LCD_DATA19 GND 157 GND GND 158 GND GND 159 GND P5_6/LCD_DATA22 160 RZM-LCD_DATA22 GND 161 GND P5_7/LCD_DATA23 162 RZM-LCD_DATA23 GND 163 GND GND 164 GND P1_2/SCL1 165 RZM-SCL1 P9_2/SPBCLK0 166 RZM-SPBCLK0 GND 167 GND P5_9/ET_MDC 168 RZM-ET_MDC P1_3/SDA1 169 RZM-SDA1 P5.10 CAN1TX P5_10/CAN1TX 170 RZM-CANTX P1.5 IRQ5 P1_5/IRQ5-ET_IRQ 171 RZM-ET_IRQ GND 172 GND P9.5 SPBIO10 P9_5/SPBIO10 173 RZM-SPBIO10 P9.3 SPBSSL0 P9_3/SPBSSL0 174 RZM-SPBSSL0 P11.1 LCD_DATA6 P11_1/LCD_DATA6 175 RZM-LCD_DATA6 P0.3 MD_CLKS/GPIO P0_3/MD_CLKS 176 RZM-SSCG P11.3 LCD_DATA4 P11_3/LCD_DATA4 177 RZM-LCD_DATA4 P9.4 SPBIO00 P9_4/SPBIO00 178 RZM-SPBIO00 P7.0 MD_BOOT2 P7_0/MD_BOOT2 179 RZM-BOOT2 180 P11.7 LCD_DATA0 P11_7/LCD_DATA0 181 RZM-LCD_DATA7 182 P11.2 LCD_DATA5 P11_2/LCD_DATA5 183 RZM-LCD_DATA5 184 P11.1 4 MMC_D6 P11_14/MMC_D6 185 RZM-MMC_D6 186 P11.1 2 MMC_D4 P11_12/MMC_D4 187 RZM-MMC_D4 188 GND 189 GND 190 P11.1 3 MMC_D5 P11_13/MMC_D5 P11.1 5 MMC_D7 P11_15/MMC_D7 P7.8 P7.8/IRQ1 P7_8/IRQ1 191 RZM-MMC_D5 192 193 RZM-MMC_D7 194 195 RZM-P7_8/IRQ1 196 P11.4 LCD_DATA3 P11_4/LCD_DATA3 197 RZM-LCD_DATA3 198 P11.5 LCD_DATA2 Rev 2.20 Jul 21, 2015 P11_5/LCD_DATA2 199 RZM-LCD_DATA2 PWRDWN# 200 PWRDWN# LCD Red 2 System Ground LCD Red 3 System Ground System Ground System Ground LCD Red 6 System Ground LCD Red 7 (MSB) System Ground System Ground Touch dedicated I2C1 Clock Serial FLASH Clock System Ground Management data clock Touch dedicated I2C1 Data CAN Transmit Data PHY Interrupt (active low) System Ground Serial FLASH MISO Serial FLASH SSL# LCD Blue 6 Enables Spread Spectrum Clocking in MCU by Baseboard S1.2 (ON/active GND,OFF pulled high (4.7k) on RZ Baseboard) LCD Blue 4 Serial FLASH MOSI MCU Boot Mode unconnected/reserved LCD Blue 7 (MSB) unconnected/reserved LCD Blue 5 unconnected/reserved e-MMC Data Bus D6 unconnected/reserved e-MMC Data Bus D4 unconnected/reserved System Ground unconnected/reserved e-MMC Data Bus D5 unconnected/reserved e-MMC Data Bus D7 (MSB) unconnected/reserved Baseboard Pushbutton S2 (active low w/IRQ) unconnected/reserved LCD Blue 3 unconnected/reserved LCD Blue 2 Power Down RZ Module (unconnected on Baseboard, active low) Page 34 of 68 YLCDRZA1H Technical Reference Manual 12.2 - RZ Module Schematics Rev 2.20 Jul 21, 2015 Page 35 of 68 D C B A 1 NLPORB PORB NLPWRDWN# PWRDWN# NL0VEXT +VEXT 1 10uF 10V COC1 C1 GND PIC102 PIC101 PIR101 PIR102 100K0 COR1 R1 VREF PIU10 PIU10PAD LX2 DEVSLPIN LX2 GPI3 GPIO14 FB2 GPIO15 GPO16 GPIO17 PGND2 GND PAD PGND1 FB1 LX1 19 2 2 GND PIU1019 PIU1018 18 20 21 PIU1021 PIU1020 8 PIU108 PIU106 6 7 PIU107 Program for Mode 2 Vout1 = 1.1750V Vout2 = 3.3000V Buck1->4ms->Buck2 sequence PORB = PG1 & PG2 GND 3 PIU103 14 PIU1014 15 PIU1015 16 PIU1016 17 PIU1017 5 PIU105 PIU101 1 VGND 4 PIU104 VINSEL 2 PIU102 COU1 U1 P9122 24 PIU1024 VIN 9 PIU109 PVIN1 22 PIU1022 PVIN2 23 PIU1023 PVIN2 11 1uH PIL201 COL2 L2 2.2uH PIL101 COL1 L1 PIL202 PIL102 GND PIC501 PIC502 GND PIC202 PIC201 COC5 C5 22uF 6.3V NL03V3 +3V3 COC2 C2 4.7uF 6.3V NL01V18 +1V18 GND PIC601 PIC602 GND PIC302 PIC301 COC6 C6 0.1uF COC3 C3 0.1uF +3V3 +1V18 3 COR21 R21 PIR2102 PIR2202 1 3 PILED103 PILED101 R G COLED1 LED1 Author: Jorge Amodio Date: 4/15/2015 Power Supplies and User I/O 1K50 PIR2201 470R COR22 R22 PIR2101 COC4 C4 0.1uF GND PIC402 PIC401 2 4 PILED104 PILED102 GND PIU203 3 GND Vcc 1 RST PIU201 Vss PIU20 2 COU2 U2 STM1818 Revision: v2.1 PCB02 Sheet 1 of 8 Renesas YLCDRZA1H MCU Module NLP110110LED1R P11_11-LED1R +3V3 +3V3 3 4K70 COR2 R2 NLRESET# RESET# 4 am.renesas.com/HiResGUI PIR201 PIR202 4 D C B A D C B COC22 C22 10uF 6.3V COC27 C27 10uF 6.3V GND PIC2702 PIC2701 +3V3 GND PIC2 01 PIC2 02 0.1uF 0.1uF COC28 C28 GND PIC2802 PIC2801 GND PIC2401 COC24 C24 GND PIC2402 10uF 6.3V COC7 C7 COC8 C8 0.1uF 1 0.1uF COC25 C25 GND PIC2501 PIC2502 GND PIC802 PIC801 GND PIC2601 PIC2602 GND PIC2302 PIC2301 COC26 C26 0.1uF COC23 C23 0.1uF D12 PIU60D12 C12 PIU60C12 PIU60D9 D9 W14 PIU60W14 B14 PIU60B14 AA20 PIU60AA20 W18 PIU60W18 AB21 PIU60AB21 LVDSAPVCC2 LVDSAPVCC1 LVDSPLLVCC PLLVCC VDAVCC AVCC2 AVCC1 AVREF PVCC PVCC PVCC PVCC PVCC PVCC PVCC PVCC PVCC PVCC PVCC PVCC PVCC PVCC PVCC PVCC PVCC PVCC PVCC PVCC PVCC PVCC PIU60A14 PIU60W17 PIU60AB20 PIU60A1 PIU60A8 PIU60A12 PIU60A2 PIU60B2 PIU60B21 PIU60C3 PIU60C15 PIU60C2 PIU60D4 PIU60D1 PIU60D15 PIU60D19 PIU60G2 PIU60J9 PIU60J10 PIU60J1 PIU60J12 PIU60J13 PIU60J14 PIU60K9 PIU60K1 PIU60K1 PIU60K12 PIU60K13 PIU60K14 PIU60L9 PIU60L10 PIU60L1 PIU60L12 PIU60L13 PIU60L14 PIU60M9 PIU60M1 PIU60M1 PIU60M12 PIU60M13 PIU60M14 PIU60N9 PIU60N1 PIU60N1 PIU60N12 PIU60N13 PIU60N14 PIU60P9 PIU60P1 PIU60P1 PIU60P12 PIU60P13 PIU60P14 PIU60P19 PIU60U1 PIU60U2 PIU60W1 PIU60W7 PIU60W8 PIU60W1 PIU60W15 PIU60W16 PIU60Y14 PIU60A 10 PIU60A14 PIU60AB7 PIU60AB10 PIU60AB13 PIU60AB17 PIU60AB2 2 3 Author: Jorge Amodio Date: 4/15/2015 MCU Power E4 F4 B20 C19 D7 PIU60D7 D8 PIU60D8 D16 PIU60D16 D17 PIU60D17 D18 PIU60D18 L19 PIU60L19 M19 PIU60M19 N4 PIU60N4 P4 PIU60P4 W4 PIU60W4 W5 PIU60W5 W6 PIU60W6 W12 PIU60W12 W13 PIU60W13 W19 PIU60W19 Y3 PIU60Y3 Y20 PIU60Y20 AA2 PIU60AA2 AA21 PIU60AA21 AB1 PIU60AB1 PIU60C19 PIU60B20 W10 PIU60W10 PIU60W9 W9 U19 PIU60U19 PIU60T19 PIU60T4 T4 T19 R19 PIU60R19 PIU60R4 R4 M4 PIU60M4 PIU60K19 K19 J19 PIU60J19 PIU60F4 PIU60E4 PIC1201 PIC1301 PIC1401 P I C 1 5 0 1 PIC1601 Revision: v2.1 PCB02 Sheet 2 of 8 4 PIC3902 PIC3901 COC39 C39 10uF 6.3V PIC20 1 GND PIC1901 am.renesas.com/HiResGUI PICCOC29 2902 PICCOC30 30 2 PIC31C02OC31 PIC32C02OC32 PIC3COC33 02 PIC3COC34 402 PIC3COC35 502 PICCOC36 3602 PICCOC37 3702 PIC38C02OC38 PIC2901 PIC30 1 PIC3101 PIC3201 PIC3 01 PIC3401 PIC3501 PIC3601 PIC3701 PIC3801 PIC10 1 COC21 C21 10uF 6.3V +3V3 GND PIC2102 PIC901 PIC2101 PIC1801 PIC1701 PIC1 01 +1V18 PICOC9 C902 PICCOC10 10 2 PIC1 C02OC11 PIC12C02OC12 PIC1COC13 302 PIC1COC14 402 PIC1COC15 502 PICCOC16 1602 PICCOC17 1702 PIC18C02OC18 PIC19C02OC19 PIC2COC20 02 Renesas YLCDRZA1H MCU Module GND D3 D13 PIU60D13 PIU60D3 0.1uF B1 C29 0.1uF C2 PIU60C2 4 0.1uF C30 0.1uF PIU60B1 C9 0.1uF C31 0.1uF PIC702 PIC701 VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC C10 0.1uF C32 0.1uF USBAPVCC C11 0.1uF C33 0.1uF AB14 PIU60AB14 C12 0.1uF C34 0.1uF COU6D U6D RZ/1AH-BGA324 Y13 PIU60Y13 USBAVcc 3 C13 0.1uF C35 0.1uF A 2 C14 0.1uF C36 0.1uF +3V3 VDAVSS A14 +1V18 AVSS1 AVSS2 W17 AB20 C15 C17 0.1uF C37 0.1uF C19 0.1uF 1 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS A1 A8 A12 A22 B2 B21 C3 C15 C20 D4 D10 D15 D19 G22 J9 J10 J11 J12 J13 J14 K9 K10 K11 K12 K13 K14 L9 L10 L11 L12 L13 L14 M9 M10 M11 M12 M13 M14 N9 N10 N11 N12 N13 N14 P9 P10 P11 P12 P13 P14 P19 U1 U22 W1 W7 W8 W11 W15 W16 Y14 AA10 AA14 AB7 AB10 AB13 AB17 AB22 C16 C18 0.1uF C38 0.1uF C20 0.1uF D C B A D C B A NLRESET# RESET# PIC4501 PIC4502 0.1uF COC45 C45 GND NLP1000SCL0 P1_0/SCL0 NLP1010SDA0 P1_1/SDA0 +3V3 1 GND PIC4 01 PIC4 02 6 GND 7 PIU307 OEB PIU302 PIU30PAD GND PAD CLKIN XB 5 PIU305 SDA 4 PIU304 SCL 3 PIU303 INTR PIU306 3 CLK PIU403 PIU302 XA COC44 C44 0.1uF 1 PIU301 GND 0.1uF COC43 C43 GND PIC4301 PIC4302 2 0.1uF COC42 C42 GND PIC4201 PIC4202 4 VDD PIU404 12.000MHz GND PIU402 2 OE 1 PIU401 0.1uF COC41 C41 GND PIC4101 PIC4102 COU4 U4 Si501 0.1uF COC40 C40 GND PIC40 1 PIC40 2 1 20 VDD GND 14 VDDOD PIU3014 16 CLK6PIU3016 15 CLK7PIU3015 18 VDDOC PIU3018 19 CLK4PIU3019 17 CLK5PIU3017 10 VDDOB PIU3010 9 CLK2PIU309 8 CLK3PIU308 11 VDDOA PIU3011 13 CLK0PIU3013 12 CLK1PIU3012 Si5351C COU3 U3 2 2 PIR801 0 12pF 32.768KHz PIX101 PIX102 COC48 C48 GND PIC4802 PIC4801 0 COR8 R8 PIR701 COX1 X1 0 COR6 R6 0 COR7 R7 PIR601 PIR501 COR5 R5 COC49 C49 12pF GND PIC4902 PIC4901 NLP0050ET0RESET# P0_5-ET_RESET# NLP0040MMC0RST# P0_4-MMC_RST# NLCLKMCU013MHZ CLKMCU_13MHZ PIR802 NLCLKUSB048MHZ CLKUSB_48MHZ PIR702 NLCLKAUDIO024MHZ CLKAUDIO_24MHZ PIR602 NLCLKVIDEO027MHZ CLKVIDEO_27MHZ PIR502 PIR301 PIR302 RES NMI XTAL EXTAL USB_X2 USB_X1 RTC_X2 RTC_X1 AUDIO_X2 AUDIO_X1 VIDEO_X2 AB9 PIU60AB9 P0_4/RTC_X3 AA9 PIU60AA9 P0_5/RTC_X4 PIU60Y9 PIU60Y8 Y8 Y9 AA16 PIU60AA16 AB16 PIU60AB16 AA15 PIU60AA15 AB15 PIU60AB15 AA8 PIU60AA8 AB8 PIU60AB8 W21 PIU60W21 W22 PIU60W22 Y21 PIU60Y21 VIDEO_X1 COU6C U6C RZ/1AH-BGA324 Y22 PIU60Y22 COR3 R3 4K70 TRST JP0_1/TDO JP0_0/TDI TMS TCK VRP VRM VIN1A VIN2A VIN1B VIN2B REFRIN VBUSIN0 DM_0 DP_0 VBUSIN1 DM_1 DP_1 BIAS 3 V20 U20 V21 V22 PIU60V22 U21 PIU60U21 GND COR9 R9 5K60 PIR901 0.5% GND PIC4602 PIC4601 GND Author: Jorge Amodio Date: 4/15/2015 MCU Clocks & Control Signals Y10 C9 PIU60C9 AA22 PIU60AA22 PIU60Y10 COC46 C46 0.1uF PIC4702 PIC4701 COC47 C47 0.1uF COR10 R10 24K PIR10 1 0.5% PIR10 2 PIR1 02 COR11 R11 GND GND Revision: v2.1 PCB02 Sheet 3 of 8 GND PIR1202 COR12 R12 47K0 PIR1302 COR13 R13 47K0 PIR1402 GND PIR1201 GND PIR1301 COR14 R14 22K0 GND PIR1401 4 am.renesas.com/HiResGUI 5K60 PIR1 01 0.5% NLBSCANP BSCANP NLCKIO CKIO D11 PIU60D11 PIU60V1 PIU60B12 V1 NLP0030MD0CLKS P0_3/MD_CLKS NLTRST# TRST# NLTDO TDO NLTDI TDI NLTMS TMS NLTCK TCK NLVBUSIN0 VBUSIN0 NLUSBH0N USBH_N NLUSBH0P USBH_P NLVBUSIN1 VBUSIN1 NLUSBF0N USBF_N NLUSBF0P USBF_P NLP0000MD0BOOT0 P0_0/MD_BOOT0 NLP0010MD0BOOT1 P0_1/MD_BOOT1 PIR902 COR4 R4 4K70 4 B12 Y15 PIU60Y15 Y16 PIU60Y16 A3 PIU60A3 PIU60A16 A16 PIU60V21 PIU60U20 PIU60V20 D14 C13 PIU60C13 PIU60D14 PIU60A13 PIU60B13 B13 A13 B15 A15 PIU60A15 PIU60B15 PIU60AB12 AB12 AA12 PIU60AA12 Y11 PIU60Y11 AA11 PIU60AA11 AB11 PIU60AB11 C14 PIU60C14 AA13 Y12 PIU60Y12 PIU60AA13 PIR401 PIR402 Renesas YLCDRZA1H MCU Module TESTMD(Vss) CLKTEST(Vss) BSCANP LVDSREFRIN CKIO P0_2/MD_CLK P0_3/MD_CLKS EMLE(Vss) P0_0/MD_BOOT0 P0_1/MD_BOOT1 3 D C B A D C B A NLP9020SPBCLK0 P9_2/SPBCLK0 NLP9030SPBSSL0 P9_3/SPBSSL0 NLP9040SPBIO00 P9_4/SPBIO00 NLP9050SPBIO10 P9_5/SPBIO10 NLP9060SPBIO20 P9_6/SPBIO20 NLP9070SPBIO30 P9_7/SPBIO30 1 NLP4020LCD0DATA10 P4_2/LCD_DATA10 NLP4030LCD0DATA11 P4_3/LCD_DATA11 NLP4040LCD0DATA12 P4_4/LCD_DATA12 NLP4050LCD0DATA13 P4_5/LCD_DATA13 NLP4060LCD0DATA14 P4_6/LCD_DATA14 NLP4070LCD0DATA15 P4_7/LCD_DATA15 NLP4080SD0CD P4_8/SD_CD NLP4090SD0WP P4_9/SD_WP NLP40100SD0D1 P4_10/SD_D1 NLP40110SD0D0 P4_11/SD_D0 NLP40120SD0CLK P4_12/SD_CLK NLP40130SD0CMD P4_13/SD_CMD NLP40140SD0D3 P4_14/SD_D3 NLP40150SD0D2 P4_15/SD_D2 NLP4000LCD0DATA8 P4_0/LCD_DATA8 NLP4010LCD0DATA9 P4_1/LCD_DATA9 NLP5000LCD0DATA16 P5_0/LCD_DATA16 NLP5010LCD0DATA17 P5_1/LCD_DATA17 NLP5020LCD0DATA18 P5_2/LCD_DATA18 NLP5030LCD0DATA19 P5_3/LCD_DATA19 NLP5040LCD0DATA20 P5_4/LCD_DATA20 NLP5050LCD0DATA21 P5_5/LCD_DATA21 NLP5060LCD0DATA22 P5_6/LCD_DATA22 NLP5070LCD0DATA23 P5_7/LCD_DATA23 NLP5080CS2#0SDRAM10CS# P5_8/CS2#-SDRAM1_CS# NLP5090ET0MDC P5_9/ET_MDC NLP50100CAN1TX P5_10/CAN1TX 1 C8 A6 B6 PIU60B6 C7 PIU60C7 A5 PIU60A5 B5 PIU60B5 PIU60A6 PIU60C8 P22 PIU60P22 P21 PIU60P21 N22 PIU60N22 M21 PIU60M21 M20 PIU60M20 L22 PIU60L22 L20 PIU60L20 K20 PIU60K20 K21 PIU60K21 J22 PIU60J22 H19 PIU60H19 H22 PIU60H22 G21 PIU60G21 G19 PIU60G19 F22 PIU60F22 P20 PIU60P20 P9_2/LCD1_DATA18/SPBCLK_0/LTXD0/SCK1/A0/SCL1O P9_3/LCD1_DATA19/SPBSSL_0/MLB_DAT/TxD1/SDA1O P9_4/LCD1_DATA20/SPBIO0_0/MLB_SIG/RxD1/SCL2O P9_5/LCD1_DATA21/SPBIO1_0/SSISCK2/CTS1/CS4/SDA2O P9_6/LCD1_DATA22/SPBIO2_0/SSIWS2/RTS1/CS5/SCL3O P9_7/LCD1_DATA23/SPBIO3_0/SSIDATA2/TIOC1A/SDA3O 2 P4_0/LCD0_DATA8/TIOC0A/FRE/DARC_MOUT0 P4_1/LCD0_DATA9/TIOC0B/FCLE/SCK2 P4_2/LCD0_DATA10/TIOC0C/FALE/CRx3/TxD2 P4_3/LCD0_DATA11/TIOC0D/FWE/CTx3/RxD2/DARC_MOUT5 P4_4/LCD0_DATA12/RSPCK1/TIOC4A/PWM2E/SSISCK0 P4_5/LCD0_DATA13/SSL10/TIOC4B/PWM2F P4_6/LCD0_DATA14/MOSI1/TIOC4C/PWM2G P4_7/LCD0_DATA15/MISO1/TIOC4D/PWM2H P4_8/LCD0_DATA16/LCD1_TCON3/SD_CD_0/MMC_CD P4_9/LCD0_DATA17/LCD1_TCON4/SD_WP_0 P4_10/LCD0_DATA18/LCD1_TCON5/SD_D1_0/MMC_D1 P4_11/LCD0_DATA19/LCD1_TCON6/SD_D0_0/MMC_D0 P4_12/LCD0_DATA20/LCD1_CLK/SD_CLK_0/MMC_CLK P4_13/LCD0_DATA21/LCD1_TCON0/SD_CMD_0/MMC_CMD P4_14/LCD0_DATA22/LCD1_TCON1/SD_D3_0/MMC_D3 P4_15/LCD0_DATA23/LCD1_TCON2/SD_D2_0/MMC_D2 COU6B U6B RZ/1AH-BGA324 A11 PIU60A11 P5_0/TXCLKOUTP/LCD1_DATA0/LCD0_DATA16 B11 PIU60B11 P5_1/TXCLKOUTM/LCD1_DATA1/LCD0_DATA17 A10 PIU60A10 P5_2/TXOUT2P/LCD1_DATA2/LCD0_DATA18 B10 PIU60B10 P5_3/TXOUT2M/LCD1_DATA3/LCD0_DATA19 C11 PIU60C11 P5_4/TXOUT1P/LCD1_DATA4/LCD0_DATA20 C10 PIU60C10 P5_5/TXOUT1M/LCD1_DATA5/LCD0_DATA21 A9 PIU60A9 P5_6/TXOUT0P/LCD1_DATA6/LCD0_DATA22 B9 PIU60B9 P5_7/TXOUT0M/LCD1_DATA7/LCD0_DATA23 B8 PIU60B8 P5_8/LCD0_EXTCLK/IRQ0/DV1_CLK/DV0_CLK A7 PIU60A7 P5_9/WE2/DQMUL/MDC/DV0_VSYNC/IRQ2 B7 PIU60B7 P5_10/WE3/DQMUU/AH/DV0_HSYNC/CTx1/IETxD 2 P6_0/D0/LCD1_DATA8/LRXD0/DV0_CLK/TIOC1A P6_1/D1/LCD1_DATA9/LTXD0/IRQ4/TIOC1B P6_2/D2/LCD1_DATA10/LRXD1/IRQ7/TCLKA P6_3/D3/LCD1_DATA11/LTXD1/IRQ2/CTS5 P6_4/D4/LCD1_DATA12/CRx2/IRQ3/RTS5 P6_5/D5/LCD1_DATA13/CTx2/SCK5 P6_6/D6/LCD1_DATA14/LCD0_TCON5/TxD5 P6_7/D7/LCD1_DATA15/LCD0_TCON6 P6_8/D8/DV0_DATA12/CAN_CLK P6_9/D9/DV0_DATA13/TxD0/LCD0_DATA1/IRQ1 P6_10/D10/DV0_DATA14/LCD0_TCON5/RxD0/LCD0_DATA2 P6_11/D11/DV0_DATA15/LCD0_TCON6/SCK1/LCD0_DATA3 P6_12/D12/DV0_DATA20/TXD1/LCD0_DATA4 P6_13/D13/DV0_DATA21/SCK6/RXD1/LCD0_DATA5 P6_14/D14/DV0_DATA22/TxD6/LCD0_DATA6 P6_15/D15/DV0_DATA23/RxD6/LCD0_DATA7 P3_0/LCD0_CLK/TXCLK/IRQ2/SCK2/SCIc_SCK1 P3_1/LCD0_TCON0/TXER/IRQ6/TxD2/SCIc_TXD1 P3_2/LCD0_TCON1/TXEN/RxD2/SCIc_RXD1 P3_3/LCD0_TCON2/MDIO/IRQ4/BS/SCIc_CTS1#/RTS1# P3_4/LCD0_TCON3/RXCLK/SSISCK1/AUDIO_XOUT2 P3_5/LCD0_TCON4/RXER/SSIWS1/AUDIO_XOUT3/SCIc_TXD0 P3_6/LCD0_TCON5/RXDV/SSIRxD1/SCIc_RXD0 P3_7/LCD0_TCON6/SSITxD1/LCD1_EXTCLK/SCIc_CTS0 P3_8/LCD0_DATA0/NAF0/TRACE_DATA0 P3_9/LCD0_DATA1/NAF1/TRACE_DATA1 P3_10/LCD0_DATA2/NAF2/TRACE_DATA2 P3_11/LCD0_DATA3/NAF3/TRACE_DATA3 P3_12/LCD0_DATA4/NAF4/SD_CLK_1/MMC_CLK P3_13/LCD0_DATA5/NAF5/AUDIO_XOUT/SD_CMD_1/MMC_CMD P3_14/LCD0_DATA6/NAF6/TRACE_CLK/SD_D3_1/MMC_D3 P3_15/LCD0_DATA7/NAF7/TRACE_CTRL/SD_D2_1/MMC_D2 AB6 B3 D6 C4 D5 PIU60D5 A2 PIU60A2 C1 PIU60C1 D2 PIU60D2 D1 PIU60D1 E3 PIU60E3 E2 PIU60E2 E1 PIU60E1 F3 PIU60F3 G4 PIU60G4 F2 PIU60F2 F1 PIU60F1 G3 PIU60G3 PIU60C4 PIU60D6 PIU60B3 PIU60Y7 Y7 AA6 PIU60AA6 Y5 PIU60Y5 AA4 PIU60AA4 AB3 PIU60AB3 Y4 PIU60Y4 V19 PIU60V19 W20 PIU60W20 T20 PIU60T20 T21 PIU60T21 T22 PIU60T22 R22 PIU60R22 R21 PIU60R21 R20 PIU60R20 AA7 PIU60AA7 PIU60AB6 3 CORA1DCBA CORA2DCBA CORA3DCBA CORA4DCBA PIRA104 PIRA103 PIRA102 PIRA101 PIRA204 PIRA203 PIRA202 PIRA201 PIRA304 PIRA303 PIRA302 PIRA301 PIRA404 PIRA403 PIRA402 PIRA401 PIRA105 PIRA106 PIRA107 PIRA108 PIRA205 PIRA206 PIRA207 PIRA208 PIRA305 PIRA306 PIRA307 PIRA308 PIRA405 PIRA406 PIRA407 PIRA408 5 RA1D 6 RA1C 7 RA1B 8 RA1A 5 RA2D 6 RA2C 7 RA2B 8 RA2A 5 RA3D 6 RA3C 7 RA3B 8 RA3A 5 RA4D 6 RA4C 7 RA4B 8 RA4A 3 Author: Jorge Amodio Date: 4/15/2015 Revision: v2.1 PCB02 Sheet 4 of 8 MCU Data/Address Bus, Serial & LCD Interfaces Renesas YLCDRZA1H MCU Module +3V3 NLP6000D0 P6_0/D0 NLP6010D1 P6_1/D1 NLP6020D2 P6_2/D2 NLP6030D3 P6_3/D3 NLP6040D4 P6_4/D4 NLP6050D5 P6_5/D5 NLP6060D6 P6_6/D6 NLP6070D7 P6_7/D7 NLP6080D8 P6_8/D8 NLP6090D9 P6_9/D9 NLP60100D10 P6_10/D10 NLP60110D11 P6_11/D11 NLP60120D12 P6_12/D12 NLP60130D13 P6_13/D13 NLP60140D14 P6_14/D14 NLP60150D15 P6_15/D15 NLP3000LCD0CLK P3_0/LCD_CLK NLP3010UART0TX P3_1/UART_TX NLP3020UART0RX P3_2/UART_RX NLP3030ET0MDIO P3_3/ET_MDIO NLP3040ET0RXCLK P3_4/ET_RXCLK NLP3050ET0RXER P3_5/ET_RXER NLP3060ET0RXDV P3_6/ET_RXDV NLP3070PMOD0RST# P3_7-PMOD_RST# NLP3080RZM0LED0RED P3_8-RZM_LED_RED NLP3090RZM0LED0GRN P3_9-RZM_LED_GRN NLP30100MMC0 D1 D1 P3_10/MMC_ NLP30110MMC0 D0 D0 P3_11/MMC_ NLP30120MMC0CLK CLK P3_12/MMC_ NLP30130MMC0CMD CMD P3_13/MMC_ NLP30140MMC0 D3 D3 P3_14/MMC_ NLP30150MMC0 D2 D2 P3_15/MMC_ 4 4 am.renesas.com/HiResGUI 4 4K70 3 4K70 2 4K70 1 4K70 4 4K70 3 4K70 2 4K70 1 4K70 4 4K70 3 4K70 2 4K70 1 4K70 4 4K70 3 4K70 2 4K70 1 4K70 D C B A D C B A PIRA507 PIRA506 PIRA505 PIR1602 PIRA501 PIRA502 PIRA503 PIRA504 PIR1601 CORA5DCBA PIRA508 H4 H2 H1 PIU60H1 J3 PIU60J3 J2 PIU60J2 J1 PIU60J1 K3 PIU60K3 K2 PIU60K2 K4 PIU60K4 AA17 PIU60AA17 AB18 PIU60AB18 Y17 PIU60Y17 AA18 PIU60AA18 AB19 PIU60AB19 Y18 PIU60Y18 AA19 PIU60AA19 Y19 PIU60Y19 NLP1080AN00ALS P1_8/AN0_ALS NLP1090IRQ30AUDIO0IRQ P1_9/IRQ3-AUDIO_IRQ P1_10/IRQ4-TOUCH_IRQ NLP10100IRQ40TOUCH0IRQ NLP10110TINT190PMOD0IRQ P1_11/TINT19-PMOD_IRQ NLP10120TINT200USBH0OC P1_12/TINT20-USBH_OC NLP10130USBH05V0EN P1_13-USBH_5V_EN NLP10140ET0COL P1_14/ET_COL NLP10150LCD0ON P1_15-LCD_ON PIU60H2 PIU60H4 NLP7000MD0BOOT2 P7_0/MD_BOOT2 NLP7010CS3#0SDRAM20CS# P7_1/CS3#-SDRAM2_CS# NLP7020RAS# P7_2/RAS# NLP7030CAS# P7_3/CAS# NLP7040CKE P7_4/CKE NLP7050RD0WR# P7_5/RD/WR# NLP7060WE0#0DQMLL P7_6/WE0#/DQMLL NLP7070WE1#0DQMLU P7_7/WE1#/DQMLU NLP7080IRQ1 P7_8/IRQ1 1 2 2 P1_8/AN0/IRQ2/DREQ0/VIO_D14/DV0_DATA14/MSN_VDC50 P1_9/AN1/IRQ3/VIO_D15/DV0_DATA15/MSN_VDC51 P1_10/AN2/IRQ4/TCLKB/MSN_DVDEC0 P1_11/AN3/IRQ5/TCLKD/MSN_DVDEC1 P1_12/AN4/DV0_VSYNC/VIO_FLD/MPSEL P1_13/AN5/DV0_HSYNC/WAIT/MST P1_14/AN6/COL/MSD P1_15/AN7 P7_0/MD_BOOT2/CS0/DV0_DATA16/MDC/SCK4/LTXD0/TIOC0A P7_1/CS3/DV0_DATA17/TXCLK/TXD4/DV0_CLK/SSISCK1/TIOC0B P7_2/RAS/DV0_DATA18/TXER/RXD4/CRx2/SSIWS1/TIOC0C P7_3/CAS/DV0_DATA19/TXEN/SCK7/CTx2/SSIRxD1/TIOC0D P7_4/CKE/DV0_DATA20/TXD[0]/TXD7/UARTH_CLK/SSITxD1/TIOC1A P7_5/RD/WR/DV0_DATA21/TXD[1]/RXD7/UARTH_RxD/SSISCK2/TIOC1B P7_6/WE0/DQMLL/DV0_DATA22/TXD[2]/CTS7/UARTH_TxD/SSIWS2/TIOC2A P7_7/WE1/DQMLU/DV0_DATA23/TXD[3]/RTS7/SSIDATA2/TIOC2B P7_8/RD/SSISCK3/CRx0/TIOC3A/IRQ1 P1_0/SCL0/DV0_DATA16/TCLKA/IRQ0/VIO_VD/DV0_VSYNC/SCL0I P1_1/SDA0/DV0_DATA17/TCLKC/IRQ1/VIO_HD/DV0_HSYNC/SDA0I P1_2/SCL1/DV0_DATA18/FRB/IRQ2/ICN_SCK/LCD1_EXTCLK/SCL1I P1_3/SDA1/DV0_DATA19/COL/IRQ3/ICN_SDATA/SDA1I P1_4/SCL2/DV0_CLK/CRx1/IRQ4/ICN_SCK/CAN_CLK/SCL2I P1_5/SDA2/DV1_CLK/CRx4/IRQ5/VIO_CLK/ICN_SDATA/LCD1_EXTCLK/SDA2I P1_6/SCL3/DV1_VSYNC/IERxD/IRQ6/VIO_D12/DV0_DATA12/MLB_CLK/SCL3I P1_7/SDA3/DV1_HSYNC/LRXD0/IRQ7/VIO_D13/DV0_DATA13/SDA3I COU6A U6A RZ/1AH-BGA324 K1 PIU60K1 P7_9/A1/SSIWS3/RXD[0]/CTx0/DARC_BPFCLK1/TIOC3B/IRQ0 L3 PIU60L3 P7_10/A2/SSIRxD3/RXD[1]/CTx1/DARC_FMCLK/TIOC3C/IRQ2 L2 PIU60L2 P7_11/A3/SSITxD3/RXD[2]/CRx1/DARC_FMIN/TIOC3D/IRQ3 M1 PIU60M1 P7_12/A4/SSISCK4/RXD[3]/TIOC4A/IRQ4 N1 PIU60N1 P7_13/A5/SSIWS4/MDIO/TIOC4B/IRQ5 N2 PIU60N2 P7_14/A6/SSIDATA4/CRS/TIOC4C/IRQ6 N3 PIU60N3 P7_15/A7/RSPCK0/RXCLK/CTS5/SCIc_TXD0/IrTXD/TIOC4D P1 PIU60P1 P8_0/A8/SSL00/RXER/SCK5/SCIc_SCK0 P2 PIU60P2 P8_1/A9/MOSI0/RXDV/TXD5/SCIc_RXD0/IrRXD P3 PIU60P3 P8_2/A10/MISO0/RXD5/IRQ0 R1 PIU60R1 P8_3/A11/DV1_DATA0/RSPCK2/RTS5/UARTH_CLK/IRQ1/SCK2 R2 PIU60R2 P8_4/A12/DV1_DATA1/SSL20/IERxD/RxD2 R3 PIU60R3 P8_5/A13/DV1_DATA2/MOSI2/UARTH_RxD U2 PIU60U2 P8_6/A14/DV1_DATA3/MISO2/UARTH_TxD/IETxD/TxD2 U4 PIU60U4 P8_7/A15/DV1_DATA4/AUDIO_XOUT/IRQ5/COL V2 PIU60V2 P8_8/A16/DV1_DATA5/SPBIO0_1/SPDIF_IN/TIOC1A/PWM1A/TxD3/SSISCK5 V3 PIU60V3 P8_9/A17/DV1_DATA6/SPBIO1_1/SPDIF_OUT/TIOC1B/PWM1B/RxD3/SSIWS5 W2 PIU60W2 P8_10/A18/DV1_DATA7/SPBIO2_1/TIOC3A/CTx4/PWM1C/SGOUT_0/DV0_CLK W3 PIU60W3 P8_11/A19/MLB_CLK/SPBIO3_1/TIOC3B/RxD5/PWM1D/SGOUT_1/SSITxD5 Y1 PIU60Y1 P8_12/A20/MLB_DAT/SPBCLK_1/TIOC3C/SCK5/PWM1E/SGOUT_2/SSISCK4 V4 PIU60V4 P8_13/A21/MLB_SIG/SPBSSL_1/TIOC3D/TXD5/PWM1F/SGOUT_3/SSIWS4 Y2 PIU60Y2 P8_14/A22/SPBIO4_0/SPBIO0_1/TIOC2A/RSPCK2/PWM1G/TxD4/SSIDATA4 AA1 PIU60AA1 P8_15/A23/SPBIO5_0/SPBIO1_1/TIOC2B/SSL20/PWM1H/RxD4 AB2 PIU60AB2 P9_0/A24/SPBIO6_0/CTx0/TCLKC/MOSI2/SCL0O AA3 PIU60AA3 P9_1/A25/SPBIO7_0/CRx0/IRQ0/MISO2/MSQ/SDA0O A19 PIU60A19 C17 PIU60C17 B18 PIU60B18 A18 PIU60A18 B17 PIU60B17 C16 PIU60C16 A17 PIU60A17 B16 PIU60B16 COR16 R16 4K70 NLP1020SCL1 P1_2/SCL1 NLP1030SDA1 P1_3/SDA1 NLP1040CAN1RX P1_4/CAN1RX NLP1050IRQ50ET0IRQ P1_5/IRQ5-ET_IRQ NLP1060SCL3 P1_6/SCL3 NLP1070SDA3 P1_7/SDA3 NLP1000SCL0 P1_0/SCL0 NLP1010SDA0 P1_1/SDA0 NLP70100A2 P7_10/A2 NLP70110A3 P7_11/A3 NLP70120A4 P7_12/A4 NLP70130A5 P7_13/A5 NLP70140A6 P7_14/A6 NLP70150A7 P7_15/A7 NLP8000A8 P8_0/A8 NLP8010A9 P8_1/A9 NLP8020A10 P8_2/A10 NLP8030A11 P8_3/A11 NLP8040A12 P8_4/A12 NLP8050A13 P8_5/A13 NLP8060A14 P8_6/A14 NLP8070A15 P8_7/A15 NLP808 P8_8 NLP809 P8_9 NLP80100RS0DEN P8_10/RS_DEN NLP80110RS0ON P8_11/RS_ON NLP80120PWM1E0BLEN P8_12/PWM1E-BLEN NLP80130TOUCH0RST P8_13-TOUCH_RST NLP80140RSPCK2 P8_14/RSPCK2 NLP80150SSL20 P8_15/SSL20 NLP9000MOSI2 P9_0/MOSI2 NLP9010MISO2 P9_1/MISO2 NLP7090A1 P7_9/A1 +3V3 1 8 RA5A 7 RA5B 6 RA5C 5 RA5D 1 4K70 2 4K70 3 4K70 4 4K70 3 A4 C6 B4 C5 PIU60C5 L4 PIU60L4 L1 PIU60L1 M2 PIU60M2 M3 PIU60M3 T1 PIU60T1 T2 PIU60T2 T3 PIU60T3 U3 PIU60U3 G2 PIU60G2 G1 PIU60G1 H3 PIU60H3 J4 PIU60J4 Author: Jorge Amodio Date: 4/15/2015 Revision: v2.1 PCB02 Sheet 5 of 8 MCU e-MMC, SDRAM, I2C Iinterfaces & GPIO PIU60B4 PIU60C6 PIU60A4 Y6 PIU60Y6 AB5 PIU60AB5 N19 PIU60N19 N20 PIU60N20 N21 PIU60N21 M22 PIU60M22 J21 PIU60J21 J20 PIU60J20 H21 PIU60H21 H20 PIU60H20 E21 PIU60E21 F20 PIU60F20 D22 PIU60D22 D21 PIU60D21 4 am.renesas.com/HiResGUI NLP11000LCD0DATA7 P11_0/LCD_DATA7 NLP11010LCD0DATA6 P11_1/LCD_DATA6 NLP11020LCD0DATA5 P11_2/LCD_DATA5 NLP11030LCD0DATA4 P11_3/LCD_DATA4 NLP11040LCD0DATA3 P11_4/LCD_DATA3 NLP11050LCD0DATA2 P11_5/LCD_DATA2 NLP11060LCD0DATA1 P11_6/LCD_DATA1 NLP11070LCD0DATA0 P11_7/LCD_DATA0 NLP11080LCD0DEN P11_8/LCD_DEN NLP11090LCD0VSYNC P11_9/LCD_VSYNC NLP110100LCD0HSYNC P11_10/LCD_HSYNC NLP110110LED1R P11_11-LED1R P11_12/MMC_ NLP110120MMC0 D4 D4 NLP110130MMC0 D5 D5 P11_13/MMC_ NLP110140MMC0 D6 D6 P11_14/MMC_ NLP110150MMC0 D7 D7 P11_15/MMC_ NLP10000VIO0CLK P10_0/VIO_CLK NLP10010VIO0VSYNC P10_1/VIO_VSYNC NLP10020VIO0HSYNC P10_2/VIO_HSYNC NLP10030VIO0FLD P10_3/VIO_FLD NLP10040VIO0D0 P10_4/VIO_D0 NLP10050VIO0D1 P10_5/VIO_D1 NLP10060VIO0D2 P10_6/VIO_D2 NLP10070VIO0D3 P10_7/VIO_D3 NLP10080VIO0D4 P10_8/VIO_D4 NLP10000VIO0D5 P10_0/VIO_D5 NLP100100VIO0D6 P10_10/VIO_D6 NLP100110VIO0D7 P10_11/VIO_D7 NLP100120SSISCK P10_12/SSISCK NLP100130SSIWS P10_13/SSIWS NLP100140SSIRxD P10_14/SSIRxD NLP100150SSITxD P10_15/SSITxD NLP20120SPBIO01 P2_12/SPBIO01 AB4 AA5 PIU60AA5 PIU60AB4 PIU60C18 C18 B19 PIU60B19 L21 PIU60L21 K22 PIU60K22 F21 PIU60F21 G20 PIU60G20 F19 PIU60F19 E22 PIU60E22 E20 PIU60E20 C22 PIU60C22 D20 PIU60D20 C21 PIU60C21 B22 PIU60B22 E19 PIU60E19 NLP20130SPBIO11 P2_13/SPBIO11 NLP20140SPBIO21 P2_14/SPBIO21 NLP20150SPBIO31 P2_15/SPBIO31 NLP2000ET0TXCLK P2_0/ET_TXCLK NLP2010ET0TXER P2_1/ET_TXER NLP2020ET0TXEN P2_2/ET_TXEN NLP2030ET0CRS P2_3/ET_CRS NLP2040ET0TXD0 P2_4/ET_TXD0 NLP2050ET0TXD1 P2_5/ET_TXD1 NLP2060ET0TXD2 P2_6/ET_TXD2 NLP2070ET0TXD3 P2_7/ET_TXD3 NLP2080ET0RXD0 P2_8/ET_RXD0 NLP2090ET0RXD1 P2_9/ET_RXD1 NLP20100ET0RXD2 P2_10/ET_RXD2 NLP20110ET0RXD3 P2_11/ET_RXD3 A21 4 A20 PIU60A20 PIU60A21 Renesas YLCDRZA1H MCU Module P11_0/DV0_DATA12/TIOC4A/MLB_CLK/SCK6/LCD0_DATA7/VIO_D12 P11_1/DV0_DATA13/TIOC4B/MLB_DAT/TxD6/LCD0_DATA6/VIO_D13 P11_2/DV0_DATA14/TIOC4C/MLB_SIG/RxD6/LCD0_DATA5/VIO_D14 P11_3/DV0_DATA15/TIOC4D/LCD0_DATA4/VIO_D15 P11_4/DV0_DATA16/SD_CD_0/SSISCK4/MMC_CD/LCD0_DATA3 P11_5/DV0_DATA17/SD_WP_0/SSIWS4/LCD0_DATA2 P11_6/DV0_DATA18/SD_D1_0/SSIDATA4/MMC_D1/LCD0_DATA1 P11_7/DV0_DATA19/SD_D0_0/CTS5/MMC_D0/LCD0_DATA0 P11_8/DV0_DATA20/SD_CLK_0/RTS5/MMC_CLK/LCD0_TCON6 P11_9/DV0_DATA21/SD_CMD_0/SCK5/MMC_CMD/LCD0_TCON5 P11_10/DV0_DATA22/SD_D3_0/TxD5/MMC_D3/LCD0_TCON4 P11_11/DV0_DATA23/SD_D2_0/RxD5/MMC_D2/LCD0_TCON3 P11_12/CRx1/RSPCK1/IRQ3/MMC_D4/LCD0_TCON2 P11_13/CTx1/SSL01/LCD0_TCON4/MMC_D5/LCD0_TCON1 P11_14/SPDIF_IN/MOSI1/LCD0_TCON5/MMC_D6/LCD0_TCON0 P11_15/SPDIF_OUT/MISO1/IRQ1/MMC_D7/LCD0_CLK P10_0/DV0_CLK/TCLKA/PWM2A/TXCLK/LCD0_DATA23/VIO_CLK P10_1/DV0_VSYNC/TCLKB/PWM2B/TXER/LCD0_DATA22/VIO_VD P10_2/DV0_HSYNC/TCLKC/PWM2C/TXEN/LCD0_DATA21/VIO_HD P10_3/DV0_DEN/TCLKD/PWM2D/CRS/LCD0_DATA20/VIO_FLD P10_4/DV0_DATA0/TIOC0A/PWM2E/TXD[0]/LCD0_DATA19/VIO_D0 P10_5/DV0_DATA1/TIOC0B/PWM2F/TXD[1]/LCD0_DATA18/VIO_D1 P10_6/DV0_DATA2/TIOC0C/PWM2G/TXD[2]/LCD0_DATA17/VIO_D2 P10_7/DV0_DATA3/TIOC0D/PWM2H/TXD[3]/LCD0_DATA16/VIO_D3 P10_8/DV0_DATA4/TIOC1A/RXD[0]/LCD0_DATA15/VIO_D4 P10_9/DV0_DATA5/TIOC1B/RXD[1]/LCD0_DATA14/VIO_D5 P10_10/DV0_DATA6/TIOC2A/RXD[2]/LCD0_DATA13/VIO_D6 P10_11/DV0_DATA7/TIOC2B/RXD[3]/LCD0_DATA12/VIO_D7 P10_12/DV0_DATA8/SSISCK1/RSPCK0/LCD0_DATA11/VIO_D8 P10_13/DV0_DATA9/SSIWS1/SSL00/LCD0_DATA10/VIO_D9 P10_14/DV0_DATA10/SSIRxD1/MOSI0/LCD0_DATA9/VIO_D10 P10_15/DV0_DATA11/SSITxD1/MISO0/LCD0_DATA8/VIO_D11 P2_12/D28/RSPCK0/DV0_DATA12/SPBIO4_0/CRx3/IRQ6/LCD1_DATA12/TIOC1B P2_13/D29/SSL00/DV0_DATA13/SPBIO5_0/CTx3/SCK0/LCD1_DATA13/IRQ7 P2_14/D30/MOSI0/DV0_DATA14/SPBIO6_0/CRx4/TxD0/LCD1_DATA14/IRQ0 P2_15/D31/MISO0/DV0_DATA15/SPBIO7_0/CAN_CLK/RxD0/LCD1_DATA15/IRQ1 P2_0/D16/TXCLK/DV0_DATA0/SPBIO0_1/MLB_CLK/IRQ5/VIO_D0/LCD0_DATA16 P2_1/D17/TXER/DV0_DATA1/SPBIO1_1/MLB_DAT/TIOC2A/VIO_D1/LCD0_DATA17 P2_2/D18/TXEN/DV0_DATA2/SPBIO2_1/MLB_SIG/TIOC2B/VIO_D2/LCD0_DATA18 P2_3/D19/CRS/DV0_DATA3/SPBIO3_1/IERxD/CTS1/VIO_D3/LCD0_DATA19 P2_4/D20/TXD[0]/DV0_DATA4/SSISCK5/SPBCLK_1/SCK1/VIO_D4/LCD0_DATA20 P2_5/D21/TXD[1]/DV0_DATA5/SSIWS5/SPBSSL_1/TxD1/VIO_D5/LCD0_DATA21 P2_6/D22/TXD[2]/DV0_DATA6/SSIRxD5/RxD1/VIO_D6/LCD0_DATA22 P2_7/D23/TXD[3]/DV0_DATA7/SSITxD5/IETxD/RTS1/VIO_D7/LCD0_DATA23 P2_8/D24/RXD[0]/DV0_DATA8/SSISCK0/LCD0_TCON6/LCD1_DATA8/VIO_D8/RSPCK4 P2_9/D25/RXD[1]/DV0_DATA9/SSIWS0/LRXD0/LCD1_DATA9/VIO_D9/SSL40 P2_10/D26/RXD[2]/DV0_DATA10/SSIRxD0/LTXD0/LCD1_DATA10/VIO_D10/MOSI4 P2_11/D27/RXD[3]/DV0_DATA11/SSITxD0/TIOC1A/LCD1_DATA11/VIO_D11/MISO4 3 D C B A D C B 1 NLP20120SPBIO01 P2_12/SPBIO01 NLP20130SPBIO11 P2_13/SPBIO11 NLP20140SPBIO21 P2_14/SPBIO21 NLP20150SPBIO31 P2_15/SPBIO31 NLP9050SPBIO10 P9_5/SPBIO10 NLP9060SPBIO20 P9_6/SPBIO20 NLP9070SPBIO30 P9_7/SPBIO30 NLP9040SPBIO00 P9_4/SPBIO00 NLP9030SPBSSL0 P9_3/SPBSSL0 NLP9020SPBCLK0 P9_2/SPBCLK0 +3V3 PIR1501 PIR1502 COR15 R15 4K70 PIR1701 PIR1702 COR17 R17 4K70 CORA6DCBA CORA7DCBA 2 PIRA602 PIRA604 PIRA603 PIRA601 PIRA702 PIRA704 PIRA703 PIRA701 PIRA607 PIRA605 PIRA606 PIRA608 PIRA707 PIRA705 PIRA706 PIRA708 2 7 RA6B 5 RA6D 6 RA6C 8 RA6A 7 RA7B 5 RA7D 6 RA7C 8 RA7A 2 4K70 4 4K70 3 4K70 1 4K70 2 4K70 4 4K70 3 4K70 1 4K70 A 1 PIU50PAD PIU80PAD GND GND 5 DQ0 2 DQ1 3 PIU803 DQ2/W 7 4 PIU807 DQ3/H VSS PIU804 PIU802 PIU805 COU8 U8 N25Q256A 1 8 PIU801 S VCC PIU808 6 PIU806 C GND GND 5 DQ0 2 DQ1 3 PIU503 DQ2/W 7 4 PIU507 DQ3/H VSS PIU504 PIU502 PIU505 COU5 U5 N25Q256A 1 8 PIU501 S VCC PIU508 6 PIU506 C PAD PAD COC52 C52 0.1uF GND PIC5202 PIC5201 GND PIC50 2 PIC50 1 COC50 C50 0.1uF 3 3 GND PIC5102 PIC5101 COC51 C51 0.1uF Author: Jorge Amodio Date: 4/15/2015 Dual QSPI FLASH & EEPROM GND GND 4 4 am.renesas.com/HiResGUI NLP1010SDA0 P1_1/SDA0 NLP1000SCL0 P1_0/SCL0 Revision: v2.1 PCB02 Sheet 6 of 8 Renesas YLCDRZA1H MCU Module GND PIU70PAD COU7 U7 CAT34C02 8 1 PIU708 VCC A0 PIU701 7 2 PIU707 WP A1 PIU702 6 3 PIU706 PIU703 SCL A2 5 4 PIU705 SDA VSS PIU704 PAD D C B A D C B A NL03V3 +3V3 PIRA802 PIRA803 PIRA801 PIRA804 CORA8DCBA PIRA807 PIRA806 PIRA808 PIRA805 1 P7_4/CKE CKIO COR18 R18 4.7K GND PIR1801 F2 PIU90F2 PIU90F3 F3 PIU90F1 PIU90F8 PIU90G9 CKE CLK F1 UDQM E8 PIU90E8 LDQM PIU90A9 P7_7/WE1#/DQMLU P7_6/WE0#/DQMLL P7_2/RAS# P7_3/CAS# P7_5/RD/WR# PIC5402 PIC5401 0.1uF COC54 C54 GND G9 CS F8 RAS F7 PIU90F7 CAS F9 PIU90F9 WE PIR1802 0.1uF COC53 C53 GND PIC5 02 PIC5 01 VSS VSS VSS VSSQ VSSQ VSSQ VSSQ GND PIC5602 PIC5601 A1 E3 J1 A3 PIU90A3 B7 PIU90B7 C3 PIU90C3 D7 PIU90D7 GND PIU90J1 PIU90E3 PIU90A1 PIU90E2 E2 PIU90B8 PIU90C9 C9 B8 B9 PIU90B9 A8 PIU90A8 D9 PIU90D9 C8 PIU90C8 D8 PIU90D8 PIU90E9 E9 PIU90C2 2 P6_3/D3 P6_2/D2 P6_1/D1 P6_0/D0 P6_7/D7 P6_6/D6 P6_5/D5 P6_4/D4 P6_11/D11 P6_10/D10 P6_9/D9 P6_8/D8 0.1uF COC58 C58 GND PIC5802 PIC5801 C2 D1 PIU90D1 D2 PIU90D2 E1 PIU90E1 0.1uF COC57 C57 GND PIC5702 PIC5701 P6_15/D15 P6_14/D14 P6_13/D13 P6_12/D12 0.1uF COC56 C56 2 A2 B1 PIU90B1 B2 PIU90B2 C1 PIU90C1 PIU90A2 COC55 C55 0.1uF COU9 U9 MT48LC16M16A2P A9 VDD DQ15 E7 PIU90E7 VDD DQ14 J9 PIU90J9 VDD DQ13 A7 PIU90A7 VDDQ DQ12 B3 PIU90B3 VDDQ C7 PIU90C7 VDDQ DQ11 D3 PIU90D3 VDDQ DQ10 DQ9 G8 PIU90G8 BA1 DQ8 G7 PIU90G7 BA0 DQ7 G1 PIU90G1 A12 DQ6 G2 PIU90G2 A11 DQ5 H9 PIU90H9 A10 DQ4 G3 PIU90G3 A9 H1 PIU90H1 A8 DQ3 H2 PIU90H2 A7 DQ2 H3 PIU90H3 A6 DQ1 J2 PIU90J2 A5 DQ0 J3 PIU90J3 A4 J7 PIU90J7 A3 J8 PIU90J8 A2 NC H8 PIU90H8 A1 H7 PIU90H7 A0 GND PIC5302 PIC5301 NLP5080CS2#0SDRAM10CS# P5_8/CS2#-SDRAM1_CS# P8_5/A13 P8_4/A12 P8_3/A11 P8_2/A10 P8_1/A9 P8_0/A8 P7_15/A7 P7_14/A6 P7_13/A5 P7_12/A4 P7_11/A3 P7_10/A2 P7_9/A1 P8_7/A15 P8_6/A14 +3V3 1 7 RA8B 6 RA8C 8 RA8A 5 RA8D 2 4K70 3 4K70 1 4K70 4 4K70 GND PIC5902 PIC5901 COC59 C59 0.1uF NLP7040CKE P7_4/CKE NLCKIO CKIO NLP7070WE1#0DQMLU P7_7/WE1#/DQMLU NLP7060WE0#0DQMLL P7_6/WE0#/DQMLL NLP7010CS3#0SDRAM20CS# P7_1/CS3#-SDRAM2_CS# NLP7020RAS# P7_2/RAS# NLP7030CAS# P7_3/CAS# NLP7050RD0WR# P7_5/RD/WR# NLP8050A13 P8_5/A13 NLP8040A12 P8_4/A12 NLP8030A11 P8_3/A11 NLP8020A10 P8_2/A10 NLP8010A9 P8_1/A9 NLP8000A8 P8_0/A8 NLP70150A7 P7_15/A7 NLP70140A6 P7_14/A6 NLP70130A5 P7_13/A5 NLP70120A4 P7_12/A4 NLP70110A3 P7_11/A3 NLP70100A2 P7_10/A2 NLP7090A1 P7_9/A1 NLP8070A15 P8_7/A15 NLP8060A14 P8_6/A14 3 PIC60 2 PIC60 1 COC60 C60 0.1uF GND PIC6102 PIC6101 COC61 C61 0.1uF GND PIC6202 PIC6201 G9 CS F8 RAS F7 PIU100F7 CAS F9 PIU100F9 WE F3 F2 PIU100F2 PIU100F3 VSS VSS VSS VSSQ VSSQ VSSQ VSSQ C1 C2 C9 B8 B9 PIU100B9 A8 PIU100A8 A1 E3 J1 A3 PIU100A3 B7 PIU100B7 C3 PIU100C3 D7 PIU100D7 GND PIU100J1 PIU100E3 PIU100A1 E2 PIU100E2 PIU100B8 PIU100C9 D9 PIU100D9 C8 PIU100C8 E9 D8 PIU100D8 PIU100E9 PIU100D2 D2 E1 PIU100E1 D1 PIU100D1 PIU100C2 PIU100C1 Author: Jorge Amodio Date: 4/15/2015 PIC6402 PIC6401 GND GND PIC6502 PIC6501 NLP60110D11 P6_11/D11 NLP60100D10 P6_10/D10 NLP6090D9 P6_9/D9 NLP6080D8 P6_8/D8 0.1uF COC66 C66 4 4 am.renesas.com/HiResGUI NLP6030D3 P6_3/D3 NLP6020D2 P6_2/D2 NLP6010D1 P6_1/D1 NLP6000D0 P6_0/D0 NLP6070D7 P6_7/D7 NLP6060D6 P6_6/D6 NLP6050D5 P6_5/D5 NLP6040D4 P6_4/D4 PIC6 02 PIC6 01 GND COC65 C65 0.1uF NLP60150D15 P6_15/D15 NLP60140D14 P6_14/D14 NLP60130D13 P6_13/D13 NLP60120D12 P6_12/D12 COC64 C64 0.1uF Revision: v2.1 PCB02 Sheet 7 of 8 Renesas YLCDRZA1H MCU Module CKE CLK F1 UDQM E8 PIU100E8 LDQM PIU100F1 PIU100F8 PIU100G9 A2 B1 B2 PIU100B2 PIU100B1 0.1uF COC63 C63 GND PIC6302 PIC6301 PIU100A2 0.1uF COC62 C62 COU10 U10 MT48LC16M16A2P A9 VDD DQ15 E7 PIU100E7 VDD DQ14 J9 PIU100J9 VDD DQ13 A7 PIU100A7 VDDQ DQ12 B3 PIU100B3 VDDQ C7 PIU100C7 VDDQ DQ11 D3 PIU100D3 VDDQ DQ10 DQ9 G8 PIU100G8 BA1 DQ8 G7 PIU100G7 BA0 DQ7 G1 PIU100G1 A12 DQ6 G2 PIU100G2 A11 DQ5 H9 PIU100H9 A10 DQ4 G3 PIU100G3 A9 H1 PIU100H1 A8 DQ3 H2 PIU100H2 A7 DQ2 H3 PIU100H3 A6 DQ1 J2 PIU100J2 A5 DQ0 J3 PIU100J3 A4 J7 PIU100J7 A3 J8 PIU100J8 A2 NC H8 PIU100H8 A1 H7 PIU100H7 A0 PIU100A9 GND SDRAM COR19 R19 4.7K GND PIR1901 PIR1902 PIRA902 PIRA901 PIRA903 PIRA904 CORA9DCBA PIRA907 PIRA908 PIRA906 PIRA905 3 7 RA9B 8 RA9A 6 RA9C 5 RA9D 2 4K70 1 4K70 3 4K70 4 4K70 D C B A D C B A 1 1 7 22R0 1PIRA1001 CORA10A CORA10B CORA10C CORA10D RA10A PIRA1007 5 PIRA1005 22R0 3PIRA1003 RA10C NLP30150MMC0 D2 P3_15/MMC_ D2 NLP30130MMC0 CMD P3_13/MMC_ CMD NLP30100MMC0 D1 P3_10/MMC_ D1 NLP30120MMC0 CLK P3_12/MMC_ CLK NLP30110MMC0 D0 P3_11/MMC_ D0 NLTDO TDO NLTMS TMS NLTCK TCK NLTRST# TRST# NLTDI TDI NLP3080RZM0LED0RED P3_8-RZM_LED_RED NLP0010MD0BOOT1 P0_1/MD_BOOT1 NLP1090IRQ30AUDIO0IRQ P1_9/IRQ3-AUDIO_IRQ NLP3090RZM0LED0GRN P3_9-RZM_LED_GRN NLCLKAUDIO024MHZ CLKAUDIO_24MHZ NLP1080AN00ALS P1_8/AN0_ALS NLP10130USBH05V0EN P1_13-USBH_5V_EN NLP10110TINT190PMOD0IRQ P1_11/TINT19-PMOD_IRQ NLUSBH0P 2 USBH_P PIRA1002 NLUSBH0N USBH_N RA10B NLVBUSIN0 VBUSIN0 NLVBUSIN1 VBUSIN1 NLUSBF0N USBF_N PIRA1004 4 NLUSBF0P USBF_P RA10D NLP3020UART0RX P3_2/UART_RX NLP10020VIO0HSYNC P10_2/VIO_HSYNC NLP10010VIO0VSYNC P10_1/VIO_VSYNC NLP3030ET0MDIO P3_3/ET_MDIO NLP3000LCD0CLK P3_0/LCD_CLK NLP3010UART0TX P3_1/UART_TX NLRESET# RESET# NLP0050ET0RESET# P0_5-ET_RESET# NLP0040MMC0RST# P0_4-MMC_RST# NLP11090LCD0VSYNC P11_9/LCD_VSYNC NLP80130TOUCH0RST P8_13-TOUCH_RST NLP80110RS0ON P8_11/RS_ON NLP80100RS0DEN P8_10/RS_DEN NLP11080LCD0DEN P11_8/LCD_DEN 22R0 PIRA10088 6 22R0 PIRA1006 10 PIJ1010 12 PIJ1012 14 PIJ1014 16 PIJ1016 18 PIJ1018 20 PIJ1020 22 PIJ1022 24 PIJ1024 26 PIJ1026 28 PIJ1028 30 PIJ1030 32 PIJ1032 34 PIJ1034 36 PIJ1036 38 PIJ1038 40 PIJ1040 42 PIJ1042 44 PIJ1044 46 PIJ1046 48 PIJ1048 50 PIJ1050 52 PIJ1052 54 PIJ1054 56 PIJ1056 58 PIJ1058 60 PIJ1060 62 PIJ1062 64 PIJ1064 66 PIJ1066 68 PIJ1068 70 PIJ1070 72 PIJ1072 74 PIJ1074 76 PIJ1076 78 PIJ1078 80 PIJ1080 82 PIJ1082 84 PIJ1084 86 PIJ1086 88 PIJ1088 90 PIJ1090 92 PIJ1092 94 PIJ1094 96 PIJ1096 98 PIJ1098 100 PIJ10100 5 7 PIJ107 8 PIJ108 6 PIJ106 9 PIJ109 11 PIJ1011 13 PIJ1013 15 PIJ1015 17 PIJ1017 19 PIJ1019 21 PIJ1021 23 PIJ1023 25 PIJ1025 27 PIJ1027 29 PIJ1029 31 PIJ1031 33 PIJ1033 35 PIJ1035 37 PIJ1037 39 PIJ1039 41 PIJ1041 43 PIJ1043 45 PIJ1045 47 PIJ1047 49 PIJ1049 51 PIJ1051 53 PIJ1053 55 PIJ1055 57 PIJ1057 59 PIJ1059 61 PIJ1061 63 PIJ1063 65 PIJ1065 67 PIJ1067 69 PIJ1069 71 PIJ1071 73 PIJ1073 75 PIJ1075 77 PIJ1077 79 PIJ1079 81 PIJ1081 83 PIJ1083 85 PIJ1085 87 PIJ1087 89 PIJ1089 91 PIJ1091 93 PIJ1093 95 PIJ1095 97 PIJ1097 99 PIJ1099 2 PIJ102 PIJ105 COJ1A COJ1B J1A 4 PIJ104 1 3 PIJ103 PIJ101 GND 3 2 NLP10150LCD0ON P1_15-LCD_ON NLP10080VIO0D4 P10_8/VIO_D4 NLP40100SD0D1 P4_10/SD_D1 NLP100100VIO0D6 P10_10/VIO_D6 NLP40120SD0CLK P4_12/SD_CLK NLP40130SD0CMD P4_13/SD_CMD NLP10070VIO0D3 P10_7/VIO_D3 NLP4050LCD0DATA13 P4_5/LCD_DATA13 NLP2000ET0TXCLK P2_0/ET_TXCLK NLP4060LCD0DATA14 P4_6/LCD_DATA14 NLP4090SD0WP P4_9/SD_WP NLP2010ET0TXER P2_1/ET_TXER NLP4020LCD0DATA10 P4_2/LCD_DATA10 NLP4030LCD0DATA11 P4_3/LCD_DATA11 NLP10060VIO0D2 P10_6/VIO_D2 NLP30140MMC0 D3 P3_14/MMC_ D3 NLP4010LCD0DATA9 P4_1/LCD_DATA9 NLP10140ET0COL P1_14/ET_COL NLP10120TINT200USBH0OC P1_12/TINT20-USBH_OC NLP10100IRQ40TOUCH0IRQ P1_10/IRQ4-TOUCH_IRQ NLP3040ET0RXCLK P3_4/ET_RXCLK NL03V3 +3V3 NLP3050ET0RXER P3_5/ET_RXER NLP10030VIO0FLD P10_3/VIO_FLD NLP80150SSL20 P8_15/SSL20 NLP80140RSPCK2 P8_14/RSPCK2 NLP9000MOSI2 P9_0/MOSI2 NLP9010MISO2 P9_1/MISO2 NLP3060ET0RXDV P3_6/ET_RXDV NLP3070PMOD0RST# P3_7-PMOD_RST# NLP10000VIO0CLK P10_0/VIO_CLK NLP80120PWM1E0BLEN P8_12/PWM1E-BLEN NLP809 P8_9 NLP808 P8_8 NLP110100LCD0HSYNC P11_10/LCD_HSYNC NLCKIO CKIO NLP11060LCD0DATA1 P11_6/LCD_DATA1 +VEXT NLP11070LCD0DATA0 P11_7/LCD_DATA0 NLP7080IRQ1 P7_8/IRQ1 NLP11040LCD0DATA3 P11_4/LCD_DATA3 NLP11050LCD0DATA2 P11_5/LCD_DATA2 NLP110130MMC0 D5 P11_13/MMC_ D5 NLP110150MMC0 D7 P11_15/MMC_ D7 NLP1050IRQ50ET0IRQ P1_5/IRQ5-ET_IRQ NLP9050SPBIO10 P9_5/SPBIO10 NLP11010LCD0DATA6 P11_1/LCD_DATA6 NLP11030LCD0DATA4 P11_3/LCD_DATA4 NLP7000MD0BOOT2 P7_0/MD_BOOT2 NLP11000LCD0DATA7 P11_0/LCD_DATA7 NLP11020LCD0DATA5 P11_2/LCD_DATA5 NLP110140MMC0 D6 P11_14/MMC_ D6 NLP110120MMC0 D4 P11_12/MMC_ D4 NLP1030SDA1 P1_3/SDA1 NLP1020SCL1 P1_2/SCL1 NLP2040ET0TXD0 P2_4/ET_TXD0 NLP20110ET0RXD3 P2_11/ET_RXD3 NLP100130SSIWS P10_13/SSIWS NLP2060ET0TXD2 P2_6/ET_TXD2 NLP2080ET0RXD0 P2_8/ET_RXD0 NLP10000VIO0D5 P10_0/VIO_D5 NLP4080SD0CD P4_8/SD_CD NLP100110VIO0D7 P10_11/VIO_D7 NLP40110SD0D0 P4_11/SD_D0 NLP2030ET0CRS P2_3/ET_CRS NLP40140SD0D3 P4_14/SD_D3 NLP4040LCD0DATA12 P4_4/LCD_DATA12 NLP10050VIO0D1 P10_5/VIO_D1 NLP10040VIO0D0 P10_4/VIO_D0 NLP4070LCD0DATA15 P4_7/LCD_DATA15 NLP4000LCD0DATA8 P4_0/LCD_DATA8 3 101 J1B 109 PIJ10109 111 PIJ10111 113 PIJ10113 115 PIJ10115 117 PIJ10117 119 PIJ10119 121 PIJ10121 123 PIJ10123 125 PIJ10125 127 PIJ10127 129 PIJ10129 131 PIJ10131 133 PIJ10133 135 PIJ10135 137 PIJ10137 139 PIJ10139 141 PIJ10141 143 PIJ10143 145 PIJ10145 147 PIJ10147 149 PIJ10149 151 PIJ10151 153 PIJ10153 155 PIJ10155 157 PIJ10157 159 PIJ10159 161 PIJ10161 163 PIJ10163 165 PIJ10165 167 PIJ10167 169 PIJ10169 171 PIJ10171 173 PIJ10173 175 PIJ10175 177 PIJ10177 179 PIJ10179 181 PIJ10181 183 PIJ10183 185 PIJ10185 187 PIJ10187 189 PIJ10189 191 PIJ10191 193 PIJ10193 195 PIJ10195 197 PIJ10197 199 PIJ10199 107 PIJ10107 PIJ10105 105 103 PIJ10103 PIJ10101 Author: Jorge Amodio Date: 4/15/2015 Board to Board Interconnect GND 120 PIJ10120 122 PIJ10122 124 PIJ10124 126 PIJ10126 128 PIJ10128 130 PIJ10130 132 PIJ10132 134 PIJ10134 136 PIJ10136 138 PIJ10138 140 PIJ10140 142 PIJ10142 144 PIJ10144 146 PIJ10146 148 PIJ10148 150 PIJ10150 152 PIJ10152 154 PIJ10154 156 PIJ10156 158 PIJ10158 160 PIJ10160 162 PIJ10162 164 PIJ10164 166 PIJ10166 168 PIJ10168 170 PIJ10170 172 PIJ10172 174 PIJ10174 176 PIJ10176 178 PIJ10178 180 PIJ10180 182 PIJ10182 184 PIJ10184 186 PIJ10186 188 PIJ10188 190 PIJ10190 192 PIJ10192 194 PIJ10194 196 PIJ10196 198 PIJ10198 200 PIJ10200 118 PIJ10118 PIJ10116 PIJ10114 114 116 112 PIJ10112 PIJ10110 110 108 PIJ10108 PIJ10106 106 102 104 PIJ10104 PIJ10102 4 4 am.renesas.com/HiResGUI NLPWRDWN# PWRDWN# NL01V18 +1V18 NLP9030SPBSSL0 P9_3/SPBSSL0 NLP0030MD0CLKS P0_3/MD_CLKS NLP9040SPBIO00 P9_4/SPBIO00 NLP9020SPBCLK0 P9_2/SPBCLK0 NLP5090ET0MDC P5_9/ET_MDC NLP50100CAN1TX P5_10/CAN1TX NLP5070LCD0DATA23 P5_7/LCD_DATA23 NLP5060LCD0DATA22 P5_6/LCD_DATA22 NLP5020LCD0DATA18 P5_2/LCD_DATA18 NLP5030LCD0DATA19 P5_3/LCD_DATA19 NLP5040LCD0DATA20 P5_4/LCD_DATA20 NLP5050LCD0DATA21 P5_5/LCD_DATA21 NLP5010LCD0DATA17 P5_1/LCD_DATA17 NLP5000LCD0DATA16 P5_0/LCD_DATA16 NLP1060SCL3 P1_6/SCL3 NLP1040CAN1RX P1_4/CAN1RX NLP1070SDA3 P1_7/SDA3 NLP1010SDA0 P1_1/SDA0 NLP1000SCL0 P1_0/SCL0 NLP100140SSIRxD P10_14/SSIRxD NLP2090ET0RXD1 P2_9/ET_RXD1 NLP2070ET0TXD3 P2_7/ET_TXD3 NLP20100ET0RXD2 P2_10/ET_RXD2 NL0VEXT +VEXT NLP2020ET0TXEN P2_2/ET_TXEN NLP40150SD0D2 P4_15/SD_D2 NLP100120SSISCK P10_12/SSISCK NLP2050ET0TXD1 P2_5/ET_TXD1 NLP100150SSITxD P10_15/SSITxD Revision: v2.1 PCB02 Sheet 8 of 8 Renesas YLCDRZA1H MCU Module GND Board to Board connections via PCB Edge 200-pin matching DDR2 SODIMM Socket 2 D C B A YLCDRZA1H Technical Reference Manual 12.3 - RZ Module BOM ID Description Package C1 C2 C3-4,C6,C8-20,C23-26,C28C38,C40-47,C50-66 C48,C49 C5 C7,C21-22,C27,C39 L1 L2 LED1 R1 R10 R12,R13 R14 R21 R22 R2-4,R15-19 R5-8 R9,R11 RA10 RA1-9 U1 U2 U3 U4 U5,U8 U6 U7 U9,U10 X1 CL10A106KP8NNND [Samsung] Ceramic 10uF 10V 10% X5R CL05A475MQ5NQNC [Samsung] Ceramic 4u7 6V3 20% X5R 0603 0402 CL03A104KP3NNNC [Samsung] Ceramic100n0 10V X5R 10% 0201 CL05C120JB5NNNC [Samsung] Ceramic 12p0 50V C0G 5% CL10A226MQ8NRNC [Samsung] Ceramic 22uF 6.3V X5R 20% CL05A106MQ5NUNC [Samsung] CER 10uF 6.3V X5R 20% SRN3015-2R2M [Bourns] 2.2uH 1.8A 72mOhm Inductor SRN3015-1R0Y [Bourns] 1uH 2.35A Inductor 3x3x1.5mm 598-8610-207F [Dialight] LED Bi-Color Red/Green 60/40mcd ERA-2AED104X [Panasonic] 100K0 0.5% 1/16W 25ppm ERA-2AED243X [Panasonic ] 24k0 0.5% 1/16W 25ppm ERJ-2RKF4702X [Panasonic] 47k0 1% 1/10W 100ppm ERA-2AED223X [Panasonic ] 22k0 0.5% 1/16W 25ppm ERA-2AED471X [Panasonic ] 470R 0.5% 1/16W 25ppm ERA-2AED152X [Panasonic] 1K50 0.5% 1/16W 25ppm ERA-2AED472X [Panasonic ] 4k70 0.5% 1/16W 25ppm CRCW04020000Z0ED [Vishay] 0R00 1/16W ERA-2AED562X [Panasonic ] 5k60 0.5% 1/16W 25ppm EXB-28V220JX [Panasonic] IsolArr 22R0 4x 5% 200ppm 1/16W EXB-28V472JX [Panasonic] IsolArr 4k7 5% 200ppm 1/16W 4x0402 IDTP9122 [IDT] Switcher w/I2C Dual Factory Pgm 1.18[1],3.30[2] STM1818SWX7F [STM] Reset Monitor 2.88V SI5351C [SiLabs] I2C 8 Clock Gen (T/R) Factory Pre-Programmed 501AAA-12M0000-DAGR [SiLabs] 12MHz Oscillator 50ppm N25Q256A13EF840E [Micron] NOR Serial FLASH QSPI 256Mbit R7S721001VCBG#AC0 [Renesas] RZ A1H MCU 10MB BGA324 CAT34C02HU4IGT4A [OnSemi] EEPROM I2C 2KBit w/OTP MT48LC16M16A2B4-6A IT:G TR [Micron] 32MB SDRAM 133MHz ABS07-32.768KHZ-T [Abracon] 32.768 Tuning Fork Crystal 0402 0603 0402 SMD SMD 1210 0402 0402 0402 0402 0402 0402 0402 0402 0402 0804 0804 QFN24 SOT23 QFN20 2x2.5 V-PDFN-8/8x6mm PRBG0324GA-A UDFN8 VFBGA54 2-SMD Rev 2.20 Jul 21, 2015 Page 44 of 68 YLCDRZA1H Technical Reference Manual 12.4 - Baseboard Schematics Rev 2.20 Jul 21, 2015 Page 45 of 68 D C B A COJ2 J2 PIL401 1 10uF 10V COC16 C16 GND PIC1602 PIC1601 +5V GND PIJ20SL PIJ20SH PIJ20TIP 1 2.2uH COL4 L4 1 5 PIU305 PIU30PAD GND PAD GND ILIM FAULT ENUSB EN 4 IN USB PIU304 3 PIC1301 PIC1302 10 PIR601 1% PIR602 COR6 R6 GND 6 PIU306 7 8 PIU307 PIU308 9 PIU309 PIU3010 0.1uF COC18 C18 GND PIC1801 PIC1802 COC14 C14 0.01uF COC17 C17 22uF 6.3V GND PIC1701 PIC1702 COU2 U2 TPS54232 1 8 BOOT PH PIU208 2 7 PIU202 VIN GND PIU207 3 6 PIU203 EN COMP PIU206 4 5 PIU204 SS VSENSE PIU205 PIU201 GND PIC1402 PIC1401 PIC301 PIC302 180K0 50V 0.1uF COC13 C13 GND AUX 10uF 50V COC12 C12 PIU303 PGND SW PIC1202 PIC1201 GND TPS2501 COU3 U3 2 PIU302 GND PIL402 10uF 50V COC11 C11 GND PIC1 02 PIC1 01 PIU301 10uF 50V COC10 C10 GND PIC10 2 PIC10 1 NL0VIN +VIN COC3 C3 0.1uF 2 2 PIR401 PIR402 4 PIC1501 PIC1502 COC15 C15 18pF PIL102 Y GND 2 PIU402 PIU405 COR3 R3 1K87 GND PIR301 1% PIR302 COR1 R1 10K0 PIR101 0.5% PIR102 5 3 VCC I0PIU403 1 I1PIU401 6 GND SPIU406 GND PIU404 COR4 R4 10K0 +3V3 GND PIR201 37K4 COC8 C8 270pF COR2 R2 PIC802 PIC801 PIR202 B240A COD5 D5 10uH COU4 U4 74LVC1G157GV GND PID50A PID50K PIL101 COL1 L1 PIR501 PIR502 COR5 R5 10K0 COC5 C5 4.7uF 6.3V NLRZM0USBH0OC# RZM-USBH_OC# NLUSBH05V USBH_5V NLUSBH0AUX05V USBH_AUX_5V GND PIC501 PIC502 NLRZM0USBH05V0EN RZM-USBH_5V_EN COC4 C4 22uF 6.3V GND PIC401 PIC402 +5V GND PIC601 PIC602 COC6 C6 10uF 10V 3 3 PIRA101 3 14 15 PIU1015 16 PIU1016 17 PIU1017 PIU1014 PIU103 5 PIU105 4 PIU104 PIU101 1 2 PIU102 9 PIU109 PIU10 PIU10PAD Author: Jorge Amodio Date: 7/15/2015 System and USB Host Power Supplies GND 19 PIU1019 18 PIU1018 PIU1020 8 PIU108 Renesas YLCDRZA1H Baseboard Program for Mode 0 Vout1 = 1.8000V Vout2 = 3.3000V PORB = PG1 & PG2 11 7 6 PIU106 PIU107 20 LX2 21 LX2 PIU1021 PGND1 FB1 LX1 DEVSLPIN GPI3 GPIO14 FB2 GPIO15 GPO16 GPIO17 PGND2 GND PAD VGND VINSEL VREF VIN PVIN1 22 PIU1022 PVIN2 23 PIU1023 PVIN2 24 COU1 U1 P9122 PIU1024 GND NLPORB PORB 100K0 CORA1A RA1A PIRA108 8 1 PIL302 PIL202 Revision: v2.1 PCB03 Sheet 1 of 12 1uH PIL301 COL3 L3 2.2uH PIL201 COL2 L2 COC7 C7 22uF 6.3V COC1 C1 4.7uF 6.3V NL03V3 +3V3 4 PIC202 PIC201 COC2 C2 0.1uF COC9 C9 0.1uF GND PIC902 PIC901 GND www.seriousintegrated.com GND PIC702 PIC701 GND PIC102 PIC101 NL01V8 +1V8 4 +3V3 +1V8 D C B A D C B 1 NLRZM0BLEN RZM-BLEN +5V NLLCD0VGL LCD_VGL +3V3 -8V GND PIC3702 PIC3701 COC37 C37 10uF 10V COC24 C24 22uF GND PIC2401 PIC2402 GND PIRA102 100K0 22uH PIU604 4 COL6 L6 CAT4139 COU6 U6 PIL601 GND PID40 PID403 1 SWPIU601 PIL602 PIC2701 PIC2702 GND 2 PIU602 3 SH GND FBPIU603 PIU605 VIN 5 D4B RB481K CORA1B RA1B PIRA107 COC26 C26 220nF GND PIC2601 PIC2602 COC39 C39 0.1uF GND PIC3902 PIC3901 COC25 C25 0.33uF GND PIC2501 PIC2502 PIR1201 75K0 1% PIR1202 COR12 R12 PIR10 1 499K 1% PIR10 2 COR10 R10 1 PID401 RB481K 2 PID402 COD4A COD4B D4A 2 PIR1602 COR16 R16 GND 1K10 1% PIR1601 COC27 C27 0.1uF PIR702 PIC2201 COC28 C28 470pF COD6 D6 GND PIR1701 3R0 1% PIR1702 R17 COR17 DFLS130L PID60A PID60K GND 5 COC29 C29 22pF GND PIC2901 PIC2902 17 3.9uH COL5 L5 3 COC38 C38 1uF 50V GND PIC3802 PIC3801 2 COD1A COD1B D1A 1 4 0.33uF NLBL0LED0 BL_LED- NLBL0LED0 BL_LED+ COC31 C31 0.01uF 2 PIU502 13 PIU5013 18 PIU5018 19 PIU5019 15 PIU5015 PIC3202 PIC3201 COC32 C32 1uF GND PIC2301 COC23 C23 PIU5020 PIC2302 20 PIU504 12 PIU5012 RB481K PID102 PID101 GND PIC3102 PIC3101 GD VCOM VGH CPI FBP DRVP FB SUP COC30 C30 0.01uF GND PIC30 1 PIC30 2 6 9 PIU508 PIU509 SW SW 8 PIL502 PIR802 PIU50PAD PIU5017 PIU50 PIU506 PIU503 PAD COMP PIU501 1 CTRL PGND PGND PIU5016 16 11 PIU5011 10 PIU5010 22 PIU5022 GND REF 23 PIU5023 DRVN FBN 24 7 IN VIN COR8 R8 499K PIR801 PIL501 PIU5014 PIU507 14 PIU5024 COR14 R14 33K0 GND PIC2801 PIC2802 PIR1401 PIR1402 0.33uF 21 PIU5021 TPS65150 COU5 U5 0.001uF PIC1902 COC19 C19 PIC1901 COC22 C22 PIC2202 COR7 R7 255K0 ADJ PIR701 DLY1 A 3 4 2 DLY2 1 7 2 FDLY PID104 PID103 3 4 PIC3 02 PIC3 01 PIC20 2 PIC20 1 COC33 C33 1uF COC20 C20 33pF 3 GND D1B RB481K 3 D2B 4 2 COD3A D3A COC21 C21 0.33uF PIC3401 PIC3402 COC34 C34 0.33uF RB481K 1 Author: Jorge Amodio Date: 7/15/2015 PIC3501 PIC3502 1M00 56K2 PIR1301 1% PIR1302 R13 COR13 PIR1 01 1% PIR1 02 R11 COR11 Revision: v2.1 PCB03 Sheet 2 of 12 GND COC35 C35 0.33uF GND RB481K Renesas YLCDRZA1H Baseboard LCD Power 3 GND RB481K COR15 R15 66K5 1% GND PIR1502 PIR1501 1 PIC2102 PIC2101 PID201 P PID203 ID203 PID204 PID302 PID301 COD2B COD2A D2A PID202 2 499K PIR901 1% PIR902 COR9 R9 COC36 C36 22uF NLLCD0VCOM LCD_VCOM NLLCD0VGH LCD_VGH NLLCD0AVDD LCD_AVDD 4 www.seriousintegrated.com GND PIC3601 PIC3602 3.3V 22.7V 9.74V 4 D C B A D C B 1 NLRZM0TOUCH0RST RZM-TOUCH_RST NLRZM0SCL1 RZM-SCL1 NLRZM0SDA1 RZM-SDA1 NLRZM0TOUCH0IRQ RZM-TOUCH_IRQ +3V3 4K70 CORA18A CORA18B RA18A 3PIRA803 RA8C NLRZM0LCD0VSYNC RZM-LCD_VSYNC NLRZM0LCD0DEN RZM-LCD_DEN NLRZM0LCD0DATA22 RZM-LCD_DATA22 NLRZM0LCD0HSYNC RZM-LCD_HSYNC NLRZM0LCD0CLK RZM-LCD_CLK NLRZM0LCD0DATA18 RZM-LCD_DATA18 NLRZM0LCD0DATA19 RZM-LCD_DATA19 NLRZM0LCD0DATA20 RZM-LCD_DATA20 NLRZM0LCD0DATA23 RZM-LCD_DATA23 NLRZM0LCD0DATA21 RZM-LCD_DATA21 NLRZM0LCD0DATA8 RZM-LCD_DATA8 NLRZM0LCD0DATA9 RZM-LCD_DATA9 NLRZM0LCD0DATA10 RZM-LCD_DATA10 NLRZM0LCD0DATA14 RZM-LCD_DATA14 NLRZM0LCD0DATA15 RZM-LCD_DATA15 NLRZM0LCD0DATA11 RZM-LCD_DATA11 NLRZM0LCD0DATA12 RZM-LCD_DATA12 NLRZM0LCD0DATA13 RZM-LCD_DATA13 NLRZM0LCD0DATA0 RZM-LCD_DATA0 NLRZM0LCD0DATA6 RZM-LCD_DATA6 NLRZM0LCD0DATA7 RZM-LCD_DATA7 NLRZM0LCD0DATA1 RZM-LCD_DATA1 NLRZM0LCD0DATA2 RZM-LCD_DATA2 NLRZM0LCD0DATA3 RZM-LCD_DATA3 NLRZM0LCD0DATA4 RZM-LCD_DATA4 NLRZM0LCD0DATA5 RZM-LCD_DATA5 1PIRA201 CORA2A CORA2B CORA2C CORA2D RA2A 3PIRA203 RA2C 1PIRA301 CORA3A CORA3B CORA3C CORA3D RA3A 3PIRA303 RA3C 1PIRA401 CORA4A CORA4B CORA4C CORA4D RA4A 3PIRA403 RA4C 1PIRA501 CORA5A CORA5B CORA5C CORA5D RA5A 3PIRA503 RA5C 1PIRA601 CORA6A CORA6B CORA6C CORA6D RA6A 3PIRA603 RA6C 1PIRA701 CORA7A CORA7B CORA7C CORA7D RA7A 3PIRA703 RA7C 4PIRA704 RA7D 4PIRA804 RA8D NLRZM0LCD0DATA16 RZM-LCD_DATA16 NLRZM0LCD0DATA17 RZM-LCD_DATA17 PIRA1802 PIRA1807 PIRA1801 PIRA180 2 PIRA802 RA8B 1 PIRA801 CORA8A CORA8B CORA8C CORA8D RA8A 2 RA2B 4 PIRA204 RA2D 2 PIRA302 RA3B 4 PIRA304 RA3D 2 PIRA402 RA4B 4 PIRA404 RA4D 2 PIRA502 RA5B 4 PIRA504 RA5D 2 PIRA602 RA6B 4 PIRA604 RA6D 2 PIRA702 RA7B PIRA202 RA18B 4K70 6 33R PIRA806 33R PIRA2066 33R 8 PIRA308 33R 6 PIRA306 33R 8 PIRA408 33R 6 PIRA406 33R PIRA5088 33R PIRA5066 33R 8 PIRA608 33R 6 PIRA606 33R 8 PIRA708 33R 6 PIRA706 33R 5 PIRA705 33R 5 PIRA805 33R PIRA2088 8 A 1 1 2 7 8 33R 7 PIRA807 33R PIRA808 7 33R 5 PIRA205 33R PIRA3077 33R PIRA3055 33R PIRA4077 33R 5 PIRA405 33R 7 PIRA507 33R 5 PIRA505 33R 7 PIRA607 33R 5 PIRA605 33R PIRA7077 33R PIRA207 0.1uF COC40 C40 GND PIC40 2 PIC40 1 +3V3 0.1uF COC41 C41 CLK HSYNC VSYNC DEN R6 R0 R1 R2 R3 R4 R7 R5 G0 G1 G2 G6 G7 G3 G4 G5 B0 B6 B7 B1 B2 B3 B4 B5 GND PIC4102 PIC4101 2 GND 0.1uF COC42 C42 GND PIC4202 PIC4201 2 PIC4 02 PIC4 01 0.1uF COC44 C44 GND 31 PIU7031 PIU7052 TxCLK IN TxIN0 52 TxIN1 54 PIU7054 TxIN2 55 PIU7055 TxIN3 56 PIU7056 TxIN4 2 PIU702 TxIN5 3 PIU703 TxIN6 4 PIU704 TxIN7 6 PIU706 TxIN8 7 PIU707 TxIN9 8 PIU708 TxIN10 10 PIU7010 TxIN11 11 PIU7011 TxIN12 12 PIU7012 TxIN13 14 PIU7014 TxIN14 15 PIU7015 TxIN15 16 PIU7016 TxIN16 18 PIU7018 TxIN17 19 PIU7019 TxIN18 20 PIU7020 TxIN19 22 PIU7022 TxIN20 23 PIU7023 TxIN21 24 PIU7024 TxIN22 25 PIU7025 TxIN23 27 PIU7027 TxIN24 28 PIU7028 TxIN25 30 PIU7030 TxIN26 50 PIU7050 TxIN27 51 PIU7051 DS90C383B COU7 U7 COC43 C43 0.1uF GND PIC4302 PIC4301 PLL GND PLL GND GND GND GND GND GND LVDS GND TxOUT 0TxOUT 0+ TxOUT 1TxOUT 1+ LVDS GND TxOUT 2TxOUT 2+ TxCLKOUTTxCLKOUT+ TxOUT 3TxOUT3+ LVDS GND VCC VCC VCC VCC LVDS Vcc PLL Vcc PWRDWN 0.1uF COC45 C45 GND PIC4502 PIC4501 9 PIU7033 33 53 PIU7053 29 PIU7029 21 PIU7021 13 PIU7013 5 PIU705 35 PIU7035 PIU7046 PIU7047 47 46 45 PIU7045 43 PIU7043 42 PIU7042 41 PIU7041 40 PIU7040 39 PIU7039 38 PIU7038 37 PIU7037 36 PIU7036 48 PIU7048 PIU7049 49 PIU7032 32 34 PIU7034 PIU7044 PIU7026 26 44 17 PIU7017 PIU709 1 PIU701 GND PIR1801 COR18 R18 10K0 PIR1802 3 NLLVDS0CLK0N LVDS_CLK_N NLLVDS0CLK0P LVDS_CLK_P NLLVDS0TX30N LVDS_TX3_N NLLVDS0TX30P LVDS_TX3_P NLLVDS0TX20N LVDS_TX2_N NLLVDS0TX20P LVDS_TX2_P NLLVDS0TX00N LVDS_TX0_N NLLVDS0TX00P LVDS_TX0_P NLLVDS0TX10N LVDS_TX1_N NLLVDS0TX10P LVDS_TX1_P 3 LCD Interface Author: Jorge Amodio Date: 7/15/2015 Renesas YLCDRZA1H Baseboard NLLCD0VGH LCD_VGH NLBL0LED0 BL_LED+ NLLCD0VGL LCD_VGL NLBL0LED0 BL_LED- NLLCD0AVDD LCD_AVDD NLLCD0VCOM LCD_VCOM COC48 C48 0.1uF GND Revision: v2.1 PCB03 Sheet 3 of 12 GND PIC4801 PIC4802 PIC4702 PIC4701 COC47 C47 1uF COJ4 J4 4 www.seriousintegrated.com I2CADDR: 0x5C PIJ402 GND 2 3 PIJ403 RST 4 PIJ404 SCL 5 PIJ405 SDA 6 PIJ406 INT 7 PIJ407 NC 8 PIJ408 NC 1 VDD PIJ401 GND COJ3 J3 1 PIJ301VCOM 2 VDD PIJ302 3 VDD PIJ303 4 PIJ304NC 5 NC PIJ305 6 PIJ306NC 7 GND PIJ307 8 PIJ308RxIN09 PIJ309 RxIN0+ 10 GND PIJ3010 11 PIJ3011RxIN112 PIJ3012RxIN1+ 13 PIJ3013GND 14 RxIN2PIJ3014 15 PIJ3015RxIN2+ 16 GND PIJ3016 17 RxCLKPIJ3017 18 PIJ3018RxCLK+ 19 GND PIJ3019 20 PIJ3020RxIN321 RxIN3+ PIJ3021 22 PIJ3022GND 23 PIJ3023NC 24 NC PIJ3024 25 PIJ3025GND 26 PIJ3026NC 27 PIJ3027NC 28 NC PIJ3028 29 PIJ3029AVDD 30 GND PIJ3030 31 PIJ3031LED32 PIJ3032LED33 PIJ3033NC 34 PIJ3034NC 35 PIJ3035VGL 36 PIJ3036NC 37 PIJ3037NC 38 PIJ3038VGH 39 PIJ3039LED+ 40 PIJ3040LED+ COC46 C46 0.1uF GND PIC4602 PIC4601 4 D C B A D C B A NLRZM0SCL0 RZM-SCL0 NLRZM0SDA0 RZM-SDA0 NLRZM0SD0WP RZM-SD_WP NLRZM0SD0CD RZM-SD_CD NLRZM0SD0D0 RZM-SD_D0 NLRZM0SD0D1 RZM-SD_D1 NLRZM0SD0D2 RZM-SD_D2 1 NLRZM0SD0CLK RZM-SD_CLK NLRZM0SD0CMD RZM-SD_CMD NLRZM0SD0D3 RZM-SD_D3 NLRZM0MMC0CLK RZM-MMC_CLK NLRZM0MMC0D0 RZM-MMC_D0 NLRZM0MMC0D1 RZM-MMC_D1 NLRZM0MMC0D2 RZM-MMC_D2 NLRZM0MMC0D3 RZM-MMC_D3 NLRZM0MMC0D4 RZM-MMC_D4 NLRZM0MMC0D5 RZM-MMC_D5 NLRZM0MMC0D6 RZM-MMC_D6 NLRZM0MMC0D7 RZM-MMC_D7 NLRZM0MMC0CMD RZM-MMC_CMD NL03V3 +3V3 NLRZM0RESET# RZM-RESET# +3V3 0.1uF COC59 C59 GND PIC5902 PIC5901 4.7uF COC60 C60 GND I2CADDR: 0xD0 (Check!) COU9 U9 PCF8523 8 1 VDD OSCI PIU901 7 2 PIU907 CLKO OSCO PIU902 6 3 PIU906 SCL VBAT PIU903 5 4 PIU905 SDA VSS PIU904 PIU908 1% 2K20 COR21 R21 GND PIC60 2 PIC60 1 PIR2101 PIR2102 PIR2002 22R0 COR20 R20 PIR2001 CORA9CBA CORA10DCBA PIRA10 3 PIRA10 6 PIRA10 4 PIRA10 5 PIRA908 PIRA10 7 PIRA10 8 PIRA901 PIRA10 2 PIRA10 1 PIRA906 PIRA907 PIRA903 PIRA902 2 4 RA10D 3 RA10C 1 RA9A 2 RA10B 1 RA10A 3 RA9C 2 RA9B GND PIBAT10NEG PIBAT10POS COBAT1 BAT1 PIX101 PIX102 2 1uF COC57 C57 GND PIC5702 PIC5701 COC61 C61 0.1uF GND PIC6102 PIC6101 7 PIRA1307 22R0 6 PIRA1306 22R0 COX1 X1 32.768KHz 2 PIRA1302 CORA13B CORA13C RA13B 3 PIRA1303 RA13C 5 22K0 6 22K0 8 22K0 7 22K0 8 22K0 6 22K0 7 22K0 0.1uF COC58 C58 GND GND GND PIU10 PAD PAD COU10 U10 ATSHA204A 8 VCC 5 PIU1005 SDA 6 PIU1006 SCL 4 PIU1004 VSS PIU1008 GND PIC5802 PIC5801 PISD10C PISD10C2 PIRA1 05 CORA12DCBA PIRA1 04 PIRA1201 PIRA1208 I2CADDR: 0xC8 (Check!) CD PISD10CD CDet WP PISD10WP WPS COSD1 SD1 1 PISD101 CS/D3 2 PISD102 Din/CMD 3 PISD103 Vss 4 PISD104 Vdd 5 PISD105 CLK 6 PISD106 Vss 7 PISD107 Dout/D0 8 PISD108 D1 9 PISD109 D2 PIR1901 10K0 COR19 R19 PIR1902 PIRA1207 PIRA1 07 PIRA1 06 CORA1 DCBA 3 PIRA1202 PIRA1 02 PIRA1 03 PIRA1 01 PIRA1 08 PIRA1206 PIRA1205 3 PIC5301 PIC5302 COC53 C53 0.1uF PIRA1204 GND PIRA1203 5 RA11D 8 RA12A 7 RA12B 7 RA11B 6 RA11C 8 RA11A 6 RA12C 5 RA12D 4 47K0 1 47K0 2 47K0 2 47K0 3 47K0 1 47K0 3 47K0 4 47K0 1 A3 VDDI CLK DAT0 DAT1 DAT2 DAT3 DAT4 DAT5 DAT6 DAT7 Author: Jorge Amodio Date: 7/15/2015 VCC VCC VCC VCC VCCQ VCCQ VCCQ VCCQ VCCQ E6 F5 J10 PIU80J10 PIU80F5 PIU80P5 P5 P3 PIU80P3 PIU80N4 N4 C6 M4 PIU80M4 PIU80C6 PIU80K9 K9 PIC4902 PIC4901 PIC50 2 PIC50 1 0.1uF COC55 C55 2.2uF 4 COC51 C51 0.1uF GND PIC5102 PIC5101 COC56 C56 2.2uF GND PIC5601 PIC5602 www.seriousintegrated.com GND PIC5 01 4 COC50 C50 GND PIC5 02 COC49 C49 0.1uF GND PIU80E6 Revision: v2.1 PCB03 Sheet 4 of 12 GND PIU80E7 PIU80G5 PIU80H10 PIU80K PIU80C4 PIU80N2 PIU80N5 PIU80P4 PIU80P6 MMC, SD Card, RTCC, Crypto COC54 C54 1uF C2 PIU80C2 M6 PIU80M6 PIU80A5 A5 B2 PIU80B2 B3 PIU80B3 B4 PIU80B4 B5 PIU80B5 B6 PIU80B6 A4 PIU80A4 PIU80A3 RST CMD Renesas YLCDRZA1H Baseboard GND PIC5401 PIC5402 K5 M5 PIU80M5 PIU80K5 COU8 U8 MTFC4GMDEA VSS VSS VSS VSS E7 G5 H10 K8 VSSQ VSSQ VSSQ VSSQ VSSQ C4 N2 N5 P4 P6 COC52 C52 0.1uF GND PIC5202 PIC5201 D C B A D C B A NLRZM0SDA0 RZM-SDA0 NLRZM0SCL0 RZM-SCL0 1 NLRZM0ET0TXEN RZM-ET_TXEN NLRZM0ET0TXD0 RZM-ET_TXD0 NLRZM0ET0TXD1 RZM-ET_TXD1 NLRZM0ET0TXD2 RZM-ET_TXD2 NLRZM0ET0TXD3 RZM-ET_TXD3 NLRZM0ET0TXCLK RZM-ET_TXCLK NLRZM0ET0RXD0 RZM-ET_RXD0 NLRZM0ET0RXD1 RZM-ET_RXD1 NLRZM0ET0RXD2 RZM-ET_RXD2 NLRZM0ET0RXD3 RZM-ET_RXD3 NLRZM0ET0RXER RZM-ET_RXER PIC70 1 PIC70 2 0.1uF COC70 C70 PIC7101 PIC7102 GND GND COC71 C71 0.1uF 1 GND OE 3 CLK PIU1203 4 VDD PIU1204 GND 4 33R PIRA16022 33R PIRA16044 33R PIRA1504 MAC Address I2CADDR: 0x10 (Check!) COU13 U13 24AA02E48 4 PIU1304 VCC 3 PIU1303 SDA 1 PIU1301 SCL 2 PIU1302 VSS 25.000MHz PIU1202 2 PIU1201 COU12 U12 Si501 1 PIRA1601 5PIRA1505 RA15D 33R 7PIRA1607 3 RA16B PIRA1603 5PIRA1605 33R 2 RA16D PIRA1502 33R 1 PIRA1501 33R 33R 3 PIRA1503 15 14 13 PIU11013 20 PIU11020 22 23 24 PIU11024 25 PIU11025 26 PIU11026 27 PIU11027 GND 2 6K49 1% 10 PIU11010 8 PIU1108 PIU1109 9 PIU11023 PIU11022 PIU11014 PIU11015 PIR2402 R24 COR24 PIR2401 18 16 PIU11016 PIU11018 19 PIU11019 REXT XI XO TXC TXEN TXD0 TXD1 TXD2 TXD3 RXC RXDV RXD0 RXD1 RXD2 RXD3 RXER GND 1 PIU1 0 GND 6 PIRA1506 RA15C 8 PIRA1608 CORA16A CORA16B CORA16C CORA16D RA16A 6 PIRA1606 RA16C 7 PIRA1507 RA15B 8 PIRA1508 CORA15A CORA15B CORA15C CORA15D RA15A 33R PIRA17044 NLRZM0ET0RXCLK RZM-ET_RXCLK NLRZM0ET0RXDV RZM-ET_RXDV 5PIRA1705 RA17D 29 PIU11029 CRS/CONFIG1 28 PIU11028 COL/CONFIG0 6 PIRA1706 CORA17C CORA17D RA17C RST# MDC MDIO NLRZM0ET0CRS RZM-ET_CRS NLRZM0ET0COL RZM-ET_COL 3 PIRA1703 33R 12 11 PIU11011 32 PIU11032 COU11 U11 KSZ8081MNZ PIU11012 4K70 CORA14B RA14B PIRA1402 PIRA1407 2 NLRZM0ET0MDIO RZM-ET_MDIO NLRZM0RESET# RZM-RESET# NLRZM0ET0MDC RZM-ET_MDC NLRZM0ET0IRQ RZM-ET_IRQ +3V3 7 2 1 GND PIU10PAD PAD VDDIO RXM RXP TXM TXP LED1 LED0 INTRP VDD_1.2 VDDA_3.3 PIC6401 PIC6402 COC64 C64 0.1uF PIC6502 PIC6501 COC65 C65 22uF PIC6 01 PIC6 02 COC66 C66 0.1uF PIC6702 PIC6701 COC67 C67 47uF PIC6801 PIC6802 COC68 C68 0.1uF PIC6901 PIC6902 COC69 C69 0.1uF GND PIC6202 PIC6201 4 PIU1104 PIU1105 GND GND GND 3 GND Author: Jorge Amodio Date: 7/15/2015 Ethernet GND GND Renesas YLCDRZA1H Baseboard GND 4 4 www.seriousintegrated.com GND PIJ50C1 PIJ50C2 COJ5 J5 1 TCT 2 TD+ 3 PIJ503 TD4 PIJ504 RD+ 5 PIJ505 RD6 PIJ506 RCT 7 PIJ507 LED18 PIJ508 LED1+ 9 PIJ509 LED2+10 PIJ5010 LED2-+ COR23 R23 220R Revision: v2.1 PCB03 Sheet 5 of 12 PIR2301 5 COC63 C63 0.1uF COR22 R22 220R PIJ502 PIC6301 PIC6302 PIR2 01 PIR2302 PIJ501 COC62 C62 2.2uF COFB1 FB1 120 PIR2 02 PIU1106 6 7 PIU1107 31 PIU11031 30 PIU11030 21 PIU11021 2 PIU1102 3 PIU1103 17 PIU11017 PIFB102 PIFB101 3 C1 C2 D C B A D C B A 1 1 NLRZM0USBF0VBUS RZM-USBF_VBUS NLRZM0USBF0N RZM-USBF_N NLRZM0USBF0P RZM-USBF_P NLUSBH05V USBH_5V NLRZM0USBH0N RZM-USBH_N NLRZM0USBH0P RZM-USBH_P NLRZM0USBH0VBUS RZM-USBH_VBUS 2 PIR2601 PIC7502 PIC7501 PIR2602 600 COFB2 FB2 PIFB202 GND COC76 C76 0.1uF GND PIC7601 PIC7602 COJ7 J7 GND PIJ70C1 PIJ70C2 COJ8 J8 1 PIJ801 PIJ702 5VUSB 2 D3 PIJ703 D+ 4 PIJ704 GND 1 PIJ701 PIJ802 GND PIJ80C1 PIJ80C2 PIJ80C3 PIJ80C4 5VUSB 2 D3 PIJ803 D+ 4 PIJ804 USBID 5 DNP PIJ805 GND GND COU15 U15 TPD2E2U06 1 5 PIU1501 NC IO2PIU1505 2 PIU1502 NC 3 4 PIU1503 PIU1504 IO1 GND PIFB201 COU16 U16 TPD2E2U06 1 5 IO2PIU1605 2 PIU1602NC 3 4 PIU1603IO1 GND PIU1604 PIU1601NC COC75 C75 0.1uF GND 100R COR26 R26 150uF 16V COC74 C74 PIR2502 100R COR25 R25 PIR2501 GND PIC7401 PIC7402 2 3 3 Author: Jorge Amodio Date: 7/15/2015 USB Host & Device Renesas YLCDRZA1H Baseboard Revision: v2.1 PCB03 Sheet 6 of 12 4 www.seriousintegrated.com 4 D C B A 1 2 I2CADDR: 0x42 GND 1 3 PIJ603 5 PIJ605 7 PIJ607 9 PIJ609 11 PIJ6011 13 PIJ6013 15 PIJ6015 17 PIJ6017 PIJ601 NLRZM0VIO0D4 RZM-VIO_D4 NLRZM0VIO0D2 RZM-VIO_D2 NLRZM0VIO0D0 RZM-VIO_D0 NLRZM0VIO0D6 RZM-VIO_D6 NLRZM0SDA0 RZM-SDA0 NLRZM0VIO0HSYNC RZM-VIO_HSYNC GND 0.1uF COC72 C72 3 Camera Interface Renesas YLCDRZA1H Baseboard Revision: v2.1 PCB03 Sheet 7 of 12 www.seriousintegrated.com B A Author: Jorge Amodio Date: 7/15/2015 4 D COC73 C73 1uF PIJ602 NLCAM0XCLK PIC7202 PIC7201 4 D GND PIC7301 PIC7302 COJ6 J6 2 4 PIJ604 6 PIJ606 8 PIJ608 10 PIJ6010 12 PIJ6012 14 PIJ6014 16 PIJ6016 18 PIJ6018 GND 3 CLK PIU1403 4 VDD PIU1404 24.000MHz GND 2 OE COU14 U14 Si501 PIU1402 1 PIU1401 3 C NLRZM0SCL0 RZM-SCL0 NLRZM0VIO0VSYNC RZM-VIO_VSYNC NLRZM0VIO0CLK RZM-VIO_CLK NLRZM0VIO0D7 RZM-VIO_D7 NLRZM0VIO0D5 RZM-VIO_D5 NLRZM0VIO0D3 RZM-VIO_D3 NLRZM0VIO0D1 RZM-VIO_D1 NLRZM0RESET# RZM-RESET# +3V3 2 C B A 1 CAM_XCLK D C B 1 PIRA1904 PIRA1902 PIRA1903 PIRA1906 PIRA1901 CORA19DCBA PIRA1908 NLRS0SLEW RS_SLEW NLRS0SPB RS_SPB NLRZM0CANRX RZM-CANRX NLRZM0CANTX RZM-CANTX NLRZM0RS0ON RZM-RS_ON NLRZM0RS0DEN RZM-RS_DEN GND 1PIS1012PIS102 3PIS103 4PIS104 PIS108 PIS107 PIS106 PIS105 8 7 6 5 NLRS4850232# RS485/232# 2 PIC8101 PIC8102 COC81 C81 0.1uF PIC8201 PIC8202 0.1uF COC82 C82 GND GND PIC8302 PIC8301 COC83 C83 GND 0.1uF 11 485/232 PIU17011 PIU170PAD PIU1706 PIU1705 GND 4 Y1PIU1704 5 Z1PIU1705 GND PIC80 2 PIC80 1 PIC7901 PIC7902 GND COU18 U18 IFX1050 1 8 TXD INH PIU1808 2 7 PIU1802 GND CANH PIU1807 3 6 PIU1803 VCC CANL PIU1806 4 5 PIU1804 RXD V33V PIU1805 ON PIU1801 21 PIU17021 PIU17027 27 SLEW 14 PIU17014 SPB DY 2 A1PIU1702 3 B1PIU1703 36 C2+PIU17036 35 C2-PIU17035 37 C1+PIU17037 38 C1-PIU17038 COU17 U17 ISL41387 12 DENPIU17012 VL VCC 28 PIU17028 V- V+ NLRZM0UART0TX RZM-UART_TX 19 PIU17019 1 PIU1701 PIU17031 PIU17034 30 PIU17030 RA 29 PIU17029 RB 20 PIU17020 RXEN 17 PIU17017 RXEN COS1 S1 PIRA1905 PIRA1907 2 31 NLRZM0UART0RX RZM-UART_RX +3V3 +5V 7 RA19B 5 RA19D 6 RA19C 8 RA19A 2 100K0 4 100K0 3 100K0 1 100K0 A 1 34 PAD 16 GND 15 GND COC80 C80 0.1uF COC79 C79 0.1uF 0.1uF COC84 C84 GND PIC8401 PIC8402 PIC7 01 PIC7 02 COC77 C77 0.1uF 3 GND 3 0.1uF COC78 C78 GND Author: Jorge Amodio Date: 7/15/2015 Revision: v2.1 PCB03 Sheet 8 of 12 Industrial Networking RS485/232 & CAN NLA A NLB B NLY Y NLZ Z NLCANH CANH NLCANL CANL COJ9 J9 1 2 PIJ902 3 PIJ903 4 PIJ904 5 PIJ905 6 PIJ906 7 PIJ907 8 PIJ908 PIJ901 Renesas YLCDRZA1H Baseboard GND PIC7801 PIC7802 4 www.seriousintegrated.com 4 D C B A D C B Line In 30 COFB4 FB4 COC88 C88 10uF COC90 C90 0.1uF 10pF COC100 C100 COC93 C93 1uF GND PIC9302 PIC9301 1uF COC94 C94 1uF COC95 C95 GND PIC9402 PIC9401 PIC10 2 PIC10 1 PIR2701 10pF 10K0 COR27 R27 PIR2702 5 PIU1905 56 PIU19056 IRQ MCLK MAX98089 COU19 U19 COJ13 J13 1 NLRZM0SCL0 RZM-SCL0 2 4 PIJ1304 3 PIJ1303 1 PIJ1301 PIJ1302 GND NLAIN2 AIN2 PIC9601 1uF COC97 C97 GND PIC9701 PIC9702 PIC9602 GND PIR2802 22K0 PIR2801 COR28 R28 PIC9501 PIC9502 2 42 43 37 36 PIU19036 PIU19037 PIU19038 PIU19039 39 38 PIU19043 PIU19042 44 PIU19044 COC101 C101 GND 40 41 PIU19041 PIU19040 PIU1906 PIU19025 PIU19053 PIU1905 PIU190 PIU1908 PIU1905 INB1 INB2 INA1/EXTMICP INA2/EXTMICN MIC2P MIC2N MICBIAS MIC1P/DIGMICDATA MIC1N/DIGMICCLK 52 PIU19052 SDA 51 PIU19051 SCL COC99 C99 10pF 1uF COC92 C92 NLRZM0SDA0 RZM-SDA0 PIC9 02 PIC9 01 PIC9202 PIC9201 GND PIC10 02 PIC10 01 COC91 C91 10uF GND PIC9101 PIC9102 8 PIU1908 BCLKS1 10 PIU19010 LRCLKS1 9 PIU1909 SDINS1 7 PIU1907 SDOUTS1 NLAIN1 AIN1 PIC90 2 PIC90 1 GND COC96 C96 1uF COC89 C89 0.1uF GND PIC8902 PIC8901 PIFB302 NLRZM0SSISCK RZM-SSISCK NLRZM0SSIWS RZM-SSIWS NLRZM0SSITxD RZM-SSITxD NLRZM0SSIRxD RZM-SSIRxD PIC8 01 PIC8 02 GND PIFB402 NLRZM0AUDIO0IRQ RZM-AUDIO_IRQ NLRZM0AUDIO0CLK RZM-AUDIO_CLK PIFB401 +1V8 600 COFB3 FB3 GND 1uF PIC102 PIC102 1 GND COC102 C102 COC85 C85 10uF GND PIC8502 PIC8501 45 PIU19045 2 4 PIU1904 54 PIU19054 1 PIU1901 PIU1902 1uF COC103 C103 GND PIC103 2 PIC103 1 COC98 C98 1uF REF REG HPR HPL HPSNS SPKRP SPKRN SPKLP SPKLN 15 48 49 PIC10402 PIC10401 1uF COC104 C104 GND PIU19049 PIU19048 35 33 PIU19033 34 PIU19034 PIU19035 PIU19015 17 PIU19017 20 22 PIU19022 PIU19020 24 RECP/LOUTL/RXINP PIU19024 23 RECN/LOUTR/RXINN PIU19023 JACKSNS PIC9801 PIC9802 PIC8702 PIC8701 3 2.2uF GND COC87 C87 1uF GND 3 COC105 C105 GND PIC105 1 PIC105 2 1uF COC86 C86 GND PIC8602 PIC8601 I2CADDR: 0x20 (Check!) BLCKS2 LRCLKS2 SDINS2 SDOUTS2 PIU1903 PIU19047 PIU1903 PIU19016 PIU19021 PIU190PAD PIU19032 PIU19031 PIU19027 PIU19026 DGND AGND HPGND SPKRGND SPKLGND 3 47 30 16 21 PAD A +3V3 PIFB301 6 DVDDS1 25 PVDD 53 DVDD 32 +5V HPVSS 31 2 27 1 C1N 50 AVDD HPVDD 19 SPKLVDD 18 SPKRVDD 55 DVDDS2 C1P 26 COC106 C106 10pF Author: Jorge Amodio Date: 7/15/2015 Audio 10pF COC107 C107 GND PIC107 2 PIC107 1 GND Renesas YLCDRZA1H Baseboard GND PIC10602 PIC10601 4 3 PIJ1003 1 PIJ1001 COJ10 J10 Line Out COJ11 J11 COJ12 J12 2 5 6 3 PIJ1403 4 PIJ1404 1 PIJ1401 COJ14 J14 Revision: v2.1 PCB03 Sheet 9 of 12 PIJ1406 PIJ1405 PIJ1402 2 PIJ1202 PIJ1201 1 2 PIJ1102 1 PIJ1101 Right Speaker Left Speaker 4 www.seriousintegrated.com Headphones & Mic Keep wires as short as possible PIJ1004 2 PIJ1002 4 D C B A D C B 1 NLRZM0MD0CLKS RZM-MD_CLKS NLRZM0BOOT1 RZM-BOOT1 NLRZM0BOOT2 RZM-BOOT2 +3V3 NLRZM0P8090RxD3 RZM-P8_9/RxD3 NLRZM0P8080TxD3 RZM-P8_8/TxD3 NLRZM0MISO2 RZM-MISO2 NLRZM0RSPCK2 RZM-RSPCK2 NLRZM0SSL20 RZM-SSL20 NLRZM0MOSI2 RZM-MOSI2 +3V3 COS2 S2 COR32 R32 4K70 GND 1PIS2012PIS202 3PIS203 4PIS204 PIS208 PIS207 PIS206 PIS205 PIR3101 PIR3201 PIR3102 PIR3202 8 7 6 5 COR31 R31 4K70 GND PIJ1502 2 3 PIJ1503 4 PIJ1504 5 PIJ1505 6 PIJ1506 COJ15 J15 1 PIJ1501 8 9 PIJ1509 10 PIJ15010 11 PIJ15011 12 PIJ15012 PIJ1508 7 PIJ1507 PMOD 10K0 COR30 R30 PIR30 1 PIR30 2 NLRZM0PMOD0IRQ RZM-PMOD_IRQ NLRZM0PMOD0RST# RZM-PMOD_RST# 2 NLRZM0LED0RED RZM-LED_RED NLRZM0LED0GRN RZM-LED_GRN NLRZM0AN00ALS RZM-AN0_ALS GND PIR2901 10K0 COR29 R29 PIR2902 2 GND PIR3401 COR35 R35 PIR3502 PIR3602 1K50 PIR3601 COR36 R36 470R PIR3501 1K00 COR34 R34 PIR3402 1 3 R G COLED1 LED1 PILED103 1 4 PILED104 2 PILED102 3 VCC VCC PIU2003 4 IOUT NC PIU2004 PILED101 PIU2002 2 PIU2001 APDS-9002 COU20 U20 GND 3 GND PIS303 PIS302 PIS304 PIS301 PIR3 01 COS3 S3 10K0 3 COR33 R33 PIR3 02 4 1 3 2 A 1 Author: Jorge Amodio Date: 7/15/2015 PMOD, Boot Modes, & User I/O COS4 S4 Renesas YLCDRZA1H Baseboard GND PIS403 PIS402 PIS404 PIS401 4 1 3 2 Revision: v2.1 PCB03 Sheet 10of 12 NLRZM0RESET# RZM-RESET# NLRZM0P7080IRQ1 RZM-P7_8/IRQ1 4 www.seriousintegrated.com 4 D C B A D C B A 1 33pF PIC11401 PIC11402 PIRA2107 PIRA2108 PIRA2105 PIRA2106 PIRA2102 PIRA2101 PIRA2103 PIRA2104 CORA21DCBA NLRZM0RESET# RZM-RESET# NLRZM0TRST# RZM-TRST# NLRZM0TMS RZM-TMS 1 R47 10K0 GND PIR4701 PIR4501 7 100R 8 PIRA2208 100R 5 PIRA2205 100R 6 PIRA2206 100R PIRA2207 22R0 PIR4502 GND PIC12101 PIC12 02 PIRA20 8 PIRA20 1 PIRA20 7 PIRA20 2 1 2 GND TRESin TRSTout/TRSTin TMSout/TMSin TDIOut/TDIin COC122 C122 0.1uF PIC12 01 PIC12 02 COR40 R40 PIC12301 PIC12302 GND COC123 C123 1nF 0R00PIR4002 PIR4001 GND PILED204 PILED20 2 2 GND COC124 C124 10nF R43 1K50 GND PIC12401 PIR4301 PIC12402 PIR4302 COR43 COLED2 LED2 470R COR38 R38 PIR3801 PIR3802 PILED203 PILED201 PIR3701 COR37 R37 1K50 PIR3702 GND 3 CLK PIU2203 TCKout/TCKin TDOin PIR3901 COR39 R39 1K50 PIR3902 4 VDD PIU2204 18.4320MHz PIU2202 OE Si501 4K70 CORA20A CORA20B CORA20D RA20A COU22 U22 1 PIU2201 GND COC121 C121 15pF RA20D 4K70 GND 15pF 2PIRA2202 RA22B 1PIRA2201 CORA22A CORA22B CORA22C CORA22D RA22A 4PIRA2204 RA22D 3PIRA2203 RA22C NLRZM0TDI RZM-TDI PIRA20 5 PIRA20 4 4 COC120 C120 NLRZM0TCK RZM-TCK PIR4702COR47 PIC120 1 PIC120 2 GND PIR4202 COR42 R42 27R0 PIR4201 PIR4102 COR41 R41 27R0 PIR4101 COR45 R45 3 PIJ1703 4 PIJ1704 5 PIJ1705 2 PIJ1702 PIJ1701 COC114 C114 9 PIJ1609 NLJLink0TDI 8 JLink_TDI PIJ1608 7 PIJ1607 NLJLink0TDO 6 JLink_TDO PIJ1606 10 PIJ16010 NLRZM0TDO RZM-TDO GND PIJ170C4 PIJ170C3 PIJ170C2 PIJ170C1 5VUSB DD+ USBID GND J-Link OB USB COJ17 J17 2 PIJ1602 3 PIJ1603 4 PIJ1604 5 PIJ1605 GND NLJLink0TCK JLink_TCK NLJLink0TMS JLink_TMS 1 PIJ1601 RA20B 4K70 7 8 2 COJ16 J16 G NL03V3 +3V3 4 RA21D 2 RA21B 1 RA21A 3 RA21C 5 10K0 7 10K0 8 10K0 6 10K0 3 4 1 R 2 1 50 51 PIU21051 52 PIU21052 53 PIU21053 54 PIU21054 55 PIU21055 56 PIU21056 57 PIU21057 58 PIU21058 59 PIU21059 60 PIU21060 61 PIU21061 62 PIU21062 63 PIU21063 64 PIU21064 PIU21050 49 PIU21049 PIU210 PIU210 PIU2103 PIU2104 PIU2105 PIU2106 PIU2107 PIU2108 PIU2109 PIU210 PIU210 PIU2102 PIU210 3 PIU2104 PIU210 5 PIU2106 GND 3 3 31 30 PIU21030 29 PIU21029 28 PIU21028 27 PIU21027 26 PIU21026 25 PIU21025 24 PIU21024 23 PIU21023 22 PIU21022 21 PIU21021 20 PIU21020 19 PIU21019 18 PIU21018 17 PIU21017 PIR4602 100R PIR4601 COR46 R46 390R PIR4401 PIR4402 PIU21031 32 PIU21032 COR44 R44 PWM3/RTS0/PA7 ADTRG/CTS0/PA8 NPCS1/DRXD/PA9 NPCS2/DTXD/PA10 PWM0/NPCS0/PA11 PWM1/MISO/PA12 TIOA2/DCD1/PA26 PWM2/VTS/PA25 VDDCORE PWM1/RTS1/PA24 PWM2/MOSI/PA13 PWM3/SPCK/PA14 TIOA1/TF/PA15 TIOB1/TK/PA16 VDDIO GND PIU21048 PIU21047 PIU21046 PIU21045 PIU2104 PIU21043 PIU21042 PIU21041 PIU2104 PIU21039 PIU21038 PIU21037 PIU21036 PIU21035 PIU21034 PIU2103 TDO JTAGSEL TMS PA31/NPCS/PCK2 TCK VDDCORE ERASE DDM DDP VDDIO VDDFLASH GND XOUT XIN PLLRC VDDPLL AT91SAM7S64 COU21 U21 TDIout TDOin TRESin +3V3 TRSTin 5 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 TIOA0/PWM0/PA0 TIOB0/PWM1/PA1 GND VDDIO SCK0/PWM2/PA2 NPCS3/TWD/PA3 NPCS2/IRQ1/PA30 TCLK2/RI1/PA29 TST NRST TCLK1/DSR1/PA28 TIOB2/DTR1/PA27 TCLK0/TWCK/PA4 NPCS3/RXD0/PA5 PCK0/TXD0/PA6 TDI ADVREF GND AD4 AD5 AD6 AD7 VDDIN VDDOUT PA17/TD/PCK1/AD0 PA18/RD/PCK2/AD1 PA21/RXD/PCK1 VDDCORE PA19/RK/FIQ/AD2 PA22/TXD1/NPCS3 PA23/SCK1/PWM0 PA20/RF/IRQ0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Author: Jorge Amodio Date: 7/15/2015 COC116 C116 0.1uF GND PIC1 601 PIC1 602 GND PIC1 701 PIC1 702 COC117 C117 0.1uF 0.1uF COC111 C111 GND PIC1 02 PIC1 01 4 GND PIC1 901 PIC1 902 COC113 C113 4.7uF GND PIC1 302 PIC1 301 COC119 C119 4.7uF COC112 C112 0.1uF GND PIC1 202 PIC1 201 COC118 C118 0.1uF GND PIC1 801 PIC1 802 www.seriousintegrated.com 0.1uF Revision: v2.1 PCB03 Sheet 11of 12 JLink On Board & External JTAG Interface Renesas YLCDRZA1H Baseboard GND PIC1 501 GND PIC1 502 TDIclk COC110 C110 0.1uF GND PIC1 0 2 PIC1 0 1 COC115 C115 COC109 C109 0.1uF GND PIC109 2 PIC109 1 TMSout TCKout TDIin TCKin TMSin TRESout TRSTout 0.1uF COC108 C108 GND PIC108 2 PIC108 1 4 D C B A D C B A 1 1 SO1 COSO2 SO2 COSO3 SO3 COSO4 SO4 COSO5 SO5 COSO6 SO6 COSO1 NLRZM0MMC0CMD RZM-MMC_CMD NLRZM0MMC0D2 RZM-MMC_D2 NLRZM0MMC0D1 RZM-MMC_D1 NLRZM0MMC0CLK RZM-MMC_CLK NLRZM0MMC0D0 RZM-MMC_D0 NLRZM0TDI RZM-TDI NLRZM0TDO RZM-TDO NLRZM0TMS RZM-TMS NLRZM0TCK RZM-TCK NLRZM0TRST# RZM-TRST# NLRZM0LED0RED RZM-LED_RED NLRZM0BOOT1 RZM-BOOT1 NLRZM0AUDIO0IRQ RZM-AUDIO_IRQ NLRZM0LED0GRN RZM-LED_GRN NLRZM0AUDIO0CLK RZM-AUDIO_CLK NLRZM0P1013 RZM-P1_13 NLRZM0PMOD0IRQ RZM-PMOD_IRQ NLRZM0AN00ALS RZM-AN0_ALS NLRZM0USBH0P RZM-USBH_P NLRZM0USBH0N RZM-USBH_N NLRZM0USBF0VBUS RZM-USBF_VBUS NLRZM0USBH0VBUS RZM-USBH_VBUS NLRZM0USBF0P RZM-USBF_P NLRZM0USBF0N RZM-USBF_N NLRZM0VIO0VSYNC RZM-VIO_VSYNC NLRZM0ET0MDIO RZM-ET_MDIO NLRZM0LCD0CLK RZM-LCD_CLK NLRZM0UART0TX RZM-UART_TX NLRZM0RESET# RZM-RESET# NLRZM0P005 RZM-P0_5 NLRZM0P004 RZM-P0_4 NLRZM0UART0RX RZM-UART_RX NLRZM0VIO0HSYNC RZM-VIO_HSYNC NLRZM0LCD0VSYNC RZM-LCD_VSYNC NLRZM0TOUCH0RST RZM-TOUCH_RST NLRZM0RS0ON RZM-RS_ON NLRZM0RS0DEN RZM-RS_DEN NLRZM0LCD0DEN RZM-LCD_DEN COJ1B COJ1A J1A GND 3 PIJ103 5 PIJ105 7 PIJ107 9 PIJ109 11 PIJ1011 13 PIJ1013 15 PIJ1015 17 PIJ1017 19 PIJ1019 21 PIJ1021 23 PIJ1023 25 PIJ1025 27 PIJ1027 29 PIJ1029 31 PIJ1031 33 PIJ1033 35 PIJ1035 37 PIJ1037 39 PIJ1039 41 PIJ1041 43 PIJ1043 45 PIJ1045 47 PIJ1047 49 PIJ1049 51 PIJ1051 53 PIJ1053 55 PIJ1055 57 PIJ1057 59 PIJ1059 61 PIJ1061 63 PIJ1063 65 PIJ1065 67 PIJ1067 69 PIJ1069 71 PIJ1071 73 PIJ1073 75 PIJ1075 77 PIJ1077 79 PIJ1079 81 PIJ1081 83 PIJ1083 85 PIJ1085 87 PIJ1087 89 PIJ1089 91 PIJ1091 93 PIJ1093 95 PIJ1095 97 PIJ1097 99 PIJ1099 1 PIJ101 4 PIJ104 6 PIJ106 8 PIJ108 10 PIJ1010 12 PIJ1012 14 PIJ1014 16 PIJ1016 18 PIJ1018 20 PIJ1020 22 PIJ1022 24 PIJ1024 26 PIJ1026 28 PIJ1028 30 PIJ1030 32 PIJ1032 34 PIJ1034 36 PIJ1036 38 PIJ1038 40 PIJ1040 42 PIJ1042 44 PIJ1044 46 PIJ1046 48 PIJ1048 50 PIJ1050 52 PIJ1052 54 PIJ1054 56 PIJ1056 58 PIJ1058 60 PIJ1060 62 PIJ1062 64 PIJ1064 66 PIJ1066 68 PIJ1068 70 PIJ1070 72 PIJ1072 74 PIJ1074 76 PIJ1076 78 PIJ1078 80 PIJ1080 82 PIJ1082 84 PIJ1084 86 PIJ1086 88 PIJ1088 90 PIJ1090 92 PIJ1092 94 PIJ1094 96 PIJ1096 98 PIJ1098 100 PIJ10100 2 PIJ102 2 NLRZM0SSL20 RZM-SSL20 NLRZM0VIO0D4 RZM-VIO_D4 NLRZM0SD0D1 RZM-SD_D1 NLRZM0VIO0D6 RZM-VIO_D6 NLRZM0SD0CLK RZM-SD_CLK NLRZM0SD0CMD RZM-SD_CMD NLRZM0VIO0D3 RZM-VIO_D3 NLRZM0LCD0DATA13 RZM-LCD_DATA13 NLRZM0ET0TXCLK RZM-ET_TXCLK NLRZM0LCD0DATA14 RZM-LCD_DATA14 NLRZM0SD0WP RZM-SD_WP NLRZM0ET0TXER RZM-ET_TXER NLRZM0LCD0DATA11 RZM-LCD_DATA11 NLRZM0VIO0D2 RZM-VIO_D2 NLRZM0MMC0D3 RZM-MMC_D3 NLRZM0LCD0DATA9 RZM-LCD_DATA9 NLRZM0LCD0DATA10 RZM-LCD_DATA10 NLRZM0TOUCH0IRQ RZM-TOUCH_IRQ NLRZM0P1015 RZM-P1_15 NLRZM0USBH0OC# RZM-USBH_OC# NLRZM0ET0COL RZM-ET_COL NLRZM0VIO0FLD RZM-VIO_FLD NLRZM0ET0RXCLK RZM-ET_RXCLK NLRZM03V3 RZM_3V3 NLRZM0ET0RXER RZM-ET_RXER NLRZM0MOSI2 RZM-MOSI2 NLRZM0MISO2 RZM-MISO2 NLRZM0ET0RXDV RZM-ET_RXDV NLRZM0PMOD0RST# RZM-PMOD_RST# NLRZM0VIO0CLK RZM-VIO_CLK NLRZM0RSPCK2 RZM-RSPCK2 NLRZM0P8090RxD3 RZM-P8_9/RxD3 NLRZM0BLEN RZM-BLEN NLRZM0LCD0DATA1 RZM-LCD_DATA1 NLRZM0LCD0HSYNC RZM-LCD_HSYNC NLRZM0CKIO RZM-CKIO NLRZM0P8080TxD3 RZM-P8_8/TxD3 NL05V +5V NLRZM0LCD0DATA0 RZM-LCD_DATA0 NLRZM0MMC0D5 RZM-MMC_D5 NLRZM0MMC0D7 RZM-MMC_D7 NLRZM0P7080IRQ1 RZM-P7_8/IRQ1 NLRZM0LCD0DATA3 RZM-LCD_DATA3 NLRZM0LCD0DATA2 RZM-LCD_DATA2 NLRZM0SDA1 RZM-SDA1 NLRZM0ET0IRQ RZM-ET_IRQ NLRZM0SPBIO10 RZM-SPBIO10 NLRZM0LCD0DATA6 RZM-LCD_DATA6 NLRZM0LCD0DATA4 RZM-LCD_DATA4 NLRZM0BOOT2 RZM-BOOT2 NLRZM0LCD0DATA7 RZM-LCD_DATA7 NLRZM0LCD0DATA5 RZM-LCD_DATA5 NLRZM0MMC0D6 RZM-MMC_D6 NLRZM0MMC0D4 RZM-MMC_D4 NLRZM0SCL1 RZM-SCL1 NLRZM0VIO0D5 RZM-VIO_D5 NLRZM0ET0TXD0 RZM-ET_TXD0 NLRZM0ET0RXD3 RZM-ET_RXD3 NLRZM0SSIWS RZM-SSIWS NLRZM0ET0TXD2 RZM-ET_TXD2 NLRZM0ET0RXD0 RZM-ET_RXD0 NLRZM0SD0CD RZM-SD_CD NLRZM0VIO0D7 RZM-VIO_D7 NLRZM0SD0D0 RZM-SD_D0 NLRZM0ET0CRS RZM-ET_CRS NLRZM0SD0D3 RZM-SD_D3 NLRZM0LCD0DATA8 RZM-LCD_DATA8 NLRZM0LCD0DATA12 RZM-LCD_DATA12 NLRZM0VIO0D1 RZM-VIO_D1 NLRZM0VIO0D0 RZM-VIO_D0 NLRZM0LCD0DATA15 RZM-LCD_DATA15 Board to Board connections via DDR2 SODIMM Socket 2 3 3 101 GND Author: Jorge Amodio Date: 7/15/2015 Board to Board Interconnect GND 106 PIJ10106 108 PIJ10108 110 PIJ10110 112 PIJ10112 114 PIJ10114 116 PIJ10116 118 PIJ10118 120 PIJ10120 122 PIJ10122 124 PIJ10124 126 PIJ10126 128 PIJ10128 130 PIJ10130 132 PIJ10132 134 PIJ10134 136 PIJ10136 138 PIJ10138 140 PIJ10140 142 PIJ10142 144 PIJ10144 146 PIJ10146 148 PIJ10148 150 PIJ10150 152 PIJ10152 154 PIJ10154 156 PIJ10156 158 PIJ10158 160 PIJ10160 162 PIJ10162 164 PIJ10164 166 PIJ10166 168 PIJ10168 170 PIJ10170 172 PIJ10172 174 PIJ10174 176 PIJ10176 178 PIJ10178 180 PIJ10180 182 PIJ10182 184 PIJ10184 186 PIJ10186 188 PIJ10188 190 PIJ10190 192 PIJ10192 194 PIJ10194 196 PIJ10196 198 PIJ10198 200 PIJ10200 102 PIJ10102 104 PIJ10104 Renesas YLCDRZA1H Baseboard 105 PIJ10105 107 PIJ10107 109 PIJ10109 111 PIJ10111 113 PIJ10113 115 PIJ10115 117 PIJ10117 119 PIJ10119 121 PIJ10121 123 PIJ10123 125 PIJ10125 127 PIJ10127 129 PIJ10129 131 PIJ10131 133 PIJ10133 135 PIJ10135 137 PIJ10137 139 PIJ10139 141 PIJ10141 143 PIJ10143 145 PIJ10145 147 PIJ10147 149 PIJ10149 151 PIJ10151 153 PIJ10153 155 PIJ10155 157 PIJ10157 159 PIJ10159 161 PIJ10161 163 PIJ10163 165 PIJ10165 167 PIJ10167 169 PIJ10169 171 PIJ10171 173 PIJ10173 175 PIJ10175 177 PIJ10177 179 PIJ10179 181 PIJ10181 183 PIJ10183 185 PIJ10185 187 PIJ10187 189 PIJ10189 191 PIJ10191 193 PIJ10193 195 PIJ10195 197 PIJ10197 199 PIJ10199 103 PIJ10103 PIJ10101 J1B Revision: v2.1 PCB03 Sheet 12of 12 4 www.seriousintegrated.com NLPWRDWN# PWRDWN# NLRZM01V8 RZM_1V8 NLRZM0SPBSSL0 RZM-SPBSSL0 NLRZM0MD0CLKS RZM-MD_CLKS NLRZM0SPBIO00 RZM-SPBIO00 NLRZM0SPBCLK0 RZM-SPBCLK0 NLRZM0ET0MDC RZM-ET_MDC NLRZM0CANTX RZM-CANTX NLRZM0LCD0DATA22 RZM-LCD_DATA22 NLRZM0LCD0DATA23 RZM-LCD_DATA23 NLRZM0LCD0DATA18 RZM-LCD_DATA18 NLRZM0LCD0DATA19 RZM-LCD_DATA19 NLRZM0LCD0DATA20 RZM-LCD_DATA20 NLRZM0LCD0DATA21 RZM-LCD_DATA21 NLRZM0LCD0DATA16 RZM-LCD_DATA16 NLRZM0LCD0DATA17 RZM-LCD_DATA17 NLRZM0P107 RZM-P1_7 NLRZM0USBH05V0EN RZM-USBH_5V_EN NLRZM0CANRX RZM-CANRX NLRZM0SCL0 RZM-SCL0 NLRZM0SDA0 RZM-SDA0 NLRZM0SSIRxD RZM-SSIRxD NLRZM0ET0RXD1 RZM-ET_RXD1 NLRZM0ET0TXD3 RZM-ET_TXD3 NLRZM0ET0RXD2 RZM-ET_RXD2 +5V NLRZM0ET0TXEN RZM-ET_TXEN NLRZM0SD0D2 RZM-SD_D2 NLRZM0SSISCK RZM-SSISCK NLRZM0ET0TXD1 RZM-ET_TXD1 NLRZM0SSITxD RZM-SSITxD 4 D C B A YLCDRZA1H Technical Reference Manual 12.5 - Baseboard BOM Designator Qty Description BAT1 1 3030TR [Keystone] CR1025 SMD Coin Cell Holder C1, C5, C60, C113, C119 5 CL05A475MQ5NQNC [Samsung] Ceramic 4u7 6V3 X5R 20% C2, C3, C9, C27, C39, C40, C41, C42, C43, C44, C45, C46, C48, C49, C50, C51, C52, C53, C58, C59, C61, C63, C64, C66, C68, C69, C70, C71, C72, C75, C77, C78, C79, C80, C81, C82, C83, C84, C89, C90, C108, C109, C110, C111, C112, C115, C116, C117, C118, C122 C4, C7, C17, C65 50 CL03A104KP3NNNC [Samsung] Ceramic100n0 10V X5R 10% 4 CL10A226MQ8NRNC [Samsung] Ceramic 22uF 6.3V X5R 20% C6, C16, C37, C88, C91 5 CL10A106KP8NNND [Samsung] Ceramic 10uF 10V 10% X5R C8 1 CL05B271KB5NNNC [Samsung] Ceramic 270p 50V X7R 10% C10, C11, C12 3 CL31A106KBHNNNE [Samsung] Ceramic 10u0 50V 10% X5R C13 1 C1005X7R1H104K050BB [TDK] Ceramic 100n0 50V 10% X7R C14, C30, C31 3 CL05B103KB5NNNC [Samsung] Ceramic 10n0 50V X7R 10% C15 1 CL05C180JB5NNNC [Samsung] Ceramic 18p0 50V C0G 5% C18 1 CL05A104KO5NNNC [Samsung] Ceramic 100n0 16V 10% X7R C19 1 CL05B102KB5NNNC [Samsung] Ceramic 1n0 50V X7R 10% C20, C114 2 CL05C330JB5NNNC [Samsung] Ceramic 33p0 50V 5% NP0 C21, C22, C23, C25, C34, C35 6 C1608X5R1H334M080AB [TDK] Ceramic 330n0 50V 20% X5R C24, C36 2 CL21A226MAQNNNE [Samsung] Ceramic 22u0 25V 20% X5R C26 1 C1608X7R1H224M080AB [TDK] Ceramic 220n0 50V 20% X7R C28 1 CL05B471KB5NNNC [Samsung] Ceramic 470p0 50V 10% X7R C29 1 CL05C220JB5NNNC [Samsung] Ceramic 22p0 50V 5% NP0 C32, C33, C47, C95, C96, C97 6 CL05A105KO5NNNC [Samsung] Ceramic1u0 16V X5R 10% C38 1 CL31B105KBHNNNE [Samsung] Ceramic 1u0 50V 10% X7R C54, C57, C73, C86, C87, C92, C93, C94, C98, C102, C103, C104 C55, C56, C62, C105 12 CL03A105MQ3CSNC [Samsung] Ceramic 1u0 6.3V 20% X5R 4 CL05A225MP5NNNC [Samsung] Ceramic 2u2 10V X5R 20% C67 1 LMK316BJ476ML-T [Taiyo Yuden] Ceramic 47uF 10V 20% X5R C74 1 TPSD157M016R0150 [AVX] Tant150uF 16V 20% C76 0 CL03A104KP3NNNC [Samsung] Ceramic100n0 10V X5R 10% C85 1 CL05A106MQ5NUNC [Samsung] Ceramic10uF 6.3V X5R 20% C99, C100, C101, C106, C107 5 CL03C100DA3GNNC [Samsung] Ceramic 10p0 25V C0G/NP0 +/-0.5pF C120, C121 2 C0603C0G1E150J030BA [Murata] Ceramic 15p0 25V C0G 5% C123 1 CL03B102KA3NNNC [Samsung] Ceramic 1n0 25V 10% X7R C124 1 CL03A103KP3NNNC [Samsung] Ceramic 10n0 10V 10% X5R D1, D2, D3, D4 4 RB481KTL [Rohm] Dual Shottky Diode 30V D5 1 B240A-13-F [Diodes Inc] Schottky 40V 2A D6 1 DFLS130L-7 [Diodes Zetex] Schottky Diode 30V 310mV@1A FB1 1 BLM21AG121SN1D [Murata] Ferrite Beads120Ohm 25% 100MHz 800mA FB2, FB3 2 CIM05U601NC [Samsung] Ferrite Bead 600 Ohm 300mA 0402 FB4 1 CIS10P300AC [Samsung] Ferrite Bead 30R0 6A J1 1 1473005-4 [TE] 200Pos RA DIMM Socket 0.6mm pitch J2 1 RASM722PTR13X [Switchcraft] RA, 2.1mm 5A SMT, T/R Rev 2.20 Jul 21, 2015 Page 59 of 68 YLCDRZA1H Technical Reference Manual J3 1 XF2W-4015-1A [Omron] 40pos 0.5mm pitch FFC Dual J4 1 XF2W-0815-1A [Omron] 8pos 0.5mm pitch FFC J5 1 08B0-1X1T-36-F [Bel] MagJack 10/100 AutoMDIX LED G/Y TH J6 1 CES-109-01-T-D [Samtec] 18pos/2x9 ST F 2.54mm Hdr J7 1 USB-A-S-F-B-SM2-R-TR [Samtec] USB A 2.0 4Pin J8, J17 2 10118192-0001LF [FCI] USB Micro B Full SMT J9 1 20020110-C081A01LF [FCI] Term Block 8pos/1x8 M 3.5mm RA TH J10 1 SJ-3524-SMT-TR-GR [CUI] 3.5mm SMT Audio Jack Green J11, J12 2 SM02B-GHS-TB(LF)(SN) [JST] 2Pos/1x2 1.25mm RA J13 1 SJ-3524-SMT-TR-BE [CUI] 3.5mm SMT Audio Jack Blue J14 1 SJ-43516-SMT-TR-PI [CUI] 3.5mm SMT Audio Jack Pink/Red J15 1 SSW-106-02-F-D-RA [Samtec] 2x6 RA 0.1" F Header J16 0 TC-2050 PCB [Tag-Connect] 10pos/2x5 *NO PART PADS ONLY* L1 1 SRU1028-100Y [Bourns ] 10uH Shielded 2.8A 45mOhm 10x10x2.8mm L2, L4 2 SRN3015-2R2M [Bourns] 2.2uH 1.8A 72mOhm Inductor L3 1 SRN3015-1R0Y [Bourns] 1uH 2.35A Inductor 3x3x1.5mm L5 1 SRR6028-3R9Y [Bourns] Shielded 3.9uH 2.45A SMD Coil L6 1 SRR5028-220Y [Bourns] 22uH 1.15 30% 120mOHM,5.8x5.8x2.8mm LED1, LED2 2 598-8610-207F [Dialight] LED BiColor Red/Green 60/40mcd R1, R4, R5, R18, R19, R27, R29, R30, R33, R47 R2 10 ERA-2AED103X [Panasonic] 10K 0.5% 1/16W 25ppm 1 ERJ-2RKF3742X [Panasonic] 37k4 1% 1/10W 100ppm R3 1 ERJ-2RKF1871X [Panasonic] 1k87 1% 1/10W 100ppm R6 1 ERJ-2RKF1803X [Panasonic] 180K Ohm 1% 1/10W 100ppm R7 1 ERJ-2RKF2553X [Panasonic] 255k0 1% 1/10W 100ppm AEC-Q200 R8, R9, R10 3 ERJ-2RKF4993X [Panasonic] 499k 1% 1/10W 100ppm R11 1 ERJ-2RKF1004X [Panasonic] 1m00 1% 1/10W 100ppm R12 1 ERJ-2RKF7502X [Panasonic] 75k0 1% 1/10W 100ppm R13 1 ERJ-2RKF5622X [Panasonic] 56k2 1% 1/10W 100ppm R14 1 ERJ-2RKF3302X [Panasonic] 33k0 1% 1/10W 100ppm R15 1 ERJ-2RKF6652X [Panasonic] 66k5 1% 1/10W 100ppm R16 1 NRC04F1101TRF [NIC] 1k1 1/16W 1% 0402 R17 1 CRCW04023R00FKED [Vishay] 3R00 1% 1/16W 100ppm R20, R45 2 ERJ-2RKF22R0X [Panasonic] 22R0 1% 1/10W 100ppm R21 1 ERJ-2RKF2201X [Panasonic ] 2k2 1% 1/10W 100ppm R22, R23 2 ERJ-2RKF2200X [Panasonic] 220R 1% 1/10W 100ppm R24 1 ERJ-2RKF6491X [Panasonic] 6k49 1% 1/10W 100ppm R25, R26, R46 3 ERA-2AED101X [Panasonic ] 100R 0.5% 1/16W 25ppm R28 1 ERA-2AED223X [Panasonic ] 22k0 0.5% 1/16W 25ppm R31, R32 2 ERA-2AED472X [Panasonic ] 4k70 0.5% 1/16W 25ppm R34 1 ERA-2AED102X [Panasonic ] 1k00 0.5% 1/16W 25ppm R35, R38 2 ERA-2AED471X [Panasonic ] 470R 0.5% 1/16W 25ppm R36, R37, R39, R43 4 ERA-2AED152X [Panasonic] 1K50 0.5% 1/16W 25ppm R40 1 CRCW04020000Z0ED [Vishay] 0R00 1/16W R41, R42 2 ERJ-2RKF27R0X [Panasonic] 27R0 1% 1/10W 100ppm R44 1 ERJ-2RKF3900X [Panasonic] 390R 1% 1/10W 100ppm Rev 2.20 Jul 21, 2015 Page 60 of 68 YLCDRZA1H Technical Reference Manual RA1, RA19 2 EXB-28V104JX [Panasonic] IsolArr 100k0 5% 200ppm 1/16W 4x040 RA2, RA3, RA4, RA5, RA6, RA7, RA8, RA15, RA16, RA17 RA9, RA10 10 EXB-28V330JX [Panasonic] IsolArr 33R0 4x 5% 200ppm 1/16W 2 EXB-28V223JX [Panasonic] IsolArr 22k0 4x 5% 200ppm 1/16W RA11, RA12 2 EXB-28V473JX [Panasonic] IsolArr 47k0 4x 5% 200ppm 1/16W RA13 1 EXB-28V220JX [Panasonic] IsolArr 22R0 4x 5% 200ppm 1/16W RA14, RA18, RA20 3 EXB-28V472JX [Panasonic] IsolArr 4k7 5% 200ppm 1/16W 4x0402 RA21 1 EXB-28V103JX [Panasonic] IsolArr 10k0 5% 200ppm 1/16W 4x0402 RA22 1 EXB-28V101JX [Panasonic] IsolArr 100R 4x 5% 200ppm 1/16W S1, S2 2 219-4LPSTR [CTS] DIP Switch 4Pos 2.54mm S3, S4 2 KSC222J LFS [C&K] Sealed PB Switch 6.2x6.2mm SD1 1 10067847-001RLF [FCI] SDCard Socket SO3, SO4, SO5, SO6 4 SMTSO-M4-6ET [PEM] M4 6.0mm Standoff U1 1 P9122-S2NBGI [IDT] Switcher w/I2C Dual Fact Pgm 1.8, 3.30 U2 1 TPS54232D [TI] Buck Regulator 28V 2A U3 1 TPS2501DRCR [TI] USB Boost Power Controlller SON10 U4 1 74LVC1G157GV [NXP] Single 2-Input Multiplexer U5 1 TPS65150RGER [TI] LCD 3-output LCD power controller U6 1 CAT4139TD-GT3 [OnSemi] LED Backlight Driver U7 1 DS90CF383BMTX/NOPB [TI] RGB888 to LVDS 65MHz Serializer U8 1 MTFC4GMDEA-4M IT [Micron] 4GByte eMMC 3v3 U9 1 PCF8523TK/1,118 [NXP] Real Time Clock U10 1 ATSHA204-MAHDA-T [Atmel] CryptoAuthentication Chip U11 1 KSZ8081MNXCA TR [Micrel] Ethernet 10/100 MII PHY U12 1 501AAA25M0000DAGR [SiLabs] 25MHz Oscillator 50ppm 2x2.5mm U13 1 24AA02E48T-I/OT [Microchip] EEPROM EUI48 MAC I2C U14 1 501AAA24M0000DAGR [SiLabs] 24MHz Oscillator 50ppm 2x2.5mm U15, U16 2 TPD2E2U06DRLR [TI] ESD Transient Suppressor Dual 30kV U17 1 ISL41387IRZ-T [Intersil] RS232/RS485 Dual Mode Transceiver U18 1 IFX1050GVIOXUMA1 [Infineon] CAN Transceiver 1MBaud U19 1 MAX98089ETN+ [Maxim] Audio Codec/Amplifier U20 1 APDS-9002-021 [Avago] Ambient Light Sensor U21 1 AT91SAM7S64C-MU [Atmel] MCU U22 1 501AAA18M4320DAGR [SiLabs] 18.432MHz Osc 50ppm 2x2.5mm X1 1 ABS07-32.768KHZ-T [Abracon] 12.5pF 20ppm Rev 2.20 Jul 21, 2015 Page 61 of 68 YLCDRZA1H Technical Reference Manual Chapter 13 - Post Production Modifications 13.1 - I/O Baseboard v2.0 The I/O Baseboard v2.0 has the following post-production modification to address the issue described in the 5.5 USB Host Power Subsystem section: On v2.0 units, P1.6 was incorrectly used to drive the USB Host Power Enable (RZM-USBH_5V_EN on the RZ Module; DIMM pin 132). This port is open drain only on the MCU, and is incapable of driving high and enabling the power supply. All v2.0 units should include a post-production modification connecting U21 pin 7 (ENUSB) to U21 pin 8 (FAULT#) to enable the USB supply during all non-overcurrent situations. The unmodified v2.0 units have U21 (near the USB Host A Connector) like this: The modified 2.0 units have the two pins 7 and 8 shorted as described above: Rev 2.20 Jul 21, 2015 Page 62 of 68 YLCDRZA1H Technical Reference Manual Chapter 14 - Additional Information Further information available for this product can be found on the Renesas website at: http://am.renesas.com/HiResGUI General information on Renesas Microcontrollers can be found on the global Renesas website: http://www.renesas.com/ Rev 2.20 Jul 21, 2015 Page 63 of 68 Renesas Electronics America, Inc. 2801 Scott Boulevard Santa Clara, CA 95050-2554, US