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FM24V10
1-Mbit (128K × 8) Serial (I2C) F-RAM
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 001-84463 Rev. *J Revised December 26, 2018
1-Mbit (128K × 8) Serial (I2C) F-RAM
Features
■1-Mbit ferroelectric random access memory (F-RAM) logically
organized as 128K × 8
❐High-endurance 100 trillion (1014) read/writes
❐151-year data retention (See Data Retention and Endurance
on page 13)
❐NoDelay™ writes
❐Advanced high-reliability ferroelectric process
■Fast two-wire Serial interface (I2C)
❐Up to 3.4-MHz frequency
❐Direct hardware replacement for serial (I2C) EEPROM
❐Supports legacy timings for 100 kHz and 400 kHz
■Device ID and Serial Number
❐Manufacturer ID and Product ID
❐Unique Serial Number (FM24VN10)
■Low power consumption
❐175 A active current at 100 kHz
❐90 A (typ) standby current
❐5 A (typ) sleep mode current
■Low-voltage operation: VDD = 2.0 V to 3.6 V
■Industrial temperature: –40 C to +85 C
■8-pin small outline integrated circuit (SOIC) package
■Restriction of hazardous substances (RoHS) compliant
Functional Description
The FM24V10 is a 1-Mbit nonvolatile memory employing an
advanced ferroelectric process. A ferroelectric random access
memory or F-RAM is nonvolatile and performs reads and writes
similar to a RAM. It provides reliable data retention for 151 years
while eliminating the complexities, overhead, and system-level
reliability problems caused by EEPROM and other nonvolatile
memories.
Unlike EEPROM, the FM24V10 performs write operations at bus
speed. No write delays are incurred. Data is written to the
memory array immediately after each byte is successfully
transferred to the device. The next bus cycle can commence
without the need for data polling. In addition, the product offers
substantial write endurance compared with other nonvolatile
memories. Also, F-RAM exhibits much lower power during writes
than EEPROM since write operations do not require an internally
elevated power supply voltage for write circuits. The FM24V10 is
capable of supporting 1014 read/write cycles, or 100 million times
more write cycles than EEPROM.
These capabilities make the FM24V10 ideal for nonvolatile
memory applications, requiring frequent or rapid writes.
Examples range from data logging, where the number of write
cycles may be critical, to demanding industrial controls where the
long write time of EEPROM can cause data loss. The
combination of features allows more frequent data writing with
less overhead for the system.
The FM24V10 provides substantial benefits to users of serial
(I2C) EEPROM as a hardware drop-in replacement. The
FM24VN10 is offered with a unique serial number that is
read-only and can be used to identify a board or system. Both
devices incorporate a read-only Device ID that allows the host to
determine the manufacturer, product density, and product
revision. The device specifications are guaranteed over an
industrial temperature range of –40 C to +85 C.
For a complete list of related documentation, click here.
Address
Latch
128 K x 8
F-RAM Array
Data Latch
8
SDA
Counter
Serial to Parallel
Converter
Control Logic
SCL
WP
A2-A1
Device ID and
Serial Number
8
17
8
Logic Block Diagram
Errata: STOP condition is optional for sleep mode entry. For more information, see Errata on page 19. Details include errata trigger conditions, scope of impact, available
workarounds, and silicon revision applicability.
FM24V10
Document Number: 001-84463 Rev. *J Page 2 of 23
Contents
Pinout ................................................................................3
Pin Definitions .................................................................. 3
Functional Overview ........................................................ 4
Memory Architecture ........................................................ 4
I2C Interface ...................................................................... 4
STOP Condition (P) ..................................................... 4
START Condition (S) ................................................... 4
Data/Address Transfer ................................................ 5
Acknowledge/No-acknowledge ................................... 5
Slave Device Address ................................................. 6
High Speed Mode (Hs-mode) ......................................6
Addressing Overview .................................................. 6
Data Transfer .............................................................. 6
Memory Operation ............................................................ 6
Write Operation ........................................................... 6
Read Operation ........................................................... 7
Sleep Mode ................................................................. 9
Device ID ........................................................................... 9
Unique Serial Number (FM24VN10 only) ......................10
Function to Calculate CRC ........................................ 11
Maximum Ratings ........................................................... 12
Operating Range ............................................................. 12
DC Electrical Characteristics ........................................ 12
Data Retention and Endurance ..................................... 13
Capacitance .................................................................... 13
Thermal Resistance ........................................................ 13
AC Test Loads and Waveforms ..................................... 13
AC Test Conditions ........................................................ 13
AC Switching Characteristics ....................................... 14
Power Cycle Timing ....................................................... 15
Ordering Information ...................................................... 16
Ordering Code Definitions ......................................... 16
Package Diagram ............................................................ 17
Acronyms ........................................................................ 18
Document Conventions ................................................. 18
Units of Measure ....................................................... 18
Errata ............................................................................... 19
Part Numbers Affected .............................................. 19
FM24V10/FM24VN10 I2C F-RAM
Qualification Status ........................................................... 19
FM24V10/FM25VN10 Errata Summary .................... 19
Document History Page ................................................. 21
Sales, Solutions, and Legal Information ...................... 23
Worldwide Sales and Design Support ....................... 23
Products .................................................................... 23
PSoC® Solutions ...................................................... 23
Cypress Developer Community ................................. 23
Technical Support ..................................................... 23
FM24V10
Document Number: 001-84463 Rev. *J Page 3 of 23
Pinout
Figure 1. 8-pin SOIC pinout
WP
SCL
1
2
3
4 5
NC 8
7
6
VDD
SDA
A1
Top View
not to scale
V
SS
A2
Pin Definitions
Pin Name I/O Type Description
A2–A1 Input Device Select Address 2–1. These pins are used to select one of up to 4 devices of the same type
on the same I2C bus. To select the device, the address value on the three pins must match the corre-
sponding bits contained in the slave address. The address pins are pulled down internally.
SDA Input/Output Serial Data/Address. This is a bi-directional pin for the I2C interface. It is open-drain and is intended
to be wire-AND'd with other devices on the I2C bus. The input buffer incorporates a Schmitt trigger for
noise immunity and the output driver includes slope control for falling edges. An external pull-up resistor
is required.
SCL Input Serial Clock. The serial clock pin for the I2C interface. Data is clocked out of the device on the falling
edge, and into the device on the rising edge. The SCL input also incorporates a Schmitt trigger input
for noise immunity.
WP Input Write Protect. When tied to VDD, addresses in the entire memory map will be write-protected. When
WP is connected to ground, all addresses are write enabled. This pin is pulled down internally.
VSS Power supply Ground for the device. Must be connected to the ground of the system.
VDD Power supply Power supply input to the device.
NC No connect No connect. This pin is not connected to the die.
FM24V10
Document Number: 001-84463 Rev. *J Page 4 of 23
Functional Overview
The FM24V10 is a serial F-RAM memory. The memory array is
logically organized as 131,072 × 8 bits and is accessed using an
industry-standard I2C interface. The functional operation of the
F-RAM is similar to serial (I2C) EEPROM. The major difference
between the FM24V10 and a serial (I2C) EEPROM with the
same pinout is the F-RAM’s superior write performance, high
endurance, and low power consumption.
Memory Architecture
When accessing the FM24V10, the user addresses 128K
locations of eight data bits each. These eight data bits are shifted
in or out serially. The addresses are accessed using the I2C
protocol, which includes a slave address (to distinguish other
non-memory devices), a page select bit, and a two-byte address.
The 17-bit address consists of a page select bit followed by
16-bits. The complete address of 17-bits specifies each byte
address uniquely.
The access time for the memory operation is essentially zero,
beyond the time needed for the serial protocol. That is, the
memory is read or written at the speed of the I2C bus. Unlike a
serial (I2C) EEPROM, it is not necessary to poll the device for a
ready condition because writes occur at bus speed. By the time
a new bus transaction can be shifted into the device, a write
operation is complete. This is explained in more detail in the
interface section.
I2C Interface
The FM24V10 employs a bi-directional I2C bus protocol using
few pins or board space. Figure 2 illustrates a typical system
configuration using the FM24V10 in a microcontroller-based
system. The industry standard I2C bus is familiar to many users
but is described in this section.
By convention, any device that is sending data onto the bus is
the transmitter while the target device for this data is the receiver.
The device that is controlling the bus is the master. The master
is responsible for generating the clock signal for all operations.
Any device on the bus that is being controlled is a slave. The
FM24V10 is always a slave device.
The bus protocol is controlled by transition states in the SDA and
SCL signals. There are four conditions including START, STOP,
data bit, or acknowledge. Figure 3 on page 5 and Figure 4 on
page 5 illustrates the signal conditions that specify the four
states. Detailed timing diagrams are shown in the electrical
specifications section.
STOP Condition (P)
A STOP condition is indicated when the bus master drives SDA
from LOW to HIGH while the SCL signal is HIGH. All operations
using the FM24V10 should end with a STOP condition. If an
operation is in progress when a STOP is asserted, the operation
will be aborted. The master must have control of SDA in order to
assert a STOP condition.
START Condition (S)
A START condition is indicated when the bus master drives SDA
from HIGH to LOW while the SCL signal is HIGH. All commands
should be preceded by a START condition. An operation in
progress can be aborted by asserting a START condition at any
time. Aborting an operation using the START condition will ready
the FM24V10 for a new operation.
If during operation the power supply drops below the specified
VDD minimum, the system should issue a START condition prior
to performing another operation.
Figure 2. System Configuration using Serial (I2C) nvSRAM
Microcontroller
Vcc
SDA
SCL
Vcc
Vcc
1A1A1A
A2 A2 A2
LCSLCSLCS
SDA ADSADS
PWPWPW
#0 #1 #3
RPmin = (VDD - VOLmax) / IOL
RPmax = tr / (0.8473 * Cb)
FM24V10
Document Number: 001-84463 Rev. *J Page 5 of 23
Data/Address Transfer
All data transfers (including addresses) take place while the SCL
signal is HIGH. Except under the three conditions described
above, the SDA signal should not change while SCL is HIGH.
Acknowledge/No-acknowledge
The acknowledge takes place after the 8th data bit has been
transferred in any transaction. During this state the transmitter
should release the SDA bus to allow the receiver to drive it. The
receiver drives the SDA signal LOW to acknowledge receipt of
the byte. If the receiver does not drive SDA LOW, the condition
is a no-acknowledge and the operation is aborted.
The receiver would fail to acknowledge for two distinct reasons.
First is that a byte transfer fails. In this case, the no-acknowledge
ceases the current operation so that the device can be
addressed again. This allows the last byte to be recovered in the
event of a communication error.
Second and most common, the receiver does not acknowledge
to deliberately end an operation. For example, during a read
operation, the FM24V10 will continue to place data onto the bus
as long as the receiver sends acknowledges (and clocks). When
a read operation is complete and no more data is needed, the
receiver must not acknowledge the last byte. If the receiver
acknowledges the last byte, this will cause the FM24V10 to
attempt to drive the bus on the next clock while the master is
sending a new command such as STOP.
Figure 3. START and STOP Conditions
full pagewidth
SDA
SCL
P
STOP Condition
SDA
SCL
S
START Condition
Figure 4. Data Transfer on the I2C Bus
handbook, full pagewidth
S
or
P
SDA
S
P
SCL
STOP or
START
condition
S
START
condition
2 3 4 - 8 9
ACK
9
ACK
78
12
MSB Acknowledgement
signal from slave
Byte complete
Acknowledgement
signal from receiver
1
Figure 5. Acknowledge on the I2C Bus
handbook, full pagewidth
S
START
Condition
9821
Clock pulse for
acknowledgement
No Acknowledge
Acknowledge
DATA OUTPUT
BY MASTER
DATA OUTPUT
BY SLAVE
SCL FROM
MASTER
FM24V10
Document Number: 001-84463 Rev. *J Page 6 of 23
Slave Device Address
The first byte that the FM24V10 expects after a START condition
is the slave address. As shown in Figure 6, the slave address
contains the device type or slave ID, the device select address
bits, a page select bit, and a bit that specifies if the transaction is
a read or a write.
Bits 7–4 are the device type (slave ID) and should be set to
1010b for the FM24V10. These bits allow other function types to
reside on the I2C bus within an identical address range. Bits 3–2
are the device select address bits. They must match the corre-
sponding value on the external address pins to select the device.
Up to four FM24V10 devices can reside on the same I2C bus by
assigning a different address to each. Bit 1 is the page select bit
and is effectively the address MSB, A16. It specifies the
64K-byte block of memory that is targeted for the current
operation. Bit 0 is the read/write bit (R/W). R/W = ‘1’ indicates a
read operation and R/W = ‘0’ indicates a write operation.
High Speed Mode (Hs-mode)
The FM24V10 supports a 3.4-MHz high speed mode. A master
code (00001XXXb) must be issued to place the device into high
speed mode. Communication between master and slave will
then be enabled for speeds up to 3.4-MHz. A STOP condition will
exit Hs-mode. Single- and multiple-byte reads and writes are
supported.
Addressing Overview
After the FM24V10 (as receiver) acknowledges the slave
address, the master can place the memory address on the bus
for a write operation. The address requires a 1-bit page select
and two bytes. Since the device uses 17-bit address, the page
select bit is the MSB of the address followed by the remaining
16-bit address. The complete 17-bit address is latched internally.
Each access causes the latched address value to be incre-
mented automatically. The current address is the value that is
held in the latch; either a newly written value or the address
following the last access. The current address will be held for as
long as power remains or until a new value is written. Reads
always use the current address. A random read address can be
loaded by beginning a write operation as explained below.
After transmission of each data byte, just prior to the
acknowledge, the FM24V10 increments the internal address
latch. This allows the next sequential byte to be accessed with
no additional addressing. After the last address (1FFFFh) is
reached, the address latch will roll over to 00000h. There is no
limit to the number of bytes that can be accessed with a single
read or write operation.
Data Transfer
After the address bytes have been transmitted, data transfer
between the bus master and the FM24V10 can begin. For a read
operation the FM24V10 will place 8 data bits on the bus then wait
for an acknowledge from the master. If the acknowledge occurs,
the FM24V10 will transfer the next sequential byte. If the
acknowledge is not sent, the FM24V10 will end the read
operation. For a write operation, the FM24V10 will accept 8 data
bits from the master then send an acknowledge. All data transfer
occurs MSB (most significant bit) first.
Memory Operation
The FM24V10 is designed to operate in a manner very similar to
other I2C interface memory products. The major differences
result from the higher performance write capability of F-RAM
technology. These improvements result in some differences
between the FM24V10 and a similar configuration EEPROM
during writes. The complete operation for both writes and reads
is explained below.
Write Operation
All writes begin with a slave address, then a memory address.
The bus master indicates a write operation by setting the LSB of
the slave address (R/W bit) to a ‘0’. After addressing, the bus
master sends each byte of data to the memory and the memory
generates an acknowledge condition. Any number of sequential
bytes may be written. If the end of the address range is reached
internally, the address counter will wrap from 1FFFFh to 00000h.
Unlike other nonvolatile memory technologies, there is no
effective write delay with F-RAM. Since the read and write
access times of the underlying memory are the same, the user
experiences no delay through the bus. The entire memory cycle
occurs in less time than a single bus clock. Therefore, any
operation including read or write can occur immediately following
a write. Acknowledge polling, a technique used with EEPROMs
to determine if a write is complete is unnecessary and will always
return a ready condition.
Figure 6. Memory Slave Device Address
handbook, halfpage
R/W
LSBMSB
Slave ID
10 10A2 A16
A1
Device
Select
Page
select
Figure 7. Data transfer format in Hs-mode
handbook, full pagewidth
F/S-mode Hs-mode F/S-mode
01
/A 1 DATA
n (bytes + ack.)
W/R
S
MASTER CODE S SLAVE ADD.
Hs-mode continues
SSLAVE ADD.
P
No Acknowledge
Acknowledge or
No Acknowledge
FM24V10
Document Number: 001-84463 Rev. *J Page 7 of 23
Internally, an actual memory write occurs after the 8th data bit is
transferred. It will be complete before the acknowledge is sent.
Therefore, if the user desires to abort a write without altering the
memory contents, this should be done using START or STOP
condition prior to the 8th data bit. The FM24V10 uses no page
buffering.
The memory array can be write-protected using the WP pin.
Setting the WP pin to a HIGH condition (VDD) will write-protect
all addresses. The FM24V10 will not acknowledge data bytes
that are written to protected addresses. In addition, the address
counter will not increment if writes are attempted to these
addresses. Setting WP to a LOW state (VSS) will disable the write
protect. WP is pulled down internally.
Figure 8 and Figure 9 below illustrate a single-byte and
multiple-byte write cycles in F/S mode. Figure 10 below illustrate
a single-byte write cycles in Hs mode.
Read Operation
There are two basic types of read operations. They are current
address read and selective address read. In a current address
read, the FM24V10 uses the internal address latch to supply the
address. In a selective read, the user performs a procedure to
set the address to a specific value.
Current Address & Sequential Read
As mentioned above the FM24V10 uses an internal latch to
supply the address for a read operation. A current address read
uses the existing value in the address latch as a starting place
for the read operation. The system reads from the address
immediately following that of the last operation.
To perform a current address read, the bus master supplies a
slave address with the LSB set to a ‘1’. This indicates that a read
operation is requested. After receiving the complete slave
address, the FM24V10 will begin shifting out data from the
current address on the next clock. The current address is the
value held in the internal address latch.
Beginning with the current address, the bus master can read any
number of bytes. Thus, a sequential read is simply a current
address read with multiple byte transfers. After each byte the
internal address counter will be incremented.
Note Each time the bus master acknowledges a byte, this
indicates that the FM24V10 should read out the next sequential
byte.
Figure 8. Single-Byte Write
S A Slave Address 0Address MSB AData Byte A P
By Master
By F-RAM
Start Address & Data Stop
Acknowledge
Address LSB A
P
S
Figure 9. Multi-Byte Write
S A Slave Address 0Address MSB AData Byte A P
By Master
By F-RAM
Start
Address & Data Stop
Acknowledge
Address LSB AData Byte A
P
S
Figure 10. Hs-mode Byte Write
S A Slave Address 0Data Byte A P
By Master
By F-RAM
Start &
Enter HS-mode Address & Data
Stop &
Exit HS-mode
S 1
Start
Acknowledge
P
S
XXX10000
HS-mode command
Address MSB AAddress LSB A
No
Acknowledge
FM24V10
Document Number: 001-84463 Rev. *J Page 8 of 23
There are four ways to properly terminate a read operation.
Failing to properly terminate the read will most likely create a bus
contention as the FM24V10 attempts to read out additional data
onto the bus. The four valid methods are:
1. The bus master issues a no-acknowledge in the 9th clock
cycle and a STOP in the 10th clock cycle. This is illustrated in
the diagrams below. This is preferred.
2. The bus master issues a no-acknowledge in the 9th clock
cycle and a START in the 10th.
3. The bus master issues a STOP in the 9th clock cycle.
4. The bus master issues a START in the 9th clock cycle.
If the internal address reaches 1FFFFh, it will wrap around to
00000h on the next read cycle. Figure 11 and Figure 12 below
show the proper operation for current address reads.
Figure 11. Current Address Read
S A Slave Address 1Data Byte 1 P
By Master
By F-RAM
Start Address
Stop
Acknowledge
No
Acknowledge
Data
X
Figure 12. Sequential Read
S A Slave Address 1Data Byte 1 P
By Master
By F-RAM
Start Address
Stop
Acknowledge
No
Acknowledge
Data
Data ByteA
Acknowledge
X
Figure 13. Hs-mode Current Address Read
S A Slave Address 1Data Byte 1 P
By Master
By F-RAM
Start &
Enter HS-mode Address Stop &
Exit HS-mode
No
Acknowledge
Data
S 1
Start
Acknowledge
X
XXX10000
HS-mode command
No
Acknowledge
FM24V10
Document Number: 001-84463 Rev. *J Page 9 of 23
Selective (Random) Read
There is a simple technique that allows a user to select a random
address location as the starting point for a read operation. This
involves using the first three bytes of a write operation to set the
internal address followed by subsequent read operations.
To perform a selective read, the bus master sends out the slave
address with the LSB (R/W) set to 0. This specifies a write
operation. According to the write protocol, the bus master then
sends the address bytes that are loaded into the internal address
latch. After the FM24V10 acknowledges the address, the bus
master issues a START condition. This simultaneously aborts
the write operation and allows the read command to be issued
with the slave address LSB set to a ‘1’. The operation is now a
current address read.
Sleep Mode
A low power mode called Sleep Mode is implemented on the
FM24V10 device. The device will enter this low power state when
the Sleep command 86h is clocked-in. Sleep Mode entry can be
entered as follows:
1. The master sends a START command.
2. The master sends Reserved Slave ID F8h.
3. The FM24V10 sends an ACK.
4. The master sends the I2C-bus slave address of the slave
device it needs to identify. The last bit is a ‘Don’t care’ value
(page select and R/W bits). Only one device must
acknowledge this byte (the one that has the I2C-bus slave
address).
5. The FM24V10 sends an ACK.
6. The master sends a Re-START command.
7. The master sends Reserved Slave ID 86h.
8. The FM24V10 sends an ACK.
9. The master sends STOP to ensure the device enters sleep
mode.
Note Errata: Step 9 - Sending STOP is an optional step for
FM24V10. The FM24V10 starts entering the Sleep mode from
step 8 and releases the SDA line when in the Sleep mode. The
LOW to HIGH transition on the SDA line when I2C clock is HIGH
generates an unintended STOP. For more information, see
Errata on page 19.
Once in sleep mode, the device draws IZZ current, but the device
continues to monitor the I2C pins. Once the master sends a
Slave Address that the FM24V10 identifies, it will “wakeup” and
be ready for normal operation within tREC time. As an alternative
method of determining when the device is ready, the master can
send read or write commands and look for an ACK. While the
device is waking up, it will NACK the master until it is ready.
Device ID
The FM24V10 device incorporates a means of identifying the
device by providing three bytes of data, which are manufacturer
ID, product ID, and die revision. The Device ID is read-only. It
can be accessed as follows:
1. The master sends a START command.
2. The master sends Reserved Slave ID F8h.
3. The FM24V10 sends an ACK.
4. The master sends the I2C-bus slave address of the slave
device it needs to identify. The last bit is a ‘Don’t care’ value
(page select and R/W bits). Only one device must
acknowledge this byte (the one that has the I2C-bus slave
address).
5. The FM24V10 sends an ACK.
6. The master sends a Re-START command.
7. The master sends Reserved Slave ID F9h.
8. The FM24V10 sends an ACK.
9. The Device ID Read can be done, starting with the 12
manufacturer bits, followed by the 9 device identification bits,
and then the 3 die revision bits.
10.The master ends the Device ID read sequence by NACKing
the last byte, thus resetting the slave device state machine
and allowing the master to send the STOP command.
Note The reading of the Device ID can be stopped anytime by
sending a NACK command.
Figure 14. Selective (Random) Read
S A Slave Address 1Data Byte 1 P
By Master
By F-RAM
Start Address
Stop
No
Acknowledge
Data
S A Slave Address 0Address MSB A
Start
Address
Acknowledge
Address LSB A
P
SX
Figure 15. Sleep Mode Entry
S A P
By Master
By F-RAM
Start Address Stop
S ARsvd Slave ID (F8) Slave Address A
Start
Address
Acknowledge
Rsvd Slave ID (86)
XX
FM24V10
Document Number: 001-84463 Rev. *J Page 10 of 23
Note Product ID bit 4 = S/N, Product ID bit 0 = reserved.
Unique Serial Number (FM24VN10 only)
The FM24VN10 device also incorporates a read-only 8-byte
serial number. It can be used to uniquely identify a pc board or
system. The serial number includes a 40-bit unique number, an
8-bit CRC, and a 16-bit number that can be defined upon request
by the customer. If a customer-specific number is not requested,
the 16-bit Customer Identifier is 0000h. The 8 bytes of data are
accessed via a slave address sequence similar to the Device ID.
The serial number can be read by the system as follows:
1. The master sends a START command
2. The master sends Reserved Slave ID F8h
3. The FM24VN10 sends an ACK.
4. The master sends the I2C-bus slave address of the slave
device it needs to identify. The last two bits are ‘Don’t care’
values. Only one device must acknowledge this byte (the one
that has the I2C-bus slave address).
5. The FM24VN10 sends an ACK.
6. The master sends a Re-START command
7. The master sends Reserved Slave ID CDh to read the serial
number.
8. The FM24VN10 sends an ACK.
9. The master ends the serial number read sequence by
NACKing the last byte, thus resetting the slave device state
machine and allowing the master to send the STOP
command.
The 8-bit CRC value can be used to compare to the value calcu-
lated by the controller. If the two values match, then the commu-
nication between slave and master was performed without
errors. The function (shown in Function to Calculate CRC on
page 11) is used to calculate the CRC value. To perform the
calculation, 7 bytes of data are filled into a memory buffer in the
same order as they are read from the part - i.e. byte7, byte6,
byte5, byte4, byte3, byte2, byte1 of the serial number. The calcu-
lation is performed on the 7 bytes, and the result should match
the final byte out from the part which is byte0, the 8-bit CRC
value.
Note Contact factory for requesting a customer identifier number.
Table 1. Device ID
Device Device ID
(3 bytes)
Device ID Description
23–12
(12 bits)
11–8
(4 bits)
7–3
(5 bits)
2–0
(3 bits)
Manufacturer ID Product ID
Density Variation Die Rev
FM24V10 004400h 000000000100 0100 N0000 000
FM24VN10 004480h 000000000100 0100 10000 000
Figure 16. Read Device ID
S AData Byte Data Byte 1 P
By Master
By F-RAM
Start Address
Stop
No
Acknowledge
Data
S ARsvd Slave ID (F8) Slave Address A
Start
Address
Acknowledge
Rsvd Slave ID (F9) A A Data Byte
Acknowledge
XX
Table 2. 8-Byte Serial Number (read-only)
Customer IDENTIFIER 40-bit UNIQUE NUMBER 8-bit CRC
SN(63–56) SN(55–48) SN(47–40) SN(39–32) SN(31–24) SN(23–16) SN(15–8) SN(7–0)
Figure 17. 8-byte Serial Number (read-only)
S AData Byte 7 1 P
By Master
By F-RAM
Start Address
Stop
No
Acknowledge
Data
S ARsvd Slave ID (F8) Slave Address A
Start
Address
Acknowledge
Rsvd Slave ID (CD) A A Data Byte 0
Acknowledge
XX
FM24V10
Document Number: 001-84463 Rev. *J Page 11 of 23
Function to Calculate CRC
BYTE calcCRC8( BYTE* pData, int nBytes )
{
static BYTE crctable[256] = {
};
BYTE crc = 0;
.................... while( nBytes-- ) crc = crctable[crc ^ *pData++];
return crc;
}
0x00, 0x07, 0x0E, 0x09, 0x1C, 0x1B, 0x12, 0x15,
0x38, 0x3F, 0x36, 0x31, 0x24, 0x23, 0x2A, 0x2D,
0x70, 0x77, 0x7E, 0x79, 0x6C, 0x6B, 0x62, 0x65,
0x48, 0x4F, 0x46, 0x41, 0x54, 0x53, 0x5A, 0x5D,
0xE0, 0xE7, 0xEE, 0xE9, 0xFC, 0xFB, 0xF2, 0xF5,
0xD8, 0xDF, 0xD6, 0xD1, 0xC4, 0xC3, 0xCA, 0xCD,
0x90, 0x97, 0x9E, 0x99, 0x8C, 0x8B, 0x82, 0x85,
0xA8, 0xAF, 0xA6, 0xA1, 0xB4, 0xB3, 0xBA, 0xBD,
0xC7, 0xC0, 0xC9, 0xCE, 0xDB, 0xDC, 0xD5, 0xD2,
0xFF, 0xF8, 0xF1, 0xF6, 0xE3, 0xE4, 0xED, 0xEA,
0xB7, 0xB0, 0xB9, 0xBE, 0xAB, 0xAC, 0xA5, 0xA2,
0x8F, 0x88, 0x81, 0x86, 0x93, 0x94, 0x9D, 0x9A,
0x27, 0x20, 0x29, 0x2E, 0x3B, 0x3C, 0x35, 0x32,
0x1F, 0x18, 0x11, 0x16, 0x03, 0x04, 0x0D, 0x0A,
0x57, 0x50, 0x59, 0x5E, 0x4B, 0x4C, 0x45, 0x42,
0x6F, 0x68, 0x61, 0x66, 0x73, 0x74, 0x7D, 0x7A,
0x89, 0x8E, 0x87, 0x80, 0x95, 0x92, 0x9B, 0x9C,
0xB1, 0xB6, 0xBF, 0xB8, 0xAD, 0xAA, 0xA3, 0xA4,
0xF9, 0xFE, 0xF7, 0xF0, 0xE5, 0xE2, 0xEB, 0xEC,
0xC1, 0xC6, 0xCF, 0xC8, 0xDD, 0xDA, 0xD3, 0xD4,
0x69, 0x6E, 0x67, 0x60, 0x75, 0x72, 0x7B, 0x7C,
0x51, 0x56, 0x5F, 0x58, 0x4D, 0x4A, 0x43, 0x44,
0x19, 0x1E, 0x17, 0x10, 0x05, 0x02, 0x0B, 0x0C,
0x21, 0x26, 0x2F, 0x28, 0x3D, 0x3A, 0x33, 0x34,
0x4E, 0x49, 0x40, 0x47, 0x52, 0x55, 0x5C, 0x5B,
0x76, 0x71, 0x78, 0x7F, 0x6A, 0x6D, 0x64, 0x63,
0x3E, 0x39, 0x30, 0x37, 0x22, 0x25, 0x2C, 0x2B,
0x06, 0x01, 0x08, 0x0F, 0x1A, 0x1D, 0x14, 0x13,
0xAE, 0xA9, 0xA0, 0xA7, 0xB2, 0xB5, 0xBC, 0xBB,
0x96, 0x91, 0x98, 0x9F, 0x8A, 0x8D, 0x84, 0x83,
0xDE, 0xD9, 0xD0, 0xD7, 0xC2, 0xC5, 0xCC, 0xCB,
0xE6, 0xE1, 0xE8, 0xEF, 0xFA, 0xFD, 0xF4, 0xF3
FM24V10
Document Number: 001-84463 Rev. *J Page 12 of 23
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. These user guidelines are not tested.
Storage temperature ................................ –65 °C to +125 °C
Maximum accumulated storage time
At 125 °C ambient temperature ................................. 1000 h
At 85 °C ambient temperature ................................ 10 Years
Ambient temperature
with power applied ................................... –55 °C to +125 °C
Supply voltage on VDD relative to VSS .........–1.0 V to +4.5 V
Input voltage .......... –1.0 V to + 4.5 V and VIN < VDD + 1.0 V
DC voltage applied to outputs
in High-Z state .................................... –0.5 V to VDD + 0.5 V
Transient voltage (< 20 ns)
on any pin to ground potential ............ –2.0 V to VDD + 2.0 V
Package power dissipation capability
(TA = 25 °C) ................................................................. 1.0 W
Surface mount lead soldering temperature
(10 seconds) ............................................................ +260 °C
Electrostatic Discharge Voltage
Human Body Model (AEC-Q100-002 Rev. E) .................. 2.5 kV
Charged Device Model (AEC-Q100-011 Rev. B) ............. 1.25 kV
Machine Model (AEC-Q100-003 Rev. E) ............................ 200 V
Latch-up current .................................................... > 140 mA
* Exception: The “VIN < VDD + 1.0 V” restriction does not apply
to the SCL and SDA inputs.
Operating Range
Range Ambient Temperature (TA) VDD
Industrial –40 C to +85 C 2.0 V to 3.6 V
DC Electrical Characteristics
Over the Operating Range
Parameter Description Test Conditions Min Typ [1] Max Unit
VDD Power supply 2.0 3.3 3.6 V
IDD Average VDD current SCL toggling
between
VDD – 0.2 V and VSS,
other inputs VSS or
VDD – 0.2 V.
fSCL = 100 kHz – – 175 A
fSCL = 1 MHz – – 400 A
fSCL = 3.4 MHz – – 1000 A
ISB Standby current SCL = SDA = VDD. All other inputs VSS
or VDD. Stop command issued.
–90150A
IZZ Sleep mode current SCL = SDA = VDD. All other inputs VSS
or VDD. Stop command issued.
–58A
ILI Input leakage current
(Except WP and A2–A1)
VSS < VIN < VDD –1 – +1 A
Input leakage current
(for WP and A2–A1)
VSS < VIN < VDD –1 – +100 A
ILO Output leakage current VSS < VIN < VDD –1 – +1 A
VIH Input HIGH voltage 0.7 × VDD –V
DD + 0.3 V
VIL Input LOW voltage –0.3 – 0.3 × VDD V
VOL1 Output LOW voltage IOL = 2 mA, VDD > 2.7 V – – 0.4 V
VOL2 Output LOW voltage IOL = 150 A––0.2V
Rin[2] Input resistance (WP, A2–A1) For VIN = VIL (Max) 50 – – k
For VIN = VIH (Min) 1––M
Notes
1. Typical values are at 25 °C, VDD = VDD (typ). Not 100% tested.
2. The input pull-down circuit is strong (50 k) when the input voltage is below VIL and weak (1 M) when the input voltage is above VIH.
FM24V10
Document Number: 001-84463 Rev. *J Page 13 of 23
AC Test Conditions
Input pulse levels .................................10% and 90% of VDD
Input rise and fall times .................................................10 ns
Input and output timing reference levels ................0.5 × VDD
Output load capacitance ............................................ 100 pF
Data Retention and Endurance
Parameter Description Test condition Min Max Unit
TDR Data retention TA = 85 C10–Years
TA = 75 C38–
TA = 65 C 151 –
NVCEndurance Over operating temperature 1014 – Cycles
Capacitance
Parameter [3] Description Test Conditions Max Unit
COOutput pin capacitance (SDA) TA = 25 C, f = 1 MHz, VDD = VDD(typ) 8 pF
CIInput pin capacitance 6pF
Thermal Resistance
Parameter [3] Description Test Conditions 8-pin SOIC Unit
JA Thermal resistance
(junction to ambient)
Test conditions follow standard test methods and
procedures for measuring thermal impedance, per
EIA/JESD51.
138 C/W
JC Thermal resistance
(junction to case)
40 C/W
AC Test Loads and Waveforms
Figure 18. AC Test Loads and Waveforms
3.6 V
OUTPUT
100 pF
1.8 k
Note
3. These parameters are guaranteed by design and are not tested.
FM24V10
Document Number: 001-84463 Rev. *J Page 14 of 23
AC Switching Characteristics
Over the Operating Range
Parameter [4]
Description
F/S-mode [5] Hs-mode[5]
Unit
Cypress
Parameter
Alt.
Parameter Min Max Min Max
fSCL[6] SCL clock frequency –1.0 –3.4 MHz
tSU; STA Start condition setup for repeated Start 260 –160 –ns
tHD;STA Start condition hold time 260 –160 –ns
tLOW Clock LOW period 500 –160 –ns
tHIGH Clock HIGH period 260 –60 –ns
tSU;DAT[7] tSU;DATA Data in setup 50 –10 –ns
tHD;DAT tHD;DATA Data in hold 0 – 0 – ns
tDH Data output hold (from SCL @ VIL) 0 – 0 – ns
tR[8] trInput rise time –120 –80 ns
tF[8] tfInput fall time –120 –80 ns
tSU;STO STOP condition setup 260 –160 –ns
tAA tVD;DATA SCL LOW to SDA Data Out Valid –450 –130 ns
tBUF Bus free before new transmission 500 –300 –ns
tSP Noise suppression time constant on SCL, SDA –50 – 5 ns
Figure 19. Read Bus Timing Diagram
Figure 20. Write Bus Timing Diagram
tSU:SDA
Start
tR
`tF
Stop Start
tBUF
tHIGH
1/fSCL
tLOW tSP tSP
Acknowledge
tHD:DAT
tSU:DAT
tAA tDH
SCL
SDA
tSU:STO
Start Stop Start Acknowledge
tAA
tHD:DAT
tHD:STA tSU:DAT
SCL
SDA
Notes
4. Test conditions assume signal transition time of 10 ns or less, timing reference levels of VDD/2, input pulse levels of 0 to VDD(typ), and output loading of the specified
IOL and load capacitance shown in Figure 18 on page 13.
5. Bus Load (Cb) considerations; Cb < 500 pF for I2C clock frequency (SCL) 1 MHz; Cb < 100 pF for SCL at 3.4 MHz.
6. The speed-related specifications are guaranteed characteristic points along a continuous curve of operation from DC to fSCL (max).
7. In Hs-mode and VDD < 2.7 V, the tSU:DAT (min.) spec is 15 ns.
8. These parameters are guaranteed by design and are not tested.
FM24V10
Document Number: 001-84463 Rev. *J Page 15 of 23
Power Cycle Timing
Over the Operating Range
Parameter Description Min Max Unit
tPU Power-up VDD(min) to first access (START condition) 250 –µs
tPD Last access (STOP condition) to power-down (VDD(min)) 0 – µs
tVR [9, 10] VDD power-up ramp rate 50 –µs/V
tVF [9, 10] VDD power-down ramp rate 100 –µs/V
tREC [10] Recovery time from sleep mode –400 µs
Figure 21. Power Cycle Timing
SDA
~
~
~
~
tPU
tVR tVF
VDD
VDD(min)
tPD
VDD(min)
I C START
2I C STOP
2
Notes
9. Slope measured at any point on the VDD waveform.
10. Guaranteed by design.
FM24V10
Document Number: 001-84463 Rev. *J Page 16 of 23
Ordering Information
Ordering Code Package
Diagram Package Type Operating
Range
FM24V10-G 51-85066 8-pin SOIC Industrial
FM24V10-GTR
FM24VN10-G 8-pin SOIC, Serial Number
FM24VN10-GTR
All these parts are Pb-free. Contact your local Cypress sales representative for availability of these parts.
Ordering Code Definitions
Option: X = Blank or TR
Blank = Standard; TR = Tape and Reel
Package Type:
G = 8-pin SOIC
Density: 10 = 1-Mbit
N = Serial Number
Voltage: V = 2.0 V to 3.6 V
I2C F-RAM
Cypress
24FM V N 10 - G X
FM24V10
Document Number: 001-84463 Rev. *J Page 17 of 23
Package Diagram
Figure 22. 8-pin SOIC (150 Mils) Package Outline, 51-85066
51-85066 *I
FM24V10
Document Number: 001-84463 Rev. *J Page 18 of 23
Acronyms Document Conventions
Units of Measure
Acronym Description
ACK Acknowledge
CMOS Complementary Metal Oxide Semiconductor
EIA Electronic Industries Alliance
I2C Inter-Integrated Circuit
I/O Input/Output
JEDEC Joint Electron Devices Engineering Council
LSB Least Significant Bit
MSB Most Significant Bit
NACK No Acknowledge
RoHS Restriction of Hazardous Substances
R/W Read/Write
SCL Serial Clock Line
SDA Serial Data Access
SOIC Small Outline Integrated Circuit
WP Write Protect
Symbol Unit of Measure
°C degree Celsius
Hz hertz
Kb 1024 bit
kHz kilohertz
kkilohm
MHz megahertz
Mmegaohm
Amicroampere
smicrosecond
mA milliampere
ms millisecond
ns nanosecond
ohm
%percent
pF picofarad
Vvolt
Wwatt
FM24V10
Document Number: 001-84463 Rev. *J Page 19 of 23
Errata
This document describes the errata for the serial I2C F-RAM FM24V10/FM24VN10 (1-Mbit) product. Details include errata trigger
conditions, scope of impact, available workarounds, and silicon revision applicability. Compare this document to the device’s datasheet
for a complete functional description.
Contact your local Cypress Sales Representative if you have questions. You can also send your related queries directly to
cypressfram@cypress.com.
Part Numbers Affected
FM24V10/FM24VN10 I2C F-RAM Qualification Status
Production parts.
FM24V10/FM25VN10 Errata Summary
The following table defines the errata applicability to available FM24V10/FM24VN10 devices.
1. The I2C F-RAM enters Sleep mode without the STOP condition
■Problem Definition
When the I2C master sends the last Reserved Slave ID (86h) of the Sleep command sequence, as shown in Figure 23, the I2C
F-RAM returns an acknowledgement (ACK) and releases the SDA line after the rising edge of the 9th clock. If this LOW to HIGH
transition on the SDA line happens when the I2C clock is HIGH, it artificially generates an unintended STOP.
Part Number Device Characteristics
FM24V10 1-Mbit (128K × 8) Serial (I2C) F-RAM with Device ID, 2.0 V to 3.6 V, Industrial temperature
FM24VN10 1-Mbit (128K × 8) Serial (I2C) F-RAM with Device ID and Unique Serial Number, 2.0 V to 3.6 V, Industrial
temperature
Items Part Number Silicon Revision Fix Status
1. The I2C F-RAM enters Sleep mode without the
STOP condition
FM24V10-G
FM24V10-GTR
FM24VN10-G
FM24VN10-GTR
Rev A None.
Figure 23. I2C F-RAM Sleep Cycle
FM24V10
Document Number: 001-84463 Rev. *J Page 20 of 23
■Parameters Affected
None of the existing parameters are affected.
■Trigger Condition(S)
The I2C master sends the last Reserved Slave ID (86h) of the Sleep command and receives an ACK from the I2C F-RAM. The I2C
F-RAM starts entering the Sleep mode from the 9th rising edge of the I2C clock and releases the SDA line when in the Sleep mode.
The LOW to HIGH transition on the SDA line when I2C clock is HIGH generates an unintended STOP.
■Scope of Impact
The ongoing I2C communication can be disrupted due to unintended STOP generated by the I2C F-RAM slave.
■Workaround
This issue can be mitigated by implementing one of the following two methods:
❐The I2C master ignores any unintended STOP generated by the I2C F-RAM slave.
❐The I2C master latches the ACK on the 9th rising edge of the I2C clock and starts driving the SDA line LOW. This will ensure when
the I2C F-RAM enters Sleep and releases the SDA line; it still remains LOW driven by the I2C master. This will prevent unintended
LOW to HIGH transition when SCL is LOW.
■Fix Status
This issue is applicable to all the existing I2C F-RAM parts shown in this errata. The existing parts are in production status and will
continue serving with errata. There is no plan to fix this issue in the existing silicon.
FM24V10
Document Number: 001-84463 Rev. *J Page 21 of 23
Document History Page
Document Title: FM24V10, 1-Mbit (128K × 8) Serial (I2C) F-RAM
Document Number: 001-84463
Rev. ECN No. Orig. of
Change
Submission
Date Description of Change
** 3902204 GVCH 02/25/2013 New spec
*A 3996669 GVCH 05/13/2013 Added Appendix A - Errata for FM24V10 and FM24VN10
*B 4045469 GVCH 06/30/2013 All errata items are fixed and the errata is removed.
*C 4283424 GVCH 02/18/2014 Updated Maximum Ratings:
Added “Maximum junction temperature” and its corresponding details.
Added “DC voltage applied to outputs in High-Z state” and its corresponding
details.
Added “Transient voltage (< 20 ns) on any pin to ground potential” and its
corresponding details.
Added “Package power dissipation capability (TA = 25 °C)” and its
corresponding details.
Removed “Package Moisture Sensitivity Level (MSL)” and its corresponding
details.
Added “Latch-up current” and its corresponding details.
Updated DC Electrical Characteristics:
Removed existing details of ILI parameter and splitted ILI parameter into two
rows namely “Input leakage current (Except WP and A2–A1)” and “Input
leakage current (for WP and A2–A1)” and added corresponding values.
Updated Data Retention and Endurance:
Removed existing details of TDR parameter.
Added details of TDR parameter corresponding to “TA = 85 °C”, “TA = 75 °C”
and “TA = 65 °C”.
Added NVC parameter and its corresponding details.
Added Thermal Resistance.
Updated Package Diagram:
Removed Package Marking Scheme (top mark).
Removed “Ramtron Revision History”.
Updated to Cypress template.
Completing Sunset Review.
*D 4564960 GVCH 11/10/2014 Updated Functional Description:
Added “For a complete list of related documentation, click here.” at the end.
*E 4700243 GVCH 03/26/2015 Updated Package Diagram:
spec 51-85066 – Changed revision from *F to *G.
Added Errata.
*F 4781095 GVCH 05/29/2015 Updated Ordering Information:
No change in part numbers.
Fixed Typo (Replaced “001-85066” with “51-85066” in “Package Diagram”
column).
Updated to new template.
*G 4874648 ZSK / PSR 08/06/2015 Updated Maximum Ratings:
Removed “Maximum junction temperature” and its corresponding details.
Added “Maximum accumulated storage time” and its corresponding details.
Added “Ambient temperature with power applied” and its corresponding
details.
FM24V10
Document Number: 001-84463 Rev. *J Page 22 of 23
*H 5366088 GVCH 07/22/2016 Updated Pin Definitions:
Added details corresponding to “NC” pin.
Updated Package Diagram:
spec 51-85066 – Changed revision from *G to *H.
Updated to new template.
*I 5738855 GNKK 05/16/2017 Updated Cypress logo and copyright.
*J 6422002 GVCH 12/26/2018 Updated Maximum Ratings:
Replaced “–55 °C to +125 °C” with “–65 °C to +125 °C” in ratings corresponding
to “Storage temperature”.
Updated Package Diagram:
spec 51-85066 – Changed revision from *H to *I.
Updated to new template.
Completing Sunset Review.
Document History Page (continued)
Document Title: FM24V10, 1-Mbit (128K × 8) Serial (I2C) F-RAM
Document Number: 001-84463
Rev. ECN No. Orig. of
Change
Submission
Date Description of Change
Document Number: 001-84463 Rev. *J Revised December 26, 2018 Page 23 of 23
FM24V10
© Cypress Semiconductor Corporation, 2013–2018. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC (“Cypress”). This document,
including any software or firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
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(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress’s patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. No computing
device can be absolutely secure. Therefore, despite security measures implemented in Cypress hardware or software products, Cypress does not assume any liability arising out of any security breach,
such as unauthorized access to or use of a Cypress product. In addition, the products described in these materials may contain design defects or errors known as errata which may cause the product
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