LP3856ESX-3.3/NOPB - NATIONAL SEMICONDUCTOR

LP3853,LP3856

LP3853/LP3856 3A Fast Response Ultra Low Dropout Linear Regulators

Literature Number: SNVS173F

LP3853/LP3856

March 4, 2011

3A Fast Response Ultra Low Dropout Linear Regulators

General Description

The LP3853/LP3856 series of fast ultra low-dropout linear

regulators operate from a +2.5V to +7.0V input supply. Wide

range of preset output voltage options are available. These

ultra low dropout linear regulators respond very quickly to step

changes in load, which makes them suitable for low voltage

microprocessor applications. The LP3853/LP3856 are devel-

oped on a CMOS process which allows low quiescent current

operation independent of output load current. This CMOS

process also allows the LP3853/LP3856 to operate under ex-

tremely low dropout conditions.

Dropout Voltage: Ultra low dropout voltage; typically 39mV

at 300mA load current and 390mV at 3A load current.

Ground Pin Current: Typically 4mA at 3A load current.

Shutdown Mode: Typically 10nA quiescent current when the

shutdown pin is pulled low.

Error Flag: Error flag goes low when the output voltage drops

10% below nominal value.

SENSE: Sense pin improves regulation at remote loads.

Precision Output Voltage: Multiple output voltage options

are available ranging from 1.8V to 5.0V with a guaranteed

accuracy of ±1.5% at room temperature, and ±3.0% over all

conditions (varying line, load, and temperature).

Features

■Ultra low dropout voltage

■Stable with selected ceramic capacitors

■Low ground pin current

■Load regulation of 0.08%

■10nA quiescent current in shutdown mode

■Guaranteed output current of 3A DC

■Available in TO-263 and TO-220 packages

■Output voltage accuracy ± 1.5%

■Error flag indicates output status

■Sense option improves load regulation

■Overtemperature/overcurrent protection

■−40°C to +125°C junction temperature range

Applications

■Microprocessor power supplies

■Stable with ceramic output capacitors

■GTL, GTL+, BTL, and SSTL bus terminators

■Power supplies for DSPs

■SCSI terminator

■Post regulators

■High efficiency linear regulators

■Battery chargers

■Other battery powered applications

Typical Application Circuits

20030901

**SD and ERROR pins must be pulled high through a 10kΩ pull-up resistor. Connect the ERROR pin to ground if this function is not used. See Application

Hints for more information.

LP3853/LP3856 3A Fast Ultra Low Dropout Linear Regulators

20030934

**SD pin must be pulled high through a 10kΩ pull-up resistor. See Application Hints for more information.

Connection Diagrams

20030905

Top View

TO220-5 Package

Bent, Staggered Leads

20030906

Top View

TO263-5 Package

Pin Description for TO220-5 and TO263-5 Packages

Pin # LP3853 LP3856

Name Function Name Function

1 SD Shutdown SD Shutdown

2 VIN Input Supply VIN Input Supply

3 GND Ground GND Ground

4 VOUT Output Voltage VOUT Output Voltage

5 ERROR ERROR Flag SENSE Remote Sense Pin

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LP3853/LP3856

Ordering Information

20030931

Package Type Designator is "T" for TO220 package, and "S" for TO263 package.

TABLE 1. Package Marking and Ordering Information

Output

Voltage Order Number Description

(Current, Option) Package Type Package Marking Supplied As

5.0 LP3853ES-5.0 3A, Error Flag TO263-5 LP3853ES-5.0 Rail

5.0 LP3853ESX-5.0 3A, Error Flag TO263-5 LP3853ES-5.0 Tape and Reel

3.3 LP3853ES-3.3 3A, Error Flag TO263-5 LP3853ES-3.3 Rail

3.3 LP3853ESX-3.3 3A, Error Flag TO263-5 LP3853ES-3.3 Tape and Reel

2.5 LP3853ES-2.5 3A, Error Flag TO263-5 LP3853ES-2.5 Rail

2.5 LP3853ESX-2.5 3A, Error Flag TO263-5 LP3853ES-2.5 Tape and Reel

1.8 LP3853ES-1.8 3A, Error Flag TO263-5 LP3853ES-1.8 Rail

1.8 LP3853ESX-1.8 3A, Error Flag TO263-5 LP3853ES-1.8 Tape and Reel

5.0 LP3856ES-5.0 3A, SENSE TO263-5 LP3856ES-5.0 Rail

5.0 LP3856ESX-5.0 3A, SENSE TO263-5 LP3856ES-5.0 Tape and Reel

3.3 LP3856ES-3.3 3A, SENSE TO263-5 LP3856ES-3.3 Rail

3.3 LP3856ESX-3.3 3A, SENSE TO263-5 LP3856ES-3.3 Tape and Reel

2.5 LP3856ES-2.5 3A, SENSE TO263-5 LP3856ES-2.5 Rail

2.5 LP3856ESX-2.5 3A, SENSE TO263-5 LP3856ES-2.5 Tape and Reel

1.8 LP3856ES-1.8 3A, SENSE TO263-5 LP3856ES-1.8 Rail

1.8 LP3856ESX-1.8 3A, SENSE TO263-5 LP3856ES-1.8 Tape and Reel

5.0 LP3853ET-5.0 3A, Error Flag TO220-5 LP3853ET-5.0 Rail

3.3 LP3853ET-3.3 3A, Error Flag TO220-5 LP3853ET-3.3 Rail

2.5 LP3853ET-2.5 3A, Error Flag TO220-5 LP3853ET-2.5 Rail

1.8 LP3853ET-1.8 3A, Error Flag TO220-5 LP3853ET-1.8 Rail

5.0 LP3856ET-5.0 3A, SENSE TO220-5 LP3856ET-5.0 Rail

3.3 LP3856ET-3.3 3A, SENSE TO220-5 LP3856ET-3.3 Rail

2.5 LP3856ET-2.5 3A, SENSE TO220-5 LP3856ET-2.5 Rail

1.8 LP3856ET-1.8 3A, SENSE TO220-5 LP3856ET-1.8 Rail

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LP3853/LP3856

Block Diagrams

LP3853

20030903

LP3856

20030929

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LP3853/LP3856

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

Storage Temperature Range −65°C to +150°C

Lead Temperature

(Soldering, 5 sec.) 260°C

ESD Rating (Note 3) 2 kV

Power Dissipation (Note 2) Internally Limited

Input Supply Voltage (Survival) −0.3V to +7.5V

Shutdown Input Voltage (Survival) −0.3V to 7.5V

Output Voltage (Survival), (Note

6), (Note 7) −0.3V to +6.0V

IOUT (Survival) Short Circuit Protected

Maximum Voltage for ERROR Pin VIN

Maximum Voltage for SENSE Pin VOUT

Operating Ratings

Input Supply Voltage (Note 11) 2.5V to 7.0V

Shutdown Input Voltage −0.3V to 7.0V

Maximum Operating Current (DC) 3A

Junction Temperature −40°C to +125°C

Electrical Characteristics

LP3853/LP3856

Limits in standard typeface are for TJ = 25°C, and limits in boldface type apply over the full operating temperature range. Unless

otherwise specified: VIN = VO(NOM) + 1V, IL = 10 mA, COUT = 10µF, VSD = 2V.

Symbol Parameter Conditions Typ

(Note 4)

LP3853/6 (Note 5)Units

Min Max

Output Voltage Tolerance

(Note 8)

VOUT +1V ≤ VIN ≤ 7.0V

10 mA ≤ IL ≤ 3A 0-1.5

-3.0

+1.5

+3.0 %

ΔV OL

Output Voltage Line Regulation

(Note 8)VOUT +1V ≤ VIN ≤ 7.0V 0.02

0.06 %

ΔVO/ ΔIOUT

Output Voltage Load Regulation

(Note 8)10 mA ≤ IL ≤ 3A 0.08

0.14 %

VIN - VOUT

Dropout Voltage

(Note 10)

IL = 300 mA 39 50

65 mV

IL = 3A 390 450

600

IGND

Ground Pin Current In Normal

Operation Mode

IL = 300 mA 4 9

10 mA

IL = 3A 4 9

IGND

Ground Pin Current In Shutdown

Mode

VSD ≤ 0.3V 0.01 10 µA

-40°C ≤ TJ ≤ 85°C 50

IO(PK) Peak Output Current VO ≥ VO(NOM) - 4% 4.5 A

Short Circuit Protection

ISC Short Circuit Current 6 A

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LP3853/LP3856

Symbol Parameter Conditions Typ

(Note 4)

LP3853/6 (Note 5)Units

Min Max

Shutdown Input

VSDT Shutdown Threshold

VSDT Rising from 0.3V until

Output = ON 1.3 2

VSDT Falling from 2.0V until

Output = OFF 1.3 0.3

TdOFF Turn-off delay IL = 3A 20 µs

TdON Turn-on delay IL = 3A 25 µs

ISD SD Input Current VSD = VIN 1 nA

Error Flag

VTThreshold (Note 9) 10 5 16 %

VTH Threshold Hysteresis (Note 9) 5 2 8 %

VEF(Sat) Error Flag Saturation Isink = 100µA 0.02 0.1 V

Td Flag Reset Delay 1 µs

Ilk Error Flag Pin Leakage Current 1 nA

Imax Error Flag Pin Sink Current VError = 0.5V 1 mA

AC Parameters

PSRR Ripple Rejection

VIN = VOUT + 1V

COUT = 10uF

VOUT = 3.3V, f = 120Hz

VIN = VOUT + 0.5V

COUT = 10uF

VOUT = 3.3V, f = 120Hz

ρn(l/f Output Noise Density f = 120Hz 0.8 µV

enOutput Noise Voltage

BW = 10Hz – 100kHz

VOUT = 2.5V 150

µV (rms)

BW = 300Hz – 300kHz

VOUT = 2.5V 100

Note 1: Absolute maximum ratings indicate limits beyond which damage to the device may occur. Operating ratings indicate conditions for which the device is

intended to be functional, but does not guarantee specific performance limits. For guaranteed specifications and test conditions, see Electrical Characteristics.

The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under

the listed test conditions.

Note 2: At elevated temperatures, devices must be derated based on package thermal resistance. The devices in TO220 package must be derated at θjA = 50°

C/W (with 0.5in2, 1oz. copper area), junction-to-ambient (with no heat sink). The devices in the TO263 surface-mount package must be derated at θjA = 60°C/W

(with 0.5in2, 1oz. copper area), junction-to-ambient. See Application Hints.

Note 3: The human body model is a 100pF capacitor discharged through a 1.5kΩ resistor into each pin.

Note 4: Typical numbers are at 25°C and represent the most likely parametric norm.

Note 5: Limits are guaranteed by testing, design, or statistical correlation.

Note 6: If used in a dual-supply system where the regulator load is returned to a negative supply, the output must be diode-clamped to ground.

Note 7: The output PMOS structure contains a diode between the VIN and VOUT terminals. This diode is normally reverse biased. This diode will get forward

biased if the voltage at the output terminal is forced to be higher than the voltage at the input terminal. This diode can typically withstand 200mA of DC current

and 1Amp of peak current.

Note 8: Output voltage line regulation is defined as the change in output voltage from the nominal value due to change in the input line voltage. Output voltage

load regulation is defined as the change in output voltage from the nominal value due to change in load current. The line and load regulation specification contains

only the typical number. However, the limits for line and load regulation are included in the output voltage tolerance specification.

Note 9: Error Flag threshold and hysteresis are specified as percentage of regulated output voltage. See Application Hints.

Note 10: Dropout voltage is defined as the minimum input to output differential voltage at which the output drops 2% below the nominal value. Dropout voltage

specification applies only to output voltages of 2.5V and above. For output voltages below 2.5V, the drop-out voltage is nothing but the input to output differential,

since the minimum input voltage is 2.5V.

Note 11: The minimum operating value for VIN is equal to either [VOUT(NOM) + VDROPOUT] or 2.5V, whichever is greater.

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LP3853/LP3856

Typical Performance Characteristics Unless otherwise specified: TJ = 25°C, COUT = 10µF,

CIN = 10µF, S/D pin is tied to VIN, VOUT = 2.5V, VIN = VO(NOM) + 1V, IL = 10 mA.

Dropout Voltage vs Output Load Current

20030962

Ground Current vs Output Load Current

VOUT = 5V

20030953

Ground Current vs Output Voltage

IL = 3A

20030954

Shutdown IQ vs Junction Temperature

20030955

Errorflag Threshold vs Junction Temperature

20030957

DC Load Reg. vs Junction Temperature

20030958

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LP3853/LP3856

DC Line Regulation vs Temperature

20030959

VIN vs VOUT Over Temperature

20030960

Noise vs Frequency

20030961

Load Transient Response

CIN = COUT = 10µF, OSCON

20030971

Load Transient Response

CIN = COUT = 100µF, OSCON

20030972

Load Transient Response

CIN = COUT = 100µF, POSCAP

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LP3853/LP3856

Load Transient Response

CIN = COUT = 10µF, TANTALUM

20030974

Load Transient Response

CIN = COUT = 100µF, TANTALUM

20030975

Load Transient Response

CIN = COUT = 10µF, OSCON

20030976

Load Transient Response

CIN = COUT = 100µF, OSCON

20030977

Load Transient Response

CIN = COUT = 100µF, POSCAP

20030978

Load Transient Response

CIN = COUT = 10µF, TANTALUM

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LP3853/LP3856

Load Transient Response

CIN = COUT = 100µF, TANTALUM

20030980

Load Transient Response

CIN = 4 x 10µF CERAMIC

COUT = 3 x 10µF CERAMIC

20030981

Load Transient Response

CIN = 4 x 10µF CERAMIC

COUT = 3 x 10µF CERAMIC

20030982

Load Transient Response

CIN = 2 x 10µF CERAMIC

COUT = 2 x 10µF CERAMIC

20030983

Load Transient Response

CIN = 2 x 10µF CERAMIC

COUT = 2 x 10µF CERAMIC

20030984

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LP3853/LP3856

Application Hints

EXTERNAL CAPACITORS

Like any low-dropout regulator, external capacitors are re-

quired to assure stability. These capacitors must be correctly

selected for proper performance.

INPUT CAPACITOR: An input capacitor of at least 10µF is

required. Ceramic or Tantalum may be used, and capacitance

may be increased without limit

OUTPUT CAPACITOR: An output capacitor is required for

loop stability. It must be located less than 1 cm from the device

and connected directly to the output and ground pins using

traces which have no other currents flowing through them

(see PCB Layout section).

The minimum amount of output capacitance that can be used

for stable operation is 10µF. For general usage across all load

currents and operating conditions, the part was characterized

using a 10µF Tantalum input capacitor. The minimum and

maximum stable ESR range for the output capacitor was then

measured which kept the device stable, assuming any output

capacitor whose value is greater than 10µF (see Figure 1 be-

low).

20030970

FIGURE 1. ESR Curve for COUT (with 10µF Tantalum Input

Capacitor)

It should be noted that it is possible to operate the part with

an output capacitor whose ESR is below these limits, assum-

ing that sufficient ceramic input capacitance is provided. This

will allow stable operation using ceramic output capacitors

(see next section).

OPERATION WITH CERAMIC OUTPUT CAPACITORS

LP385X voltage regulators can operate with ceramic output

capacitors if the values of input and output capacitors are se-

lected appropriately. The total ceramic output capacitance

must be equal to or less than a specified maximum value in

order for the regulator to remain stable over all operating con-

ditions. This maximum amount of ceramic output capacitance

is dependent upon the amount of ceramic input capacitance

used as well as the load current of the application. This rela-

tionship is shown in Figure 2, which graphs the maximum

stable value of ceramic output capacitance as a function of

ceramic input capacitance for load currents of 1A, 2A, and 3A.

For example, if the maximum load current is 1A, a 10µF ce-

ramic input capacitor will allow stable operation for values of

ceramic output capacitance from 10µF up to about 500µF.

20030985

FIGURE 2. Maximum Ceramic Output Capacitance vs

Ceramic Input Capacitance

If the maximum load current is 2A and a 10µF ceramic input

capacitor is used, the regulator will be stable with ceramic

output capacitor values from 10µF up to about 50µF. At 3A of

load current, the ratio of input to output capacitance required

approaches 1:1, meaning that whatever amount of ceramic

output capacitance is used must also be provided at the input

for stable operation. For load currents between 1A, 2A, and

3A, interpolation may be used to approximate values on the

graph. When calculating the total ceramic output capacitance

present in an application, it is necessary to include any ce-

ramic bypass capacitors connected to the regulator output.

SELECTING A CAPACITOR

It is important to note that capacitance tolerance and variation

with temperature must be taken into consideration when se-

lecting a capacitor so that the minimum required amount of

capacitance is provided over the full operating temperature

range. In general, a good Tantalum capacitor will show very

little capacitance variation with temperature, but a ceramic

may not be as good (depending on dielectric type). Aluminum

electrolytics also typically have large temperature variation of

capacitance value.

Equally important to consider is a capacitor's ESR change

with temperature: this is not an issue with ceramics, as their

ESR is extremely low. However, it is very important in Tanta-

lum and aluminum electrolytic capacitors. Both show increas-

ing ESR at colder temperatures, but the increase in aluminum

electrolytic capacitors is so severe they may not be feasible

for some applications (see Capacitor Characteristics Sec-

tion).

CAPACITOR CHARACTERISTICS

CERAMIC: For values of capacitance in the 10 to 100 µF

range, ceramics are usually larger and more costly than tan-

talums but give superior AC performance for bypassing high

frequency noise because of very low ESR (typically less than

10 mΩ). However, some dielectric types do not have good

capacitance characteristics as a function of voltage and tem-

perature.

Z5U and Y5V dielectric ceramics have capacitance that drops

severely with applied voltage. A typical Z5U or Y5V capacitor

can lose 60% of its rated capacitance with half of the rated

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LP3853/LP3856

voltage applied to it. The Z5U and Y5V also exhibit a severe

temperature effect, losing more than 50% of nominal capac-

itance at high and low limits of the temperature range.

X7R and X5R dielectric ceramic capacitors are strongly rec-

ommended if ceramics are used, as they typically maintain a

capacitance range within ±20% of nominal over full operating

ratings of temperature and voltage. Of course, they are typi-

cally larger and more costly than Z5U/Y5U types for a given

voltage and capacitance.

TANTALUM: Solid Tantalum capacitors are typically recom-

mended for use on the output because their ESR is very close

to the ideal value required for loop compensation.

Tantalums also have good temperature stability: a good qual-

ity Tantalum will typically show a capacitance value that

varies less than 10-15% across the full temperature range of

125°C to −40°C. ESR will vary only about 2X going from the

high to low temperature limits.

The increasing ESR at lower temperatures can cause oscil-

lations when marginal quality capacitors are used (if the ESR

of the capacitor is near the upper limit of the stability range at

room temperature).

ALUMINUM: This capacitor type offers the most capacitance

for the money. The disadvantages are that they are larger in

physical size, not widely available in surface mount, and have

poor AC performance (especially at higher frequencies) due

to higher ESR and ESL.

Compared by size, the ESR of an aluminum electrolytic is

higher than either Tantalum or ceramic, and it also varies

greatly with temperature. A typical aluminum electrolytic can

exhibit an ESR increase of as much as 50X when going from

25°C down to −40°C.

It should also be noted that many aluminum electrolytics only

specify impedance at a frequency of 120 Hz, which indicates

they have poor high frequency performance. Only aluminum

electrolytics that have an impedance specified at a higher fre-

quency (between 20 kHz and 100 kHz) should be used for the

LP385X. Derating must be applied to the manufacturer's ESR

specification, since it is typically only valid at room tempera-

ture.

Any applications using aluminum electrolytics should be thor-

oughly tested at the lowest ambient operating temperature

where ESR is maximum.

TURN-ON CHARACTERISTICS FOR OUTPUT VOLTAGES

PROGRAMMED TO 2.0V OR BELOW

As Vin increases during start-up, the regulator output will track

the input until Vin reaches the minimum operating voltage

(typically about 2.2V). For output voltages programmed to

2.0V or below, the regulator output may momentarily exceed

its programmed output voltage during start up. Outputs pro-

grammed to voltages above 2.0V are not affected by this

behavior.

PCB LAYOUT

Good PC layout practices must be used or instability can be

induced because of ground loops and voltage drops. The in-

put and output capacitors must be directly connected to the

input, output, and ground pins of the regulator using traces

which do not have other currents flowing in them (Kelvin con-

nect).

The best way to do this is to lay out CIN and COUT near the

device with short traces to the VIN, VOUT, and ground pins. The

regulator ground pin should be connected to the external cir-

cuit ground so that the regulator and its capacitors have a

"single point ground".

It should be noted that stability problems have been seen in

applications where "vias" to an internal ground plane were

used at the ground points of the IC and the input and output

capacitors. This was caused by varying ground potentials at

these nodes resulting from current flowing through the ground

plane. Using a single point ground technique for the regulator

and it's capacitors fixed the problem.

Since high current flows through the traces going into VIN and

coming from VOUT, Kelvin connect the capacitor leads to these

pins so there is no voltage drop in series with the input and

output capacitors.

RFI/EMI SUSCEPTIBILITY

RFI (radio frequency interference) and EMI (electromagnetic

interference) can degrade any integrated circuit's perfor-

mance because of the small dimensions of the geometries

inside the device. In applications where circuit sources are

present which generate signals with significant high frequen-

cy energy content (> 1 MHz), care must be taken to ensure

that this does not affect the IC regulator.

If RFI/EMI noise is present on the input side of the regulator

(such as applications where the input source comes from the

output of a switching regulator), good ceramic bypass capac-

itors must be used at the input pin of the IC.

If a load is connected to the IC output which switches at high

speed (such as a clock), the high-frequency current pulses

required by the load must be supplied by the capacitors on

the IC output. Since the bandwidth of the regulator loop is less

than 100 kHz, the control circuitry cannot respond to load

changes above that frequency. This means the effective out-

put impedance of the IC at frequencies above 100 kHz is

determined only by the output capacitor(s).

In applications where the load is switching at high speed, the

output of the IC may need RF isolation from the load. It is

recommended that some inductance be placed between the

output capacitor and the load, and good RF bypass capacitors

be placed directly across the load.

PCB layout is also critical in high noise environments, since

RFI/EMI is easily radiated directly into PC traces. Noisy cir-

cuitry should be isolated from "clean" circuits where possible,

and grounded through a separate path. At MHz frequencies,

ground planes begin to look inductive and RFI/EMI can cause

ground bounce across the ground plane.

In multi-layer PCB applications, care should be taken in layout

so that noisy power and ground planes do not radiate directly

into adjacent layers which carry analog power and ground.

OUTPUT NOISE

Noise is specified in two ways-

Spot Noise or Output noise density is the RMS sum of all

noise sources, measured at the regulator output, at a specific

frequency (measured with a 1Hz bandwidth). This type of

noise is usually plotted on a curve as a function of frequency.

Total output Noise or Broad-band noise is the RMS sum of

spot noise over a specified bandwidth, usually several

decades of frequencies.

Attention should be paid to the units of measurement. Spot

noise is measured in units µV/√Hz or nV/√Hz and total output

noise is measured in µV(rms).

The primary source of noise in low-dropout regulators is the

internal reference. In CMOS regulators, noise has a low fre-

quency component and a high frequency component, which

depend strongly on the silicon area and quiescent current.

Noise can be reduced in two ways: by increasing the transis-

tor area or by increasing the current drawn by the internal

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LP3853/LP3856

reference. Increasing the area will decrease the chance of

fitting the die into a smaller package. Increasing the current

drawn by the internal reference increases the total supply

current (ground pin current). Using an optimized trade-off of

ground pin current and die size, LP3853/LP3856 achieves

low noise performance and low quiescent current operation.

The total output noise specification for LP3853/LP3856 is

presented in the Electrical Characteristics table. The Output

noise density at different frequencies is represented by a

curve under typical performance characteristics.

SHORT-CIRCUIT PROTECTION

The LP3853 and LP3856 are short circuit protected and in the

event of a peak over-current condition, the short-circuit con-

trol loop will rapidly drive the output PMOS pass element off.

Once the power pass element shuts down, the control loop

will rapidly cycle the output on and off until the average power

dissipation causes the thermal shutdown circuit to respond to

servo the on/off cycling to a lower frequency. Please refer to

the section on thermal information for power dissipation cal-

culations.

ERROR FLAG OPERATION

The LP3853/LP3856 produces a logic low signal at the Er-

ror Flag pin when the output drops out of regulation due to low

input voltage, current limiting, or thermal limiting. This flag has

a built in hysteresis. The timing diagram in Figure 3 shows the

relationship between the ERROR flag and the output voltage.

In this example, the input voltage is changed to demonstrate

the functionality of the Error Flag.

The internal Error flag comparator has an open drain output

stage. Hence, the ERROR pin should be pulled high through

a pull up resistor. Although the ERROR flag pin can sink cur-

rent of 1mA, this current is energy drain from the input supply.

Hence, the value of the pull up resistor should be in the range

of 10kΩ to 1MΩ. The ERROR pin must be connected to

ground if this function is not used. It should also be noted

that when the shutdown pin is pulled low, the ERROR pin is

forced to be invalid for reasons of saving power in shutdown

mode.

20030907

FIGURE 3. Error Flag Operation

SENSE PIN

In applications where the regulator output is not very close to

the load, LP3856 can provide better remote load regulation

using the SENSE pin. Figure 4 depicts the advantage of the

SENSE option. LP3853 regulates the voltage at the output

pin. Hence, the voltage at the remote load will be the regulator

output voltage minus the drop across the trace resistance. For

example, in the case of a 3.3V output, if the trace resistance

is 100mΩ, the voltage at the remote load will be 3V with 3A

of load current, ILOAD. The LP3856 regulates the voltage at

the sense pin. Connecting the sense pin to the remote load

will provide regulation at the remote load, as shown in Figure

4. If the sense option pin is not required, the sense pin must

be connected to the VOUT pin.

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LP3853/LP3856

20030908

FIGURE 4. Improving remote load regulation using LP3856

SHUTDOWN OPERATION

A CMOS Logic low level signal at the Shutdown (SD) pin will

turn-off the regulator. Pin SD must be actively terminated

through a 10kΩ pull-up resistor for a proper operation. If this

pin is driven from a source that actively pulls high and low

(such as a CMOS rail to rail comparator), the pull-up resistor

is not required. This pin must be tied to Vin if not used.

The Shutdown (SD) pin threshold has no voltage hysteresis.

If the Shutdown pin is actively driven, the voltage transition

must rise and fall cleanly and promptly.

DROPOUT VOLTAGE

The dropout voltage of a regulator is defined as the minimum

input-to-output differential required to stay within 2% of the

nominal output voltage. For CMOS LDOs, the dropout voltage

is the product of the load current and the Rds(on) of the in-

ternal MOSFET.

REVERSE CURRENT PATH

The internal MOSFET in LP3853 and LP3856 has an inherent

parasitic diode. During normal operation, the input voltage is

higher than the output voltage and the parasitic diode is re-

verse biased. However, if the output is pulled above the input

in an application, then current flows from the output to the

input as the parasitic diode gets forward biased. The output

can be pulled above the input as long as the current in the

parasitic diode is limited to 200mA continuous and 1A peak.

POWER DISSIPATION/HEATSINKING

LP3853 and LP3856 can deliver a continuous current of 3A

over the full operating temperature range. A heatsink may be

required depending on the maximum power dissipation and

maximum ambient temperature of the application. Under all

possible conditions, the junction temperature must be within

the range specified under operating conditions. The total pow-

er dissipation of the device is given by:

PD = (VIN−VOUT)IOUT+ (VIN)IGND

where IGND is the operating ground current of the device

(specified under Electrical Characteristics).

The maximum allowable temperature rise (TRmax) depends on

the maximum ambient temperature (TAmax) of the application,

and the maximum allowable junction temperature (TJmax):

TRmax = TJmax− TAmax

The maximum allowable value for junction to ambient Ther-

mal Resistance, θJA, can be calculated using the formula:

θJA = TRmax / PD

LP3853 and LP3856 are available in TO-220 and TO-263

packages. The thermal resistance depends on amount of

copper area or heat sink, and on air flow. If the maximum al-

lowable value of θJA calculated above is ≥ 60 °C/W for TO-220

package and ≥ 60 °C/W for TO-263 package no heatsink is

needed since the package can dissipate enough heat to sat-

isfy these requirements. If the value for allowable θJA falls

below these limits, a heat sink is required.

HEATSINKING TO-220 PACKAGE

The thermal resistance of a TO220 package can be reduced

by attaching it to a heat sink or a copper plane on a PC board.

If a copper plane is to be used, the values of θJA will be same

as shown in next section for TO263 package.

The heatsink to be used in the application should have a

heatsink to ambient thermal resistance,

θHA≤ θJA − θCH − θJC.

In this equation, θCH is the thermal resistance from the case

to the surface of the heat sink and θJC is the thermal resis-

tance from the junction to the surface of the case. θJC is about

3°C/W for a TO220 package. The value for θCH depends on

method of attachment, insulator, etc. θCH varies between 1.5°

C/W to 2.5°C/W. If the exact value is unknown, 2°C/W can be

assumed.

HEATSINKING TO-263 PACKAGE

The TO-263 package uses the copper plane on the PCB as

a heatsink. The tab of these packages are soldered to the

copper plane for heat sinking. Figure 5 shows a curve for the

θJA of TO-263 package for different copper area sizes, using

a typical PCB with 1 ounce copper and no solder mask over

the copper area for heat sinking.

www.national.com 14

LP3853/LP3856

20030932

FIGURE 5. θJA vs Copper (1 Ounce) Area for TO-263

package

As shown in the figure, increasing the copper area beyond 1

square inch produces very little improvement. The minimum

value for θJA for the TO-263 package mounted to a PCB is

32°C/W.

Figure 6 shows the maximum allowable power dissipation for

TO-263 packages for different ambient temperatures, assum-

ing θJA is 35°C/W and the maximum junction temperature is

125°C.

20030933

FIGURE 6. Maximum power dissipation vs ambient

temperature for TO-263 package

15 www.national.com

LP3853/LP3856

Physical Dimensions inches (millimeters) unless otherwise noted

TO220 5-lead, Molded, Stagger Bend Package (TO220-5)

NS Package Number T05D

For Order Numbers, refer to the “Ordering Information” section of this document.

www.national.com 16

LP3853/LP3856

TO263 5-Lead, Molded, Surface Mount Package (TO263-5)

NS Package Number TS5B

For Order Numbers, refer to the “Ordering Information” section of this document.

17 www.national.com

LP3853/LP3856

Notes

LP3853/LP3856 3A Fast Ultra Low Dropout Linear Regulators

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