© Semiconductor Components Industries, LLC, 2015
March, 2019 − Rev. 0
1Publication Order Number:
NCV7357/D
NCV7357
CAN FD Transceiver, High
Speed
Description
The NCV7357 CAN transceiver is the interface between
a controller area network (CAN) protocol controller and the physical
bus. The transceiver provides differential transmit capability to the bus
and differential receive capability to the CAN controller.
The NCV7357 is an addition to the CAN high−speed transceiver
family complementing NCV7344 CAN stand−alone transceivers and
previous generations such as AMIS42665, AMIS3066x, etc.
The NCV7357 guarantees additional timing parameters to ensure
robust communication at data rates beyond 1 Mbps to cope with CAN
flexible data rate requirements (CAN FD). These features make the
NCV7357 an excellent choice for all types of HS−CAN networks, in
nodes that require only a basic CAN capability.
Features
•Compatible with ISO 11898−2:2016
•CAN FD Timing Specified up to 5 Mbps
•VIO Pin on NCV7357−3 Version Allowing Direct Interfacing with
3 V to 5 V Microcontrollers
•Low Current, Listen Only Silent Mode
•Low Electromagnetic Emission (EME) and High Electromagnetic
Immunity
•Very Low EME without Common−mode (CM) Choke
•No Disturbance of the Bus Lines with an Unpowered Node
•Transmit Data (TxD) Dominant Timeout Function
•Under All Supply Conditions the Chip Behaves Predictably
•Very High ESD Robustness of Bus Pins, >8 kV System ESD Pulses
•Thermal Protection
•Bus Pins Short Circuit Proof to Supply Voltage and Ground
•Bus Pins Protected Against Transients in an Automotive
Environment
•These are Pb−free Devices
Quality
•Wettable Flank Package for Enhanced Optical Inspection
•NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
Typical Applications
•Automotive
•Industrial Networks
MARKING DIAGRAM
www.onsemi.com
See detailed ordering, marking and shipping information on
page 11 of this data sheet.
ORDERING INFORMATION
NV7357−X = Specific Device Code
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G= Pb−Free Package
NV7357−X
ALYWG
G
1
NV7357−X
ALYWG
G
1
8
SOIC−8
D SUFFIX
CASE 751AZ
DFNW8
MW SUFFIX
CASE 507AB
PIN ASSIGNMENT
TxD
RxD
S
NC (−0)
VIO (−3)
CANL
CANH
VCC
GND EP
18
1
2
3
4
8
7
6
5
TxD
RxD
S
NC (−0)
VIO (−3)
CANL
CANH
VCC
GND
NCV7357−X
NCV7357D1x
(Top View)
NCV7357MWx
(Top View)
NCV7357
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3
VCC
Micro−
controller
NC
VBAT
GND
2
5
CANH
CANL
3
6
7
CAN
BUS
.
5V −reg
RLT =60W
RLT =60W
GND
S
RxD
TxD 1
4
8
IN OUT
VCC
NCV
7357−
0
Figure 3. Application Diagram NCV7357−0
5V −reg
VCC
Micro−
controller
VIO
VBAT
GND
2
5
CANH
CANL
3
6
7
CAN
BUS
.
3V −reg
RLT =60W
RLT =60W
GND
S
RxD
TxD 1
4
8
NCV7357−3
IN OUT
IN OUT
Figure 4. Application Diagram NCV7357−3
Table 1. PIN FUNCTION DESCRIPTION
Pin Name Description
1 TxD Transmit data input; low input Ù dominant driver; internal pull−up current
2 GND Ground
3 VCC Supply voltage
4 RxD Receive data output; dominant transmitter Ù low output
5
5
NC
VIO
Not connected. On NCV7357−0 only
Digital Input / Output pins supply voltage. On NCV7357−3 only
6 CANL Low−level CAN bus line (low in dominant mode)
7 CANH High−level CAN bus line (high in dominant mode)
8 S Silent mode control input; internal pull−up current
EP Exposed Pad. Recommended to connect to GND or left floating in application
(DFNW8 package only).
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FUNCTIONAL DESCRIPTION
High speed CAN FD transceiver
NCV7357 implements high−speed physical layer CAN
FD transceiver compatible with ISO11898−2, implementing
following optional features or alternatives:
•Extended bus load range
•Transmit dominant timeout, long
•Support of bit rates up to 5 Mbps
•Normal Bus biasing
Operating Modes
NCV7357 provides two modes of operation as illustrated
in Table 2. These modes are selectable through pin S.
Table 2. OPERATING MODES
Pin S Mode Pin TxD BUS Pin RxD
Low Normal
0 Dominant 0
1 Recessive 1
High Silent
XDominant
(1) 0
X Recessive 1
1. CAN BUS driven by another transceiver on the BUS
2. ’X’ = don’t care
Power−off
This virtual mode is entered as soon as the VCC or VIO
undervoltage condition is detected. The internal logic is
reset and the transceiver is disabled. CAN bus pins are kept
floating. As soon as both VCC and VIO voltages rise above
corresponding undervoltage recovery thresholds, the device
proceeds to Normal or Silent mode, depending on S pin
state.
Normal Mode
In the normal mode, the transceiver is able to
communicate via the bus lines. The signals are transmitted
and received to the CAN controller via the pins TxD and
RxD. The slopes on the bus lines outputs are optimized to
give low EME.
Silent Mode
In the silent mode, the transmitter is disabled. The bus pins
are in recessive state independent of TxD input. Transceiver
listens to the bus and provides data to controller, but
controller is prevented from sending any data to the bus.
Silent mode
Power−off
Normal mode
Any
mode CAN: off (no bias)
RxD: High−Z
TxD, S: High−Z
S = Low S = High
CAN: Tx/Rx
CAN bias: VCC/2
CAN: Rx only
CAN bias: VCC/2
S = Low
No UV
and S = High
Notes:
NCV7357−0
UV detected: VCC < VUVDVCC
No UV: VCC > VUVDVCC
S = High
No UV
and S = Low
UV
detected
NCV7357−3
UV detected: VCC < VUVDVCC and/or VIO < VUVDVIO
No UV: VCC > VUVDVCC and VIO > VUVDVIO
Overtemperature Detection
A thermal protection circuit protects the IC from damage
by switching off the transmitter if the junction temperature
exceeds TJ(sd) value. Because the transmitter dissipates most
of the power, the power dissipation and temperature of the
IC is reduced. All other IC functions continue to operate.
The transmitter off−state resets when the temperature
decreases below the shutdown threshold and pin TxD goes
high. The thermal protection circuit is particularly needed
when a bus line short circuits.
TxD Dominant Timeout Function
A TxD dominant timeout timer circuit prevents the bus
lines being driven to a permanent dominant state (blocking
all network communication) if pin TxD is forced
permanently low by a hardware and/or software application
failure. The timer is triggered by a negative edge on pin TxD.
If the duration of the low−level on pin TxD exceeds the
internal timer value tdom(TxD), the transmitter is disabled,
driving the bus into a recessive state. The timer is reset by a
positive edge on pin TxD.
This TxD dominant timeout time tdom(TxD) defines the
minimum possible bit rate to 17 kbps.
Fail Safe Features
A current−limiting circuit protects the transmitter output
stage from damage caused by accidental short circuit
to either positive or negative supply voltage, although
power dissipation increases during this fault condition.
Detection of undervoltage on supply pin (VCC or VIO)
causes switching off device. After supply voltage is
recovered TxD pin must be first released to high to allow
sending dominant bits again.
The pins CANH and CANL are protected from
automotive electrical transients (according to ISO 7637; see
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Figure 7). Pins TxD and S are biased internally should the
input become disconnected. Pins TxD, S and RxD will be
floating, preventing reverse supply should the VCC supply
be removed.
VIO Supply Pin
The VIO pin (available only on NCV7357−3 version)
should be connected to microcontroller supply pin. By using
VIO supply pin shared with microcontroller the I/O levels
between microcontroller and transceiver are properly
adjusted. See Figure 4.
Definitions
All voltages are referenced to GND (pin 2). Positive
currents flow into the IC. Sinking current means the current
is flowing into the pin; sourcing current means the current
is flowing out of the pin.
ABSOLUTE MAXIMUM RATINGS
Table 3. ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Conditions Min. Max. Unit
VSUP Supply voltage VCC, VIO −0.3 +6.0 V
VCANH DC voltage at pin CANH 0 < VCC < 5.5 V; no time limit −42 +42 V
VCANL DC voltage at pin CANL 0 < VCC < 5.5 V; no time limit −42 +42 V
VCANH − CANL DC voltage between CANH and CANL −42 +42 V
VI/O DC voltage at pin TxD, RxD, S −0.3 +6.0 V
VesdHBM Electrostatic discharge voltage at all
pins, Component HBM
(Note 3) −6 +6 kV
VesdCDM Electrostatic discharge voltage at all
pins, Component CDM
(Note 4) −750 +750 V
VesdIEC Electrostatic discharge voltage at pins
CANH and CANL,
System HBM (Note 6)
(Note 5)
−8 +8 kV
Vschaff Voltage transients, pins CANH, CANL.
According to ISO7637−3, Class C
(Note 6)
test pulses 1 −100 V
test pulses 2a +75 V
test pulses 3a −150 V
test pulses 3b +100 V
Latch−up Static latch−up at all pins (Note 7) 150 mA
Tstg Storage temperature −55 +150 °C
TJMaximum junction temperature −40 +170 °C
MSLSOIC Moisture sensitivity level for SOIC−8 2 −
MSLDFN Moisture sensitivity level for DFNW8 1−
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
3. Standardized human body model electrostatic discharge (ESD) pulses in accordance to EIA−JESD22. Equivalent to discharging a 100 pF
capacitor through a 1.5 kW resistor
4. Standardized charged device model ESD pulses when tested according to AEC−Q100−011
5. System human body model electrostatic discharge (ESD) pulses in accordance to IEC 61000−4−2. Equivalent to discharging a 150 pF
capacitor through a 330 W resistor referenced to GND
6. Results were verified by external test house
7. Static latch−up immunity: Static latch−up protection level when tested according to EIA/JESD78
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Table 4. THERMAL CHARACTERISTICS
Parameter Symbol Value Unit
Thermal characteristics SOIC−8 (Note 8)
Thermal Resistance Junction−to−Air, Free air, 1S0P PCB (Note 9)
Thermal Resistance Junction−to−Air, Free air, 2S2P PCB (Note 10)
RqJA
RqJA
131
81
°C/W
°C/W
Thermal characteristics DFNW8 (Note 8)
Thermal Resistance Junction−to−Air, Free air, 1S0P PCB (Note 9)
Thermal Resistance Junction−to−Air, Free air, 2S2P PCB (Note 10)
RqJA
RqJA
125
58
°C/W
°C/W
8. Refer to ELECTRICAL CHARACTERISTICS, RECOMMENDED OPERATING RANGES and/or APPLICATION INFORMATION for Safe
Operating parameters
9. Values based on test board according to EIA/JEDEC Standard JESD51−3, signal layer with 10% trace coverage
10.Values based on test board according to EIA/JEDEC Standard JESD51−7, signal layers with 10% trace coverage
Table 5. ELECTRICAL CHARACTERISTICS (VCC = 4.75 V to 5.25 V; VIO = 2.8 V to 5.25 V; for typical values TA = 25°C, for
min/max values TJ = −40 to +150°C; RLT = 60 W, CRxD = 15 pF; unless otherwise noted. All voltages are referenced to GND (pin 2).
Positive currents flow into the respective pin; (Notes 11))
Symbol Parameter Conditions Min Typ Max Unit
SUPPLY (Pin VCC)
VCC Power supply voltage (Note 12) 4.75 5.0 5.25 V
ICC Supply current in Normal mode Dominant; VTxD = Low 30 45 55 mA
Recessive; VTxD = High 2.0 5.0 10 mA
Normal mode, Dominant; VTxD = 0
V; one of bus wires shorted
−3 V ≤ (VCANH, VCANL) ≤ +18 V
2.0 −
105 mA
ICCS Supply current in silent mode
NCV7357−3 version
0.1 −1.3 mA
Supply current in silent mode
NCV7357−0 version
0.1 −1.5 mA
VUVDVCC Undervoltage detection on VCC pin 3.5 4.0 4.3 V
VIO SUPPLY VOLTAGE (Pin VIO) Only for NCV7357−3 version
VIO Supply voltage on pin VIO 2.8 −5.5 V
IIOS Supply current on pin VIO in silent mode VTxD = VIO −120 200 mA
IIONM Supply current on pin VIO during normal
mode
Dominant; VTxD = Low −700 900
mA
Recessive; VTxD = High −460 600
VUVDVIO Undervoltage detection voltage on VIO
pin
2.0 2.3 2.6 V
TRANSMITTER DATA INPUT (Pin TxD)
VIH High−level input voltage Output recessive 2.0 − − V
VIL Low−level input voltage Output dominant −0.3 −0.8 V
IIH High−level input current VTxD = VCC / VIO −5.0 0 5.0 mA
IIL Low−level input current VTxD = 0 V −300 −150 −75 mA
CiInput capacitance (Note 13) −5 10 pF
TRANSMITTER DATA INPUT (Pin S)
VIH High−level input voltage Silent mode 2.0 − − V
VIL Low−level input voltage Normal mode −0.3 −0.8 V
IIH High−level input current VS = VCC / VIO −1.0 0 1.0 mA
IIL Low−level input current VS = 0 V −15 − −1.0 mA
CiInput capacitance (Note 13) −5 10 pF
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Table 5. ELECTRICAL CHARACTERISTICS (VCC = 4.75 V to 5.25 V; VIO = 2.8 V to 5.25 V; for typical values TA = 25°C, for
min/max values TJ = −40 to +150°C; RLT = 60 W, CRxD = 15 pF; unless otherwise noted. All voltages are referenced to GND (pin 2).
Positive currents flow into the respective pin; (Notes 11))
RECEIVER DATA OUTPUT (Pin RxD)
IOH High−level output current Normal mode
VRxD = VCC / VIO – 0.4 V
−8.0 −3.0 −1.0 mA
IOL Low−level output current VRxD = 0.4 V 1.0 6.0 12 mA
CAN TRANSMITTER (PINS CANH AND CANL)
Vo(dom)(CANH) Dominant output voltage at pin CANH Normal mode; VTxD = Low;
t < tdom(TxD); 50 W < RLT < 65 W2.75 3.5 4.5 V
Vo(dom)(CANL) Dominant output voltage at pin CANL Normal mode; VTxD = Low;
t < tdom(TxD); 50 W < RLT < 65 W0.5 1.5 2.25 V
Vo(rec) Recessive output voltage at pins CANH
and CANL
Normal or Silent mode;
VTxD = High
or VTxD = Low and t > tdom(TxD);
no load
2.0 2.5 3.0 V
Vo(dom)(diff) Differential dominant output voltage
(VCANH − VCANL)
Normal mode; VTxD = Low;
t < tdom(TxD); 45 W < RLT < 65 W1.5 2.25 3.0 V
Vo(dom)(diff)_ARB Normal mode; VTxD = Low;
t < tdom(TxD); RLT = 2 240 W
(Note 13)
1.5 −5.0 V
Vo(rec)(diff) Differential recessive output voltage
(VCANH − VCANL)
Normal or Silent mode;
VTxD = High
or VTxD = Low and t > tdom(TxD);
no load
−50 0 +50 mV
Vo(dom)(sym) Dominant output voltage driver symmetry
Vo(dom)(sym) = Vo(CANH)(dom) +
Vo(CANL)(dom)
TxD = square wave up to 1 MHz;
CST = 4.7 nF 0.9 1.0 1.1 VCC
Io(sc)(CANH) Short circuit output current at pin CANH
in dominant
Normal mode; TxD = Low,
t < tdom(TxD); −3V ≤ VCANH ≤
+18 V
−100 −70 +1.0 mA
Io(sc)(CANL) Short circuit output current at pin CANL in
dominant
Normal mode; TxD = Low,
t < tdom(TxD); −3V ≤ VCANL ≤
+36 V
−1.0 +70 +100 mA
Io(sc)(rec) Short circuit output current at pins CANH
and CANL in recessive
Normal or Silent mode;
TxD = High,
−27 V < VCANH, VCANL < + 32 V
−5.0 −+5.0 mA
CAN RECEIVER (Pins CANH and CANL)
ILEAK(off) Input leakage current 0 W < R(VCC to GND) < 1 MW
VCANH = VCANL = 5 V −5.0 0 +5.0 mA
VCC = VIO = 0 V
VCANH = VCANL = 5 V −5.0 0 +5.0 mA
Vi(rec)(diff)_NM Differential input voltage range
recessive state
Normal or Silent mode;
−12 V ≤ VCANH, VCANL ≤ +12 V;
no load
−3.0 −0.5 V
Vi(dom)(diff)_NM Differential input voltage range
dominant state
Normal or Silent mode;
−12 V ≤ VCANH, VCANL ≤ +12 V;
no load
0.9 −8.0 V
Vi(th)(diff)_NM Differential receiver threshold voltage
voltage
Normal or Silent mode;
−12 V ≤ VCANH, VCANL ≤ +12 V;
no load
0.5 −0.9 V
Vi(th)(diff)_NM_E Normal or Silent mode; extended,
−30 V ≤ VCANH, VCANL ≤ +35 V;
no load
0.4 −1.0 V
Ri(cm) Common−mode input resistance at pins
CANH and CANL
−2 V ≤ VCANH, VCANL ≤ +7 V 15 25 37 kW
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Table 5. ELECTRICAL CHARACTERISTICS (VCC = 4.75 V to 5.25 V; VIO = 2.8 V to 5.25 V; for typical values TA = 25°C, for
min/max values TJ = −40 to +150°C; RLT = 60 W, CRxD = 15 pF; unless otherwise noted. All voltages are referenced to GND (pin 2).
Positive currents flow into the respective pin; (Notes 11))
Ri(cm)(m) Matching between pin CANH and pin
CANL common mode input resistance
VCANH = VCANL = + 5 V −1 0 +1 %
Ri(diff) Differential input resistance Ri(diff) = Ri(cm)(CANH) +
Ri(cm)(CANL)
−2 V ≤ VCANH, VCANL ≤ + 7 V
25 50 75 kW
CiInput capacitance at pins CANH and
CANL
VTxD = High; (Note 13) −7.5 20 pF
Ci(diff) Differential input capacitance VTxD = High; (Note 13) −3.75 10 pF
TIMING CHARACTERISTICS (see Figure 5, Figure 6 and Figure 8)
td(TxD−BUSon) Propagation delay TxD to bus active Normal mode (Note 14) −75 −ns
td(TxD−BUSoff) Propagation delay TxD to bus inactive Normal mode (Note 14) −85 −ns
td(BUSon−RxD) Propagation delay bus active to RxD Normal or Silent mode (Note 14) −24 −ns
td(BUSoff−RxD) Propagation delay bus inactive to RxD Normal or Silent mode (Note 14) −32 −ns
tpd_dr Propagation delay TxD to RxD dominant
to recessive transition
Normal mode (Note 14) 50 100 210 ns
tpd_rd Propagation delay TxD to RxD recessive
to dominant transition
Normal mode (Note 14) 50 120 210 ns
td(s−nm) Operating mode change delay Silent mode to Normal mode 5.0 11 50 ms
tdom(TxD) TxD dominant timeout Normal mode; VTxD = Low 1.0 −10 ms
tbit(RxD) Bit time on RxD pin tbit(TxD) = 500 ns (Note 14) 400 −550 ns
tbit(TxD) = 200 ns (Note 14) 120 −220 ns
tbit(Vi(diff)) Bit time on bus (CANH − CANL pin) tbit(TxD) = 500 ns (Note 14) 435 −530 ns
tbit(TxD) = 200 ns (Note 14) 155 −210 ns
Dtrec
Receiver timing symmetry
Δtrec = tbit(RxD) − tbit(Vi(diff))
tbit(TxD) = 500 ns (Note 14) −65 −40 ns
tbit(TxD) = 200 ns (Note 14) −45 −15 ns
THERMAL SHUTDOWN
TJ(sd) Shutdown junction temperature Junction temperature rising 160 180 200 °C
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
11. Performance guaranteed over the indicated operating temperature range by design and/or characterization tested at TJ = TA = 25°C. Low
duty cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible.
12.In the range between VUVDVCC and 4.75 V and from 5.25 V to 6 V the chip is fully functional; some parameters may be outside of the
specification
13.Values based on design and characterization, not tested in production
14.CLT = 100 pF, CST not present, CRxD = 15 pF
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MEASUREMENTS SETUPS AND DEFINITIONS
Figure 5. Transceiver Timing Diagram − Propagation Delays
td(TxD−BUSon)
Vi(diff) =
VCANH − V
CANL
dominant
900 mV
500 mV
recessive
0.3 x VIO*
recessive
0.7 x VIO*
TxD
CANH
CANL
td(BUSon−RXD) td(TxD−BUSoff) td(BUSoff−RXD)
RxD
0.3 x VIO*0.7 x VIO*
RxD
0.3 x VIO*
0.7 x VIO*
TxD 0.3 x VIO*
5 x tbit(TxD) tpd_rd
tbit(TxD)
tpd_dr tbit(RxD)
0.7 x VIO*
0.3 x VIO*
Vi(diff) =
VCANH − V
CANL
900 mV
500 mV
tbit(Vi(diff))
Edge length below 10 ns
Edge length below 10 ns
*On NCV7357−0 version VIO is replaced by VCC
*On NCV7357−0 version VIO is replaced by VCC
Figure 6. Transceiver Timing Diagram − Loop Delay and Recessive Bit Time
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Table 6. ISO 11898−2:2016 Parameter Cross−Reference Table
ISO 11898−2:2016 Specification NCV7357 Datasheet
Parameter Notation Symbol
DOMINANT OUTPUT CHARACTERISTICS
Single ended voltage on CAN_H VCAN_H Vo(dom)(CANH)
Single ended voltage on CAN_L VCAN_L Vo(dom)(CANL)
Differential voltage on normal bus load VDiff Vo(dom)(diff)
Differential voltage on effective resistance during arbitration VDiff Vo(dom)(diff)_ARB
Differential voltage on extended bus load range (optional) VDiff Vo(dom)(diff)
DRIVER SYMMETRY
Driver symmetry VSYM Vo(dom)(sym)
DRIVER OUTPUT CURRENT
Absolute current on CAN_H ICAN_H Io(SC)(CANH)
Absolute current on CAN_L ICAN_L Io(SC)(CANL)
RECEIVER OUTPUT CHARACTERISTICS, BUS BIASING ACTIVE
Single ended output voltage on CAN_H VCAN_H NA
Single ended output voltage on CAN_L VCAN_L NA
Differential output voltage VDiff NA
RECEIVER OUTPUT CHARACTERISTICS, BUS BIASING INACTIVE
Single ended output voltage on CAN_H VCAN_H Vo(off) (CANH)
Single ended output voltage on CAN_L VCAN_L Vo(off) (CANL)
Differential output voltage VDiff Vo(off) (diff)
OPTIONAL TRANSMIT DOMINANT TIMEOUT
Transmit dominant timeout, long tdom tdom(TxD)
Transmit dominant timeout, short tdom NA
STATIC RECEIVER INPUT CHARACTERISTICS, BUS BIASING ACTIVE/ INACTIVE
Recessive state differential input voltage range VDiff Vi(rec)(diff)_NM
Dominant state differential input voltage range VDiff Vi(dom)(diff)_NM
RECEIVER INPUT RESISTANCE
Differential internal resistance RDiff Ri(diff)
Single ended internal resistance RCAN_H
RCAN_L
Ri(cm)
Ri(cm)
RECEIVER INPUT RESISTANCE MATCHING
Matching a of internal resistance mRRi(cm)(m)
IMPLEMENTATION LOOP DELAY REQUIREMENT
Loop delay tLoop tpd_rd
tpd_dr
OPTIONAL IMPLEMENTATION DATA SIGNAL TIMING REQUIREMENTS FOR USE WITH BIT RATES ABOVE 1 MBIT/S AND UP
TO 2 MBIT/S
Transmitted recessive bit width @ 2 Mbit/s tBit(Bus) tbit(Vi(diff))
Received recessive bit width @ 2 Mbit/s tBit(RXD) tbit(RxD)
Receiver timing symmetry @ 2 Mbit/s DtRec Dtrec
OPTIONAL IMPLEMENTATION DATA SIGNAL TIMING REQUIREMENTS FOR USE WITH BIT RATES ABOVE 2 MBIT/S AND UP
TO 5 MBIT/S
Transmitted recessive bit width @ 5 Mbit/s tBit(Bus) tbit(Vi(diff))
Transmitted recessive bit width @ 5 Mbit / s tBit(RXD) tbit(RxD)
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Received recessive bit width @ 5 Mbit / s DtRec Dtrec
MAXIMUM RATINGS OF VCAN_H, VCAN_L AND VDIFF
Maximum rating VDiff VDiff VCANH − CANL
General maximum rating VCAN_H and VCAN_L VCAN_H
VCAN_L
VCANH
VCANL
Optional: Extended maximum rating VCAN_H and VCAN_L VCAN_H
VCAN_L NA
MAXIMUM LEAKAGE CURRENTS ON CAN_H AND CAN_L, UNPOWERED
Leakage current on CAN_H, CAN_L ICAN_H,
ICAN_L ILEAK(off)
BUS BIASING CONTROL TIMINGS
CAN activity filter time, long tFilter NA
CAN activity filter time, short tFilter NA
Wake−up timeout, short tWake NA
Wake−up timeout, long tWake NA
Timeout for bus inactivity (Required for selective wake−up implementation only) tSilence NA
Bus Bias reaction time (Required for selective wake−up implementation only) tBias NA
Table 7. ORDERING INFORMATION
Part Number Description Temperature Range Package Shipping
NCV7357D10R2G High Speed CAN FD
Transceiver
−40°C to +150°C
SOIC 150 8 GREEN
(Matte Sn, JEDEC
MS−012) (Pb−Free)
3000 / Tape & Reel
NCV7357D13R2G High Speed CAN FD
Transceiver with VIO pin 3000 / Tape & Reel
NCV7357MW0R2G High Speed CAN FD
Transceiver
−40°C to +150°C
DFNW8
Wettable Flank
(Pb−Free)
3000 / Tape & Reel
NCV7357MW3R2G High Speed CAN FD
Transceiver with VIO pin 3000 / Tape & Reel
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PACKAGE DIMENSIONS
SOIC−8
CASE 751AZ
ISSUE B
7.00
8X
0.76
8X
1.52
1.27
DIMENSIONS: MILLIMETERS
1
PITCH
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
RECOMMENDED
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION.
ALLOWABLE PROTRUSION SHALL BE 0.004 mm IN EXCESS OF
MAXIMUM MATERIAL CONDITION.
4. DIMENSION D DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS
OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS
SHALL NOT EXCEED 0.006 mm PER SIDE. DIMENSION E1 DOES
NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD
FLASH OR PROTRUSION SHALL NOT EXCEED 0.010 mm PER SIDE.
5. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOT
TOM. DIMENSIONS D AND E1 ARE DETERMINED AT THE OUTER
MOST EXTREMES OF THE PLASTIC BODY AT DATUM H.
6. DIMENSIONS A AND B ARE TO BE DETERMINED AT DATUM H.
7. DIMENSIONS b AND c APPLY TO THE FLAT SECTION OF THE LEAD
BETWEEN 0.10 TO 0.25 FROM THE LEAD TIP.
8. A1 IS DEFINED AS THE VERTICAL DISTANCE FROM THE SEATING
PLANE TO THE LOWEST POINT ON THE PACKAGE BODY.
14
85
SEATING
PLANE
DETAIL A
0.10 C
A1
DIM MIN MAX
MILLIMETERS
h0.25 0.41
A--- 1.75
b0.31 0.51
L0.40 1.27
e1.27 BSC
c0.10 0.25
A1 0.10 0.25
L2
M
0.25 A-B
b8X
CD
A
B
C
TOP VIEW
SIDE VIEW
0.25 BSC
E1 3.90 BSC
E6.00 BSC
D
e
D
0.20 C
0.10 C
2X
NOTE 6
NOTES 4&5
NOTES 4&5
SIDE VIEW
END VIEW
E E1
D
0.10 C D
D
NOTES 3&7
NOTE 6
NOTE 8
A
A2
A2 1.25 ---
D4.90 BSC
H
SEATING
PLANE
DETAIL A
LC
L2
h
45 CHAMFER5
c
NOTE 7
GENERIC
MARKING DIAGRAM*
*This information is generic. Please refer
to device data sheet for actual part
marking. Pb−Free indicator, “G”, may
or not be present.
NCV7357
www.onsemi.com
14
DFNW8 3x3, 0.65P
CASE 507AB
ISSUE D
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.10 AND
0.20mm FROM THE TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
5. THIS DEVICE CONTAINS WETTABLE FLANK
DESIGN FEATURES TO AID IN FILLET FORMA-
TION ON THE LEADS DURING MOUNTING.
ÉÉÉ
ÉÉÉ
ÉÉÉ
A
B
E
D
D2
E2
BOTTOM VIEW
b
e
8X
0.10 B
0.05
AC
CNOTE 3
PIN ONE
REFERENCE
TOP VIEW
A
A3
0.05 C
0.05 C
CSEATING
PLANE
SIDE VIEW
L
8X
14
58
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
RECOMMENDED
DETAIL B
DETAIL A
NOTE 4
e/2
GENERIC
MARKING DIAGRAM*
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”, may
or may not be present. Some products may
not follow the Generic Marking.
(Note: Microdot may be in either location)
SOLDERING FOOTPRINT*
DIM MIN NOM
MILLIMETERS
A0.80 0.85
A1 −−− −−−
b0.25 0.30
D
D2 2.30 2.40
E
E2 1.50 1.60
e0.65 BSC
L0.35 0.40
A3 0.20 REF
2.95 3.00
K
A4
L3
MAX
2.95 3.00
0.90
0.05
0.35
2.50
1.70
0.45
3.05
3.05
0.00 0.05 0.10
ALTERNATE
CONSTRUCTION
DETAIL A
L3
SECTION C−C
PLATED
A4
SURFACES
L3
L3
L
DETAIL B
PLATING
EXPOSED
COPPER
A4
A1
L
C
C
PACKAGE
OUTLINE
14
85
8X
0.75
2.55
1.76
0.33
0.65
PITCH
3.30
8X
DIMENSIONS: MILLIMETERS
2.28
K
0.30 REF
0.10 −−− −−−
NCV7357
www.onsemi.com
15
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